JP2006158001A - Inverter device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an inverter device where loss is small and distortion of an output current or output voltage is small. <P>SOLUTION: An inverter circuit 10 is equipped with a bridge circuit 11 composed of an upper arm switch Q1 and a lower arm switch Q2 and a bridge circuit 12 composed of an upper arm switch Q3 and a lower arm switch Q4. The upper arm switches Q1 and Q3 are switch elements capable of high-frequency switching, and the lower arm switches Q2 and Q4 are switching elements low in ON voltage. For the first half of each cycle of AC output, it is PWM-controlled with the bridge circuit 11, and the polarity of the output is set with the bridge circuit 12, and for the second half of each cycle of AC output, it is PWM-controlled with the bridge circuit 12, and also the polarity of the output is set with the bridge circuit 11. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an inverter device that converts DC power into AC power and outputs the power.

  FIG. 5 is a configuration diagram of a general inverter device. In FIG. 5, the inverter circuit 100 converts DC power from the input power supply 110 into AC power having a predetermined frequency and supplies the AC power to the load 130. Here, an input capacitor C <b> 1 is provided between the input power supply 110 and the inverter circuit 100. A filter 120 including a coil L1 and an output capacitor C2 is provided between the inverter circuit 100 and the load 130.

  Inverter circuit 100 includes a first bridge circuit including upper arm switch Q1 and lower arm switch Q2 connected in series with each other, and an upper arm switch Q3 and lower arm switch Q4 connected in series with each other. A second bridge circuit is provided. Then, an unillustrated control circuit controls the switches Q1 to Q4, thereby generating AC power having a predetermined frequency. Each of the switches Q1 to Q4 is a switching element such as a transistor.

One technique for reducing the loss in the inverter device configured as described above is described in Patent Document 1. In the inverter device described in Patent Document 1, as shown in FIG. 6, high-frequency switching (for example, several kHz to several tens kHz) is performed on the switches Q1 and Q2, and the amplitude of the output voltage is controlled. On the other hand, switching (for example, 50/60 Hz) for switching the polarity of the output voltage is performed for the switches Q3 and Q4. By introducing this configuration, the number of times of switching of the switches Q3 and Q4 is significantly reduced, so that the switching loss is reduced. That is, the loss in the inverter device can be reduced.
Japanese Unexamined Patent Publication No. 2000-152661 (FIG. 3, paragraphs 0039 to 0042 of the specification)

  In the inverter device described in Patent Document 1, switching elements having a low on-voltage are used as the switches Q3 and Q4 driven at a low frequency. Thereby, the loss of the inverter circuit 100 is further reduced.

  In general, in the inverter device having the above-described configuration, in order to avoid a current flowing so as to pass through the upper arm switch and the lower arm switch connected to each other, an inactive period for simultaneously turning off both switches during switching ( Dead time) is set. However, in the configuration described in Patent Document 1, switching elements having a low on-voltage are used as the switches Q3 and Q4. Here, when comparing elements having the same rated voltage and rated current, a switching element having a low on-voltage generally has a low switching speed. For this reason, it is necessary to set a large pause period for the switches Q3 and Q4. As a result, odd-order harmonics increase near the timing at which the polarity of the output voltage of the inverter device switches (that is, near the output zero-cross point), and distortion of the output voltage worsens.

  An object of the present invention is to provide an inverter device with low loss and low distortion of output current or output voltage.

  The inverter device of the present invention is a device that generates alternating current of a predetermined cycle, and includes a first bridge circuit and a second upper arm switching composed of a first upper arm switching element and a first lower arm switching element. An inverter circuit including a second bridge circuit composed of an element and a second lower arm switching element, and a control means for controlling each of the switching elements. The on-voltages of the first and second lower arm switching elements are lower than the on-voltages of the first and second upper arm switching elements, respectively. Further, the control means performs high-frequency switching for alternately turning on the first upper arm switching element and the first lower arm switching element for each cycle, and the second upper arm switching element and A first control for holding the second lower arm switching element in a different state; holding the first upper arm switching element and the first lower arm switching element in a different state; Second control is performed to perform high-frequency switching that alternately turns on the arm switching element and the second lower arm switching element.

  In the inverter device, the on-voltage of the switching element and the switching speed are in a trade-off relationship. That is, the ON voltage of the first and second lower arm switching elements is low, while the switching speed of the first and second upper arm switching elements is fast. As a result, each of the first and second bridge circuits is composed of a combination of an element having a high switching speed and an element having a low on-voltage, and a bridge circuit composed of a combination of elements having a low on-voltage. Compared with, the downtime (dead time) can be reduced. In both the first and second controls, two of the four switching elements are not substantially switched, so that switching loss is suppressed.

  In the above inverter device, the same effect is obtained even if the relationship between the on-voltage and the switching speed of the first and second lower arm switching elements and the first and second upper arm switching elements is reversed. The effect is obtained.

  In the inverter apparatus, the control means may generate a PWM control signal for the high-frequency switching based on an error between a current to be supplied to a load and an output current of the inverter circuit. Thus, the present invention can be applied to a current control type inverter device.

  Alternatively, in the inverter device, the control means may generate a PWM control signal for the high-frequency switching based on an error between a voltage to be applied to a load and an output voltage of the inverter circuit. Thus, the present invention can be applied to a voltage control type inverter device.

  Further, in the inverter device, each of the execution times of the first and second controls is set to a half of the predetermined period, and the control means determines the direction of the current or voltage flowing through the load in the first control. In the first control, the second upper arm switching element and the second lower arm switching element are controlled in the first control so that the direction of the current or voltage flowing through the load in the second control is reversed. In the second control, the first upper arm switching element and the first lower arm switching element may be controlled. This invention presents a specific configuration for generating alternating-current power having a predetermined period.

  An inverter device according to another aspect of the present invention is an inverter device that generates alternating current with a predetermined cycle, and includes an inverter circuit including a plurality of bridge circuits each including an upper arm switching element and a lower arm switching element, and the switching element. Control means for controlling. One of the upper arm switching element and the lower arm switching element in each bridge circuit has an on voltage lower than the other on voltage. In addition, the control means performs high-frequency switching that alternately turns on the upper arm switching element and the lower arm switching element of at least one bridge circuit for each cycle, and performs upper arm switching of at least another bridge circuit. Control is performed to keep the element and the lower arm switching element in different states.

  In this case, the alternating current is a three-phase alternating current, three bridge circuits are provided, and the control means alternately turns on the upper and lower arm switching elements of the two bridge circuits for each period. Two-phase modulation control may be performed in which high-frequency switching is performed and the upper arm switching element and the lower arm switching element of the remaining one bridge circuit are held in different states.

  According to the present invention, since the downtime of the upper and lower switching elements constituting the bridge circuit can be shortened, the odd-order harmonics are reduced, and distortion of the output current or output voltage is improved while suppressing loss.

  FIG. 1 is a configuration diagram of an inverter device according to an embodiment of the present invention. Note that the basic configuration of the inverter device 1 of the embodiment is the same as that of the general inverter device shown in FIG. 5, and the DC power output from the input power supply 110 is converted to AC at a predetermined frequency (for example, 50/60 Hz). It is converted into electric power and supplied to the load 130. Here, the inverter device 1 is assumed to be a current control type inverter device for controlling the output current.

  The inverter circuit 10 includes a bridge circuit (first bridge circuit) 11 and a bridge circuit (second bridge circuit) 12 to which an input voltage Vin is applied. The bridge circuit 11 includes an upper arm switch (first upper arm switching element) Q1 and a lower arm switch (first lower arm switching element) Q2 connected in series with each other. The bridge circuit 12 includes an upper arm switch (second upper arm switching element) Q3 and a lower arm switch (second lower arm switching element) Q4 connected in series with each other. In addition, IGBT is used for each switch Q1-Q4, the collector terminal of upper arm switch Q1 is connected to the positive voltage terminal of input power supply 110, and the emitter terminal of upper arm switch Q1 is connected to the collector terminal of lower arm switch Q2. The emitter terminal of the lower arm switch Q2 is connected to the negative voltage terminal of the input power supply 110. Similarly, the collector terminal of the upper arm switch Q3 is connected to the positive voltage terminal of the input power supply 110, the emitter terminal of the upper arm switch Q3 is connected to the collector terminal of the lower arm switch Q4, and the emitter terminal of the lower arm switch Q4 is input. The negative voltage terminal of the power supply 110 is connected. Further, diodes D1 to D4 are connected in antiparallel to the switches Q1 to Q4, respectively.

  A MOSFET can be used for each switching element. In this case, since the parasitic diode is built in the MOSFET, the parasitic diode can be used instead of the diodes D1 to D4. In the case of MOSFET, the drain terminal and the source terminal correspond to the collector terminal and emitter terminal of the IGBT, respectively.

  The upper arm switches Q1 and Q3 are switching elements that can perform high-frequency switching. Here, “high frequency switching is possible” means that the voltage fall time between the collector and the emitter at the turn-on and the collector-emitter at the turn-off so that it can follow a PWM signal of about several kHz to several tens of kHz described later. This means that the rise time of the element is sufficiently short or the input capacitance of the element is small. On the other hand, the lower arm switches Q2 and Q4 are switching elements each having a low on-voltage (or low on-resistance). Here, it is desirable that the ON voltages of the lower arm switches Q2 and Q4 are designed to be as low as possible within a range in which a necessary breakdown voltage can be secured in order to reduce the loss of the inverter circuit 10.

  Incidentally, in general, the switching loss and the steady loss of a switching element such as a transistor are in a trade-off relationship with each other as shown in FIG. Here, the switching loss is approximately proportional to the switching speed of the switching element, and the steady loss is approximately proportional to the ON voltage of the switching element. Therefore, the switching speed of the switching element and the ON voltage are in a trade-off relationship with each other. That is, in the inverter device 1, elements having a faster switching speed than the lower arm switches Q2 and Q4 are used as the upper arm switches Q1 and Q3, and the upper arm switches Q1 and Q4 are used as the upper arm switches Q1 and Q4. An element having an on-voltage lower than Q3 is used.

  The control circuit (control means) 20 generates a control signal for controlling the switches Q1 to Q4 based on an error between the command value of the current to be supplied to the load and the output current of the inverter circuit 10. Here, the current to be supplied to the load may be, for example, a current required by the load or a predetermined current. The output current of the inverter circuit 10 is detected using the shunt resistor Rs. Further, the control signal is a gate signal given to the gates of the switches Q1 to Q4. The control circuit 20 includes, for example, a microcomputer that executes a program described in advance and a hardware circuit that generates a control signal from the output of the microcomputer.

  FIG. 3 is a timing chart illustrating the operation of the inverter device 1 according to the embodiment. Here, the output voltage of the inverter device 1 and the gate signals of the switches Q1 to Q4 are drawn. Each of the switches Q1 to Q4 is controlled to be on when the corresponding gate signal is at the H level, and is controlled to be off when the corresponding gate signal is at the L level. In addition, the first half and the second half of each cycle of the AC output of the inverter device 1 will be referred to as “first period” and “second period”, respectively.

  In the first period, the control circuit 20 executes the following control (first control). That is, the upper arm switch Q1 and the lower arm switch Q2 constituting the bridge circuit 11 are high-frequency switched by a PWM signal for generating an output voltage having a sine curve characteristic. At this time, the upper arm switch Q1 and the lower arm switch Q2 are alternately controlled to be in an ON state so as to be reversed with respect to each other. On the other hand, the upper arm switch Q3 and the lower arm switch Q4 constituting the bridge circuit 12 are held in different states so that the polarity of the output voltage (or output current) becomes “positive”. In this example, the upper arm switch Q3 is held in the off state, and the lower arm switch Q4 is held in the on state.

  The current flow during this period is as follows. That is, when the upper arm switch Q1 and the lower arm switch Q2 are “on” and “off”, respectively, the current output from the input power supply 110 causes the upper arm switch Q1, the coil L1, the load 130, and the lower arm switch Q4 to To the input power supply 110. Further, when the upper arm switch Q1 and the lower arm switch Q2 are “off” and “on”, respectively, the flow recirculates through the path of the load 130 → the lower arm switch Q4 → the diode D2 → the coil L1 → the load 130.

  On the other hand, in the second period, the control circuit 20 executes the following control (second control). That is, the upper arm switch Q3 and the lower arm switch Q4 constituting the bridge circuit 12 are high-frequency switched by a PWM signal for generating an output voltage (or output current) having a sine curve characteristic. At this time, the upper arm switch Q3 and the lower arm switch Q4 are alternately controlled to be in an ON state so as to be inverted. On the other hand, the upper arm switch Q1 and the lower arm switch Q2 constituting the bridge circuit 11 are held in different states so that the polarity of the output voltage becomes “negative”. In this example, the upper arm switch Q1 is held in the off state, and the lower arm switch Q2 is held in the on state.

  The current flow during this period is as follows. That is, when the upper arm switch Q3 and the lower arm switch Q4 are “on” and “off”, respectively, the current output from the input power supply 110 causes the upper arm switch Q3, the load 130, the coil L1, and the lower arm switch Q2 to To the input power supply 110. Further, when the upper arm switch Q3 and the lower arm switch Q4 are “off” and “on”, respectively, the refrigerant flows through a path of load 130 → coil L1 → lower arm switch Q2 → diode D4 → load 130.

  Next, the inverter device 1 of the embodiment and the inverter device described in Patent Document 1 are compared. In the inverter device described in Patent Document 1, the polarity of the output voltage is switched using switches Q3 and Q4 shown in FIG. Therefore, in order to prevent the switches Q3 and Q4 from being turned on simultaneously when switching the polarity of the output voltage, as shown in FIG. 4A, the sum of the turn-off time of the switch Q3 and the turn-on time of the switch Q4 (or It is necessary to provide a rest period longer than the period Td1 corresponding to the sum of the turn-on time of the switch Q3 and the turn-off time of the switch Q4. However, the switches Q3 and Q4 are both switching elements having a low on-voltage. A switching element with a low on-voltage inevitably has a long turn-on time and turn-off time. Therefore, in the inverter device described in Patent Document 1, the pause time becomes longer in the vicinity of the timing at which the polarity of the output voltage of the inverter device is switched (that is, in the vicinity of the output zero-cross point). As a result, the odd-order harmonics become large and the distortion of the output voltage deteriorates.

  On the other hand, in the inverter device 1 according to the embodiment, as described above, the bridge circuit 11 and the bridge circuit 12 are switching elements (upper arm switches Q1, Q3) capable of high-frequency switching and switching with low on-voltage, respectively. It consists of elements (lower arm switches Q2, Q4). Therefore, as shown in FIG. 4B, the turn-on time / turn-off time of the switching elements (upper arm switches Q1, Q3) capable of high-frequency switching and the switching elements (lower arm switches Q2, Q4) having a low on-voltage. It is only necessary to provide a period corresponding to the sum of the turn-off time / turn-on time, i.e., a rest period longer than the period Td2. Accordingly, since this period Td2 is shorter than the period Td1 of the inverter device described in Patent Document 1, it is possible to shorten the pause period. As a result, odd harmonics are suppressed particularly near the timing at which the polarity of the output current or output voltage of the inverter device 1 is switched (that is, near the output zero-cross point), and distortion of the output current or output voltage is improved. The

  In the inverter device 1 of the embodiment, as described with reference to FIG. 3, the upper arm switch Q3 and the lower arm switch Q4 are not substantially switched in the first period in each cycle of the AC output, In the second period, the upper arm switch Q1 and the lower arm switch Q2 are not substantially switched. That is, the switching loss is substantially the same as the loss of the inverter device described in Patent Document 1 in which the switching loss of the switches Q3 and Q4 does not occur over the entire period.

  As described above, the inverter device 1 according to the embodiment has substantially the same loss as the inverter device described in Patent Document 1, but can suppress distortion of the output current or the output voltage.

In addition, the inverter apparatus of this invention is not limited to the above-mentioned embodiment, The following aspect is also included.
(1) A switching element having a low on-voltage may be used as each upper arm switch, and a switching element capable of high-frequency switching may be used as each lower arm switch.

  (2) A voltage control type inverter device that controls the output while monitoring the output voltage may be used. In this case, the control circuit 20 generates a control signal for controlling the switches Q1 to Q4 based on an error between the command value of the voltage to be supplied to the load and the output voltage of the inverter circuit 10.

  (3) The number of phases of the output of the inverter is arbitrary, and can be applied to a three-phase or multiphase inverter. For example, in the case of a three-phase inverter, the bridge circuit corresponding to two of the three phases performs high-frequency switching, and the bridge circuit corresponding to the remaining one phase performs two-phase modulation control that maintains the upper and lower arm switches in different states. That's fine.

  (4) A converter circuit (insulated DC / DC converter, step-down converter, step-up converter, etc.) for controlling the voltage may be provided between the input power supply 110 and the inverter circuit 10.

It is a block diagram of the inverter apparatus which concerns on embodiment of this invention. It is a figure which shows the characteristic of a switching element. It is a timing chart explaining operation | movement of the inverter apparatus of embodiment. It is a figure which shows the structure of the inverter apparatus of embodiment with respect to a prior art. It is a block diagram of a general inverter apparatus. It is a figure explaining operation | movement of the inverter apparatus of patent document 1. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Inverter apparatus 10 Inverter circuit 11, 12 Bridge circuit Q1, Q3 Upper arm switch Q2, Q4 Lower arm switch 20 Control circuit 110 Input power supply 120 Filter 130 Load

Claims (7)

An inverter device that generates alternating current with a predetermined cycle,
A first bridge circuit composed of a first upper arm switching element and a first lower arm switching element, and a second bridge circuit composed of a second upper arm switching element and a second lower arm switching element An inverter circuit comprising:
Control means for controlling each of the switching elements,
The on-voltages of the first and second lower arm switching elements are lower than the on-voltages of the first and second upper arm switching elements, respectively.
The control means performs high-frequency switching for alternately turning on the first upper arm switching element and the first lower arm switching element for each cycle, and the second upper arm switching element and the first upper arm switching element. First control for holding the two lower arm switching elements in different states, holding the first upper arm switching element and the first lower arm switching element in different states and switching the second upper arm switching element An inverter device, wherein second control is performed to perform high-frequency switching that alternately turns on the element and the second lower arm switching element. An inverter device that generates alternating current with a predetermined cycle,
A first bridge circuit composed of a first upper arm switching element and a first lower arm switching element, and a second bridge circuit composed of a second upper arm switching element and a second lower arm switching element An inverter circuit comprising:
Control means for controlling each of the switching elements,
The on-voltages of the first and second lower arm switching elements are higher than the on-voltages of the first and second upper arm switching elements, respectively.
The control means performs high-frequency switching for alternately turning on the first upper arm switching element and the first lower arm switching element for each cycle, and the second upper arm switching element and the first upper arm switching element. First control for holding the two lower arm switching elements in different states, holding the first upper arm switching element and the first lower arm switching element in different states and switching the second upper arm switching element An inverter device, wherein second control is performed to perform high-frequency switching that alternately turns on the element and the second lower arm switching element. The said control means produces | generates the PWM control signal for the said high frequency switching based on the difference | error of the electric current which should be supplied to load, and the output current of the said inverter circuit. Inverter device. The said control means produces | generates the PWM control signal for the said high frequency switching based on the difference | error of the voltage which should be applied to load, and the output voltage of the said inverter circuit. Inverter device. The execution times of the first and second controls are each half of the predetermined period,
The control means performs the first control in the first control so that the direction of the current or voltage flowing in the load in the first control is opposite to the direction of the current or voltage flowing in the load in the second control. 2 upper arm switching elements and the second lower arm switching element are controlled, and the first upper arm switching element and the first lower arm switching element are controlled in the second control. The inverter device according to claim 1 or 2. An inverter device that generates alternating current with a predetermined cycle,
An inverter circuit comprising a plurality of bridge circuits composed of an upper arm switching element and a lower arm switching element;
Control means for controlling the switching element,
The on-voltage of one of the upper arm switching element and the lower arm switching element in each bridge circuit is lower than the other on-voltage,
The control means performs high-frequency switching for alternately turning on the upper arm switching element and the lower arm switching element of at least one bridge circuit for each period, and at least another upper arm switching element of the bridge circuit and An inverter device that performs control to hold the lower arm switching elements in different states. The alternating current is a three-phase alternating current,
There are three bridge circuits,
The control means performs high-frequency switching for alternately turning on the upper arm switching element and the lower arm switching element of the two bridge circuits for each cycle, and the upper arm switching element and the lower arm of the remaining one bridge circuit. The inverter device according to claim 6, wherein two-phase modulation control is performed to hold the switching elements in different states.

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