JP2006157780A - Amplifier circuit apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an amplifier circuit apparatus the gain of which is not varied due to variations in MOS transistors. <P>SOLUTION: Even number stages (k stages) of amplifier circuits 10, 20, ..., 40 each employing the MOS transistors are connected in series, an output terminal of the amplifier circuit 40 of the final stage is connected to an output terminal of the first stage amplifier circuit 10, an input terminal of the first stage amplifier circuit 10 is used for an input terminal 2 of the amplifier circuit apparatus 1, and an input terminal of the final stage amplifier circuit 40 (an output terminal of the amplifier circuit 30 at a stage just before the final stage) is used for an output terminal 3 of the amplifier circuit apparatus 1. In the case of k=2n=2, the input terminal of the final stage (second stage) amplifier circuit 40 becomes the output terminal of the first stage amplifier circuit 10. Let a voltage current conversion coefficient of the first stage amplifier circuit 10 be gm1 and a voltage current conversion coefficient of the final stage amplifier circuit 40 be gmk, then the whole gain G of the amplifier circuit apparatus 1 is determined only by a ratio of the grn1 to the grnk as expressed in an equation of G=-(gm1/gmk). <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an amplifier circuit device using a MOS (Metal Oxide Semiconductor) transistor.

  As an amplifier circuit for amplifying high-frequency signals in receivers and processing analog signals in various devices, it is possible to obtain high gain with a low power consumption, simple configuration, and digital / analog mixed loading. An amplifier circuit using a MOS transistor by a CMOS (Complementary MOS) process is preferable because of easy chip formation.

  In the conventional CMOS amplifier circuit, as shown in FIG. 9, an input signal voltage Vin is converted into an output signal current i by a voltage-current converter 101 using a MOS transistor, as shown in FIG. The output signal voltage Vout is extracted by R. The voltage source 103 is for output bias.

  In the configuration of FIG. 9, when the voltage-current conversion coefficient of the voltage-current converter 101 is gm, the output signal current i is expressed by the equation (21) in FIG. 10 and the gain G of the amplifier circuit is expressed by the equation (23) in FIG.

  Therefore, the gain G can be controlled by controlling the voltage-current conversion coefficient gm, and a variable gain amplifier circuit can be realized.

  Furthermore, as a variable gain amplifier circuit using MOS transistors, Patent Document 1 (Japanese Patent Laid-Open No. 2003-168938) discloses an amplifier circuit using bipolar transistors and MOS transistors as shown in FIG. .

  In the amplifier circuit of FIG. 11, the collectors of NPN transistors 201 and 202 are connected to a power supply 219 via resistors 203 and 204, respectively, and the emitters of NPN transistors 201 and 202 are grounded via resistors 205 and 206, respectively. The drain and source of the NMOS transistor 207 are connected between the emitters of the NPN transistors 201 and 202, and the control voltage Vagc from the control voltage source 208 is supplied to the gate of the NMOS transistor 207 via the resistor 209, and the input terminal 211 The differential input signals Vin (+) and Vin (−) are supplied from the NPN transistors 201 and 212 to the bases of the NPN transistors 201 and 202, and the differential outputs are output from the collectors of the NPN transistors 201 and 202 to the output terminals 213 and 214. No. Vout (-) and Vout (+) is taken out.

  In this amplifier circuit, when the mutual conductance of the NMOS transistor 207 is gm0, the resistance values of the resistors 203 and 204 are R1, the resistance value of the resistor 205 is R2, the resistance value of the resistor 206 is R3, and the resistance value of the resistor 209 is R5. The gain G is represented by the equation (31) in FIG.

  Therefore, the gain G can be changed by controlling the mutual conductance gm0 of the NMOS transistor 207 by the control voltage Vagc.

The prior art documents listed above are as follows.
JP 2003-168938 A

  As described above, in the conventional amplifier circuit shown in FIG. 9 or FIG. 11, the gain G is the voltage current generated by the MOS transistor as represented by the equation (23) in FIG. 10 or the equation (31) in FIG. It becomes a function of the conversion coefficient gm or the mutual conductance gm0 of the MOS transistor, and the gain G can be controlled by gm or gm0.

  However, the voltage-current conversion coefficient gm and the mutual conductance gm0 vary depending on the variation of the MOS transistor, and in the conventional amplifier circuit, the gain G has a resistance component (correlation unrelated to the variation of the gm or gm0 and the MOS transistor) ( Therefore, the variation of the MOS transistor, that is, the variation of gm or gm0 becomes the variation of the gain G as it is, and the gain G varies for each amplifier circuit.

  In view of this, the present invention is designed so that the gain does not vary due to variations in MOS transistors.

  In the amplifier circuit device according to the present invention, even-numbered amplifier circuits each using MOS transistors are connected in series, and the output terminal of the final-stage amplifier circuit is connected to the output terminal of the first-stage amplifier circuit. A signal output is taken out from the input terminal of the amplifier circuit.

  In the amplifier circuit device of the present invention having the above configuration, when the voltage-current conversion coefficient of the first-stage amplifier circuit is gm1, and the voltage-current conversion coefficient of the last-stage amplifier circuit is gmk, the gain G of the entire amplifier circuit apparatus is , G = − (gm1 / gmk), which is determined only by the ratio of gm1 and gmk.

  Therefore, the variation in the MOS transistors constituting the first-stage amplifier circuit and the variation in the MOS transistors constituting the final-stage amplifier circuit are canceled each other, and the gain G becomes uniform.

  In addition, fluctuations in the voltage-current conversion coefficients gm1 and gmk due to temperature changes and the like are canceled out, so that the gain G does not fluctuate due to temperature changes and the like, and a stable operation can be obtained.

  As described above, in the amplifier circuit device according to the present invention, the gain does not vary due to variations in MOS transistors, and the gain does not vary due to a temperature change or the like.

[1. Basic Configuration of Amplifier Circuit Device: FIGS. 1 and 2]
FIG. 1 shows a basic configuration of an amplifier circuit device according to the present invention.

  In the amplifier circuit device 1 of the present invention, even-numbered (k-stage) amplifier circuits 10, 20... 40 each using MOS transistors are connected in series, and the output terminal of the final-stage amplifier circuit 40 is connected to the first stage. The input terminal of the first stage amplifier circuit 10 is the input terminal 2 of the amplifier circuit apparatus 1 and the input terminal of the final stage amplifier circuit 40 (the stage immediately before the last stage) The output terminal 3 of the amplifier circuit 30 is defined as the output terminal 3 of the amplifier circuit device 1.

  When k = 2n, n ≧ 1 (n = 1, 2, 3...) and k = 2n = 2, there is no amplifier circuit 20 or 30 shown in the figure, and the final stage (second stage) amplification is performed. The input end of the circuit 40 is the output end of the first stage amplifier circuit 10.

  In this amplifier circuit device 1, the input signal voltage of the amplifier circuit device 1 is Vin, the voltage-current conversion coefficient of the first-stage amplifier circuit 10 is gm1, the output signal current of the amplifier circuit 10 is I1, and the amplifier circuit 40 of the last stage is Assuming that the voltage-current conversion coefficient is gmk, the output signal current of the amplifier circuit 40 is Ik, and the output signal voltage of the amplifier circuit device 1 is Vout, the output signal currents I1 and Ik are respectively expressed by the equations (1) and (2) in FIG. 2), and the absolute values are the same and the directions are opposite to each other, as shown in the equation (3) in FIG. 2, the equation (4) in FIG. Is determined only by the ratio between gm1 and gmk, as represented by equation (5) in FIG.

  Therefore, the variation of the MOS transistors constituting the first stage amplifier circuit 10 and the variation of the MOS transistors constituting the final stage amplifier circuit 40 are canceled each other, and the gain G becomes uniform.

  In addition, fluctuations in the voltage-current conversion coefficients gm1 and gmk due to temperature changes and the like are canceled out, so that the gain G does not fluctuate due to temperature changes and the like, and a stable operation can be obtained. In addition, since a plurality of stages (even stages) of amplifier circuits are connected in series, the loop gain is increased and the distortion characteristics are improved.

  In the case of two stages, which is the minimum number of stages, Vout = −Vin when the bias is adjusted, and the amplifier circuit device 1 becomes an inverting amplifier circuit with a gain of 1.

  Further, with the configuration as shown in FIG. 1, at least the first stage amplifier circuit 10 and the last stage amplifier circuit 40 are variable gain amplifier circuits, so that the gain G of the entire amplifier circuit apparatus 1 is increased. A variable gain amplifier circuit device that can be changed can be obtained.

[2. Example of canceling DC offset: FIGS. 3 and 4]
FIG. 3 shows an example in which four stages of amplifier circuits 10, 20, 30 and 40 are connected in series with k = 2n = 4. Each of the amplifier circuits 10, 20, 30 and 40 is an inverting amplifier circuit and a voltage-current converter circuit.

  The output terminal of the final stage (fourth stage) amplifier circuit 40 is connected to the output terminal of the first stage amplifier circuit 10, and the input terminal of the first stage amplifier circuit 10 is connected to the input terminal 2 of the amplifier circuit device 1. The input terminal of the final stage (fourth stage) amplifier circuit 40 (the output terminal of the third stage amplifier circuit 30) is the output terminal 3 of the amplifier circuit device 1.

  Therefore, when the voltage-current conversion coefficient of the first stage amplifier circuit 10 is gm1, and the voltage-current conversion coefficient of the final stage (fourth stage) amplifier circuit 40 is gmk, the gain G of the amplifier circuit device 1 is the same as described above. Is determined only by the ratio between gm1 and gmk, as represented by equation (5) in FIG.

  In this case, the reference bias voltage Vref is applied from the external voltage source 4 to the voltage-current conversion circuits of the amplifier circuits 10, 20, 30 and 40 in each stage. However, in practice, a DC offset is generated with respect to the optimum bias voltage. Therefore, the DC offset detection cancel circuit that detects and cancels the DC offset for the amplifier circuits 10, 20, 30, and 40 of each stage. 50, 60, 70 and 80 are connected. This facilitates connection to the next stage amplifier circuit.

  FIG. 4 shows a specific example of each stage of the amplifier circuit (voltage-current converter circuit) and DC offset detection cancel circuit in the case of the configuration as shown in FIG.

  In this example, the amplifier circuit 10 includes a source / drain of the PMOS transistor 11, a drain / source of the NMOS transistor 12, and a drain / source of the NMOS transistor 13 in series between the power supply 5 from which the power supply voltage Vdd is obtained and the ground. Connected to.

  The PMOS transistor 11 and the NMOS transistor 12 form a CMOS inverter. The gates of the PMOS transistor 11 and the NMOS transistor 12 are connected to the input terminal of the amplifier circuit 10, that is, the input terminal 2 of the amplifier circuit device 1, and the drains thereof are connected. Thus, the output terminal of the amplifier circuit 10 is used. The correction voltage Vn is supplied from the DC offset detection cancel circuit 50 to the gate of the NMOS transistor 13.

  In the DC offset detection cancel circuit 50, the source / drain of the PMOS transistor 51, the drain / source of the NMOS transistor 52, and the drain / source of the NMOS transistor 53 are connected in series between the power supply 5 and the ground, like the amplifier circuit 10. Connected to.

  The PMOS transistor 51 and the NMOS transistor 52 form a CMOS inverter. The gates of the PMOS transistor 51 and the NMOS transistor 52 are connected, the reference bias voltage Vg is supplied to the connection point, the drains are connected, and the connection point is obtained. Voltage Vof is supplied to the non-inverting input terminal of the operational amplifier 54, the reference bias voltage Vg is supplied to the inverting input terminal of the operational amplifier 54, and the output voltage Vn of the operational amplifier 54 is supplied to the gate of the NMOS transistor 53. , And the gate of the NMOS transistor 13 of the amplifier circuit 10.

  In this configuration, the CMOS inverter composed of the PMOS transistor 11 and the NMOS transistor 12, the CMOS inverter composed of the PMOS transistor 11 and the NMOS transistor 12, and the PMOS transistor 51 and the NMOS transistor by the feedback loop composed of the CMOS inverter composed of the PMOS transistor 51 and NMOS transistor 52, the operational amplifier 54, and the NMOS transistors 53 and 13. A DC offset of the CMOS inverter composed of the transistor 52 is detected and canceled.

  Specifically, when the output voltage Vof of the CMOS inverter of the DC offset detection cancel circuit 50 becomes higher than the reference bias voltage Vg, the output voltage Vn of the operational amplifier 54 increases, the drain resistance of the NMOS transistor 53 decreases, and the output voltage When Vof becomes low and the output voltage Vof becomes lower than the reference bias voltage Vg, the output voltage Vn of the operational amplifier 54 becomes low, the drain resistance of the NMOS transistor 53 becomes large, and the output voltage Vof becomes high.

  Accordingly, the output voltage Vn of the operational amplifier 54 is converged to a voltage value that makes the output voltage Vof of the CMOS inverter of the DC offset detection cancel circuit 50 equal to the reference bias voltage Vg, and thereby the amplifier circuit 10 and the DC offset detection. The DC offset of the CMOS inverter of the cancel circuit 50 is canceled, and for example, the output DC voltage of each CMOS inverter is set to Vdd / 2.

  Although omitted in FIG. 4, the second stage amplifier circuit 20 and the DC offset detection cancel circuit 60, the third stage amplifier circuit 30 and the DC offset detection cancel circuit 70, and the final stage (fourth stage) amplifier circuit 40 and The DC offset detection cancel circuit 80 is similarly configured, and the DC offset is similarly canceled.

  In the example of FIG. 4, NMOS transistors 13 and 53 are connected as correction MOS transistors to the ground side of the CMOS inverter, that is, the sources of the NMOS transistors 12 and 52, respectively, in the amplification circuit and the DC offset detection cancel circuit of each stage. In this case, a PMOS transistor may be connected as a correction MOS transistor to the power source side of the CMOS inverter, that is, to the sources of the PMOS transistors 11 and 51, respectively.

[3. Example in which the amplifier circuit at each stage is a composite CMOS circuit .... FIGS. 5 to 8]
As the amplifier circuit device, it is not necessary to apply a reference bias voltage from the outside to the amplifier circuits in each stage, and no DC offset is generated, so that a DC offset detection cancel circuit can be omitted.

  An example is shown in FIG. In this example, the amplifier circuits 10, 20, 30 and 40 are each composed of a composite CMOS circuit (complementary composite MOS circuit).

  Specifically, the first-stage amplifier circuit 10 includes an NMOS transistor 14, a PMOS transistor 15, an NMOS transistor 16, and a PMOS transistor 17, and all the MOS transistors have a back gate connected to a source and an NMOS transistor. 14 and PMOS transistor 17 connect the gate and drain, respectively.

  The source of the NMOS transistor 14 and the source of the PMOS transistor 15 are connected, and the NMOS transistor 14 and the PMOS transistor 15 constitute a composite PMOS transistor that operates as one PMOS transistor. The source of the PMOS transistor 17 and the NMOS transistor 16 The PMOS transistor 17 and the NMOS transistor 16 constitute a composite NMOS transistor that operates as one NMOS transistor.

  At this time, the gate of the PMOS transistor 15 forms the gate of the composite PMOS transistor, the drain of the PMOS transistor 15 forms the drain of the composite PMOS transistor, and the gate and drain of the NMOS transistor 14 forms the source of the composite PMOS transistor. The gate of the NMOS transistor 16 forms the gate of the composite NMOS transistor, the drain of the NMOS transistor 16 forms the drain of the composite NMOS transistor, and the gate and drain of the PMOS transistor 17 forms the source of the composite NMOS transistor.

  The source of the composite PMOS transistor (gate and drain of the NMOS transistor 14) is connected to the power supply 5, the source of the composite NMOS transistor (gate and drain of the PMOS transistor 17) is grounded, and the gate of the composite PMOS transistor (PMOS transistor 15). And the gate of the composite NMOS transistor (gate of the NMOS transistor 16) are connected to the input terminal of the amplifier circuit 10, and the drain of the composite PMOS transistor (drain of the PMOS transistor 15) and the drain of the composite NMOS transistor (NMOS transistor 16). To the output terminal of the amplifier circuit 10.

  For each MOS transistor, the amplifier circuits 20, 30 and 40 are configured in the same manner as indicated by reference numerals of the 20th, 30th and 40th series, respectively, instead of the 10th reference numeral.

  In the example of FIG. 5, the input / output bias of each stage of the amplifier circuits 10, 20, 30 and 40 is always determined to be Vdd / 2 which is ½ of the power supply voltage Vdd.

  For this reason, the output voltages of the respective amplifier circuits are equalized, the connection to the next stage is facilitated, the reference bias voltage does not need to be applied from the outside, and no DC offset is generated, so that no DC offset detection cancel circuit is required. . Therefore, the circuit configuration of the entire amplifier circuit device 1 is simplified, and low power consumption can be realized.

  As described above, even when the amplifier circuits 10, 20, 30 and 40 in each stage are constituted by composite CMOS circuits, at least the amplifier circuit 10 in the first stage and the amplifier circuit 40 in the final stage (fourth stage) are variable gain amplified. By using a circuit, the gain G of the entire amplifier circuit device 1 can be changed.

  An example is shown in FIG. In this example, in the first stage amplifier circuit 10, the source of the composite PMOS transistor (gate and drain of the NMOS transistor 14) is connected to the power supply 5 via the load 18a, and the source of the composite NMOS transistor (PMOS transistor 17). Of the composite PMOS transistor and the source of the composite PMOS transistor (gate and drain of the NMOS transistor 14) in parallel with the composite CMOS circuit constituted by the composite PMOS transistor and the composite NMOS transistor. A variable current source 19 is connected between the source of the NMOS transistor (the gate and drain of the PMOS transistor 17).

  Also in the final stage (fourth stage) amplifier circuit 40, the source of the composite PMOS transistor (gate and drain of the NMOS transistor 44) is connected to the power source 5 via the load 48a, and the source of the composite NMOS transistor (PMOS transistor 47). Of the composite PMOS transistor and the source (gate and drain of the NMOS transistor 44) in parallel with the composite CMOS circuit constituted by the composite PMOS transistor and the composite NMOS transistor. A variable current source 49 is connected between the source of the NMOS transistor (the gate and drain of the PMOS transistor 47).

  As shown in FIG. 7, each of the variable current sources 19 and 49 connects the drain 91D of the NMOS transistor 91 to the source of the composite PMOS transistor (the gate and drain of the NMOS transistor 14 or 44), and the source 91S of the NMOS transistor 91. Is connected to the source of the composite NMOS transistor (the gate and drain of the PMOS transistor 17 or 47), and the variable voltage source 92 for gain control is connected to the gate of the NMOS transistor 91. The NMOS transistor 91 also has a back gate connected to the source.

  In the example of FIGS. 6 and 7, the loads 18a and 18b of the amplifier circuit 10 are resistors having the same resistance value R1, and the current flowing in the composite CMOS circuit constituted by the composite PMOS transistor and the composite NMOS transistor is Id1, the variable current The current of the source 19 is Ic1, the current flowing through the loads 18a and 18b is (Id1 + Ic1), the source voltage of the composite PMOS transistor (drain voltage of the NMOS transistor 14) is Va1, and the source voltage of the composite NMOS transistor (drain voltage of the PMOS transistor 17) ) Is Vb1, and the voltage of the variable voltage source 92 constituting the variable current source 19 is Vc1, the voltages Va1 and Vb1 are expressed by the equations (11) and (12) of FIG. As shown in Equation (13), the voltage Va1 and the voltage V 1 sums Vdd, and the output bias Vg1 of the amplifier circuit 10 is assumed to be represented by the equation in Figure 8 (14).

  Similarly, the loads 48a and 48b of the amplifier circuit 40 are resistors having the same resistance value Rk, the current flowing through the composite CMOS circuit constituted by the composite PMOS transistor and the composite NMOS transistor is Idk, and the current of the variable current source 49 is Ick. The current flowing through the loads 48a and 48b is (Idk + Ick), the source voltage of the composite PMOS transistor (drain voltage of the NMOS transistor 44) is Vak, the source voltage of the composite NMOS transistor (drain voltage of the PMOS transistor 47) is Vbk, and is variable. When the voltage of the variable voltage source 92 constituting the current source 49 is Vck, the input / output bias Vgk of the amplifier circuit 40 is represented by the equation (15) in FIG.

  That is, in the examples of FIGS. 6 and 7, by controlling the voltage Vc1 to control the current Ic1 of the variable current source 19, the current (Id1 + Ic1) flowing through the loads 18a and 18b changes, and the voltages Va1 and Vb1 change. As a result, the equivalent gate-source voltage of the composite PMOS transistor and composite NMOS transistor constituting the amplifier circuit 10 changes, and the current Id1 flowing through the composite PMOS transistor and composite NMOS transistor changes, and the gain of the amplifier circuit 10 changes. Similarly, by controlling the voltage Vc2 to control the current Ick of the variable current source 49, the current (Idk + Ick) flowing through the loads 48a and 48b changes, and the voltages Vak and Vbk change. A composite PMOS transistor constituting the amplifier circuit 40 and The equivalent gate-source voltage of the combined NMOS transistor changes, and the current Idk flowing through the composite PMOS transistor and the composite NMOS transistor changes, so that the gain of the amplifier circuit 40 can be changed and is independent of the control of these gains. In addition, the input / output biases of the amplifier circuits 10, 20, 30 and 40 can always be held at a constant value Vdd / 2.

  In the example of FIG. 6 as well, the input / output bias of each stage of the amplifier circuits 10, 20, 30 and 40 is always determined to be Vdd / 2 regardless of the control of the gain G of the amplifier circuit device 1 in this way. The output voltages of the amplifier circuits are equalized, the connection to the next stage is facilitated, the reference bias voltage does not need to be externally applied, and no DC offset is generated, so that no DC offset detection cancel circuit is required.

  Note that the variable current sources 19 and 49 can also be configured by PMOS transistors and variable voltage sources, respectively.

It is a figure which shows the basic composition of the amplifier circuit apparatus of this invention. It is a figure which shows the type | formula used for description of the amplifier circuit apparatus of FIG. It is a figure which shows the example which connects a DC offset detection cancellation circuit to the amplifier circuit of each stage. It is a figure which shows the specific example of the amplifier circuit and DC offset detection cancellation circuit of the amplifier circuit apparatus of FIG. It is a figure which shows the example in case the amplifier circuit of each stage is used as a composite CMOS circuit. FIG. 6 is a diagram illustrating an example in which the amplifier circuit device of FIG. 5 is a variable gain amplifier circuit device. It is a figure which shows an example of the variable current source in the amplifier circuit apparatus of FIG. It is a figure which shows the type | formula used for description of the amplifier circuit apparatus of FIG. It is a figure which shows the general structure of the conventional amplifier circuit using a MOS transistor. FIG. 10 is a diagram illustrating an equation for explaining the amplifier circuit of FIG. 9. It is a figure which shows the amplifier circuit shown by patent document 1. FIG. It is a figure which shows the type | formula used for description of the amplifier circuit of FIG.

Explanation of symbols

  Since all the main parts are described in the figure, they are omitted here.

Claims (7)

  Even-numbered amplifier circuits each using MOS transistors are connected in series, the output terminal of the final-stage amplifier circuit is connected to the output terminal of the first-stage amplifier circuit, and the signal is output from the input terminal of the final-stage amplifier circuit Amplifying circuit device from which is taken out. The amplifier circuit device according to claim 1,
An amplifier circuit device characterized in that at least the first-stage and final-stage amplifier circuits are variable gain amplifier circuits. The amplifier circuit device according to claim 1,
An amplifier circuit device, wherein a DC offset detection cancel circuit for detecting and canceling the DC offset is connected to each stage of the amplifier circuit. The amplifier circuit device according to claim 3,
Each stage DC offset detection cancel circuit includes a CMOS inverter, a correction MOS transistor having a drain connected to the ground side or power supply side of the CMOS inverter, and an operational amplifier, and an input terminal of the CMOS inverter, and A reference bias voltage is supplied to the inverting input terminal of the operational amplifier, the output voltage of the CMOS inverter is supplied to the non-inverting input terminal of the operational amplifier, and the output voltage of the operational amplifier is connected to the correction MOS transistor. Is supplied to the gate,
Each stage amplification circuit has a CMOS inverter and a correction MOS transistor having a drain connected to the ground side or power supply side of the CMOS inverter, and the DC of the same stage is connected to the gate of the correction MOS transistor. The output voltage of the operational amplifier of the offset detection cancel circuit is supplied.
An amplifier circuit device characterized by that. The amplifier circuit device according to claim 1, wherein each stage of the amplifier circuit includes:
A first NMOS transistor and a PMOS transistor, and a second NMOS transistor and a PMOS transistor, each having a back gate connected to the source;
The first NMOS transistor and the PMOS transistor operate as one PMOS transistor by connecting the gate and drain of the first NMOS transistor and connecting the source of the first NMOS transistor and the source of the first PMOS transistor. A composite PMOS transistor
The second NMOS transistor and the PMOS transistor operate as one NMOS transistor by connecting the gate and drain of the second PMOS transistor and connecting the source of the second PMOS transistor and the source of the second NMOS transistor. A composite NMOS transistor,
The gate of the first PMOS transistor and the gate of the second NMOS transistor are connected to serve as an input terminal,
The drain of the first PMOS transistor and the drain of the second NMOS transistor are connected to form an output terminal.
An amplifier circuit device configured as a composite CMOS circuit. The amplifier circuit device according to claim 5, wherein
At least the first and last stage amplifier circuits are respectively
Between the drain and gate of the first NMOS transistor that forms the source of the composite PMOS transistor and a first potential point, and the drain and gate of the second PMOS transistor that forms the source of the composite NMOS transistor A load is connected between the gate and a second potential point lower than the first potential point, and a variable current source is connected in parallel with the composite CMOS circuit including the composite PMOS transistor and the composite NMOS transistor. A connected variable gain amplifier circuit;
An amplifier circuit device characterized by that. The amplifier circuit device according to claim 6, wherein
The variable current source includes a MOS transistor whose drain and source are connected in parallel with the composite CMOS circuit, and a variable voltage source that applies a control voltage to the gate of the MOS transistor.
An amplifier circuit device characterized by that.

Images