JP2006156914A - Method for manufacturing nitride semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a nitride semiconductor device with a planar structure which is capable of executing high-resistance element isolation. <P>SOLUTION: The manufacturing method is used for manufacturing a nitride semiconductor device composed of the Group III-V nitride semiconductor layer laminated on a substrate. A coating film including at least one of iron, carbon, and zinc or magnesium is formed on the surface of an element isolation region. After that, one of iron, carbon, and zinc or magnesium is dispersed in the nitride semiconductor layer as impurities by heat treatment. The element isolation region is formed with high insulation properties. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a nitride semiconductor device using a nitride semiconductor as an active layer, and more particularly to a method for manufacturing a nitride semiconductor device that can reduce the leakage current and perform planar element isolation.

  3A and 3B are a plan view (FIG. 3a) and a cross-sectional view of a nitride semiconductor device made of a conventional group III-V nitride semiconductor (FIG. FIG. 3c shows a cross-sectional view of the BB ′ plane). The nitride semiconductor device shown in FIG. 3 has a so-called HEMT structure, on a substrate 11 made of silicon carbide (SiC), a buffer layer 12 made of aluminum nitride (AlN), and a channel layer 13 made of gallium nitride (GaN). The channel layer 13 has a structure in which a spacer layer 14 made of non-doped aluminum gallium nitride (AlGaN), a carrier supply layer 15 made of n-type aluminum gallium nitride, and a Schottky layer 16 made of non-doped aluminum gallium nitride are sequentially laminated. In the vicinity of the heterojunction interface consisting of the spacer layer 14, a two-dimensional electron gas layer consisting of a potential well and having extremely high electron mobility is formed. In the nitride semiconductor device having such a structure, the carrier (two-dimensional electron gas) flowing between the source electrode 20a and the drain electrode 20b is controlled by controlling the voltage applied to the gate electrode 21 in Schottky contact with the Schottky layer 16. Is controlling.

  Such element isolation of the nitride semiconductor device is performed by removing a semiconductor layer in a region partitioning the nitride semiconductor device formation region by a dry etching method to form a recess 22 (FIGS. 3a and 3b). In such a structure, the gate electrode 21 crosses the level difference of the concave portion 22, and a lead portion such as a pad is formed on the bottom surface portion of the concave portion 22 (FIG. 3c). The element isolation method having the structure in which the concave portion 22 is formed in this way is called a mesa structure, and is a method conventionally used in the manufacturing process of this type of semiconductor device.

Further, instead of etching, for example, nitrogen ions are accelerated at 20 keV, 100 keV, and the dose amount is 1 × 10 ¹⁴ cm ⁻² , so that the sheet resistance is 1 × 10 ⁸ Ω / □. A method of isolating a planar structure by forming the element isolation region is reported (Non-Patent Document 1).
Nakayama et al., “High Voltage / High Output AlGaN / GaN Recessed Gate FET with Field Plate”, IEICE Technical Report, IEICE, January 12, 2004, Vol. 103, no. 558, p. 57-62

  In such conventional mesa structure element isolation, when the gate electrode is formed by the lift-off method, it is necessary to form a photoresist having a film thickness that is at least as large as the step of the recess 22 and to form a gate electrode having a short gate length. There was a problem that could not.

  Further, in the element isolation of the planar structure reported so far, it has been necessary to form an element isolation region having a large sheet resistance in order to further reduce the leakage current of the gate electrode.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a nitride semiconductor device that solves the above problems and has a planar structure and enables high-resistance element isolation, and a method for manufacturing the same.

  In order to achieve the above object, the invention according to claim 1 of the present application provides at least one group III element consisting of at least one of the group consisting of gallium, aluminum, boron and indium, and at least one of the group consisting of nitrogen, phosphorus and arsenic. In a method of manufacturing a nitride semiconductor device including a group III-V nitride semiconductor layer composed of a group V element containing nitrogen, the nitride semiconductor layer including the group III-V nitride semiconductor layer is formed on a substrate. And forming a coating film containing at least one of iron, carbon, zinc or magnesium as an impurity in a region defining the nitride semiconductor device formation region on the surface of the nitride semiconductor layer, and then performing a heat treatment. Performing a step of diffusing the impurity in the nitride semiconductor layer to form an element isolation region of the nitride semiconductor device; removing the coating film; and It is characterized in that a step of exposing a location formation region.

  The invention according to claim 2 of the present application is the method for manufacturing a nitride semiconductor device according to claim 1, wherein the nitride semiconductor device formation region is covered on the surface of the nitride semiconductor layer of the nitride semiconductor device formation region, And a step of patterning a mask material so as to expose a region defining the nitride semiconductor device forming region, and forming the coating film on the mask material and the exposed surface of the nitride semiconductor layer. To do.

  The invention according to claim 3 is the nitride semiconductor device manufacturing method according to claim 1 or 2, wherein an SOG film is used as the coating film.

According to the manufacturing method of the present invention, the element isolation region is formed by thermally diffusing from the coating film into the nitride semiconductor layer using at least one of iron, carbon, zinc, and magnesium as an impurity, thereby forming the element isolation region. Is 1 × 10 ⁹ Ω / □ or more, and the leakage current can be reduced as compared with the prior art. In particular, in a semiconductor device having a structure in which a gate electrode is formed in the element isolation region, leakage current from the gate electrode can be reduced.

  In addition, since the manufacturing method of the present invention includes only normal manufacturing processes such as mask film patterning, SOG film formation, and heat treatment according to a normal nitride semiconductor device manufacturing process, the controllability of the manufacturing process is improved. In addition, a nitride semiconductor device having excellent element isolation characteristics can be manufactured with a high yield.

  Hereinafter, the nitride semiconductor device of the present invention will be described in accordance with its manufacturing process, taking as an example a case where iron is mainly doped as an impurity.

  The present invention will be described in detail according to a manufacturing process, taking as an example a HEMT which is a nitride semiconductor device composed of a III-V group nitride semiconductor layer. FIG. 1 is a plan view (FIG. 1a) and a sectional view of a nitride semiconductor device formed according to the present invention (a sectional view taken along the line AA 'in FIG. 1a is shown in FIG. 1b, and a sectional view taken along the line BB' in FIG. 1a). The figure is shown in FIG. 1c). FIG. 2 shows a manufacturing process of the nitride semiconductor device of the present invention.

  First, as shown in FIG. 2A, on a substrate 11 made of silicon carbide (SiC), a buffer layer 12 made of aluminum nitride (AlN) having a thickness of about 200 nm, and a non-doped gallium nitride (GaN having a thickness of 2.5 μm). ), A spacer layer 14 made of undoped aluminum gallium nitride (AlGaN) having a thickness of 7 nm, a carrier supply layer 15 made of n-type aluminum gallium nitride having a thickness of 15 nm, and an undoped aluminum gallium nitride having a thickness of 3 nm. A semiconductor substrate having a structure in which the Schottky layers 16 are sequentially stacked is prepared. Here, the nitride semiconductor layer can be grown by an ordinary MOCVD (metal organic chemical vapor deposition) method or MBE (molecular beam epitaxial) method.

Next, the silicon oxide film 17 serving as an iron diffusion mask is patterned so as to cover the region where the nitride semiconductor device is to be formed. Next, an SOG (spin-on-glass) film 18 (coating film) to which an iron compound is added is formed on the surfaces of the Schottky layer 16 and the silicon oxide film 17. Specifically, an iron compound (Fe (NO ₃ ) · 9H ₂ O) with respect to 100 ml of an organic solvent containing a silanol compound (R _n Si (OH) _4-n ) (for example, OCDtype-1 manufactured by Tokyo Ohka Kogyo Co., Ltd.) A solution with 1 g added is prepared and spin-coated on the Schottky layer 16 and the silicon oxide film 17. This is fired to form the SOG film 18. Thereafter, heat treatment is performed to diffuse iron (Fe) added to the SOG film 18 to form a gallium nitride layer in which iron (Fe) is diffused, that is, an iron-doped layer 19. The iron-doped layer 19 exhibits high insulation (sheet resistance is 1 × 10 ⁹ Ω / □ or more), and the surface from which the SOG film 18 is removed is the same surface as the HEMT formation region (FIG. 2c).

  Next, the silicon oxide film 17 is removed, and a source electrode 20a and a drain electrode 20b made of a laminate of titanium (Ti) / aluminum (Al) or the like are formed on the exposed Schottky layer 16, and patterned at 800 ° C. for 30 seconds. After the ohmic contact is formed by the rapid heating process, a gate electrode 21 made of a nickel (Ni) / gold (Au) laminate or the like is patterned to form a Schottky contact with the Schottky layer 16 (FIG. 2d). ). Hereinafter, the HEMT can be formed by a normal manufacturing process.

  The nitride semiconductor device formed in this way has a planar structure with a highly insulating iron-doped layer 19 (FIG. 1c), and there is no concern about gate electrode breakage. Reliability is improved.

Further, the sheet resistance is 1 × 10 ⁹ Ω / □ or more, and an element isolation region having a sheet resistance 10 times or more larger than that of the conventionally proposed ion implantation method can be formed.

  In the present invention, the silicon oxide film 17 is used as a diffusion mask. However, the present invention is not limited to this as long as it becomes a diffusion mask and can be removed without diffusing iron in the nitride semiconductor device formation region. . Similarly, the SOG film 19 is used as the coating film, but it is limited to this as long as the film contains iron (Fe) as an impurity and can diffuse the iron into the nitride semiconductor layer by heat treatment. It will never be done. When a coating film that can be further patterned is used, after the coating film is patterned so as to cover the element isolation region, heat treatment can be performed, and the formation of a diffusion mask becomes unnecessary.

As described above, the case of thermally diffusing iron (Fe) as an impurity has been described in detail, but the present invention thermally diffuses carbon (C), zinc (Zn), and magnesium (Mg) in addition to iron (Fe). You can also. In the case of thermally diffusing these impurities, the impurities contained in the coating film may be diffused into the nitride semiconductor layer by heat treatment according to a known manufacturing method. For example, zinc using an SOG film (Zn), in the case of diffusing magnesium (Mg) is a solution obtained by addition of these metal compounds in an organic solvent containing a silanol compound _{(R n Si (OH) 4} -n) After preparing and spin-coating on the semiconductor layer, it can be baked to form a coating film.

BRIEF DESCRIPTION OF THE DRAWINGS It is explanatory drawing of the nitride semiconductor device formed by this invention, (a) is a top view, (b) And (c) has shown sectional drawing. It is explanatory drawing of the manufacturing method of the nitride semiconductor device of this invention. It is explanatory drawing of this kind of conventional nitride semiconductor device, (a) is a top view, (b) And (c) has shown sectional drawing.

Explanation of symbols

11; substrate; 12; buffer layer; 13; channel layer; 14; spacer layer;
15; carrier supply layer, 16; Schottky layer, 17; silicon oxide film, 18; SOG film,
19; iron doped layer, 20a; source electrode, 20b; drain electrode, 21; gate electrode,
22; recess

Claims (3)

Group III-V nitride composed of a group III element consisting of at least one of the group consisting of gallium, aluminum, boron and indium and a group V element containing at least nitrogen from the group consisting of nitrogen, phosphorus and arsenic In a method for manufacturing a nitride semiconductor device comprising a semiconductor layer,
Forming a nitride semiconductor layer comprising the group III-V nitride semiconductor layer on a substrate;
A coating film containing at least one of iron, carbon, zinc, and magnesium as an impurity is formed in a region defining the nitride semiconductor device formation region on the surface of the nitride semiconductor layer, and then heat treatment is performed, and the nitridation is performed. Diffusing the impurities in the oxide semiconductor layer to form an element isolation region of the nitride semiconductor device;
Removing the coating film and exposing the nitride semiconductor device formation region. A method of manufacturing a nitride semiconductor device, comprising: In the manufacturing method of the nitride semiconductor device according to claim 1,
A surface of the nitride semiconductor layer in the nitride semiconductor device formation region is covered with the nitride semiconductor device formation region, and a mask material is patterned so as to expose a region partitioning the nitride semiconductor device formation region, A method of manufacturing a nitride semiconductor device, comprising: forming a covering film on a mask material and the exposed surface of the nitride semiconductor layer. In the manufacturing method of the nitride semiconductor device according to claim 1 or 2,
A method of manufacturing a nitride semiconductor device, wherein an SOG film is used as the covering film.

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