JP2006156591A - Manufacturing method of semiconductor device - Google Patents

Abstract

An ultra-fine and ultra-high aspect ratio contact hole is formed.
After a resist pattern is formed on an interlayer insulating film, an organic substance is deposited on the resist by plasma irradiation using a fluorinated hydrocarbon gas, and then contact holes in the interlayer insulating film are formed in-situ. Before etching or depositing an organic substance on the resist pattern, heat treatment is performed to flow the resist, and the resist opening 15 is reduced to form a minute contact hole in a short process and at low cost.
[Selection] Figure 1

Description

The present invention relates to a method for manufacturing a semiconductor device, and relates to a method for manufacturing a semiconductor device having an ultra high aspect ratio and an ultra fine contact hole.

  As the integration and miniaturization of semiconductor integrated circuits progress, the gate electrode is thinned and the gate oxide film is thinned, and accordingly, the fine processing limit is being reached also in the contact formation process for connecting the substrate and the wiring layer. In the contact hole forming step, miniaturization progresses, and a desired contact hole diameter is about 90 nm. Further, as the miniaturization progresses, the connection hole portion may reach the element isolation region, and the function of element isolation may not be achieved, leading to the generation of leakage current. In order to protect the element isolation region, a contrivance has been made to protect the oxide film in the element isolation part by forming a nitride film below the insulating layer of only the oxide film. Furthermore, the enhancement of functions of devices has progressed due to the mixed mounting of Logic and DRAM, and semiconductor microfabrication technology represented by ULSI is extremely difficult. Among them, the formation of the contact hole is an extremely important process for the LSI manufacturing process in order to connect the transistor and the wiring. However, as the miniaturization progresses, the light source of the exposure apparatus becomes ArF, and a resist that conforms to the resolution is used with a high resolution. Further, as means for performing fine processing, means for using an immersion method at the time of exposure has been proposed.

However, the introduction of the liquid immersion method or the like requires a great deal of cost and new technology development. On the other hand, since the resist for ArF light source is inferior in etching resistance, there is a concern about the influence of plasma damage. In particular, when the aspect ratio is high, the effect becomes large. Further, since the formation of a fine pattern is affected by standing waves, a process using an antireflection film on an interlayer insulating film is common. When this process is used, it is necessary to etch the antireflection film after forming the resist pattern and then etch the interlayer insulating film. If the resist surface is roughened in the etching of the antireflection film, an ultra-small contact hole called a spike of about 1/10 to 1/100 of the desired pattern is generated on the interlayer insulating film in the contact hole forming process, resulting in poor insulation, etc. Could cause defects.

JP 2001-53061 A

The present invention was made to solve the problems of the prior art when forming the above-described conventional high aspect ratio and ultrafine contact hole. An object of the present invention is to provide a semiconductor manufacturing method capable of preventing generation and forming a high aspect ratio and ultrafine contact hole.

The first aspect of the present invention includes a step of forming an interlayer insulating film on a semiconductor substrate;
Forming a resist film on the interlayer insulating film;
Forming a resist opening by exposing and developing the resist film; and
Forming a surface film on the upper surface of the resist film;
A method of manufacturing a semiconductor device, comprising: at least a step of etching the interlayer insulating film to form an insulating film opening.

The second aspect of the present invention includes a step of forming an interlayer insulating film on a semiconductor substrate;
Forming a resist film on the interlayer insulating film;
Forming a resist opening by exposing and developing the resist film; and
Flowing the resist film by applying a heat treatment to the resist film, and reducing the resist opening;
Forming a surface film on the upper surface of the resist film;
A method of manufacturing a semiconductor device, comprising: at least a step of etching the interlayer insulating film to form an insulating film opening.

In the first and second semiconductor device manufacturing methods, an antireflection film can be formed on the interlayer insulating film, and a resist film can be formed on the antireflection film. In the surface film formation step, CF ₄ , CHF ₃ , CH ₂ F ₂ , CH ₃ F, HBr, Cl ₂ , C ₂ F ₄ , C ₂ F ₆ , C ₄ F ₈ , C ₅ F ₈ , A surface film is formed by using at least one of C ₄ F ₆ , CF ₃ I, NF ₃ , and SF ₆ and setting the gas pressure to 1.333 Pa (10 mTorr) to 6.665 Pa (50 mTorr). Is preferred. The interlayer insulating film may be a single layer film of silicon nitride film, silicon carbide film, silicon carbonitride film, silicon carbonate film, silicon oxynitride film, SiO ₂ , SiOF, BPSG, PSG, or organic silicon film, or A multilayer film using two or more types is preferable. The antireflection film is preferably a film using a silicon film, a silicon oxynitride film, or an organic material film. Furthermore, the surface roughness of the resist film is preferably Ra = 15.0 nm or less.

According to the present invention, it is possible to manufacture a semiconductor device having an ultra-high aspect ratio and an ultra-fine contact hole by preventing the resist surface from being roughened and preventing the occurrence of spikes.

[First Embodiment]
Hereinafter, a first embodiment of the present invention will be described with reference to FIG. 1 which is a schematic diagram of the process.

The first step is a step of forming an interlayer insulating film on the semiconductor substrate.
That is, as shown in FIG. 1A, an interlayer insulating film 12 is formed on the surface of a semiconductor substrate 11 having a silicon substrate or a base layer formed on the surface of the silicon substrate. As the interlayer insulating film, a material comprising a silicon nitride film, a silicon carbide film, a silicon carbonitride film, a silicon carbonation film, a silicon oxynitride film, SiO ₂ , SiOF, BPSG, PSG, or an organic silicon film is used and applied. A film can be formed by a known film formation method such as a plasma CVD method.
If necessary, an antireflection film 13 made of an inorganic material or an organic material can be provided on the surface of the interlayer insulating film 12 following this step. The antireflection film is preferably a known film material such as a silicon film, a silicon oxynitride film, or an organic material film.

  The next step is a step of forming a resist film 14 on the interlayer insulating film 12 or the antireflection film 13 as shown in FIG. In the present invention, the exposure light is not particularly limited, but ArF or F2 excimer laser is preferably used to form a fine pattern. Therefore, in this step, a resist material that is exposed to these lasers is employed.

  In the next step, as shown in FIG. 1C, the resist film 14 is exposed and developed to form a resist opening 15.

The next step is a step of forming a surface film 16 on the upper surface of the resist film 14 and the side surfaces of the resist opening 15 as shown in FIG. In the present embodiment, the surface film 16 is formed of CF ₄ , CHF ₃ , CH ₂ F ₂ , CH ₃ F, HBr, Cl ₂ , C ₂ F ₄ , C ₂ F ₆ , C ₄ F ₈ , C ₅ F. ₈ , C ₄ F ₆ , CF ₃ I, NF ₃ , SF ₆ can be used to form a film using, for example, an RIE apparatus. The gas pressure in the reaction chamber is preferably 1.333 Pa (10 mTorr) to 6.665 Pa (50 mTorr). As a result, a surface film having a thickness of 3 to 20 nm is formed. If the thickness of the surface film is smaller than this, it will not be effective enough to prevent spikes. On the other hand, in order to form a thick surface film, a longer film forming step is required, which is not practical. Further, when the gas pressure is lower than 1.333 Pa (10 mTorr), it takes a long time to form the surface film 16 having a required film thickness, which is not practical. On the other hand, when the gas pressure exceeds 6.665 Pa (50 mTorr), the thickness of the generated surface film 16 becomes non-uniform, and the shape of the contact hole is deformed.

  The next step is a step of etching the interlayer insulating film 12 to form an insulating film opening 15 in the interlayer insulating film 12 as shown in FIG. In this process, the apparatus used in the surface film forming process, which is the previous process, is continuously used, and a dry etching gas is supplied to the apparatus instead of the raw material gas for forming the surface film, thereby efficiently performing the etching. It can be carried out.

Subsequently, as shown in FIG. 1 (f), the surface film 16, the resist film 14, and the antireflection film 13 are removed by ashing using a known asher device, thereby obtaining an ultra-high aspect ratio and ultra-fine. A semiconductor device including the interlayer insulating film 12 having the contact hole 17 can be manufactured.

[Second Embodiment]
In the second embodiment, after forming the resist film opening 15 in the resist film 14 in the step of FIG. 1C in the first embodiment, the formation of the surface film 16 in FIG. Before, the resist material 14 is heat-treated, and the resist is caused to flow to shrink the opening, thereby reducing the diameter of the resist film opening.
In this step, the temperature of the heat treatment and the heating time conditions vary depending on the resist material used, the contact hole diameter, and the shrink amount, but can be performed in the range of about 100 to 180 ° C. for 10 to 120 seconds.

In this embodiment, by adding this process to the process of the first embodiment, an insulating film opening (contact) having a very small diameter can be used without adopting a lithography process using light having a shorter wavelength. Hole) can be formed.

[Third Embodiment]
In the present embodiment, a single layer film is used as an interlayer insulating film in the first embodiment. However, in this embodiment, a silicon nitride film, a silicon carbide film, a silicon carbonitride film, A multilayer film is formed by using two or more kinds of materials consisting of a silicon carbonate film, a silicon oxynitride film, SiO ₂ , SiOF, BPSG, PSG, or an organic silicon film.

  Hereinafter, a third embodiment of the present invention will be described with reference to FIG. Note that a detailed description of the configuration equivalent to that of the first embodiment is omitted.

The first step is a step of forming a first interlayer insulating film 22 on the semiconductor substrate 21 as shown in FIG. As the interlayer insulating film, a silicon nitride film, a silicon carbide film, a silicon carbonitride film, a silicon carbonation film, a silicon oxynitride film, a material composed of SiO ₂ , SiOF, BPSG, PSG, or an organic silicon film is used for coating. A well-known thin film forming method such as a plasma CVD method can be employed.

The next step is a step of forming a second interlayer insulating film 23 on the surface of the first interlayer insulating film 22 as shown in FIG. As the second interlayer insulating film material, similarly to the first interlayer insulating film material, a silicon nitride film, a silicon carbide film, a silicon carbonitride film, a silicon carbonation film, a silicon oxynitride film, SiO ₂ , SiOF A material such as BPSG, PSG, or an organic silicon film can be used.

Thereafter, in the same manner as in the first embodiment, an antireflection film 24 is formed on the surface of the second interlayer insulating film 23 as necessary, and then a resist film 25 is formed on the surface of the antireflection film 24. (FIG. 2C). Thereafter, a resist film opening 26 is formed in the resist film 25 by a known lithography method (FIG. 2D). Next, a surface film 27 is formed on the surface of the resist film 25 having the opening and the inner surface of the resist film opening 26 by the same means as in the first embodiment (FIG. 2E). Next, using the resist film 25 having the resist film opening 26 as a mask, the second interlayer insulating film 23 is etched to form an opening (FIG. 2F). Subsequently, the first interlayer insulating film is formed. The film 22 is etched to form an opening (FIG. 2G). Thereafter, the surface film 27, the resist film 25, and the antireflection film 24 are removed by ashing to form an insulating film opening 28 in the first interlayer insulating film 22 and the second interlayer insulating film 23 on the semiconductor substrate. (FIG. 2 (h)).

[Example 1]
As shown in FIG. 1, an 80 nm antireflection film 13 and a 400 nm resist film 14 are formed on a 600 nm interlayer insulating film 12 formed by plasma CVD using a TEOS (Tetraethoxysilane) gas on a Si substrate 11. The mask pattern was transferred by a known lithography method using an ArF exposure machine to form a resist opening 15 (contact hole) in the resist film 14. Note that the opening of the resist film was heat-treated at 160 ° C. for 60 s to shrink the opening of the resist mask. As a result, the opening size of the resist was 90 nm.

Next, the surface film 16 was formed under the condition of 6.665 Pa (50 mTorr) using a mixed gas of CH ₃ F: 50 sccm and Ar: 200 sccm using an ICP type reactive ion etching apparatus.

Subsequently, the antireflection film was etched at 0.9995 Pa (15 mTorr) using a mixed gas of CF ₄ : 50 sccm, O ₂ : 50 sccm, and Ar: 200 sccm, and the remaining etching product was removed with the same apparatus. Then, using a mixed gas of C ₄ F ₆ : 50 sccm, CO: 50 sccm, O ₂ : 50 sccm and Ar: 200 sccm, the interlayer insulating film (SiO ₂ ) is etched at 6.665 Pa (50 mTorr), A contact hole 17 was formed. At this time, the remaining film thickness of the resist was 300 nm at the wafer central portion and 285 nm at the outer peripheral portion.

Further, ashing with oxygen plasma was performed to remove the resist film. The diameter of the contact hole obtained at this time was about 90 nm on the surface portion for both the central portion and the outer peripheral portion of the wafer. In this case, the same effect was observed even when the gas used was CH ₂ F ₂ , CHF ₃ , or CF ₄ singly or as a mixture of two or more as the surface film forming step.

  As described above, the etching resistance of the resist was improved by forming a film with a CHF gas on the surface before etching the antireflection film. In addition, it was possible to prevent the contact hole from expanding by forming a film on the contact hole. Furthermore, the in-plane distribution of the hole diameter was uniform.

[Example 2]
As shown in FIG. 2, a silicon nitride film formed by LP-CVD using HCD (Hexa-Chloro-Disilane) gas as the first interlayer insulating film 22 is deposited on the semiconductor substrate 21. A TEOS (Tetraethoxysilane) gas was used as the second interlayer insulating film 23, and an 80 nm antireflection film 24 and a 400 nm resist film 25 were formed on a 450 nm silicon oxide film formed by plasma CVD. Next, the mask pattern was transferred by a known lithography method in which this resist film was exposed using an ArF exposure machine, and a resist film opening 26 was formed in the resist film 25.

  Next, the resist film opening 26 was shrunk by heat-treating the resist film 25 having the resist film opening 26 at 160 ° C. for 60 s. As a result, the opening size of the resist was 90 nm.

Next, the surface film 27 was formed under the condition of 6.665 Pa (50 mTorr) using a mixed gas of CH ₃ F: 50 sccm and Ar: 200 sccm using an ICP type reactive ion etching apparatus. Subsequently, the antireflection film 24 was etched at 0.9995 Pa (15 mTorr) by using a mixed gas of CF ₄ : 50 sccm, O ₂ : 50 sccm, and Ar: 200 sccm. Subsequently, after removing the residual etching product in the same apparatus, continuously, using a mixed gas of C ₄ F ₆ : 50 sccm, CO: 50 sccm, O ₂ : 50 sccm and Ar: 200 sccm, 6.665 Pa (50 mTorr) Then, the second interlayer insulating film 23 (silicon oxide film) is etched, and then the first interlayer insulating film 22 (silicon nitride film) is etched with CH ₂ F ₂ : 40 sccm, O ₂ : 50 sccm and Ar: 400 sccm. As a result, contact holes 28 were formed. At this time, the residual film thickness of the resist was 225 nm at the wafer central portion and 200 nm at the outer peripheral portion. Further, ashing with oxygen plasma was performed to remove the resist. The diameter of the contact hole obtained at this time was about 105 nm in the central portion and the outer peripheral portion of the wafer at the surface portion. In this case, the same effect was observed even when the gas used was CH ₂ F ₂ , CHF ₃ , or CF ₄ singly or as a mixture of two or more as the surface film forming step.

  By forming a film with CHF-based gas on the surface before the antireflection film is etched, the resistance of the resist to etching is improved. Even if the silicon oxide film and the silicon nitride film are continuously etched, the resist residue remains. The film has a thickness of 200 nm or more, and it has been revealed that the film has sufficient etching resistance. Further, as in Example 1, the contact hole diameter was also reduced. Furthermore, the in-plane distribution of the hole diameter was uniform.

[Comparative example]
As shown in FIG. 3, using a TEOS (Tetraethoxysilane) gas as an interlayer insulating film 32 on the Si substrate 31, a 400 nm resist film 34 is formed on the 600 nm interlayer insulating film 32 formed by plasma CVD, The resist pattern opening 35 was formed by transferring the mask pattern. Next, etching was performed using the resist film opening 35 as a mask to form a contact hole 36. The resist mask was exposed to a diameter of 120 nm using an ArF exposure machine. Etching is performed using an ICP type reactive ion etching apparatus, and etching of the antireflection film is performed using a mixed gas of CF ₄ : 50 sccm, O ₂ : 50 sccm, and Ar: 200 sccm at 1.995 Pa (15 mTorr), After removing the remaining etching product with the same apparatus, a mixed gas of C ₄ F ₆ : 50 sccm, CO: 50 sccm, O ₂ : 50 sccm, and Ar: 200 sccm is used continuously for etching the interlayer insulating film (SiO ₂ ). Etching was performed at 6.665 Pa (50 mTorr). At this time, the residual film thickness of the resist was 250 nm at the wafer central portion and 240 nm at the outer peripheral portion. Further, ashing with oxygen plasma was performed to remove the resist. The diameter of the contact hole obtained at this time was about 120 nm in the central portion and the outer peripheral portion of the wafer at the surface portion. In addition, generation of spikes 37 was observed in the interlayer insulating film 32.

From the results of the examples and comparative examples of the present invention, it has been clarified that according to the present invention, a contact hole having a small diameter can be obtained.

Process sectional drawing for demonstrating the 1st Embodiment of this invention Process sectional drawing for demonstrating the 3rd Embodiment of this invention Process sectional drawing for demonstrating the manufacturing method of the conventional semiconductor device

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 ... Semiconductor substrate 12 ... Interlayer insulation film 13 ... Antireflection film 14 ... Resist film 15 ... Resist opening 16 ... Surface film 17 ... Insulation film opening (contact hole) )
DESCRIPTION OF SYMBOLS 21 ... Semiconductor substrate 22 ... 1st interlayer insulation film 23 ... 2nd interlayer insulation film 24 ... Antireflection film 25 ... Resist film 26 ... Resist opening part 27 ... Surface film 28 ... Opening of insulating film (contact hole)
DESCRIPTION OF SYMBOLS 31 ... Semiconductor substrate 32 ... Interlayer insulating film 33 ... Antireflection film 34 ... Resist film 35 ... Resist film opening 36 ... Insulating film opening (contact hole)
37 ... Spike

Claims (7)

Forming an interlayer insulating film on the semiconductor substrate;
Forming a resist film on the interlayer insulating film;
Forming a resist opening by exposing and developing the resist film; and
Forming a surface film on the upper surface of the resist film;
A method of manufacturing a semiconductor device, comprising: at least a step of etching the interlayer insulating film to form an insulating film opening. Forming an interlayer insulating film on the semiconductor substrate;
Forming a resist film on the interlayer insulating film;
Forming a resist opening by exposing and developing the resist film; and
Flowing the resist film by applying a heat treatment to the resist film, and reducing the resist opening;
Forming a surface film on the upper surface of the resist film;
A method of manufacturing a semiconductor device, comprising: at least a step of etching the interlayer insulating film to form an insulating film opening.   3. The method of manufacturing a semiconductor device according to claim 1, wherein an antireflection film is formed on the interlayer insulating film and a resist film is formed on the antireflection film. Method. In the step of forming the surface film, CF ₄ , CHF ₃ , CH ₂ F ₂ , CH ₃ F, HBr, Cl ₂ , C ₂ F ₄ , C ₂ F ₆ , C ₄ F ₈ , C ₅ F ₈ , C ₄ A surface film is formed by using at least one of F ₆ , CF ₃ I, NF ₃ , and SF ₆ and setting the gas pressure to 1.333 Pa (10 mTorr) to 6.665 Pa (50 mTorr). A method for manufacturing a semiconductor device according to claim 1 or 2. The interlayer insulating film may be a single layer film or two types of silicon nitride film, silicon carbide film, silicon carbonitride film, silicon carbonate film, silicon oxynitride film, SiO ₂ , SiOF, BPSG, PSG, or organic silicon film 3. The method of manufacturing a semiconductor device according to claim 1, wherein a multilayer film using the above is used.   3. The method of manufacturing a semiconductor device according to claim 1, wherein the antireflection film is a film using a silicon film, a silicon oxynitride film, or an organic material film. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the resist film has a surface roughness Ra = 15.0 nm or less.

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