JP2006147845A - Semiconductor apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem of difficulty in improving both operation speed and power consumption at the same time, under the limit of specified manufacturing condition as the operation speed is improved but power consumption increases when a gate threshold voltage is lowered, while the power consumption is reduced but the operation speed drops if the gate threshold voltage is raised with a trade off relationship between operation speed and power consumption of a CMOS circuit under the limit of specified manufacturing condition, especially under the limit of manufacturing condition for miniaturization with the gate threshold voltage of an MOSFET determining balancing between them. <P>SOLUTION: A method and a circuit are proposed for instantaneously changing a gate threshold value according to changes of signals in the circuit to improve the relationship between operation speed and power consumption of a CMOS circuit. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

The present invention relates to a semiconductor device, and in particular, is a technology that enables both high speed and low power and compatibility with a wide range of power supply voltages.

In recent years, with the expansion of CMOS LSI (Complementary Metal Oxide Semiconductor Large Scale Integrated Circuits), MOSFETs constituting the CMOS LSI have become smaller and the power supply voltage has decreased. As the power supply voltage decreases, the threshold voltage of the MOSFET gate also decreases. In a CMOS LSI, the threshold voltage is often about 5 to 1/6 of the power supply voltage. For example, when the power supply voltage (V _DD ) is 5 V, the threshold voltage (V _TP ) of the P-channel MOSFET is about −0.9 V, and the threshold voltage (V _TN ) of the N-channel MOSFET is about 0.9 V. . When the power supply voltage drops to 2.5V, V _TP is approximately -0.5 V, V _TN is approximately 0.5V. The threshold voltages V _TP and V _TN of the two MOSFETs are reduced almost in proportion to the power supply voltage V _{DD because} of the speed, power consumption, and stable operation of the CMOS (Complementary Metal Oxide Semiconductor) circuit. It ’s a trade-off.

In the P-channel MOSFET, the voltage applied to the gate is conductive from 0 to V _DD + V _TP , otherwise it is non-conductive, in the N-channel MOSFET, the voltage applied to the gate is conductive from V _TN to V _DD , otherwise Non-conducting. If the range of conduction in these MOSFETs is expanded, a large current flows through the CMOS circuit and the circuit operates at high speed, but the power consumption increases. On the contrary, if the non-conduction range is wide, the current flowing through the CMOS circuit becomes small and the operation of the circuit becomes slow, but the power consumption can be reduced. Also, by taking a wide range of MOSFET non-conduction, the difference in resistance between MOSFET conduction and non-conduction can be made extremely large, and the circuit can operate stably.

MTCMOS (Multi-Threshold Voltage) is a technology for controlling the threshold voltage of P-channel MOSFETs and N-channel MOSFETs that make up CMOS circuits to reduce the speed and power consumption of CMOS circuits.
CMOS) and VTCMOS (Variable Threshold Voltage CMOS) are known.

In MTCMOS, a low threshold voltage is used in a portion where high speed operation of a circuit is required, and a high threshold voltage is used in a portion where high speed operation is not required or a portion used during standby. That is, MTCMOS is a method of setting different threshold voltages at circuit locations. MTCMOS is described in Non-Patent Document 1.

VTCMOS lowers the threshold voltage by placing importance on power consumption over the high speed of the circuit when the circuit is in a normal operating state, and focuses on the power consumption when the circuit is in a standby state. To increase. As a method of changing the threshold voltage, a voltage is applied to a substrate region where a P-channel MOSFET or an N-channel MOSFET is formed. That is, this is a method of controlling the threshold voltage from the outside using the substrate bias effect of the MOSFET. In this case, the voltage (substrate bias voltage) applied to the substrate region is constant during the period in which the circuit is in the operating state or in the standby state, and thus the threshold voltage is constant within each period. VTCMOS is described in Non-Patent Document 2.
Proceedings of the 2003 international symposium on low power electronics and design, p.110-115, Seoul, Korea Japanese Journal of Applied Physics, Vol.40, Part 1, No.4B, pp.2854-2858, April 2001

Taking the CMOS inverter as an example, the most frequently used basic circuit in CMOS LSIs, the operating speed and power consumption will be explained. FIG. 2 shows a CMOS inverter circuit. The MOSFET on the positive power supply V _DD side (upper side in FIG. 2) is a P-channel MOSFET, and the MOSFET on the ground side (lower side in FIG. 2) is an N-channel MOSFET. The input signal is applied to the gate electrodes of the two MOSFETs, and the output signal is extracted from the node connecting the drain electrodes of the two MOSFETs. A capacitor is connected to the output terminal, which represents a load (that is, an input capacitor of the CMOS circuit at the next stage) connected to the output of the CMOS inverter. The substrate of the P-channel MOSFET is connected to the positive power supply side. The substrate of the N-channel MOSFET is connected to the ground side. When the power supply voltage V _DD = 3.5V is used, the threshold voltage V _TP = −0.6V of the P-channel MOSFET, and the threshold voltage V _TN = 0.6V of the N-channel MOSFET, The operation will be described. The voltage of the input signal changes in a pulse form in the range from zero to the positive power supply voltage (V _DD = 3.5V).

When the input signal is zero voltage, the N-channel MOSFET is non-conductive, the P-channel MOSFET is conductive, and the output terminal voltage is high (V _DD = 3.5V). When the input signal rises to a high voltage (V _DD = 3.5V), the N-channel MOSFET becomes conductive and the P-channel MOSFET becomes non-conductive, and the voltage at the output terminal becomes zero voltage. Regardless of whether the input signal is at zero voltage or V _DD , either the P-channel MOSFET or the N-channel MOSFET is non-conductive, there is no current flowing from the power supply side to the ground side, and the CMOS is in terms of power consumption. Excellent circuit. Further, while the input signal changes from zero voltage to V _DD or during changes from V _DD to zero voltage, there is a period in which both the P-channel MOSFET and the N-channel MOSFET is turned on, the power supply side during this period Current flows from the ground to the ground side. This current is called a through current.

The voltage change of the output signal when the input signal changes in a pulse shape within the range of zero voltage and V _DD will be described. FIG. 3 shows voltage waveforms of the input signal and the output signal. The input signal rises from zero voltage to V _DD = 3.5V with rise time Tr. In response to this change in the input signal, as described above, the output signal falls from V _DD = 3.5 V to zero voltage. This change in the output signal is generated with some time delay (in FIG. 3, the delay time Tpd is defined by an intermediate value between the input signal and the output signal). As the input signal rises, the N-channel MOSFET becomes conductive and discharges the charge charged in the load capacitance shown in FIG. It takes time until the charge disappears, and the above-mentioned delay occurs. When the input signal falls from V _DD = 3.5V to zero voltage at the fall time Tf, the output signal rises from zero voltage to V _DD = 3.5V. Again, this change in output signal occurs with some delay from the change in input signal. This is because it takes time for the P-channel MOSFET to conduct to charge the load capacitance and to accumulate the charge. Although this delay time is not shown in FIG. 3, the circuit is usually designed so as to be close to the above-described Tpd. This delay time Tpd is called a gate delay time.

In the CMOS inverter, the gate delay time Tpd and the energy consumed when the input rises and falls are in a trade-off relationship, and it is a big problem to achieve both.

表１ CMOSインバータのゲート遅延時間と消費エネルギー The balance of these two parameters is determined by the threshold voltages V _TP and V _TN of the P-channel MOSFET and N-channel MOSFET. Specific numerical examples are shown below. Regarding the shape of the CMOS inverter, for P-channel MOSFET, channel width W = 260 μm, channel length L = 0.35 μm, gate oxide thickness = 7.8 nm, for N-channel MOSFET, channel width W = 130 μm, channel length L = 0.35 μm, gate oxide thickness = 7.8 nm, load capacitance C _L = 0.6 pF (corresponding to the CMOS inverter of the same shape connected to the next stage), power supply voltage V _DD = 3.5 V, input signal rise and rise For fall time Tr = Tf = 1.5 ns, change threshold voltages V _TP and V _TN , average gate delay time at input rise and fall, total consumption at input rise and fall The energy is shown in Table 1. Comparing the results in this table with V _TP = -0.6V and V _TN = 0.6V as a reference, when the threshold voltage decreases (V _TP = -0.3V, V _TN = 0.3V), the gate delay time is Smaller but more consumed energy. On the contrary, when the threshold voltage increases (V _TP = −0.9 V, V _TN = 0.9 V), the energy consumption decreases but the gate delay time increases. It can be seen that the gate delay time and energy consumption are in a trade-off relationship, and the balance between the two is determined by the threshold voltages (V _TP , V _TN ). As described above, the threshold voltages V _TP and V _TN are usually set to about one fifth to one sixth of the power supply voltage. The threshold voltage is set lower than this in a circuit that requires high-speed operation, and the threshold voltage is set higher in a circuit that emphasizes low power consumption.

Table 1 CMOS inverter gate delay time and energy consumption

MTCMOS and VTCMOS have advanced the above-described concept of setting the threshold voltages V _TP and V _TP in consideration of the speed and power consumption of the CMOS circuit. In MTCMOS, a low threshold voltage is set in a circuit portion where high speed operation is required, and a high threshold voltage is set in a circuit portion where high speed operation is not required. That is, this is a method in which different values of threshold voltage are used in circuit portions. In this method, it cannot be said that the operation speed and the power consumption are compatible. VTCMOS is a method of changing the threshold voltage according to the operating state of the circuit. In a state where the circuit is operating normally and high speed is required, the threshold voltage is lowered, and if the circuit is in a standby state, the threshold voltage is increased with an emphasis on power consumption. As a method of changing the threshold voltage, a voltage is applied to a substrate region where a P-channel MOSFET or an N-channel MOSFET is formed. A so-called substrate bias effect is used. Since the voltage applied to the substrate region (substrate bias) is constant during a period in which the circuit is in operation or in a standby state, the threshold voltage is constant within each period. In MTCMOS and VTCMOS, the threshold voltage does not change dynamically according to the signal in the circuit, but is a constant value during the operation of the circuit.

Further, when the threshold voltage is reduced in proportion to the power supply voltage, the problem of power consumption occurs due to the following phenomenon. If the MOSFET gate voltage changes around the threshold voltage, the MOSFET does not change abruptly from non-conductive to conductive or from conductive to non-conductive. The change in the resistance of the MOSFET before and after the threshold voltage is gradual, transitioning from non-conduction to weak conduction and further to conduction. When the threshold voltage is decreased as the power supply voltage is lowered, the proportion of the weak conduction range increases, and the non-conduction range narrows. Further, the resistance of the MOSFET in non-conduction decreases, and the power consumption in the standby state of the CMOS increases. This is a big problem in low power supply voltage.

  The present invention is a method for instantaneously changing a threshold voltage in response to a change in a signal in a circuit in a CMOS circuit.

In the CMOS inverter, as shown in FIG. 4, A is a terminal of the substrate of the P-channel MOSFET, and B is a terminal of the substrate of the N-channel MOSFET. By applying a voltage to these A and B, the threshold voltages of the P-channel MOSFET and N-channel MOSFET can be changed. The present invention is a method for instantaneously changing the voltages A and B in response to a change in input voltage.

When the voltage of the input signal rises from the zero voltage to the power supply voltage V _DD , the voltage of A is made higher than V _{DD and} the voltage of B is made higher than the zero voltage. By doing so, the threshold voltage V _TN of the N-channel MOSFET becomes small, the discharge of the load capacitance is accelerated, and the gate delay time is reduced. The threshold voltage V _TP of the P-channel MOSFET becomes deep (increases in absolute value), the through current is reduced, and the energy consumption is reduced. Both the gate delay time and energy consumption of the CMOS inverter are improved. When the voltage of the input signal falls from the power supply voltage V _DD to zero voltage, the voltage of A is made lower than V _{DD and} the voltage of B is made lower than zero voltage. By doing so, the threshold voltage V _TP of the P-channel MOSFET becomes shallow (decreases in absolute value), charging of the load capacitance is accelerated, and the gate delay time is reduced. The threshold voltage V _TN of the N-channel MOSFET is increased, the through current is reduced, and the energy consumption is reduced. At this time, both the gate delay time and energy consumption of the CMOS inverter are improved. That is, when the input signal voltage increases, the A and B voltages are increased, and when the input signal voltage decreases, the A and B voltages are decreased, thereby reducing the gate delay time and energy consumption of the CMOS inverter. Can improve.

In the CMOS circuit, the relationship between the speed of the CMOS circuit and the power consumption can be improved by using a circuit that instantaneously changes the threshold voltage of the present invention in response to a change in the signal in the circuit. In other words, the power consumption can be reduced to increase the speed, or the increase in power consumption can be suppressed to increase the speed.

In a CMOS circuit, the threshold voltage of the MOSFET is set higher in advance at a low power supply voltage by using a circuit that instantaneously changes the threshold voltage of the present invention in response to a change in the signal in the circuit. It is possible to reduce power consumption during standby of the CMOS circuit.

In a CMOS circuit, the threshold voltage of the MOSFET is set higher in advance at a low power supply voltage by using a circuit that instantaneously changes the threshold voltage of the present invention in response to a change in the signal in the circuit. Therefore, the CMOS circuit can be operated stably.

According to the present invention, it is possible to realize a CMOS circuit that operates at a higher speed, operates at a low power consumption and is stable, and a CMOS LSI chip and an electronic device composed thereof.

An example of a principle circuit capable of realizing this is shown in FIG. In FIG. 1, the input terminal (In) and the ground are divided by capacitors C1 and C3, and the intermediate point is connected to the terminal A of the substrate of the P-channel MOSFET. Similarly, the capacitance C2 and C4 are divided between the input terminal (In) and the ground, and the intermediate point is connected to the terminal B of the substrate of the N-channel MOSFET. The terminal A and the power supply terminal are connected by a resistor R5, and the terminal B and the ground are connected by a resistor R6. The initial voltages at terminals A and B are set to the power supply voltage V _DD and zero voltage through R5 and R6, respectively. Further, after the voltage at the terminal A and the terminal B rises or falls at the time of the rise or fall of the voltage of the input signal, the terminal A, through the terminals R5 and R6 before the fall or rise of the voltage of the input signal continues. The voltage at terminal B is restored to the original initial voltage (power supply voltage V _DD and zero voltage). By making C1 larger than C3 and C2 larger than C4, most of the change in the voltage of the input signal can be reflected in the change in the voltage of A and B. C3 and C4 voltage change, C1 and C2 voltage change is small). Also, if C3 and C4 are made smaller, the capacity seen from the input terminal will not be increased. The circuit of FIG. 1 can increase the A and B voltages when the input signal voltage increases, and can decrease the A and B voltages when the input signal voltage decreases. Time and energy consumption can be improved.

In FIG. 1, after the voltage at the terminal A and the terminal B rises or falls at the rise or fall of the voltage of the input signal, and before the fall or rise of the voltage of the input signal continues, the terminal A through R5 and R6. In order to restore the voltage at the terminal B to the original initial voltage (the power supply voltage V _DD and the zero voltage), the values of the resistors R5 and R6 must be C1 · R5 << Tw, C2 · R6 << Tw. Here, Tw is the pulse width of the input signal shown in FIG. In view of the above, as an example, C1 = 0.8 pF, C2 = 0.4 pF, C3 = 0.08 pF, C4 = 0.04 pF, V TP = -0.6V, under the condition of _{V TN = 0.6V, R5 = 1} kΩ, If R6 = 2 kΩ, C1 ・ R5 = C2 ・ R6 = 0.8 ns,
The average gate delay time at the rise and fall of the input, and the total energy consumption at the rise and fall of the input, the gate delay time = 8.92 × 10 ⁻¹¹ s and the energy consumption = 6.66 × 10 ^{− 11} J becomes, V _TP = -0.6 V in the value of the above table, as compared with the case of V _TN = 0.6V, energy consumption is almost the same, the gate delay time is made improved by 29%.

The improvement of the gate delay time by the circuit of FIG. 1 becomes significant when the rise and fall of the input signal are delayed. If only the results are shown for Tr = Tf = 2.5 ns, the improvement in gate delay time is 35% when C1, C2, C3, C4, R5, and R6 are the same as described above.

1, the substrate-source capacitance, the substrate-drain capacitance, and the substrate-gate capacitance are distributed in the respective terminals A and B of the P-channel MOSFET and N-channel MOSFET substrate. Because of these capacitances, the circuit of FIG. 1 with the capacitors C3 and C4 removed, that is, the circuit of FIG. 5 (C1 = 0.8 pF, C2 = 0.4 pF, R5 = 1 kΩ, R6 = 2 kΩ), Tr When the average gate delay time at the rise and fall of the input and the total energy consumption at the rise and fall of the input are calculated for the case of = Tf = 1.5 ns, the gate delay time = 8.83 × 10 ⁻¹¹ s, consumption Energy = 6.60 × 10 ⁻¹¹ J. Compared to the case of V _TP = −0.6 V and V _TN = 0.6 V in the above table, the energy consumption is almost the same and the gate delay time is 30%. It has been improved. From these results, it can be seen that the capacitors C3 and C4 in FIG. 1 can be omitted.

In the circuit of FIG. 5, the change of the input signal is represented by the capacitors C1 and C2 to the substrate terminals A and B of the P-channel MOSFET and N-channel MOSFET, and the gate threshold voltage of both MOSFETs is dynamically controlled. As a result, CMOS inverters have been increased in speed (reduced gate delay time). In this circuit, in which the capacitor C2 is removed and the resistor R6 is short-circuited, that is, the circuit shown in FIG. 6, the change of the input signal appears only at the substrate terminal A of the P-channel MOSFET. When Tr = Tf = 1.5 ns, the average gate delay time at the time of input rise and fall, and the total energy consumption at the time of input rise and fall, the gate delay time = 1.1 × 10 ⁻¹⁰ s, Energy consumption = 6.69 × 10 ⁻¹¹ J. Compared to the case of V _TP = −0.6 V and V _TN = 0.6 V in the above table, the energy consumption is almost the same, and the gate delay time is 13 % Improvement.

In the circuit of FIG. 5 in which the capacitor C1 is removed and the resistor R5 is short-circuited, that is, the circuit shown in FIG. 7, the change of the input signal appears only at the substrate terminal B of the N-channel MOSFET. When Tr = Tf = 1.5 ns, the average gate delay time at input rise and fall, and the total energy consumption at input rise and fall, the gate delay time = 1.04 × 10 ^-10 s, Energy consumption = 6.71 × 10 ⁻¹¹ J. Compared to the case of V _TP = −0.6 V and V _TN = 0.6 V in the above table, the energy consumption is almost the same and the gate delay time is 18 % Improvement.

In order to realize the circuit of FIG. 5 on the semiconductor surface, a triple well structure in which the substrate of the P channel MOSFET and the N channel MOSFET is configured as an N well and a P well, respectively, is preferable. An explanatory diagram of the triple well structure is shown in FIG. FIG. 8 shows a case where a P-type substrate is used. An N-well is formed on a part of the substrate surface, and a P-channel MOSFET is formed therein. A deep N well is formed in another part of the substrate surface, and a P well is formed therein. This P well is used as a substrate of an N channel MOS transistor. Thus, by providing the substrate of the P-channel MOSFET and the N-channel MOS transistor independently as an N well and a P well, a change in the input signal of the CMOS inverter can appear in the N well and the P well.

FIG. 9 shows an example of a method for realizing the P-channel MOSFET, the capacitor C1, and the resistor R5 of FIG. 5 or 6 on the semiconductor surface. An N-well is formed on the surface of a P-type substrate, a P-channel MOSFET and a capacitor C1 are formed therein, and a resistor R5 is realized as a thin film on an insulating film (field oxide film) outside the N-well. An N-type high impurity layer higher than the impurity concentration of the well is formed on a part of the surface of the N well so that the capacitance value of C1 can be easily realized.

Description of the method for realizing the N-channel MOSFET, the capacitor C2, and the resistor R6 of FIG. 5 or 7 on the semiconductor surface is omitted, but a circuit similar to FIG. 9 may be configured in the P-well.

In order to realize the circuit of FIG. 6 or 7 on the semiconductor surface, a triple well structure is not necessary. To realize the circuit of FIG. 6, an N-well structure using a normal P-type substrate may be used.
To realize the circuit of FIG. 7, a P-well structure using a normal N-type substrate may be used.

All the descriptions so far have been made on the improvement of the present invention in a CMOS circuit using a normal semiconductor substrate. When an SOI (Silicon on Insulator) wafer is used as a semiconductor substrate, the improvement by the circuit of the present invention appears more remarkably. This will be described below. FIG. 10 shows a configuration for realizing a P-channel MOSFET and an N-channel MOSFET on the surface of the SOI wafer. A thick insulating film layer is formed over the semiconductor substrate, and a thin single crystal semiconductor film is further formed thereon. A P-channel MOSFET and an N-channel MOSFET are realized using this thin single crystal semiconductor as shown in FIG. By adopting such a structure, the drain regions (shown by D in FIG. 10) of the P-channel MOSFET and the N-channel MOSFET are not in direct contact with the semiconductor substrate, that is, between the drain region and the semiconductor substrate. A thick insulating film is interposed, and the capacitance between the drain region and the semiconductor substrate is reduced. For this reason, a CMOS circuit using an SOI wafer operates at a higher speed than a CMOS circuit using an ordinary semiconductor substrate (referred to as bulk silicon to distinguish it from an SOI wafer).

The circuit of FIG. 2 serving as a reference for comparison of the present invention is configured on an SOI wafer. Channel length (L), channel width (W), gate oxide film thickness, threshold voltage (V _TP , V _TN ), power supply voltage (V _DD ), load capacitance (C _L ) of P-channel MOSFET and N-channel MOSFET Is set to the same value as in the case of bulk silicon. When the input signal rise and fall time Tr = Tf = 1.5 ns, the average gate delay time at the input rise and fall, and the total energy consumption at the input rise and fall, find the gate delay. Time = 1.04 × 10 ⁻¹⁰ s, energy consumption = 6.39 × 10 ⁻¹¹ J. The circuit of FIG. 5 is configured on an SOI wafer, and C1 = 0.8 pF, C2 = 0.4 pF, R5 = 1 kΩ, and R6 = 2 kΩ as in the case of bulk silicon. When the input signal rise and fall times Tr = Tf = 1.5 ns, the average gate delay time at the input rise and fall, and the total energy consumption at the input rise and fall, find the gate delay. Time = 5.88 × 10 ^-11 s, energy consumption = 6.17 × 10 ^-11 J. Compared to the above case, the energy consumption is not much different and the gate delay time is improved by 43%. This is larger than the 30% improvement in the case of bulk silicon.

FIG. 11 shows an example of a method for realizing the P-channel MOSFET, the capacitor C1, and the resistor R5 of FIG. 5 or 6 on the SOI wafer. An N-type single crystal semiconductor thin film is formed on the thick insulating film layer, and a P-channel MOSFET, a capacitor C1, and a resistor R5 are formed therein. A part of the N-type single crystal semiconductor thin film is made into an N-type high impurity layer having a higher impurity concentration so that the C1 capacitance value can be easily realized.

All the discussions so far have been directed to the CMOS inverter shown in FIG. 2, by dynamically changing the gate threshold voltage of the P-channel MOSFET and N-channel MOSFET constituting the CMOS inverter in synchronization with the input signal of the CMOS inverter. Various methods for speeding up CMOS inverters have been proposed. The methods proposed so far are not limited to inverters, and many gate circuits, that is, many CMOS logic circuits, exhibit the effect of reducing the gate delay time. FIG. 12 shows a circuit in which the present invention is applied to a 2-input CMOS NAND circuit, and FIG. 13 shows a circuit in which the present invention is applied to a 2-input CMOS NOR circuit.

The discussion so far has also shown that the CMOS threshold voltage of the P-channel MOSFET and N-channel MOSFET constituting the CMOS logic circuit is dynamically changed in synchronization with the input signal immediately before the CMOS logic circuit. A method for realizing high-speed circuit has been proposed. However, the signal that dynamically changes the gate threshold voltage of the P-channel MOSFET and the N-channel MOSFET is not limited to the input signal immediately before the logic circuit. In order for the present invention to be more effective, it is better to change the gate threshold voltages of the P-channel MOSFET and N-channel MOSFET constituting the logic circuit before the input signal reaches the logic circuit. Good. A simple specific example will be described.

The circuit shown in FIG. 14B is a circuit in which four stages of CMOS inverters are connected in cascade. As shown in FIG. 14A, when a large inverter circuit (D) that directly drives a large load capacity (C _L ) is driven by an output signal of the small inverter circuit (A), the delay of the signal increases. In order to prevent this, the circuit shown in FIG. 14 (b) is used, and signal delays are obtained by inserting inverters (B) and (C) that are sequentially increased between the inverter circuits (A) and (D). To prevent the increase.
In the method described so far, the output signal of the inverter (C) is used as a signal for changing the gate threshold voltage of the P-channel MOSFET and the N-channel MOSFET that constitute the inverter (D), so that the inverter (D ) To reduce the gate delay time. In this circuit, the output signal of the inverter (A) changes in phase with the output signal of the inverter (C) and changes faster than the output signal of the inverter (C). Therefore, the output signal of the inverter (A) is better than the output signal of the inverter (C) as the signal for changing the gate threshold voltage of the P-channel MOSFET and the N-channel MOSFET constituting the inverter (D).

In the description so far, a planar MOSFET using an oxide as a gate insulator has been taken as an example of an element constituting a CMOS circuit. However, the gist of the present invention is not related to the type of gate insulator or the structure of the transistor, but is a complementary circuit that uses an insulated gate field effect transistor widely regardless of the structure. The present invention relates to control of gate threshold voltages of transistors and N-channel insulated gate field effect transistors.

Circuit to apply substrate bias with CMOS inverter CMOS inverter circuit Voltage waveform of input and output signals The figure for demonstrating the substrate bias of a CMOS inverter Circuit with capacitors C3 and C4 removed from the circuit shown in FIG. Circuit with capacitor C2 and resistor R6 removed from the circuit shown in FIG. Circuit with capacitor C1 and resistor R5 removed from the circuit shown in FIG. Triple well structure 1 is an explanatory diagram for realizing a part of the circuit of FIG. 1, a P-channel MOSEFT, a capacitor C1, and a resistor R5 on a semiconductor surface. Drawing that configures P-channel MOSFET and N-channel MOSFET on the surface of SOI wafer FIG. 1 is an explanatory diagram for realizing a part of the circuit of FIG. 1, a P channel MOSEFT, a capacitor C1, and a resistor R5 on an SOI wafer; (a) a view from above; ; (C) Section at cut surface B (capacitance C1, resistance R5 part) Example of applying substrate bias in 2-input CMOS NAND circuit Example of applying substrate bias in 2-input CMOS NOR circuit Example of circuit for applying voltage to substrate of inverter D with output signal of inverter A; (a) Circuit for driving large inverter D with small inverter A; (b) Inverters B and C between inverters A and D Inserted circuit

Explanation of symbols

R5, R6, R5A, R5B, R6A, R6B ... Resistance, CL, C1, C2, C3, C4, C1A, C1B, C2A, C2B ... Capacitance, In, InA, InB ... Signal input, Out ... Signal output, Tr ... Rise time, Tf ... Fall time, Tpd ... Gate delay time, G ... Gate, S ... Source, D ... Drain, VDD ...・ Power supply potential

Claims (3)

In a CMOS circuit using a P-channel MOSFET and an N-channel MOSFET, the potential of a certain contact in the circuit changes to a rectangular wave shape composed of a first potential and a second potential, and the potential of the contact changes from the first potential to the second potential. When the voltage rises or falls from the second potential to the first potential, the gate threshold voltage of the P-channel MOSFET and / or the N-channel MOSFET changes in a direction that accelerates the operation of the CMOS circuit according to the change, and after the change, A semiconductor device comprising means for recovering the changed gate threshold voltage to the value before the change when the contact potential holds the first potential or the second potential.
2. The semiconductor device according to claim 1, wherein the substrate bias effect of the MOSFET is used as means for changing the gate threshold voltage of the P-channel MOSFET and / or the N-channel MOSFET.
The contact and the substrate bias node of the target MOSFET are connected by a circuit including an electrostatic capacity, and the power supply and ground that provide the substrate bias node of the target MOSFET and the value at which the substrate bias recovers 3. The semiconductor device according to claim 2, wherein the nodes are connected by a circuit including a resistor.

Images