JP2006146757A - Register for debugging and data transfer method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a register for debugging and a data transfer method, capable of transferring data of continuous addresses in a debug memory space with a small number of clocks. <P>SOLUTION: Shift-out of data from a PrAcc register and an address register, and shift-in of the data to the PrAcc register and a data register are simultaneously executed. When a shifted-out value of the address register is an expected value, an instruction to execute writing of the shifted-in data into the data register and writing into the PrAcc register is used. By sequentially inputting the data acquired from the address next expected with the access and the PrAcc data controlling pending of processor access such that the debugging is successively executed as the shifted-in data, the data are sequentially acquired from the continuous addresses in the debug memory space, and are sequentially written in the data register. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a debugging register included in an EJTAG on-chip debugging circuit, and a data transfer method to the register.

  Conventionally, ICE (In-circuit Emulator) has been widely used for software development of a system incorporating a microprocessor. However, due to advances in semiconductor microfabrication technology, microprocessors have become faster, larger, and more diverse, and as so-called single-chip integration that incorporates CPU peripheral functions has progressed, ICE has become more complex, and its development has It became costly and time consuming. In addition, there is a tendency for the life cycle of the CPU to be shortened, and it has become difficult for conventional ICE to meet market demands.

  In order to solve these problems, an on-chip debugging method in which a debugging function is embedded in the microprocessor itself has been proposed (see, for example, Patent Document 1).

  One of these on-chip debugging methods is the EJTAG (Enhanced JTAG) method. In the EJTAG method, a debug circuit is added to a JTAG test circuit used for a boundary scan test, thereby enabling debugging of software of a system incorporating a microprocessor.

  When performing on-chip debugging by the EJTAG method, as shown in FIG. 4, an EJTAGTAP (EJTAG test access port) 100 incorporated in the microprocessor 10 and a debug host 20 are connected via an EJTAG probe 30. As a result, a debug control instruction and data necessary for debugging are communicated between the debug host 20 and the microprocessor 10.

  FIG. 5 shows an overview of EJTAGTAP100.

  The EJTAGTAP 100 includes a TAP controller 101 for controlling a test operation, an instruction register 102 for writing a debug instruction, and a data register group 103 having a plurality of data registers.

  In addition, the EJTAGTAP 100 has a test clock (TCK), a test mode (TMS), a test data in (TDI), and a test data out (TDO) as terminals for communicating with the debug host 20, and optionally a test reset (TRST). ) Can be provided.

  The data register group 103 includes an address register 1031 for designating an address of the debug memory space, a data register 1032 for transferring and writing data at the address designated by the address register 1031 from the debug memory space, and control such as resetting of the processor. A control register 1033 is included. Which data register is selected depends on the value of the instruction register 102.

  The control register 1033 includes a PrAcc area where a PrAcc signal is written. This PrAcc signal controls the pending processor access. That is, when PrAcc = 1, processor access is pending, and when PrAcc = 0, processor access pending is released.

  Conventionally, each register of the instruction register 102 and the data register group 103 is configured by a shift register, the input is commonly connected to the input terminal TDI, and the output is connected to the output terminal TDO via the selector 1034 and the selector 104. Has been. The TAP controller 101 controls which register of the instruction register 102 and the plurality of data register groups 103 receives data.

  FIG. 6 shows a state transition diagram of the TAP controller 101.

  The state transition of the TAP controller 101 is controlled by the value of TMS, and the operation in each state (state) is synchronized with TCK.

  In FIG. 6, the state transition from Select-DR-Scan to Update-DR (DR: data register) represents the execution of reading / writing data from / to each register of the data register group 103, from Select-IR-Scan to Update-IR. A state transition to (IR: instruction register) represents execution of reading / writing of data with respect to the instruction register 102.

  Therefore, when the microprocessor 10 is in a debug state and data acquired from the debug memory space of the debug host 20 is transferred and written to the data register 1032, three types of control register 1033, address register 1031, and data register 1032 are used. It is necessary to control the reading and writing of registers. Therefore, it is necessary to rewrite the instruction code written to the instruction register 102 every time the register to be read / written is switched.

  When the microprocessor 10 is in a debug state and data acquired from the debug memory space is to be transferred and written to the data register 1032, after the microprocessor 10 sets PrAcc = 1, reading / writing of each register is performed as follows: Done.

(1) Reading the control register 1033 for confirming PrAcc = 1 (2) Writing the address register selection instruction to the instruction register 102 (3) Reading the address value from the address register 1031 (4) Data register selection instruction Write to instruction register 102 (5) Write data to data register 1032 (6) Write control register selection instruction to instruction register 102 (7) Write PrAcc = 0 from debug host 20 to control register 1033

  If the address register 1031, the data register 1032 and the control register 1033 are 32 bits each, 36 clocks are required for the state transition from Select-DR-Scan to Update-DR and back to Select-DR-Scan. When 102 is 8 bits, 13 clocks are required for the state transition from Select-IR-Scan to Update-IR to return to Select-IR-Scan. Therefore, in this case, the number of clocks required to execute the above-described procedures (1) to (7) is 183 (= 36 + 13 + 36 + 13 + 36 + 13 + 36).

As described above, in the configuration of the conventional data register group shown in FIG. 5 used for debugging, the above-described case is possible even when data at consecutive addresses in the debug memory space is continuously transferred to the data register during debugging. There is a problem that it is necessary to repeatedly execute the above procedure, and a large number of clocks are required for data transfer.
JP 2004-206283 A (page 4, FIG. 1)

  SUMMARY OF THE INVENTION An object of the present invention is to provide a debug register and a data transfer method capable of transferring data at consecutive addresses in a debug memory space with a small number of clocks.

  According to one aspect of the present invention, the first PrAcc is a debugging register mounted on an EJTAG-compliant microprocessor, which stores an address register, a data register, and a PrAcc signal that controls pending processor access. There is provided a debugging register comprising a register, a second PrAcc register in which the PrAcc signal is stored, and a control register having a PrAcc area in which the PrAcc signal is written.

  According to another aspect of the present invention, there is provided a debugging register mounted on an EJTAG-compliant microprocessor, a shift register having parallel input and parallel output functions, and a parallel input and parallel output function. A PrAcc register for storing a PrAcc signal for controlling the pending of processor access, an address register to which data output in parallel from the shift register is written, a data register to which data output in parallel from the shift register is written, A control register having a PrAcc bit area into which data output in parallel from the shift register and the PrAcc register is written, and the Pr of the address register and the control register Debug register parallel output data from the cc area, characterized in that the input in parallel to the shift register and the PrAcc register is provided.

  According to another aspect of the present invention, there is provided a method for transferring data to a debug register of an EJTAG-compliant microprocessor having an address register, a data register, and a PrAcc register as debug registers, the method comprising: Data shift-out and data shift-in to the data register and the PrAcc register are simultaneously performed, and the data register and PrAcc of the shifted-in data when the value of the address register shifted out is an expected value. An instruction for executing a write to the register; when acquiring data sequentially from successive addresses in the debug memory space and sequentially writing to the data register, the instruction is used; A data transfer method is provided in which data acquired from an address that is expected to be accessed next and PrAcc data that controls pending processor access are input so that debugging can be continuously executed. Is done.

  According to the present invention, reading of the address value from the address register and writing of the data to the data register are continuously executed by executing only one instruction. Therefore, data at consecutive addresses in the debug memory space can be obtained with a small number of clocks. Can be continuously transferred to the data register, and the data transfer rate can be improved.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a block diagram illustrating a configuration of a debug register according to the first embodiment of the present invention.

  The data register group 1 constituting the debug register includes an address register 11, a data register 12, a control register 13, a first PrAcc register 11A, and a second PrAcc register 12A.

  The address register 11, the data register 12, and the control register 13 form a shift register, and their inputs are connected to a common input terminal. This input terminal is connected to the TDI of the EJTAGTAP 100 shown in FIG.

  The output of the address register 11 is connected to the first PrAcc register 11A, and the address register 11 and the first PrAcc register 11A can be connected to operate as one shift register.

  The output of the data register 12 is connected to the second PrAcc register 12A, and the data register 12 and the second PrAcc register 12A can be connected to operate as one shift register.

  The output of the address register 11, the output of the data register 12, the output of the control register 13, the output of the first PrAcc register 11A, and the output of the second PrAcc register 12A are connected to the selector 14, and depending on the type of debug instruction It is determined whether the output of the register is output to the output terminal. The output terminal is connected to the TDO of the EJTAGTAP 100 shown in FIG.

  In the first PrAcc register 11A and the second PrAcc register 12A, the value of the PrAcc signal for controlling the pending of the processor access is written. Writing the value of the PrAcc signal to the first PrAcc register 11A is performed by connecting the first PrAcc register 11A to the address register 11 and shifting in the value of the PrAcc signal from the input terminal (TDI). Similarly, the value of the PrAcc signal is written into the second PrAcc register 12A by connecting the second PrAcc register 12A to the data register 12 and shifting in the value of the PrAcc signal from the input terminal (TDI). Done.

  The control register 13 has a PrAcc area 13A in which the PrAcc signal is written, and the PrAcc signal value is written by the microprocessor. The PrAcc signal value written to the PrAcc area 13A is written to the first PrAcc register 11A in the Capture-DR state in the state of the TAP controller shown in FIG. The PrAcc signal value shifted in the second PrAcc register 12A is written to the PrAcc area 13A of the control register 13 in the Update-DR state in the TAP controller state shown in FIG.

  When the microprocessor is in the debug state and the data acquired from the debug memory space of the debug host 20 is transferred and written to the data register 12 of this embodiment, the address register 11 and the first PrAcc register 11A are connected, The data register 12 and the second PrAcc register 12A are connected, and the processor access pending is controlled by shifting the value of PrAcc from TDI into the first PrAcc register 11A or the second PrAcc register 12A.

  Next, a method for continuously writing data at consecutive addresses in the debug memory space to the data register 12 of this embodiment will be described using the flowchart of FIG.

  Here, a “download instruction” is provided as a new debugging instruction. When this “download instruction” is in the instruction register, in the Shift-DR state in the state of the TAP controller shown in FIG. 6, the value obtained by connecting the address register 11 and the first PrAcc register 11A is output from TDO as a shift-out output. In the Update-DR state, the value shifted in from TDI is written to the shift register shift formed by connecting the data register 12 and the second PrAcc register 12A.

  The address register 11 and the data register 12 are each composed of 32 bits.

  When it is in a situation where data at successive addresses in the debug memory space is continuously transferred to the microprocessor, a "download instruction" is first written to the instruction register (step S1).

  Next, when Select-DR → Capture-DR → Shift-DR × 32 times is executed under the control of the TAP controller, the value of the address register 11 and the value of the first PrAcc register 11A are shifted out to TDO, and TDI is output. Is shifted in and input as data to the data register 12 and PrAcc = 0 as a value to be written to the second PrAcc register 12A (step S2). At this time, as the data to be input to the data register 12, the value of the data stored at the next address is given to the TDI in anticipation of continuous addresses.

  Here, the value of the PrAcc signal shifted out is confirmed (step S3). The PrAcc value shifted out at this time is a value written by the microprocessor. When this value is “1”, the microprocessor requests debugging, and when it is “0”, it means that no debugging request is generated from the microprocessor.

  Therefore, when the shifted PrAcc signal value is “0”, Shift-DR is further executed to shift in PrAcc = 1 (step S4), and Update-DR is passed through the Exit1-DR state. The state is changed (step S5), PrAcc = 1 is written to the second PrAcc register 12A (step S6), and the process returns to step S2. However, the act of writing PrAcc = 1 to the second PrAcc register 12A is ignored in the EJTAG specification.

  On the other hand, when the PrAcc value read from the TDO is “1”, it is simultaneously determined whether or not the value of the address register 11 read from the TDO matches the expected address (step S7).

  When the value of the address register 11 read from the TDO matches the expected address (YES), since data to the data register 12 and PrAcc = 0 have already been input in step S2, the Exit1-DR state is changed. Then, the state transits to the Update-DR state (step S8). With this transition, the input data is written to the data register 12, and PrAcc = 0 is written to the PrAcc area 13A of the control register 13 (step S9).

  When PrAcc = 0 is written in the PrAcc area 13A of the control register 13, the pending processor access is released, and the microprocessor executes a certain process described in the program. After the execution of the process, when the microprocessor sets PrAcc = 1 in the PrAcc area 13A of the control register 13 again, the next continuous data input in step S2 is executed.

  On the other hand, if the PrAcc value read from the TDO is “0”, it can be determined that the end of the continuous data is stored in the address corresponding to the value of the address register 11 read from the TDO. As a data and PrAcc signal value, PrAcc = 0 is shifted in from TDI (step S10).

  Subsequently, a transition is made to the Update-DR state via the Exit1-DR state (step S11), and the data shifted in is written to the data register 12, and PrAcc = 0 is written to the PrAcc area 13A of the control register 13. (Step S12), execution of the “download instruction” is terminated.

  According to the above-described method, it is possible to continuously write data at consecutive addresses in the debug memory space to the data register only by writing the “download instruction” once in the instruction register. As a result, the number of processing clocks can be significantly reduced while the instruction code in the instruction register must be rewritten every time the address register and the data register are switched.

  For example, the number of clocks required for one data transfer is shown in parentheses after each state along the state transition of the TAP controller as follows.

  Select-DR (1)-> Capture-DR (1)-> Shift-DR (1) x 32-> Exit1-DR (1)-> Update-DR (1)-> Select-DR (1). . This is a significant reduction in the number of processing clocks compared to the conventional processing requiring 183 clocks, and data transfer can be performed at a high speed.

  FIG. 3 is a block diagram illustrating a configuration of a debug register according to the second embodiment of the present invention.

  The data register group 2 constituting the debug register includes a shift register 20, a PrAcc register 20A, an address register 21, a data register 22, and a control register 23. The control register 23 has a PrAcc area 23A as a PrAcc signal write area.

  In this embodiment, unlike the first embodiment, only the shift register 20 is connected to the input terminal (TDI), and the output of the PrAcc register 20A obtained by connecting the PrAcc register 20A to the shift register 20 or the output of the shift register 20 alone is the selector. 24 is selected and output to the output terminal (TDO). The selection depends on the type of debug instruction.

  The shift register 20 and the PrAcc register 20A have a parallel input function and a parallel output function, respectively. Data output in parallel from the shift register 20 is written to either the data register 22 or the control register 23. However, the PrAcc value output in parallel from the PrAcc register 20A can be written in the PrAcc area 23A of the control register 23.

  On the other hand, data output from any one of the address register 21, the data register 22, and the control register 23 is input in parallel to the shift register 20. However, the PrAcc value output from the PrAcc area 23A of the control register 23 is input in parallel to the PrAcc register 20A.

  With such a configuration, shift-in input and shift-out output to the address register 21, data register 22, and control register 23 of this embodiment can be performed using one shift register 20 and one PrAcc register 20A.

  When data at consecutive addresses in the debug memory space is continuously written in the data register 22 of the present embodiment, a “download instruction” is newly provided as in the first embodiment. However, the “download instruction” in this embodiment functions as follows.

  That is, in this embodiment, when the “download instruction” is in the instruction register, in the Capture-DR state of the TAP controller, the data output in parallel from the address register 21 is input in parallel to the shift register 20 and the PrAcc of the control register 23 is input. The PrAcc value output from the area 23A is input in parallel to the PrAcc register 20A. In the Shift-DR state, the address value and PrAcc value input in the Capture-DR state are shifted out to TDO, and at the same time, data to be written to the data register and PrAcc value are shifted in from TDI. Further, in the Update-DR state, the shift-in input data is written to the data register 22, and the PrAcc value is written to the PrAcc area 23A of the control register 23.

  By executing the flow shown in FIG. 2 using such a “download instruction”, in this embodiment as well as in the first embodiment, data at consecutive addresses in the debug memory space is transferred with a small number of clocks. You can write to the register.

  According to the configuration of the data register group of this embodiment, only one shift register connected to the input terminal (TDI) is provided for the address register, the data register, and the control register, and the circuit configuration is simplified. Can be

1 is a block diagram showing a configuration of a debug register according to Embodiment 1 of the present invention. The flowchart which shows the flow of the data transfer method concerning the Example of this invention. FIG. 9 is a block diagram illustrating a configuration of a debug register according to the second embodiment of the present invention. The figure which shows the debugging system using EJTAG. The block diagram which shows the example of a structure of TAP of the microprocessor based on EJTAG. The state transition diagram of the TAP controller of the microprocessor based on EJTAG.

Explanation of symbols

1, 2 Data register group 11, 21 Address register 12, 22 Data register 13, 23 Control register 11A, 12A, 20A PrAcc register 13A, 23A PrAcc area 14, 24 Selector 20 Shift register

Claims (5)

A debugging register mounted on an EJTAG compliant microprocessor,
An address register;
A data register;
A first PrAcc register storing a PrAcc signal that controls pending processor access;
A second PrAcc register in which the PrAcc signal is stored;
A debug register comprising a control register having a PrAcc area in which the PrAcc signal is written.   Depending on the type of debug instruction, the address register and the first PrAcc register are connected and used as one shift register, and the data register and the second PrAcc register are connected and used as one shift register. The debugging register according to claim 1, wherein: A debugging register mounted on an EJTAG compliant microprocessor,
A shift register having parallel input and parallel output functions;
A PrAcc register having a parallel input and parallel output function and storing a PrAcc signal for controlling the pending of processor access;
An address register to which data output in parallel from the shift register is written;
A data register to which data output in parallel from the shift register is written;
A control register having a PrAcc bit area into which data output in parallel from the shift register and the PrAcc register is written, and data output in parallel from the PrAcc area in the address register and the control register A debugging register, wherein the PrAcc register is inputted in parallel.   4. The debugging register according to claim 3, wherein the shift register and the PrAcc register are connected to be used as one shift register depending on a type of debugging instruction. A method of transferring data to a debug register of an EJTAG compliant microprocessor comprising an address register, a data register, and a PrAcc register as debug registers,
Simultaneously shifting out data from the address register and the PrAcc register and shifting data into the data register and the PrAcc register, and shifting in when the value of the shifted out address register is the expected value An instruction to execute writing of data into the data register and the PrAcc register;
When sequentially acquiring data from successive addresses in the debug memory space and sequentially writing to the data register, use the instruction,
When executing the instruction, as the data to be shifted in, the data acquired from the address that is expected to be accessed next and the PrAcc data for controlling the pending of the processor access so that the debugging is continuously executed are input. A data transfer method characterized by the above.

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