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JP2006140258A - Resin-sealing semiconductor device - Google Patents

Resin-sealing semiconductor device Download PDF

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Publication number
JP2006140258A
JP2006140258A JP2004327499A JP2004327499A JP2006140258A JP 2006140258 A JP2006140258 A JP 2006140258A JP 2004327499 A JP2004327499 A JP 2004327499A JP 2004327499 A JP2004327499 A JP 2004327499A JP 2006140258 A JP2006140258 A JP 2006140258A
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JP
Japan
Prior art keywords
resin
semiconductor device
sealing
lead terminal
sealed
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2004327499A
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Japanese (ja)
Inventor
Yuji Morinaga
雄司 森永
Yoshimasa Kobayashi
義政 小林
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Shindengen Electric Manufacturing Co Ltd
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Shindengen Electric Manufacturing Co Ltd
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Priority to JP2004327499A priority Critical patent/JP2006140258A/en
Publication of JP2006140258A publication Critical patent/JP2006140258A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a novel resin-sealing semiconductor device for reducing wire disconnection failures due to generation of cracks. <P>SOLUTION: The resin-sealing semiconductor device 10 is formed by electrically connecting a semiconductor element 1 and a lead terminal 3, and then sealing these components with resin. In this resin-sealing semiconductor device 10, a non-resin-sealed part 5, exposed from the resin sealing part 4 formed by resin-sealing of a part including a side surface of the lead terminal, is provided, when the semiconductor element and lead terminal are sealed with resin. A recess 6 is then formed by punching or etching a part or the entire part of the side edge of the non-resin-sealing part. The non-resin-sealing part, where the recess is formed, can be physically connected with an external circuit 20. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、半導体素子とリード端子とを電気的に接続し、これらを樹脂封止してなる樹脂封止型半導体装置に関するものである。   The present invention relates to a resin-encapsulated semiconductor device in which a semiconductor element and a lead terminal are electrically connected and these are resin-encapsulated.

従来の半導体素子１とリード端子３とを接続し、これらを樹脂封止してなる樹脂封止型半導体装置１１を、図４乃至図６に示す。具体的には、図４は、樹脂封止型半導体装置１１と外部回路（プリント基板）２０とを物理的に接続した状態の透過斜視図を示し、図５及び図６は、樹脂封止型半導体装置１１の底面図及び図４図示Ｂ−Ｂ断面図を示す。   4 to 6 show a resin-encapsulated semiconductor device 11 in which a conventional semiconductor element 1 and lead terminals 3 are connected and these are resin-encapsulated. Specifically, FIG. 4 shows a transparent perspective view in a state where the resin-sealed semiconductor device 11 and the external circuit (printed circuit board) 20 are physically connected, and FIGS. 5 and 6 are resin-sealed types. The bottom view of the semiconductor device 11 and BB sectional drawing shown in FIG. 4 are shown.

この従来例に係る樹脂封止型半導体装置１１は、リード端子３ａ，３ｂを二つ設け、一方のリード端子３ａに半導体素子１を載置して、半導体素子１と一方のリード端子３ａとを電気的に接続してある。他方のリード端子３ｂに対しては、半導体素子１とリード端子３ｂとを金属ワイヤーなどの接続子２を用いて接続して、半導体素子１と他方のリード端子３ｂとを電気的に接続してある。これらを樹脂封止する。その際、リード端子３ａ，３ｂの一部を樹脂封止部４より露出させ、露出した部分に端子部７を設けて、リード端子３ａ，３ｂと外部回路２０と物理的に接続していた（例えば、特許文献１参照）。
特開２００１−３３２６７５公報 The resin-encapsulated semiconductor device 11 according to this conventional example is provided with two lead terminals 3a and 3b, the semiconductor element 1 is placed on one lead terminal 3a, and the semiconductor element 1 and one lead terminal 3a are connected. It is electrically connected. For the other lead terminal 3b, the semiconductor element 1 and the lead terminal 3b are connected using a connector 2 such as a metal wire, and the semiconductor element 1 and the other lead terminal 3b are electrically connected. is there. These are resin-sealed. At that time, a part of the lead terminals 3a, 3b was exposed from the resin sealing part 4, and the terminal part 7 was provided in the exposed part to physically connect the lead terminals 3a, 3b and the external circuit 20 ( For example, see Patent Document 1).
JP 2001-332675 A

しかし、従来の樹脂封止型半導体装置は、リード端子３ａ，３ｂの概ね底面を樹脂封止部４より露出させて、外部回路２０と物理的に接続させる端子部７を設けていたため、はんだがぬれる量が少なく、はんだの厚さが薄くなるため、クラックが発生するなどの断線不良が生じるおそれがあった。また、端子部７はリード端子３ａ，３ｂの概ね底面に設けてあるため、外部回路２０と物理的に接続した際の状態が確認し難いという課題もある。   However, since the conventional resin-encapsulated semiconductor device is provided with the terminal portion 7 that exposes the substantially bottom surfaces of the lead terminals 3a and 3b from the resin-encapsulated portion 4 and is physically connected to the external circuit 20, the solder is removed. Since the amount of wetting is small and the thickness of the solder is thin, there is a possibility that a disconnection failure such as a crack may occur. In addition, since the terminal portion 7 is provided on substantially the bottom surface of the lead terminals 3a and 3b, there is a problem that it is difficult to confirm the state when physically connected to the external circuit 20.

本発明は、上記問題に鑑みてなされたものであり、クラックの発生による断線不良を低減することができる新規な樹脂封止型半導体装置を提供する。   The present invention has been made in view of the above problems, and provides a novel resin-encapsulated semiconductor device that can reduce disconnection failure due to the occurrence of cracks.

上記課題を解決するために、本発明に係る樹脂封止型半導体装置は、半導体素子とリード端子とを電気的に接続し、これらを樹脂封止してなる樹脂封止型半導体装置において、前記半導体素子及びリード端子を樹脂封止した際に、前記リード端子の側面を含めた一部を樹脂封止してなる樹脂封止部より露出させて非樹脂封止部を設け、この非樹脂封止部の側縁の一部又は全部を打ち出し、若しくは、エッチングして凹部を形成して、前記凹部を形成した非封止樹脂部と外部回路とを物理的に接続できるように構成してあることを特徴とする。   In order to solve the above-described problems, a resin-encapsulated semiconductor device according to the present invention includes a resin-encapsulated semiconductor device in which a semiconductor element and a lead terminal are electrically connected, and these are resin-encapsulated. When the semiconductor element and the lead terminal are resin-sealed, a part including the side surface of the lead terminal is exposed from the resin-sealed part formed by resin sealing to provide a non-resin-sealed part. A part or all of the side edge of the stop portion is punched out or etched to form a recess so that the non-sealing resin portion formed with the recess can be physically connected to an external circuit. It is characterized by that.

本発明によれば、リード端子の一部を樹脂封止部より露出させて非樹脂封止部を設け、この非樹脂封止部の側縁に打ち出し、若しくは、エッチングして凹部を形成し、非樹脂封止部と凹部で外部回路と物理的に接続できるように構成してあることから、接合面積が増えて、はんだがぬれる量が従来より増え、はんだが厚くなるため、クラックの発生が低減でき、断線不良を低減することができる効果がある。   According to the present invention, a part of the lead terminal is exposed from the resin sealing portion to provide a non-resin sealing portion, and is punched out to the side edge of the non-resin sealing portion or etched to form a recess. Since it is configured so that it can be physically connected to the external circuit by the non-resin sealing part and the concave part, the joining area increases, the amount of solder wetting increases compared to the past, and the solder becomes thicker, so cracks occur It is possible to reduce the disconnection failure.

また、凹部を形成したことにより、リード端子の側縁も凹部があるためフィレットが形成され易く、半導体装置の側面にできるため、外部回路と接続した際の状態の確認が容易に行える効果がある。   In addition, since the concave portion is formed, the side edge of the lead terminal also has a concave portion, so that a fillet is easily formed and can be formed on the side surface of the semiconductor device, so that it is possible to easily confirm the state when connected to an external circuit. .

発明を実施するための最良の形態の構成図を図１乃至図４に示す。具体的には、図１は、樹脂封止型半導体装置１０と外部回路（プリント基板）２０とを物理的に接続した状態の透過斜視図を示し、図２及び図３は、樹脂封止型半導体装置１０の底面図及び図１図示Ａ−Ａ断面図を示す。なお、従来例と同様の部材については、本実施例において、同様の図番を付してある。   A configuration diagram of the best mode for carrying out the invention is shown in FIGS. Specifically, FIG. 1 shows a transparent perspective view of a state in which a resin-sealed semiconductor device 10 and an external circuit (printed circuit board) 20 are physically connected, and FIGS. 2 and 3 are resin-sealed types. The bottom view of the semiconductor device 10 and AA sectional drawing shown in FIG. 1 are shown. In addition, about the member similar to a prior art example, the same figure number is attached | subjected in a present Example.

この実施形態に係る樹脂封止型半導体装置１０は以下のように構成してある。リード端子３ａ，３ｂを二つ設けてある。一方のリード端子３ａは他方のリード端子３ｂより幅が広く、一方のリード端子３ａ上に半導体素子１を載置できるように構成してある。半導体素子１を一方のリード端子３ａ上に載置することにより、半導体素子１と一方のリード端子３ａとを電気的に接続してある。他方のリード端子３ｂに対しては、半導体素子１とリード端子３ｂとを金属ワイヤーなどの接続子２を用いて接続して、半導体素子１と他方のリード端子３ｂとを電気的に接続してある。   The resin-encapsulated semiconductor device 10 according to this embodiment is configured as follows. Two lead terminals 3a and 3b are provided. One lead terminal 3a is wider than the other lead terminal 3b, and the semiconductor element 1 can be placed on the one lead terminal 3a. By placing the semiconductor element 1 on one lead terminal 3a, the semiconductor element 1 and one lead terminal 3a are electrically connected. For the other lead terminal 3b, the semiconductor element 1 and the lead terminal 3b are connected using a connector 2 such as a metal wire, and the semiconductor element 1 and the other lead terminal 3b are electrically connected. is there.

リード端子３ａ，３ｂの側面を含めた一部に非樹脂封止部５を設けてある。この非樹脂封止部５は、半導体素子１及びリード端子３ａ，３ｂを樹脂封止する際に、樹脂封止部４より露出する部分である。本実施形態においては、この非樹脂封止部５の側縁の一部を打ち出して凹部６を形成してある。なお、凹部６はエッチングして形成することも可能である。以上のようにリード端子３ａ，３ｂを構成し、半導体素子１及びリード端子３ａ，３ｂを樹脂封止する。その際、リード端子３ａ，３ｂの非樹脂封止部５の一部を端子部７とし、リード端子３ａ，３ｂとプリント基板で構成した外部回路２０と物理的に接続できるように構成してある。   The non-resin sealing part 5 is provided in a part including the side surfaces of the lead terminals 3a and 3b. The non-resin sealing portion 5 is a portion exposed from the resin sealing portion 4 when the semiconductor element 1 and the lead terminals 3a and 3b are resin-sealed. In this embodiment, a part of the side edge of the non-resin sealing portion 5 is punched out to form the recess 6. The concave portion 6 can also be formed by etching. The lead terminals 3a and 3b are configured as described above, and the semiconductor element 1 and the lead terminals 3a and 3b are sealed with resin. At that time, a part of the non-resin-sealed portion 5 of the lead terminals 3a and 3b is used as the terminal portion 7 so that the lead terminals 3a and 3b can be physically connected to the external circuit 20 formed of a printed board. .

以上のように構成してある本実施形態に係る樹脂封止型半導体装置１０は、従来の樹脂封止型半導体装置と同様に、リード端子３ａ，３ｂの底面に設けた端子部７と外部回路２０に設けた端子部２１との間に、はんだを塗ることにより、樹脂封止型半導体装置１０と外部回路２０とを物理的に接続することができる。   The resin-encapsulated semiconductor device 10 according to the present embodiment configured as described above includes the terminal portion 7 provided on the bottom surface of the lead terminals 3a and 3b and an external circuit, as in the conventional resin-encapsulated semiconductor device. The resin-encapsulated semiconductor device 10 and the external circuit 20 can be physically connected by applying solder between the terminal portion 21 provided on the terminal 20.

本実施形態に係る樹脂封止型半導体装置１０はリード端子３ａ，３ｂの一部を樹脂封止部４より露出させて非樹脂封止部５を設け、この非樹脂封止部５の側縁に打ち出しして凹部６を形成したことにより、樹脂封止型半導体装置１０と外部回路２０との接合面積が増えて、はんだがぬれる量が従来より増える。そのため、はんだが厚くなり、クラックの発生が低減でき、断線不良を低減することができる。   In the resin-encapsulated semiconductor device 10 according to the present embodiment, a part of the lead terminals 3a and 3b is exposed from the resin-encapsulated part 4, and a non-resin-encapsulated part 5 is provided. Since the recess 6 is formed by stamping, the bonding area between the resin-encapsulated semiconductor device 10 and the external circuit 20 is increased, and the amount of solder to be wet is increased compared to the conventional case. As a result, the solder becomes thick, the occurrence of cracks can be reduced, and disconnection defects can be reduced.

また、リード端子３ａ，３ｂの側縁に打ち出しして凹部６を形成したことにより、フィレットが形成され易い。さらに、図１で示すように、樹脂封止型半導体装置１０の側縁から凹部６を確認することができるため、樹脂封止型半導体装置１０と外部回路２０と接続した際の状態の確認が容易に行える。   Further, since the recess 6 is formed by punching out to the side edges of the lead terminals 3a and 3b, a fillet is easily formed. Further, as shown in FIG. 1, since the recess 6 can be confirmed from the side edge of the resin-encapsulated semiconductor device 10, the confirmation of the state when the resin-encapsulated semiconductor device 10 and the external circuit 20 are connected can be confirmed. Easy to do.

本発明によれば、リード端子の一部を樹脂封止部より露出させて非樹脂封止部を設け、この非樹脂封止部の側縁に打ち出し、若しくは、エッチングして凹部を形成し、非樹脂封止部と凹部で外部回路と物理的に接続できるように構成してあることから、接合面積が増えて、はんだがぬれる量が従来より増え、はんだが厚くなるため、クラックの発生が低減でき、断線不良を低減することができる。   According to the present invention, a part of the lead terminal is exposed from the resin sealing portion to provide a non-resin sealing portion, and is punched out to the side edge of the non-resin sealing portion or etched to form a recess. Since it is configured so that it can be physically connected to the external circuit by the non-resin sealing part and the concave part, the joining area increases, the amount of solder wetting increases compared to the past, and the solder becomes thicker, so cracks occur It is possible to reduce the disconnection failure.

また、凹部を形成したことにより、リード端子の側縁も凹部があるためフィレットが形成され易く、半導体装置の側面にできるため、外部回路と接続した際の状態の確認が容易に行える。   In addition, since the recesses are formed on the side edges of the lead terminals because the recesses are formed, a fillet is easily formed and the side surface of the semiconductor device can be formed. Therefore, the state when connected to an external circuit can be easily confirmed.

本発明に係る樹脂封止型半導体装置における発明を実施するための最良の形態の外部回路と物理的に接続した状態の透過斜視図である。1 is a transparent perspective view in a state physically connected to an external circuit of the best mode for carrying out the invention in a resin-encapsulated semiconductor device according to the present invention. FIG. 図１図示樹脂封止型半導体装置の底面図である。FIG. 2 is a bottom view of the resin-encapsulated semiconductor device illustrated in FIG. 1. 図１図示樹脂封止型半導体装置の図１図示Ａ−Ａ断面図である。FIG. 2 is a cross-sectional view of the resin-encapsulated semiconductor device illustrated in FIG. 従来の樹脂封止型半導体装置と外部回路とを物理的に接続した状態の透過斜視図である。It is a permeation | transmission perspective view of the state which connected the conventional resin-encapsulated semiconductor device and the external circuit physically. 図４図示樹脂封止型半導体装置の底面図である。FIG. 5 is a bottom view of the resin-encapsulated semiconductor device illustrated in FIG. 4. 図４図示樹脂封止型半導体装置の図４図示Ｂ−Ｂ断面図である。FIG. 5 is a sectional view of the resin-encapsulated semiconductor device shown in FIG.

符号の説明Explanation of symbols

１ 半導体素子
２ 接続子
３ａ，３ｂ リード端子
４ 樹脂封止部
５ 非樹脂封止部
６ 凹部
７ 端子部
１０，１１ 樹脂封止型半導体装置
２０ 外部回路（プリント基板）
２１ 外部回路２０の端子部 DESCRIPTION OF SYMBOLS 1 Semiconductor element 2 Connector 3a, 3b Lead terminal 4 Resin sealing part 5 Non-resin sealing part 6 Recessed part 7 Terminal part 10, 11 Resin sealing type semiconductor device 20 External circuit (printed circuit board)
21 Terminal of external circuit 20

Claims (1)

半導体素子とリード端子とを電気的に接続し、これらを樹脂封止してなる樹脂封止型半導体装置において、前記半導体素子及びリード端子を樹脂封止した際に、前記リード端子の側面を含めた一部を樹脂封止してなる樹脂封止部より露出させて非樹脂封止部を設け、この非樹脂封止部の側縁の一部又は全部を打ち出し、若しくは、エッチングして凹部を形成して、前記凹部を形成した非封止樹脂部と外部回路とを物理的に接続できるように構成してあることを特徴とする樹脂封止型半導体装置。 In a resin-encapsulated semiconductor device in which a semiconductor element and a lead terminal are electrically connected and sealed with resin, when the semiconductor element and the lead terminal are sealed with resin, the side surfaces of the lead terminal are included. A part of the non-resin-sealed part is exposed by exposing the part from the resin-sealed part formed by resin-sealing, and a part or all of the side edge of the non-resin-sealed part is punched out or etched to form the recess. A resin-encapsulated semiconductor device, wherein the non-encapsulated resin portion formed with the concave portion and an external circuit can be physically connected.
JP2004327499A 2004-11-11 2004-11-11 Resin-sealing semiconductor device Pending JP2006140258A (en)

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WO2007135949A1 (en) 2006-05-19 2007-11-29 Fujikura Ltd. Method for producing electrode substrate, electrode substrate, photoelectric converter and dye-sensitized solar cell
JP2015195389A (en) * 2015-06-17 2015-11-05 大日本印刷株式会社 Semiconductor device and manufacturing method thereof

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JP2000294719A (en) * 1999-04-09 2000-10-20 Hitachi Ltd Lead frame, semiconductor device using the same, and method of manufacturing the same
JP2000294715A (en) * 1999-04-09 2000-10-20 Hitachi Ltd Semiconductor device and method of manufacturing semiconductor device
JP2001077271A (en) * 1999-09-01 2001-03-23 Matsushita Electronics Industry Corp Lead frame and manufacture of resin sealed semiconductor device using the same
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JP2000294715A (en) * 1999-04-09 2000-10-20 Hitachi Ltd Semiconductor device and method of manufacturing semiconductor device
JP2001077271A (en) * 1999-09-01 2001-03-23 Matsushita Electronics Industry Corp Lead frame and manufacture of resin sealed semiconductor device using the same
JP2004207275A (en) * 2002-12-20 2004-07-22 Sanyo Electric Co Ltd Circuit device and its manufacturing method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007135949A1 (en) 2006-05-19 2007-11-29 Fujikura Ltd. Method for producing electrode substrate, electrode substrate, photoelectric converter and dye-sensitized solar cell
JP2015195389A (en) * 2015-06-17 2015-11-05 大日本印刷株式会社 Semiconductor device and manufacturing method thereof

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