JP2006134400A - Method of reading storage device, storage device, and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To read a memory element even when it is insufficient to separate a read-out bias area from a write bias area or an erasure bias area. <P>SOLUTION: The method for reading the storage device, in which memory elements are arranged in matrix, is constituted so that the same voltage as applied voltage of the memory element is applied. When applied voltage of the memory element is changed, a variation point of a resistance value of the memory element is detected based on difference between applied voltage of a comparing circuit constituted so that applied voltage is changed a prescribed time after the applied voltage of the memory element is changed, and a state of the resistance value of the memory element is discriminated based on whether or not there is the polarity of applied voltage to the memory cell and the change point of the resistance value of the memory cell. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a reading method of a storage device, a storage device, and a semiconductor device. Specifically, the present invention relates to a reading method of a memory device including a memory cell using a memory element that stores and holds information according to an electrical resistance state, such a memory device, and a semiconductor device having such a memory device.

In information devices such as computers, DRAM (Dynamic Random Access Memory) having a high-speed operation and a high density is widely used as a random access memory.
However, since DRAM is a volatile memory in which information disappears when the power is turned off, a nonvolatile memory in which information does not disappear is desired.

  As nonvolatile memories which are expected to be promising in the future, resistance change type memories such as FeRAM (ferroelectric memory), MRAM (magnetic memory), phase change memory, PMC (Programmable Metallization Cell), and RRAM have been proposed. (For example, refer nonpatent literature 1.).

  In the case of these memories, it is possible to keep the written information for a long time without supplying power. In addition, in the case of these memories, it is considered that by making them non-volatile, the refresh operation is unnecessary and power consumption can be reduced accordingly.

  Hereinafter, the resistance change memory will be described with reference to the drawings. Here, a resistance change memory using a resistance change memory element (hereinafter referred to as a memory element) as a memory cell will be described.

FIG. 7 is a graph showing a change in current-voltage (IV) of a memory element used in a conventional resistance change type memory. This memory element has a small resistance value in the initial state, but the + X [ A] When the above current flows, the resistance value increases. The resistance value is a constant value, and then continues to hold the resistance value (high resistance value) even if the current is returned to 0A.
Note that the operation of changing the memory element from a low resistance state to a high state is defined as writing, and the applied current at this time is defined as a writing current threshold value.

Next, when a current is passed through the memory element in the opposite direction and the current value is increased, the resistance value decreases at -X [A] in FIG. 7, and the resistance value is reduced to the same low value as in the initial state. Change. Thereafter, even when the current is returned to 0 A, the resistance value (low resistance value) is kept.
Note that an operation for changing the resistance value of the memory element from a high state to a low state is defined as erasing, and the applied current at this time is defined as an erasing current threshold.

  In this way, the resistance value of the memory element can be reversibly changed by flowing positive and negative currents through the memory element. In addition, when no current flows through the memory element, that is, when the current is 0 A, two states of a low resistance state and a high resistance state can be taken, and by correlating these states with data 1 and 0, One-bit data can be stored.

  Here, when the operation of determining whether the resistance value of the memory element is low or high is defined as reading, the reading of the conventional memory element is performed by the bias of the readable memory element (hereinafter referred to as reading bias). The memory element can be erased by applying a voltage once under the condition and the bias of the writable memory element (hereinafter referred to as the write bias), or by the read bias condition and the erasable memory element. This is done by applying a voltage once under a bias (hereinafter referred to as erase bias) condition.

Specifically, when a current is applied in the writing direction, the resistance value of the memory element having a low resistance value is R _L , and the resistance value of the memory element having a high resistance value is R _H , _RL and R _{Assuming that} the intermediate resistance value of _H is R, first, the resistance value of the memory element and the write bias condition (FIG. 8A) under the read bias condition (the condition indicated by the symbol α in FIGS. 8A and 8B). ), (B) The condition indicated by the symbol β in the figure) is measured for the resistance value of the memory element. When the resistance value of the memory element under the read bias condition is smaller than R and the resistance value of the memory element under the write bias condition is larger than R, the state before the memory element is read (hereinafter referred to as “read”). It is determined that the resistance value is low (refer to FIG. 8A), and the resistance value of the memory element under both the read bias condition and the write condition is lower than R. If it is larger, it is determined that the initial state of the memory element is a state in which the resistance value is high (see FIG. 8B).

  On the other hand, when a current is applied in the erasing direction, the resistance value of the memory element and the erasing bias condition (FIG. 8 (c)) under the read bias condition (the condition indicated by the symbol α in FIGS. 8 (c) and 8 (d)). ) And (d) under the condition indicated by symbol β), the resistance value of the memory element is measured. When the resistance value of the memory element under the read bias condition is larger than R and the resistance value of the memory element under the erase bias condition is smaller than R, the initial state of the memory element is a state in which the resistance value is high. (See FIG. 8C.) When the resistance value of the memory element under the read bias condition and the erase bias condition is both smaller than R, the initial resistance value of the memory element is low. It is determined that it is in a state (see FIG. 8D).

Nikkei Electronics Nikkei Business Publications, No. 789, February 12, 2001

  By the way, the above-described conventional reading of the memory device is based on the premise that the reading bias region and the writing bias region or the erasing bias region can be separated. However, writing and erasing a large number of memory devices with the same reference are performed. In such a case, the read bias region and the write bias region or the erase bias region may not be sufficiently separated due to process variations during the manufacture of the memory element.

In recent LSIs, the range of voltage that can be applied to the memory element tends to become smaller as the process proceeds, so the read bias region and the write bias region or the erase bias region may not be sufficiently separated.
For example, when the power supply voltage is 2.5 V, even if the read bias region indicated by symbol a in FIG. 9 and the write bias region indicated by symbol b in FIG. 9 can be separated (see FIG. 9A). When the power supply voltage is 1.5 V, the read bias region and the write bias region may not be separated even with the same memory element (see FIG. 9B).

  As described above, when the read bias region and the write bias region or the erase bias region cannot be separated, the conventional read method described above cannot read the memory element.

  The present invention has been made in view of the above points, and a memory capable of realizing reading of a memory element even when the read bias region and the write bias region or the erase bias region are not sufficiently separated. An object of the present invention is to provide a device reading method, a storage device, and a semiconductor device.

  In order to achieve the above object, a reading method of a storage device according to the present invention changes from a low resistance state to a high resistance state by applying an electric signal equal to or higher than a first threshold signal, A reading method of a memory device in which memory elements having a characteristic that a resistance value changes from a high state to a low state by applying an electric signal equal to or higher than a second threshold signal having a polarity different from that of the threshold signal are arranged in a matrix A step of applying an electric signal equal to or higher than a first threshold signal or an electric signal equal to or higher than a second threshold signal to the memory element and detecting a change point of a resistance value of the memory element; And determining the state of the resistance value of the memory element based on the polarity of the electric signal applied to and the presence or absence of a change point of the resistance value of the memory element.

  Here, an electrical signal equal to or higher than the first threshold signal or an electrical signal equal to or higher than the second threshold signal is applied to the memory element, and a change point of the resistance value of the memory element is detected, whereby the read bias condition and the writing are It can be determined whether or not the resistance value of the memory element has changed without measuring the resistance value of the memory element under the bias condition or the erase bias condition. That is, when the change point of the resistance value of the memory element is detected, it can be understood that the resistance value of the memory element has changed by the application of the electric signal, and when the change point of the resistance value of the memory element is not detected, the electric signal It can be seen that the resistance value of the memory element is not changed by the application of.

  Then, the state of the resistance value of the memory element can be determined based on the polarity of the electrical signal applied to the memory element and the presence or absence of a change point of the resistance value of the memory element. That is, when an electrical signal equal to or higher than the first threshold signal is applied to the memory element, the memory element after reading is in a written state and has a high resistance value regardless of the initial state of the memory element. Therefore, when the change point of the resistance value of the memory element is detected, it is understood that the resistance value of the memory element before reading is low, and when the change point of the resistance value of the memory element is not detected, reading is performed. It can be seen that the resistance value of the previous memory element is high. On the other hand, when an electrical signal equal to or higher than the second threshold signal is applied to the memory element, the memory element after reading is erased and the resistance value is low regardless of the initial state of the memory element. Therefore, when the change point of the resistance value of the memory element is detected, the resistance value before reading is found to be high, and when the change point of the resistance value of the memory element is not detected, the memory before reading is stored. It can be seen that the resistance value of the element is low.

  In order to achieve the above object, the storage device of the present invention changes from a low resistance value to a high resistance state by applying an electric signal equal to or higher than the first threshold signal, and the first threshold value A storage device in which storage elements having a characteristic that a resistance value changes from a high state to a low state by applying an electric signal equal to or higher than a second threshold signal having a polarity different from that of a signal is arranged in a matrix, A reading circuit for detecting a change point of the resistance value of the memory element is provided.

  Here, the resistance value of the memory element is measured without measuring the resistance value of the memory element under the read bias condition and the write bias condition or the erase bias condition by the read circuit that detects the change point of the resistance value of the memory element. You can see if has changed.

  In order to achieve the above object, the semiconductor device of the present invention changes from a low resistance state to a high state by applying an electric signal equal to or higher than the first threshold signal, and the first threshold value A semiconductor device having a memory device in which memory elements having a characteristic in which a resistance value changes from a high state to a low state when an electric signal equal to or higher than a second threshold signal having a polarity different from that of a signal is applied are arranged in a matrix And the same voltage as the voltage applied to the memory element is applied, and when the voltage applied to the memory element changes, a delay of a predetermined time from the time when the voltage applied to the memory element changes. And a detection circuit configured to detect a change point of the resistance value of the storage element from a difference between the application voltage of the storage element and the application voltage of the comparison circuit.

  Here, the voltage applied to the memory element is configured to be the same as the voltage applied to the memory element, and when the voltage applied to the memory element changes, the voltage applied to the memory element changes from the time of change. The detection circuit that detects the change point of the resistance value of the memory element from the difference in the applied voltage of the comparison circuit configured to change the applied voltage with a predetermined time delay, and thereby the read bias condition and the write bias condition or the erase bias It can be determined whether or not the resistance value of the memory element has changed without measuring the resistance value of the memory element under the conditions.

  In the reading method, the storage device, and the semiconductor device of the above-described storage device of the present invention, separation of the bias region is a problem even when the read bias region and the write bias region or the erase bias region are not sufficiently separated. Thus, reading of the memory element can be performed.

Hereinafter, embodiments of the present invention will be described with reference to the drawings to provide an understanding of the present invention.
FIG. 1 is a circuit diagram for explaining an example of a memory device to which the present invention is applied. The readout circuit 1 shown here is a resistance change type memory element having IV characteristics as shown in FIG. (Hereinafter referred to as a memory element.) A is connected to a memory cell C formed by connecting a MOS transistor T in series with A. Specifically, one end of the memory element is connected to one end of the MOS transistor, the gate of the MOS transistor is connected to the word line W, the other end of the memory element is connected to the bit line, and the other end of the MOS transistor is grounded (ground potential). The read circuit is connected to the bit line.

  The readout circuit shown here includes a first operational amplifier 2, a second operational amplifier 3, a third operational amplifier 4, a fourth operational amplifier 5, a first p-type MOS transistor 6, a second p-type MOS transistor 7, 3 p-type MOS transistor 8, first n-type MOS transistor 9, and first capacitor element 10.

  An external input voltage V is input to the negative phase input side of the first operational amplifier, a bit line potential is input to the positive phase input side, and the output side of the first operational amplifier is connected to the gate of the first p-type MOS transistor. In addition to being connected, they are connected to the negative phase input sides of the third operational amplifier and the fourth operational amplifier. Note that one end of the first p-type MOS transistor is connected to a bit line.

  An external input voltage V is input to the negative phase input side of the second operational amplifier, and the same voltage as the voltage applied to one end of the first n-type MOS transistor is input to the positive phase input side. The output side of the operational amplifier is connected to the gate of the second p-type MOS transistor and to the positive phase input side of the third operational amplifier and the fourth operational amplifier. One end of the second p-type MOS transistor is connected to one end of the first n-type MOS transistor, and the other end of the first n-type MOS transistor is grounded (ground potential).

  The output side of the third operational amplifier is grounded (ground potential) via the first capacitor element and is connected to the gate of the first n-type MOS transistor. The output side of the fourth operational amplifier is It is connected to the gate of the third p-type MOS transistor. Note that one end of the third p-type MOS transistor is grounded (ground potential) via the external resistor 11.

Hereinafter, the operation of the readout circuit configured as described above will be described.
First, in the readout circuit configured as described above, a bit line clamp voltage is applied as an external input voltage to the negative phase input side of the first operational amplifier. Specifically, the voltage applied to the negative phase input side of the first operational amplifier is a low voltage of about 0.1 V, and a bias voltage at the time of reading the memory element is applied.
In addition, the clamp voltage of the first n-type MOS transistor is input as an external input voltage to the negative phase input side of the second operational amplifier. Note that the voltage applied to the negative phase input of the second operational amplifier is set to the same voltage as the voltage applied to the negative phase input of the first operational amplifier, so that the voltage at the point indicated by X in FIG. The voltage at the point indicated by the middle symbol Y is equal.

By applying an external input voltage to the negative-phase input side of the first operational amplifier as described above, the voltage at the point indicated by the symbol X in FIG. 1 is the bit line clamp voltage (0.1 V). The gate voltage VP1 of the first p-type MOS transistor is output so that
Similarly, by applying an external input voltage to the opposite phase input side of the second operational amplifier as described above, the second operational amplifier has the voltage at the point indicated by symbol Y in FIG. The gate voltage VP2 of the second p-type MOS transistor is output so that the clamp voltage (0.1 V) is obtained.

  When the output voltage VP1 of the first operational amplifier is applied to the negative phase input side and the output voltage VP2 of the second operational amplifier is applied to the positive phase input side, the third operational amplifier has a difference between VP1 and VP2. The gate voltage Vb of the first n-type MOS transistor is output so as to eliminate this. At this time, the current I1 flowing through the first n-type MOS transistor and the current I2 flowing through the memory element have a proportional relationship, and I1 = αI2 (α: proportional constant).

  Now, the case where the memory element is read by the read circuit configured as described above will be described separately for (1) when a current is applied in the write direction and (2) when a current is applied in the erase direction.

(1) When reading is performed by applying a current in the writing direction [A] When the initial state of the memory element is a low resistance value When the initial state of the memory element is a low resistance value, the external input voltage When the value of the current flowing through the memory element reaches the write current threshold value and writing is performed and the resistance value changes from a low state to a high state, the output voltage VP1 of the first operational amplifier rises substantially simultaneously. (See symbol VP1 in FIG. 2 (a)).
Further, when the current value flowing through the memory element reaches the write current threshold value and writing is performed and the resistance value changes from a low state to a high state, the output voltage VP2 of the second operational amplifier also increases (FIG. 2). (See (a) middle sign VP2.) In order to increase the output voltage VP2, it is necessary to charge the capacitance of the first capacitor element. Then, while the capacitance of the first capacitor element is charged, the output voltage Vb of the third operational amplifier decreases (see FIG. 2B).
Here, when the output voltage Vb of the third operational amplifier decreases, the output voltage Vc of the fourth operational amplifier also decreases (see FIG. 2C).

[B] When the initial state of the memory element is a state with a high resistance value When the initial state of the memory element is a state with a high resistance value, the external input voltage is increased and the value of the current flowing through the memory element is the write current. Even if the threshold value is reached, the resistance value does not change.
Accordingly, since the output voltage VP1 of the first operational amplifier and the output voltage VP2 of the second operational amplifier do not change (see FIG. 3A), the output voltage of the third operational amplifier does not change (FIG. 3B). As a result, the output voltage of the fourth operational amplifier does not change (see FIG. 3C).

  Accordingly, when reading is performed by applying a voltage in the writing direction, if the output voltage of the fourth operational amplifier is changed, the initial state of the memory element is a low resistance value, and the output voltage of the fourth operational amplifier is low. If there is no change, it can be determined that the initial state of the memory element has a high resistance value.

(2) When reading is performed by applying a current in the erasing direction [C] When the initial state of the memory element is a high resistance value When the initial state of the memory element is a high resistance value, the external input voltage When the value of the current flowing through the memory element reaches the erase current threshold and erase is performed and the resistance value changes from a high state to a low state, the output voltage VP1 of the first operational amplifier decreases substantially at the same time. (See symbol VP1 in FIG. 4 (a)).
When the value of the current flowing through the memory element reaches the erase current threshold and erasing is performed and the resistance value changes from a high state to a low state, the output voltage VP2 of the second operational amplifier also decreases (FIG. 4). (See (a) the middle sign VP2.) In order to reduce the output voltage VP2, it is necessary to discharge the capacitance of the first capacitor element. Then, while discharging the capacitance of the first capacitor element, the output voltage Vb of the third operational amplifier rises (see FIG. 4B).
Here, when the output voltage Vb of the third operational amplifier rises, the output voltage of the fourth operational amplifier also rises (see FIG. 4C).

[D] When the initial state of the memory element is a state with a low resistance value When the initial state of the memory element is a state with a low resistance value, the external input voltage is increased and the value of the current flowing through the memory element becomes the erase current. Even if the threshold value is reached, the resistance value does not change.
Therefore, since the output voltage VP1 of the first operational amplifier and the output voltage VP2 of the second operational amplifier do not change (see FIG. 5A), the output voltage of the third operational amplifier does not change (FIG. 5B). As a result, the output voltage of the fourth operational amplifier does not change (see FIG. 5C).

  Accordingly, when reading is performed by applying a voltage in the erasing direction, if the output voltage of the fourth operational amplifier is changed, the initial state of the memory element is a high resistance value, and the output voltage of the fourth operational amplifier is high. If there is no change, it can be determined that the initial state of the memory element has a low resistance value.

  Note that since the above-described reading method is so-called destructive reading in which writing or erasing is performed while reading is performed, when the resistance value of the memory element changes after reading, processing for returning the memory element to the state before reading is performed. It is necessary to rewrite or re-erase. However, when the resistance value of the memory element is not changed by the read operation, rewriting or erasing is not necessary.

  In an example of a memory device to which the present invention is applied, the initial state of the memory element can be determined based on the change in the output voltage of the fourth operational amplifier and the current application direction (write direction or erase direction). The memory element can be read without causing a problem of region separation.

  FIG. 6 is a circuit diagram for explaining another example of a memory device to which the present invention is applied. The read circuit shown here is connected to a memory cell in the same manner as the example of the memory device to which the present invention is applied. Has been.

  The readout circuit shown here includes a fifth operational amplifier 12, a sixth operational amplifier 13, a fourth p-type MOS transistor 14, a fifth p-type MOS transistor 15, a second n-type MOS transistor 16, and a second capacitor. It is composed of an element 17.

  An external input voltage V is input to the negative phase input side of the fifth operational amplifier, and the same voltage as the voltage applied to one end of the second n-type MOS transistor is input to the positive phase input side. Is connected to the gates of the fourth p-type MOS transistor and the fifth p-type MOS transistor.

One end of the fourth p-type MOS transistor is connected to one end of the second n-type MOS transistor, and is connected to the positive phase input side of the sixth operational amplifier. The other end of the second n-type MOS transistor is grounded (ground potential).
Furthermore, one end of the fifth p-type MOS transistor is connected to the bit line and also connected to the negative phase input side of the sixth operational amplifier.

  The output side of the sixth operational amplifier is connected to the gate of the second n-type MOS transistor and grounded (ground potential) via the second capacitor element.

Hereinafter, the operation of the readout circuit configured as described above will be described.
First, in the readout circuit configured as described above, an external input voltage V is applied to the negative phase input side of the fifth operational amplifier.

  When the external input voltage V is applied, the fifth operational amplifier outputs the gate voltages of the fourth p-type MOS transistor and the fifth p-type MOS transistor, and the external input voltage V and the positive-phase input side of the sixth operational amplifier Is adjusted so that the voltage (NodeA) to be applied is equal.

  Further, the sixth operational amplifier outputs the gate voltage of the second n-type MOS transistor, and the voltage (NodeB) applied to the negative phase input side of the sixth operational amplifier is adjusted to be equal to NodeA. . This adjustment adjusts the fifth operational amplifier.

  After these adjustments, the external input potential V, NodeA, and NodeB become the same potential, and the external input voltage V becomes the clamp voltage of the memory element. At this time, the current I3 flowing through the second n-type MOS transistor and the current I2 flowing through the memory element have a proportional relationship, and I3 = βI2 (β: proportional constant).

  In the read circuit configured as described above, as in the example of the read circuit to which the present invention is applied, the external input voltage is increased, and the current value flowing through the memory element is changed to the write current threshold value or the erase current threshold value. The initial state of the memory element can be determined on the basis of the change in the output voltage of the sixth operational amplifier and the current application direction at the time of reaching the threshold value. Can be done.

  Note that in a read circuit used in another example of the memory device to which the present invention is applied, the first operational amplifier, the second operational amplifier, and the third operational amplifier in the read circuit used in the example of the above-described memory device to which the present invention is applied. This function is performed by the fifth operational amplifier and the sixth operational amplifier. In particular, the sixth operational amplifier performs the functions of the second operational amplifier and the third operational amplifier, thereby reducing the number of circuits.

It is a circuit diagram for explaining an example of a storage device to which the present invention is applied. It is a graph (1) which shows the output voltage of each operational amplifier. It is a graph (2) which shows the output voltage of each operational amplifier. It is a graph (3) which shows the output voltage of each operational amplifier. It is a graph (4) which shows the output voltage of each operational amplifier. It is a circuit diagram for demonstrating another example of the memory | storage device to which this invention is applied. It is a graph which shows the current-voltage change of the memory element used for the conventional resistance change memory. It is a schematic diagram for demonstrating the conventional reading method. It is a schematic diagram for demonstrating isolation | separation of a read bias area | region and a write bias area | region.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Read circuit 2 1st operational amplifier 3 2nd operational amplifier 4 3rd operational amplifier 5 4th operational amplifier 6 1st p-type MOS transistor 7 2nd p-type MOS transistor 8 3rd p-type MOS transistor 9 1st N-type MOS transistor 10 first capacitor element 11 external resistor 12 fifth operational amplifier 13 sixth operational amplifier 14 fourth p-type MOS transistor 15 fifth p-type MOS transistor 16 second n-type MOS transistor 17 Second capacitor element

Claims (5)

When an electric signal equal to or higher than the first threshold signal is applied, the resistance value changes from a low state to a high state, and an electric signal equal to or higher than the second threshold signal having a polarity different from that of the first threshold signal is applied. A memory device reading method in which memory elements having a characteristic in which a resistance value changes from a high state to a low state by being arranged in a matrix form,
Applying an electrical signal greater than or equal to a first threshold signal or an electrical signal greater than or equal to a second threshold signal to the memory element and detecting a change point of the resistance value of the memory element;
And a step of determining the state of the resistance value of the memory element based on the polarity of the electric signal applied to the memory element and the presence or absence of a change point of the resistance value of the memory element. The change point of the resistance value of the memory element is
An applied voltage of the memory element;
The same voltage as the voltage applied to the memory element is applied, and when the voltage applied to the memory element changes, the voltage applied is delayed by a predetermined time from the time when the voltage applied to the memory element changes. The method for reading data from a storage device according to claim 1, wherein the detection is performed based on a difference between applied voltages of a comparison circuit configured to change. When an electric signal equal to or higher than the first threshold signal is applied, the resistance value changes from a low state to a high state, and an electric signal equal to or higher than the second threshold signal having a polarity different from that of the first threshold signal is applied. A storage device in which storage elements having a characteristic that the resistance value changes from a high state to a low state by being arranged in a matrix,
A storage device comprising a readout circuit that detects a change point of the resistance value of the storage element. The readout circuit is configured to be applied with the same voltage as the voltage applied to the memory element, and when the voltage applied to the memory element changes, a delay of a predetermined time from the time when the voltage applied to the memory element changes. A comparison circuit configured to change the applied voltage,
The storage device according to claim 3, further comprising: a detection circuit that detects a change point of a resistance value of the storage element from a difference between an applied voltage of the storage element and an applied voltage of the comparison circuit. When an electric signal equal to or higher than the first threshold signal is applied, the resistance value changes from a low state to a high state, and an electric signal equal to or higher than the second threshold signal having a polarity different from that of the first threshold signal is applied. A semiconductor device having a memory device in which memory elements having a characteristic in which a resistance value changes from a high state to a low state by being arranged in a matrix,
The same voltage as the voltage applied to the memory element is applied, and when the voltage applied to the memory element changes, the voltage applied is delayed by a predetermined time from the time when the voltage applied to the memory element changes. A comparison circuit configured to change,
A semiconductor device comprising: a detection circuit that detects a change point of a resistance value of the memory element from a difference between an applied voltage of the memory element and an applied voltage of the comparison circuit.

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