JP2006127234A - Memory controller, flash memory system, and flash memory control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten a processing time required for an address conversion table creation process when a virtual block is formed using a flash memory of a plurality of chips and parallel processing is executed.
A zone group is divided into a plurality of subzone groups, and a virtual block is formed independently for each subzone group. A conversion table indicating the correspondence between virtual blocks and logical addresses is created independently for each subzone group. Furthermore, a conversion table for the zone group is created by connecting the conversion tables created for each sub-zone group. In addition, address information indicating the physical address of the physical block virtually combined with the physical block is written in the physical block virtually combined, and based on this address information, virtually combined. The physical address of the physical block to be processed can be obtained.
[Selection] Figure 3

Description

  The present invention relates to a memory controller, a flash memory system, and a flash memory control method.

  In recent years, flash memories have been widely adopted as semiconductor memories used in memory systems such as memory cards and silicon disks. A flash memory is a kind of nonvolatile memory. Data stored in the flash memory is required to be retained even when power is not supplied.

  A NAND flash memory is a type of flash memory that is particularly frequently used in the above memory system. Each of the plurality of memory cells included in the NAND flash memory receives a logical value “0” from an erased state in which data indicating a logical value “1” is stored, independently of the other memory cells. It is possible to change to a writing state in which the indicated data is stored.

  In contrast, when changing from the written state to the erased state, each memory cell cannot change independently of the other memory cells. At this time, all of a predetermined number of memory cells called blocks are simultaneously erased. This batch erase operation is generally called “block erase”. The writing process or the reading process for the NAND flash memory is performed in units of a predetermined number of memory cells called pages. A block which is a unit of erasure processing is composed of a plurality of pages.

  In the writing process to the NAND flash memory, first, write data is transferred to a register in the NAND flash memory, and the write data held in the register is copied to the memory cell array. When the memory cell is changed from the erased state to the written state by this copying (writing) process, a high voltage is applied to the control gate and electrons are injected to the floating gate.

  Here, the copy (write) processing from the register to the memory cell array is started based on a write command given to the NAND flash memory. When this process is started, the NAND flash memory outputs a busy signal indicating that the process is in progress. While the busy signal is output, access to the NAND flash memory is denied, and the period during which the busy signal is output hinders speeding up of the writing process.

In order to solve this problem, in Patent Document 1 below, when a plurality of physical blocks belonging to different chips are virtually combined to form a virtual block and access to data having consecutive logical addresses, Processing can be executed in parallel for each physical block included in the block.
International Publication No. 02/046929 Pamphlet

  As described above, when a virtual block is formed by physical blocks belonging to a plurality of chips and parallel processing is executed, an address conversion table for obtaining a physical address from a logical address must be created for each chip. Therefore, if a virtual block is formed and parallel processing is executed, the speed of the writing process and the reading process can be increased, but the processing time required for the address conversion table creation process increases.

  Therefore, the present invention provides a memory controller and a flash memory system including the memory controller that can reduce the load on the address conversion table creation process when a virtual block is formed to increase the speed of the writing process, and An object of the present invention is to provide a flash memory control method.

To achieve the above object, a memory controller according to a first aspect of the present invention is a memory controller that accesses a flash memory whose storage area is composed of a plurality of chips based on a logical address supplied from a host computer. There,
Means for collecting a plurality of physical blocks in each chip to form a subzone;
Means for collecting a plurality of subzones in different chips to form a subzone group;
Means for forming a virtual block by virtually combining physical blocks selected from each subzone belonging to the same subzone group;
Means for allocating data having consecutive logical addresses to the virtual block;
Means for collecting a plurality of the sub-zone groups to form a zone group; and means for assigning a logical address area in which logical addresses are continuous to the zone group;
Means for writing address information indicating physical addresses of other physical blocks virtually combined in the physical blocks constituting the virtual block;
Access means for accessing each physical block belonging to the virtual block based on the address information;
It is characterized by providing.

  The address information may be stored in a redundant area of each physical block.

  Further, the subzone may be composed of a plurality of physical blocks having consecutive physical addresses.

  The address information may be a serial number assigned in the order of logical addresses to a plurality of physical blocks assigned to the same logical address area.

  Further, when creating a conversion table indicating the correspondence between the virtual block and the logical address, an arbitrary subzone is selected for each subzone group, and the logical address written in the redundant area of the selected subzone The conversion table may be created on the basis of the information regarding.

A memory controller for accessing a flash memory having a plurality of chips based on a logical address supplied from a host computer;
Means for collecting a plurality of physical blocks in each chip to form a subzone;
Means for collecting a plurality of said sub-zones in the same chip to form a zone;
Means for collecting a plurality of the zones in different chips to form a zone group;
Means for allocating a region of logical addresses having consecutive logical addresses to the zone group;
Means for forming a virtual block by virtually combining physical blocks selected from each zone;
Means for writing address information indicating physical addresses of other physical blocks virtually combined in the physical blocks constituting the virtual block;
Access means for accessing each physical block belonging to the virtual block based on the address information;
Means for selecting any of the subzones, and creating a conversion table based on the information about the logical address written in the redundant area of the selected subzone;
In a plurality of subzones selected when creating the conversion table, a physical block in one subzone and a physical block in another subzone may not be virtually combined.

  In order to achieve the above object, a flash memory system according to a second aspect of the present invention includes any one of the above-described memory controllers and a plurality of chips of flash memory.

In order to achieve the above object, a flash memory control method according to a third aspect of the present invention includes:
A flash memory control method for accessing a flash memory whose storage area is composed of a plurality of chips based on a logical address supplied from a host computer,
A process in which a plurality of physical blocks in the same chip are collected to form a zone, a plurality of the zones in different chips are collected to form a zone group, and a logical address area having consecutive logical addresses is assigned to the zone group. When,
Forming a plurality of groups of sub-zones in each zone, and forming a virtual block by virtually combining physical blocks selected from the sub-zones in each chip for which a correspondence relationship is set; and
A process of writing data having consecutive logical addresses to the virtual block;
A process of writing address information indicating a physical address of another physical block virtually combined in a physical block constituting the virtual block;
It is characterized by including.

  The address information may be stored in a redundant area of each physical block.

  Further, the sub-zone may be composed of a plurality of physical blocks having consecutive physical addresses.

  The address information may be a serial number assigned in the order of logical addresses to a plurality of physical blocks assigned to the same logical address area.

Further, when creating a conversion table indicating the correspondence between the virtual block and the logical address, an arbitrary subzone is selected for each subzone group, and the logical address written in the redundant area of the selected subzone The conversion table may be created on the basis of the information regarding.
In this case, the conversion table creation process for the sub-zone group may be executed in parallel in different zones.

  According to the present invention, since a virtual block is formed independently for each subzone group, a conversion table indicating the correspondence between the virtual block and the logical address can be created independently for each subzone group. Further, by concatenating the conversion tables created for each subzone group, the conversion table for the zone group can be created more efficiently. In addition, since the address information indicating the physical address of the physical block virtually combined with the physical block is written in the physically connected physical block, based on the address information, virtually The physical address of the physical block to be combined can be obtained. Therefore, when accessing a virtual block in which a plurality of physical blocks are virtually combined, it is only necessary to create an address conversion table for one physical block belonging to the same virtual block. Can access a physical block.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a block diagram schematically showing a flash memory system 1 according to an embodiment of the present invention.
As shown in FIG. 1, the flash memory system 1 includes a flash memory 2 and a memory controller 3 that controls the flash memory 2. The flash memory system 1 is usually detachably attached to the host system 4 and used as a kind of external storage device for the host system 4.
Examples of the host system 4 include various information processing apparatuses such as a personal computer and a digital still camera that process various information such as characters, sounds, and image information.
Details of the flash memory 2 and the memory controller 3 will be described below.

[Description of flash memory 2]
In this flash memory system 1, a flash memory 2 in which data is stored is composed of a NAND flash memory. The NAND flash memory is a non-volatile memory developed for use as a storage device (as an alternative to a hard disk). This NAND flash memory cannot perform random access, and writing and reading are performed in units of pages and erasing is performed in units of blocks. Since data cannot be overwritten, when data is written, data is written into the erased area.

  Since the NAND flash memory has such characteristics, normally, when data is rewritten, new data (data after rewriting) is written to the erased block that has been erased, and old data is written. A process of erasing a block in which (data before rewriting) has been written is performed.

  When rewriting such data, since the data after rewriting is written in a different block from before rewriting, the logical address given from the host system 4 side and the physical address in the flash memory 2 The correspondence between and changes dynamically every time data is rewritten. Therefore, when accessing the flash memory 2, an address conversion table showing the correspondence between logical addresses and physical addresses is usually created, and the flash memory 2 is accessed using this address conversion table.

FIG. 2 is an explanatory diagram showing the relationship between blocks and pages.
The configuration of the block and page differs depending on the specification of the flash memory. However, in the flash memory 2 of the present embodiment, as shown in FIG. 2A, one block is configured with 32 pages (P0 to P31). Each page includes a 512-byte user area and a 16-byte redundant area. As the storage capacity increases, as shown in FIG. 2B, one block is composed of 64 pages (P0 to P63), and each page is composed of a 2048-byte user area and a 64-byte redundant area. What is being provided is also provided.

  Here, the user area is mainly an area where data supplied from the host system 4 is stored, and the redundant area is stored with additional data such as an error correction code, corresponding logical address information and block status. Area. The error correction code is additional data for detecting and correcting an error included in the data stored in the user area, and is generated by an ECC block described later.

  The corresponding logical address information is written when data is stored in a physical block, and indicates information related to the logical address of the data stored in the physical block. If no data is stored in the physical block, the corresponding logical address information is not written, so whether the corresponding logical address information is written or not is the erased block. Can be judged. That is, if the corresponding logical block address is not written, it is determined that the block is an erased block.

  The block status is a flag indicating whether or not the physical block is a bad block (a physical block in which data cannot be normally written). When the physical block is determined to be a bad block, Is set with a flag indicating that it is a bad block.

  Next, the circuit configuration of the flash memory 2 will be described. A general NAND flash memory includes a register for holding write data or read data and a memory cell array for storing data. The memory cell array includes a plurality of memory cell groups in which a plurality of memory cells are connected in series, and a specific memory cell in the memory cell group is selected by a word line. Data copying (copying from the register to the memory cell or copying from the memory cell to the register) is performed between the memory cell selected by the word line and the register.

  A memory cell constituting the memory cell array is composed of a MOS transistor having two gates. Here, the upper gate is called a control gate, and the lower gate is called a floating gate. By injecting charges (electrons) into the floating gate and discharging charges (electrons) from the floating gate, Data is written or erased.

  Since the floating gate is surrounded by an insulator, the injected electrons are held for a long period of time. When injecting electrons into the floating gate, a high voltage is applied so that the control gate is at the high potential side. When electrons are injected from the floating gate, a high voltage at which the control gate is at the low potential side is applied. Applied to discharge electrons. The state in which electrons are injected into the floating gate (write state) corresponds to data having a logical value “0”, and the state in which electrons are discharged from the floating gate (erased state) has a logical value “1”. Corresponds to data.

[Description of Memory Controller 3]
The memory controller 3 includes a host interface control block 5, a microprocessor 6, a host interface block 7, a work area 8, a buffer 9, a flash memory interface block 10, and an ECC (error collection code) block 11. And a flash memory sequencer block 12. The memory controller 3 constituted by these functional blocks is integrated on one semiconductor chip. Hereinafter, the function of each functional block will be described.

The microprocessor 6 is a functional block that controls the operation of all the functional blocks constituting the memory controller 3.
The host interface control block 5 is a functional block that controls the operation of the host interface block 7. Here, the host interface control block 5 includes an operation setting register (not shown) for setting the operation of the host interface block 7, and the host interface block 7 operates based on the operation setting register.

  The host interface block 7 is a functional block that exchanges data, address information, status information, and external command information with the host system 4. That is, when the flash memory system 1 is attached to the host system 4, the flash memory system 1 and the host system 4 are connected to each other via the external bus 13. In such a state, data or the like supplied from the host system 4 to the flash memory system 1 is taken into the memory controller 3 with the host interface block 7 as an entrance, and is supplied from the flash memory system 1 to the host system 4. Are supplied to the host system 4 using the host interface block 7 as an exit.

  Further, the host interface block 7 has a register for holding a logical address, a sector number and an external command supplied from the host system 4, an error register (not shown) set when an error occurs, and the like. Yes.

  The work area 8 is a work area in which data necessary for controlling the flash memory 2 is temporarily stored, and is composed of a plurality of SRAM (Static Random Access Memory) cells.

  The buffer 9 is a functional block that temporarily holds data read from the flash memory 2 and data to be written to the flash memory 2. That is, data read from the flash memory 2 is held in the buffer 9 until the host system 4 is ready to receive data, and data to be written to the flash memory 2 is stored in the buffer 9 until the flash memory 2 is ready to write. Retained.

  The flash memory sequencer block 12 is a functional block that controls the operation of the flash memory 2 based on an internal command. The flash memory sequencer block 12 includes a plurality of registers (not shown), and information necessary for executing an internal command is set in the plurality of registers. When information necessary for executing an internal command is set in a plurality of registers, the flash memory sequencer block 12 executes processing based on the information.

  Here, the “internal command” is a command given from the memory controller 3 to the flash memory 2 and is distinguished from an “external command” which is a command given from the host system 4 to the flash memory system 1.

  The flash memory interface block 10 is a functional block that exchanges data, address information, status information, internal command information, device ID information, and the like with the flash memory 2 via the internal bus 14.

  The ECC block 11 generates an error correction code added to data to be written in the flash memory 2 and detects an error included in the read data based on the error correction code added to the read data. This is a functional block to be corrected.

[Description of Flash memory system operation]
In the flash memory system according to the present invention, a storage area of the flash memory 2 is configured by a plurality of chips, and physical blocks belonging to different chips are virtually combined to form a virtual block. This virtual block will be described with reference to FIGS.

FIG. 3 is a diagram illustrating physical blocks virtually combined.
FIG. 3 shows an example in which the storage area of the flash memory 2 is configured by four chips, chip 0, chip 1, chip 2, and chip 3. Here, a zone is formed by 1024 physical blocks in each of the chips 0 to 3. Physical blocks constituting each zone are assigned serial numbers (# 0 to # 1023) of 0 to 1023. Further, each zone is divided into subzone 0 composed of physical blocks # 0 to # 511 and subzone 1 composed of physical blocks # 512 to # 1023. In other words, a zone is formed by concatenating sub-zone 0 composed of physical blocks # 0 to # 511 and sub-zone 1 composed of physical blocks # 512 to # 1023.

  Correspondences with zones in different chips are set in the zones of each chip. FIG. 3 shows one zone in each chip for which a correspondence relationship is set. Here, the zone A in the chip 0, the zone B in the chip 1, the zone C in the chip 2 and the zone D in the chip 3 are set in correspondence, and the zones A to D form a zone group. Yes. A storage area with continuous logical addresses is assigned to the zone group. For example, a storage area for 4000 physical blocks is allocated to a zone group composed of 4096 physical blocks as shown in FIG.

  Zone A, zone B, zone C, and zone D are divided into subzone 0 and subzone 1, respectively. Zone A, zone B, zone C, and zone D are composed of subzone 0 (physical blocks # 0 to # 511). Subzones) form a subzone group. On the other hand, sub-zone 1 (sub-zone constituted by physical blocks # 512 to # 1023) of zone A, zone B, zone C and zone D also forms a sub-zone group. Hereinafter, a storage area formed by sub-zone 0 of zone A, sub-zone 0 of zone B, sub-zone 0 of zone C, and sub-zone 0 of zone D is referred to as sub-zone group 0, sub-zone 1 of zone A, sub-zone 1 of zone B, A storage area formed by the subzone 1 of the zone C and the subzone 1 of the zone D is referred to as a subzone group 1.

  In subzone group 0 and subzone group 1, virtual blocks are formed independently of each other. That is, physical blocks belonging to subzone 0 of zone A, zone B, zone C and zone D or physical blocks belonging to subzone 1 of zone A, zone B, zone C and zone D are virtually combined. A virtual block is formed, but a physical block belonging to subzone 0 of each zone and a physical block belonging to subzone 1 of a different zone are set so as not to be virtually combined.

  For example, physical block # 1 belonging to subzone 0 of zone A, physical block # 2 belonging to subzone 0 of zone B, physical block # 0 belonging to subzone 0 of zone C, and physical block # 4 belonging to subzone 0 of zone D Virtually connected to form a virtual block. In this virtual block, physical blocks belonging to subzone 0 are virtually combined. Further, physical block # 513 belonging to subzone 1 of zone A, physical block # 512 belonging to subzone 1 of zone B, physical block # 513 belonging to subzone 1 of zone C, and physical block # 514 belonging to subzone 1 of zone D are included. Virtually connected to form a virtual block. In this virtual block, physical blocks belonging to the subzone 1 are virtually combined.

  That is, in this example, a virtual block is formed with physical blocks selected one by one from the sub-zone 0 (physical blocks # 0 to # 511) of zone A, zone B, zone C, and zone D, and zone A In some cases, a virtual block is formed by physical blocks selected one by one from sub-zone 1 (physical blocks # 512 to # 1023) of zone B, zone C, and zone D.

FIG. 4 is an explanatory diagram for explaining an arrangement of user data stored in the virtual block.
Here, an array of user data stored in the virtual block will be described. FIG. 4 shows a case where each physical block forming the virtual block is composed of 32 pages. Since this virtual block is composed of four physical blocks, 128 pages of user data are stored in one virtual block. If user data for 128 pages having consecutive logical addresses is divided into pages and YD0 to YD127 are assigned in order from the lowest logical address, the user data YD0 having the lowest logical address is the physical block # 1 in zone A. User data YD1 having the next smallest logical address is assigned to page 0 (P0) of physical block # 2 in zone B.

  Hereinafter, in order from the lowest logical address, user data YD2 is allocated to page 0 (P0) of physical block # 0 in zone C, and user data YD3 is assigned to page 0 (P0 of physical block # 4 in zone D). ).

  Similarly, the user data YD4 to 127 are logical addresses for the physical block # 1, zone B physical block # 2, zone C physical block # 0, and zone D physical block # 4. Are assigned in order from the youngest.

  As described above, when user data having continuous logical addresses are sequentially assigned to physical blocks in zones A to D in units of pages, user data for a plurality of pages having continuous logical addresses is written or read. When processing, it is possible to execute processing on the chips 0 to 3 of the flash memory 2 in parallel. Further, even if the buses connected to the chips 0 to 3 are not independent for each chip, the processing in each of the chips 0 to 3 ends the transmission / reception of user data and the transmission of commands to the chips 0 to 3. It is possible to execute sequentially without waiting. By executing such parallel processing and shortening the waiting time, the processing time required for the writing process and the reading process can be shortened.

  Next, a correspondence relationship between virtual blocks formed independently for each subzone group and logical addresses will be described. The correspondence relationship between the virtual block and the logical address is managed in units of blocks by regarding the virtual block as one physical block. As shown in FIG. 3, when four physical blocks are virtually combined to form a virtual block, consecutive logical addresses are assigned to storage areas for four physical blocks.

FIG. 5 is a diagram showing a logical address space, and the logical address space is indicated by LBA (Logical Block Address).
LBA0 to LBA511 in FIG. 5 are serial numbers assigned in units of sectors. When the capacity of one sector is equal to the capacity of one page of the flash memory 2 and each physical block is composed of 32 pages, 4 A virtual block obtained by combining the physical blocks is assigned to 128 sectors in the logical address space. Therefore, if an area for 128 sectors in the logical address space is defined as one logical block group, one logical block group is assigned to one virtual block.

In the example shown in FIG. 5, serial numbers LBN0 to LBN3 are assigned to logical block groups obtained by dividing the logical address space into 128 sectors (hereinafter, the serial numbers assigned to the logical block groups are referred to as logical block serial numbers). .
The logical block serial number LBN0 corresponds to LBA0 to LBA127, the logical block serial number LBN1 corresponds to LBA128 to LBA255, and similarly, a logical block serial number is assigned to each 128 sectors.

  The logical block serial numbers LBN0 to LBN3 are written in the redundant area of the physical block in which the user data corresponding to the logical block serial number is written, and based on the written logical block serial number, Correspondence between block groups is managed.

  For example, in FIG. 3, LBN0 is written in the redundant areas of four physical blocks belonging to the virtual block in which user data corresponding to LBA0 to LBA127 is written, and user data corresponding to LBA128 to LBA255 is written. LBN1 is written in the redundant areas of the four physical blocks belonging to the virtual block.

  For example, a zone of logical addresses corresponding to 4000 physical blocks is allocated to the zone group composed of 4096 physical blocks shown in FIG. The logical address area corresponding to 4000 physical blocks is an area where logical addresses are continuous, and is divided into logical block groups corresponding to logical block serial numbers LBN0 to LBN999 every 128 sectors. User data corresponding to each logical block group of logical block serial numbers LBN0 to LBN999 may be written into subzone group 0 or subzone group 1.

  For example, when user data corresponding to the logical block serial number LBN0 is written in the subzone group 0, new user data (user data corresponding to the logical block serial number LBN0) to be replaced with this data is transferred to the subzone. You may write to Group 1.

When accessing the flash memory 2, a conversion table indicating the correspondence between the logical block group and the virtual block is used.
6A and 6B are explanatory diagrams of the conversion table.
As shown in FIG. 3, when a physical block is formed by virtually combining four physical blocks belonging to different zones, four physical blocks belonging to different zones are associated with each logical block serial number. Correspond. Therefore, a conversion table (FIG. 6A) showing the physical blocks corresponding to each logical block serial number for each zone is required.
However, when creating the conversion table as shown in FIG. 6A, the process of reading the logical block serial number written in the redundant area must be executed for the four zones. That is, when one zone is composed of 1024 physical blocks, a read process must be executed for 4096 physical blocks.

  In order to reduce the burden on the creation of the conversion table as described above, in the flash memory system 1 according to the present invention, the conversion table showing the correspondence between one physical block belonging to each virtual block and the logical block serial number For the physical block for which the correspondence relationship with the logical block serial number is not shown in the conversion table, the corresponding logical block serial number and LBA are known based on the link number described later.

  FIG. 6B shows a conversion table showing the correspondence between the sub-zone 0 (physical blocks # 0 to # 511) of zone A and the sub-zone 1 (physical blocks # 512 to # 1023) of zone B and logical block serial numbers. It is. In this conversion table, each logical block serial number LBN0 to LBN999 is assigned to any physical block of zone A subzone 0 (physical blocks # 0 to # 511) or zone B subzone 1 (physical blocks # 512 to # 1023). It shows whether it corresponds. Here, since the virtual blocks are independently formed in the subzone group 0 and the subzone group 1, the physical blocks corresponding to the same logical block serial number are the subzone 0 (physical blocks # 0 to # 511) in the zone A. And subzone 1 (physical blocks # 512 to # 1023) in zone B are not present.

  If a virtual block is not formed independently in subzone group 0 and subzone group 1, a physical block belonging to subzone 0 (physical blocks # 0 to # 511) in zone A and subzone 1 in zone B ( Virtual blocks including physical blocks belonging to physical blocks # 512 to # 1023) may be formed. In such a case, the physical blocks corresponding to the same logical block serial number are both subzone 0 (physical blocks # 0 to # 511) in zone A and subzone 1 (physical blocks # 512 to # 1023) in zone B. Will exist.

  As described above, since the virtual blocks are independently formed in the subzone group 0 and the subzone group 1, it belongs to the logical block serial number and the subzone 0 (physical blocks # 0 to # 511) of the zone A. Based on the correspondence relationship with the physical block or the correspondence relationship between the logical block serial number and the physical block belonging to the sub-zone 1 (physical block # 512 to # 1023) of zone B, zone A, zone B, zone C and zone D Can be accessed.

  For example, if the physical block # 1 of zone 0 belongs to the virtual block corresponding to the logical block serial number LBN0 based on the conversion table of FIG. 6B, this virtual block is based on the link number described later. The other three physical blocks belonging to can be obtained and the virtual block corresponding to the logical block serial number LBN0 can be accessed. Also, if it is known that the physical block # 512 of zone 1 belongs to the virtual block corresponding to the logical block serial number LBN550, the other three physical blocks belonging to this virtual block are known based on the link number described later. The virtual block corresponding to the logical block serial number LBN550 can be accessed.

  Here, the conversion table shown in FIG. 6B includes logical block serial numbers LBN0 to LBN999 and a physical block belonging to subzone 0 (physical block # 0 to # 511) of zone A, or subzone 1 (physical block # of zone B). 512 to # 1023), when the physical block serial numbers shown in the conversion table are # 0 to # 511, the physical blocks belonging to zone A correspond to When the physical block serial numbers shown in the conversion table are # 512 to # 1023, the physical blocks belonging to zone B correspond.

FIG. 7 is an explanatory diagram showing a conversion table creation method.
When creating the conversion table of FIG. 6B, as shown in FIG. 7, the read processing for the physical blocks belonging to the sub-zone 0 of the zone A, that is, the redundant areas of the physical blocks # 0 to # 511 of the zone A, The read processing for the redundant areas of the physical blocks belonging to the sub-zone of zone B, that is, the physical physical blocks # 512 to # 1023 of zone B, can proceed in parallel. Therefore, a read process for the redundant areas of subzone 0 and subzone 1 of one zone is executed, and conversion showing the correspondence between logical block serial numbers LBN0 to LBN999 and physical blocks # 0 to # 1023 belonging to one zone A conversion table can be created in a shorter time than when a table is created.

FIGS. 8A and 8B are diagrams showing logical block serial numbers and link numbers written in the redundant areas of virtually connected physical blocks.
In FIG. 8A, the physical block # 1 of zone A, the physical block # 2 of zone B, the physical block # 0 of zone C, and the physical block # 4 of zone D are virtually combined into one virtual block. , LBA0 to 127 of the logical address space are allocated to this virtual block. Therefore, the logical block serial number LBN0 corresponding to the serial numbers LBA0 to 127 in sector units is written in the redundant areas of these physical blocks.

  Similarly, in the redundant areas of the physical block # 3 of zone A, the physical block # 4 of zone B, the physical block # 5 of zone C, and the physical block # 6 of zone D that form a virtual block, The logical block serial number LBN1 corresponding to the serial numbers LBA128 to LBA255 is written. The redundant areas of the physical block # 7 in zone A, the physical block # 6 in zone B, the physical block # 8 in zone C, and the physical block # 9 in zone D, which form the virtual block, are linked in units of sectors. The logical block serial numbers LBN2 corresponding to the numbers LBA256 to LBA383 are written.

  A link number is further written in the redundant area of each physical block belonging to these virtual blocks corresponding to the logical block serial numbers LBN0 to LBN2. This link number is used to know the connection relationship of the physically connected physical blocks. For example, in the redundant area of the physical block # 1 in the zone A, the number # 2 of the physical block # 2 in the zone B that is virtually combined with the physical block # 1 is written as the link number, and the physical block in the zone B In the redundant area of # 2, the number # 0 of the physical block # 0 of the zone C virtually combined with this physical block # 2 is written as the link number. In the redundant area of the physical block # 0 in the zone C, the number # 4 of the physical block # 4 in the zone D that is virtually coupled to the physical block # 0 is written as a link number.

  Therefore, by reading the link number written in the redundant area of the physical block # 1 in the zone A, the number of the physical block # 2 in the zone B that is virtually coupled to this physical block is # 2. Obviously, by reading out the link number written in the redundant area of the physical block # 2 in the zone B, the number of the physical block # 0 in the zone C virtually combined with the physical block # 2 is # 0. I understand that. Similarly, by reading out the link number written in the redundant area of the physical block # 0 of the zone C, the number of the physical block # 4 of the zone D virtually combined with this physical block # 0 is # 4. I understand that there is.

Similarly, for the virtual blocks corresponding to the logical block serial numbers LBN1 and LBN2, the serial number of the physical block of zone B that is virtually coupled to this physical block is written as the link number in the redundant area of the physical block of zone A. In the redundant area of the physical block of zone B, the serial number of the physical block of zone C virtually linked to this physical block is written as the link number, and in the redundant area of the physical block of zone C, The serial number of the physical block in zone D virtually linked to this physical block is written as the link number.
With these link numbers, the physical block virtually combined with the physical block # 3 of the zone A is the physical block # 4 of zone B, and the physical block virtually combined with the physical block # 4 of the zone B is zone C It can be seen that the physical block # 5 of the zone C and the physical block virtually combined with the physical block # 5 of the zone C is the physical block # 6 of the zone D.
The physical block virtually combined with the physical block # 7 of zone A is the physical block # 6 of zone B, and the physical block virtually combined with the physical block # 6 of zone B is the physical block # of zone C. It can be seen that the physical block virtually combined with the physical block # 8 of the zone C is the physical block # 9 of the zone D.

  When the conversion table indicates the correspondence between the logical block serial numbers LBN0 to LBN999 and the physical blocks belonging to the subzone 0 (physical blocks # 0 to # 511) of the zone A, the conversion table is composed of physical blocks belonging to the subzone group 0. When accessing the virtual block, the link numbers are sequentially traced from the physical blocks belonging to the sub-zone 0 (physical blocks # 0 to # 511) of the zone A.

  Therefore, the link number is not written in the redundant area of the physical block of zone D, but the serial number of the physical block of zone A virtually linked to this physical block is linked to the redundant area of the physical block of zone D. If it is written as a number, it is possible to know the physical blocks of other zones virtually combined from any of the physical blocks of zones A to D. In this case, the flash memory 2 can be accessed even if the conversion table is a conversion table for any of the zones A to D.

  FIG. 8B shows that the physical block # 513 in zone A, the physical block # 512 in zone B, the physical block # 513 in zone C, and the physical block # 514 in zone D are virtually combined. Yes. The logical block serial number LBN 550 corresponding to this virtual block is written in the redundant area of these physical blocks. Similarly, in the redundant areas of the physical block # 515 of zone A, the physical block # 514 of zone B, the physical block # 517 of zone C, and the physical block # 516 of zone D forming the virtual block, the logical block is connected. No. LBN551 is written. In addition, the logical block serial numbers are included in the redundant areas of the physical block # 518 of zone A, the physical block # 520 of zone B, the physical block # 519 of zone C, and the physical block # 521 of zone D forming the virtual block. LBN552 is written.

  The link number used to know the connection relationship of the virtually connected physical blocks is also written in the redundant area of each physical block belonging to these virtual blocks corresponding to the logical block serial numbers LBN550 to 552. It is rare. These virtual blocks corresponding to the logical block serial numbers LBN 550 to LBN 552 correspond to virtual blocks configured by physical blocks belonging to the subzone group 1. When the conversion table for the subzone group 1 indicates the correspondence between the logical block serial numbers LBN0 to LBN999 and the physical blocks belonging to the subzone 1 (physical blocks # 512 to # 1023) of the zone B, the subzone 1 of the zone B (physical The link numbers are sequentially traced from the physical blocks belonging to the blocks # 512 to # 1023).

  Therefore, for the virtual blocks corresponding to the logical block serial numbers LBN550 to LBA999, the serial number of the physical block of zone C virtually linked to this physical block is written as the link number in the redundant area of the physical block of zone B. In the redundant area of the physical block of zone C, the serial number of the physical block of zone D virtually linked to this physical block is written as the link number, and in the redundant area of the physical block of zone D, A serial number of a physical block in zone A virtually linked to this physical block is written as a link number.

Based on this link number, the physical block virtually combined with the physical block # 512 of zone B is the physical block # 513 of zone C, and the physical block virtually combined with the physical block # 513 of zone C is the zone D physical block # 513. It can be seen that the physical block # 514 and the physical block virtually combined with the physical block # 514 of the zone D is the physical block # 513 of the zone A.
The physical block virtually combined with the physical block # 514 of zone B is the physical block # 517 of zone C, and the physical block virtually combined with the physical block # 517 of zone C is the physical block # of zone D. It can be seen that the physical block virtually combined with the physical block # 516 of the zone D is the physical block # 515 of the zone A.
The physical block virtually combined with the physical block # 520 of zone B is the physical block # 519 of zone C, and the physical block virtually combined with the physical block # 519 of zone C is the physical block # of zone D. 521, and the physical block virtually combined with the physical block # 521 of the zone D is the physical block # 518 of the zone A.

  When the conversion table indicates the correspondence between the logical block serial numbers LBN0 to LBN999 and the physical blocks belonging to the subzone 1 (physical blocks # 512 to # 1023) of the zone B, the conversion table is composed of physical blocks belonging to the subzone group 1. When accessing a virtual block that has been set, the link numbers are sequentially traced from the physical block belonging to the sub-zone 1 (physical blocks # 512 to # 1023) of zone B. Therefore, the link number is not written in the redundant area of the physical block of zone A, but the serial number of the physical block of zone B virtually linked to this physical block is linked to the redundant area of the physical block of zone A. If it is written as a number, it is possible to know the physical blocks of other zones virtually combined from any of the physical blocks of zones A to D. In this case, even if the conversion table is a conversion table for any of the zones A to D, the flash memory can be accessed.

  If the link number is written in the redundant area in this way, the address information (for example, the physical address and physical block of the physical block) virtually linked to this physical block from one physical block belonging to the virtual block. Serial number, etc.). Therefore, if the address information of one physical block belonging to the virtual block corresponding to the LBA supplied from the host system can be obtained from the conversion table, it is virtually combined with one physical block obtained from the conversion table. It is possible to acquire physical block address information. Further, the address information of one physical block obtained from the conversion table may be address information of any physical block belonging to the virtual block.

  When accessing the flash memory 2 based on the logical block supplied from the host system 4, first, address information of one physical block belonging to the virtual block corresponding to the logical block address supplied from the host system 4. Is obtained using the conversion table. Subsequently, the address information of the physical block virtually combined with this physical block is acquired based on the link number. Thereafter, the flash memory 2 may be accessed based on the acquired address information.

In the above description, each zone is divided into two subzones, but the number of subzones is not particularly limited.
FIG. 9 is a diagram illustrating another configuration example of the subzone.
For example, as shown in FIG. 9, it may be divided into four subzones of subzones 0-3. In this case, a physical block belonging to subzone 0 (physical blocks # 0 to # 255) in zone A, a physical block belonging to subzone 0 (physical blocks # 0 to # 255) in zone B, and a subzone 0 (physical in zone C) The physical blocks belonging to the blocks # 0 to # 255) and the physical blocks belonging to the subzone 0 of the zone D (physical blocks # 0 to # 255) are virtually combined.

  In addition, a physical block belonging to subzone 1 (physical blocks # 256 to # 511) of zone A, a physical block belonging to subzone 1 (physical blocks # 256 to # 511) of zone B, and a subzone 1 (physical block of zone C) The physical blocks belonging to # 256 to # 511) and the physical blocks belonging to subzone 1 (physical blocks # 256 to # 511) of zone D are virtually combined.

  In addition, a physical block belonging to subzone 2 (physical blocks # 512 to # 767) of zone A, a physical block belonging to subzone 2 (physical blocks # 512 to # 767) of zone B, and a subzone 2 (physical block) of zone C The physical blocks belonging to # 512 to # 767) and the physical blocks belonging to subzone 2 of zone D (physical blocks # 512 to # 767) are virtually combined.

  In addition, a physical block belonging to subzone 3 (physical blocks # 768 to # 1023) of zone A, a physical block belonging to subzone 3 (physical blocks # 768 to # 1023) of zone B, and a subzone 3 (physical block) of zone C The physical blocks belonging to # 768 to # 1023) and the physical blocks belonging to the sub-zone 3 of zone D (physical blocks # 768 to # 1023) are virtually combined.

  As the correspondence relationship between the logical block serial numbers LBN0 to LBN999 shown in the conversion table and the physical blocks belonging to the virtual block, zones A to D can be selected for each subzone. For example, a physical block belonging to subzone 0 (physical blocks # 0 to # 255) in zone A, a physical block belonging to subzone 1 (physical blocks # 256 to # 511) in zone B, and a subzone 2 (physical block # 512) in zone C To # 767) or a conversion table indicating the correspondence between physical blocks belonging to sub-zone 3 (physical blocks # 768 to # 1023) of zone D and logical block serial numbers LBN0 to LBN999.

  The conversion table is subzone 0 (physical block # 0 to # 255) of zone A, subzone 1 (physical block # 256 to # 511) of zone B, subzone 2 (physical block # 512 to # 767) of zone C, or zone In the case where the correspondence relationship between the physical blocks belonging to the D subzone 3 (physical blocks # 768 to # 1023) and the logical block serial numbers LBN0 to LBN999 is shown, the link number is traced as follows.

FIGS. 10A to 10D are explanatory diagrams of how to follow link numbers.
When tracing the link number of a virtual block composed of physical blocks belonging to subzone 0 (physical blocks # 0 to # 255) of zones A to D, subzone 0 of zone A as shown in FIG. The link numbers are traced in order from the physical blocks belonging to (physical blocks # 0 to # 255). That is, the link numbers are traced in the order of zone A, zone B, zone C, and zone D.

When tracing the link number of a virtual block composed of physical blocks belonging to subzone 1 (physical blocks # 256 to # 511) of zones A to D, subzone 1 of zone B as shown in FIG. The link numbers are traced in order from the physical block belonging to (physical blocks # 256 to # 511).
That is, the link numbers are traced in the order of zone B, zone C, zone D, and zone A.

  When tracing the link number of a virtual block composed of physical blocks belonging to the subzone 2 (physical blocks # 512 to # 767) of the zones A to D, the subzone 2 of the zone C as shown in FIG. The link numbers are traced in order from the physical block belonging to (physical blocks # 512 to # 767). That is, the link numbers are traced in the order of zone C, zone D, zone A, and zone B.

  When the link number of a virtual block composed of physical blocks belonging to subzone 3 (physical blocks # 768 to # 1023) of zones A to D is traced, subzone 3 of zone D as shown in FIG. The link numbers are traced in order from the physical block belonging to (physical blocks # 768 to # 1023). That is, the link numbers are traced in the order of zone D, zone A, zone B, and zone C.

  Note that the link number is not particularly limited as long as it is address information that allows the physical address of the physical block to be known. In addition, the number of physical blocks virtually combined, the number of physical blocks constituting the zone, the number of zones constituting the zone group, and the number of sub-zone groups included in the zone group are not particularly limited. No.

In the above description, the address information of one physical block virtually linked to each physical block is written as a link number. However, the address information or virtual addresses of a plurality of physical blocks virtually linked to each physical block are written. The address information of all the physical blocks coupled to may be written. When writing as address information and link numbers of all physical blocks that are virtually combined, it is virtually combined with that physical block simply by reading all the link numbers written in that physical block. Address information of all physical blocks that can be acquired.
Further, in the conversion table creation method of FIG. 6B shown in FIG. 7, the conversion table is created for the zone A sub-zone 0 and the zone B sub-zone 1. Therefore, the physical block belonging to the sub-zone 0 of the zone A and the physical block belonging to the sub-zone 1 of the zone B are virtually combined (forms a virtual block) to both the sub-zone 0 of the zone A and the sub-zone 1 of the zone B. If there is no physical block corresponding to the same logical block sequence number, the physical block belonging to zone C and zone D virtually combined with the physical block belonging to zone A and zone B belongs to either subzone 0 or subzone 1 No problem. That is, a physical block belonging to subzone 0 of zone A and a physical block belonging to subzone 1 of zone B, or a physical block belonging to subzone 1 of zone A and a physical block belonging to subzone 0 of zone B are virtually combined. Thus, the physical blocks belonging to Zone C and Zone D that are virtually combined with this physical block are subzone 0 of zone A and subzone 1 of zone B, regardless of whether they belong to subzone 0 or subzone 1. A conversion table can be created as a target. Therefore, at least in the multiple subzones for which the conversion table is created,
If a physical block in one subzone and a physical block in another subzone are not virtually combined, that is, a physical block in one subzone and a physical block in another subzone have the same logical block serial number If there is no corresponding physical block, the effect of the present invention can be obtained.

1 is a block diagram of a flash memory system according to an embodiment of the present invention. It is explanatory drawing which shows the relationship between a block and a page. It is a figure which shows the physical block virtually combined. It is a figure which shows the arrangement | sequence of the user data written in the physical block combined virtually. It is a figure which shows a logical address space. It is a figure which shows a conversion table. It is a figure for demonstrating the creation process of a conversion table. It is a figure which shows the logical block serial number and link number which are written in the redundancy area | region of flash memory. It is a figure which shows the other structural example of a subzone. It is a figure for demonstrating a link number.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Flash memory system 2 Flash memory 3 Memory controller 4 Host system 5 Host interface control block 6 Microprocessor 7 Host interface block 8 Work area 9 Buffer 10 Flash memory interface block 11 ECC block 12 Flash memory sequencer block 13 External bus 14 Internal bus

Claims (13)

A memory controller that accesses a flash memory having a plurality of chips based on a logical address supplied from a host computer,
Means for collecting a plurality of physical blocks in each chip to form a subzone;
Means for collecting a plurality of subzones in different chips to form a subzone group;
Means for forming a virtual block by virtually combining physical blocks selected from each subzone belonging to the same subzone group;
Means for allocating data having consecutive logical addresses to the virtual block;
Means for collecting a plurality of the sub-zone groups to form a zone group; and means for assigning a logical address area in which logical addresses are continuous to the zone group;
Means for writing address information indicating physical addresses of other physical blocks virtually combined in the physical blocks constituting the virtual block;
Access means for accessing each physical block belonging to the virtual block based on the address information;
A memory controller comprising:   The memory controller according to claim 1, wherein the address information is stored in a redundant area of each physical block.   The memory controller according to claim 1, wherein the subzone is configured by a plurality of physical blocks having consecutive physical addresses.   4. The address information according to claim 1, wherein the address information is a serial number assigned in the order of logical addresses to a plurality of physical blocks allocated to the same logical address area. Memory controller as described in.   When creating a conversion table showing the correspondence between the virtual block and the logical address, information on the logical address written in the redundant area of the selected subzone is selected for each subzone group. 5. The memory controller according to claim 1, wherein the conversion table is created based on: A memory controller that accesses a flash memory having a plurality of chips based on a logical address supplied from a host computer,
Means for collecting a plurality of physical blocks in each chip to form a subzone;
Means for collecting a plurality of said sub-zones in the same chip to form a zone;
Means for collecting a plurality of the zones in different chips to form a zone group;
Means for allocating a region of logical addresses having consecutive logical addresses to the zone group;
Means for forming a virtual block by virtually combining physical blocks selected from each zone;
Means for writing address information indicating physical addresses of other physical blocks virtually combined in the physical blocks constituting the virtual block;
Access means for accessing each physical block belonging to the virtual block based on the address information;
Means for selecting any of the subzones, and creating a conversion table based on the information about the logical address written in the redundant area of the selected subzone;
Memory configured so that physical blocks in one subzone and physical blocks in another subzone are not virtually combined in a plurality of subzones selected when creating the conversion table controller.   A flash memory system comprising the memory controller according to claim 1 and a flash memory having a plurality of chips. A flash memory control method for accessing a flash memory whose storage area is composed of a plurality of chips based on a logical address supplied from a host computer,
A process in which a plurality of physical blocks in the same chip are collected to form a zone, a plurality of the zones in different chips are collected to form a zone group, and a logical address area having consecutive logical addresses is assigned to the zone group. When,
Forming a plurality of groups of sub-zones in each zone, and forming a virtual block by virtually combining physical blocks selected from the sub-zones in each chip for which a correspondence relationship is set; and
A process of writing data having consecutive logical addresses to the virtual block;
A process of writing address information indicating a physical address of another physical block virtually combined in a physical block constituting the virtual block;
A method for controlling a flash memory, comprising:   9. The flash memory control method according to claim 8, wherein the address information is stored in a redundant area of each physical block.   10. The flash memory control method according to claim 8, wherein the sub-zone is composed of a plurality of physical blocks having consecutive physical addresses.   11. The address information according to claim 8, wherein the address information is a serial number assigned in the order of logical addresses to a plurality of physical blocks assigned to the same logical address area. The control method of the flash memory as described in 2.   When creating a conversion table showing the correspondence between the virtual block and the logical address, information on the logical address written in the redundant area of the selected subzone is selected for each subzone group. The flash memory control method according to claim 8, wherein the conversion table is created based on the method. 13. The flash memory control method according to claim 12, wherein the conversion table creation processing for the sub-zone groups is executed in parallel in different zones.

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