JP2006108452A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device which is fine in structure, as well as superior in electrical properties. <P>SOLUTION: Contact holes 11 extending to diffusion layer regions 8 respectively are formed by dry-etching a stopper film 9 through an interlayer insulating film 10 as a mask. At this time, the bottoms of the contact holes 11 are recessed from the surface of a silicon substrate 1 through overetching of the stopper film 9. In succession, after the surface of the silicon substrate 1 has been cleaned, a polysilicon film 12 is formed on the interlayer insulating film 10 so as to cover the inner surfaces of the contact holes 11. The thickness of the polysilicon film 12 is set larger than the depth, by which the bottom of the contact hole 11 is recessed from the surface of the silicon substrate 1 and set smaller than that of silicon removed by turning it into a silicide. By this setup, silicon removed from the silicon substrate 1 due to overetching and the formation of silicide can be reduced in amount. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a metal silicide layer in a diffusion layer region.

  In recent years, with the miniaturization of semiconductor devices, the junction depths of diffusion layers serving as source / drain tend to be shallow. However, as the diffusion layer becomes shallower, the diffusion layer resistance increases, and the influence of parasitic resistance on device characteristics cannot be ignored. Therefore, in order to cope with such an increase in resistance due to the extremely shallow diffusion layer, a metal silicide layer is formed (see, for example, Patent Document 1 and Patent Document 2).

  For example, a contact hole is formed in an interlayer insulating film formed on a silicon substrate, and after a cleaning process, a metal such as Ti (titanium) is deposited on the entire surface including the inside of the contact hole. Next, when heat treatment is performed, the metal and the metal react to form a metal silicide layer. Thereafter, a contact plug can be formed by filling the inside of the contact hole with a conductive layer such as W (tungsten) through the barrier metal film.

JP-A-3-285330 JP-A-6-85083

  However, when the shallow junction of the source / drain advances with further miniaturization, the following problems occur.

  First, there is a problem that junction leakage current increases in the vertical direction of the silicon substrate. That is, due to over-etching of the silicon substrate when forming the contact hole, the bottom of the contact hole has a recessed (depressed) structure with respect to the surface of the silicon substrate. For this reason, the contact hole is bonded to the silicon substrate at a deep depth of the silicon substrate with respect to the shallow source / drain, and a junction leak occurs in the vertical direction of the silicon substrate.

Secondly, there is a problem that defects occur in the silicon substrate when the conductive layer reacts with silicon. That is, side etching occurs at the bottom of the contact hole due to over-etching on the silicon substrate or wet etching in the cleaning process. Here, since the barrier metal film is formed only in a thin film thickness in the portion where the side etching occurs, the barrier property is insufficient. On the other hand, when the tungsten film is formed, WF ₆ is used as a source gas. When the barrier properties of the barrier metal film is not sufficient, the reaction occurs between the F and Si in WF _6. Since the generated SiF ₄ is vaporized, as a result, Si is consumed and defects occur in the silicon substrate.

  Third, there is a problem that the junction leakage current increases also in the lateral direction of the silicon substrate. That is, since the silicidation reaction proceeds isotropically, the contact hole is joined to the silicon substrate by overetching of the silicon substrate, and junction leakage occurs in the lateral direction of the silicon substrate.

  The present invention has been made in view of such problems. That is, an object of the present invention is to provide a method for manufacturing a semiconductor device that is fine and has excellent electrical characteristics.

  Other objects and advantages of the present invention will become apparent from the following description.

  A first invention of the present application includes a step of ion-implanting impurities into a silicon substrate to form a diffusion layer region, a step of forming an interlayer insulating film on the silicon substrate, and an interlayer insulating film using a predetermined mask The contact hole reaching the diffusion layer region is formed by dry etching, and the process of recessing the bottom surface of the contact hole from the surface of the silicon substrate by over-etching the interlayer insulating film and covering the inner surface of the contact hole with the interlayer The step of forming a polysilicon film on the insulating film, the step of forming a metal film on the polysilicon film, the step of forming a barrier metal film on the metal film, and silicide the metal film by heat treatment Forming a metal silicide layer on the diffusion layer region, and embedding a conductive layer inside the contact hole, The method of manufacturing a semiconductor device characterized by a step of forming a contact plug electrically connected to the.

  The second invention of the present application includes a step of ion-implanting impurities into a silicon substrate to form a diffusion layer region, a step of forming a stopper film on the silicon substrate, and an interlayer insulating film on the stopper film. A step of forming the opening to the stopper film by dry etching the interlayer insulating film using a predetermined mask, and dry etching of the stopper film using the interlayer insulating film as a mask. In addition to forming a contact hole, the process of recessing the bottom surface of the contact hole from the surface of the silicon substrate by over-etching the stopper film and forming a polysilicon film on the interlayer insulating film so as to cover the inner surface of the contact hole A step of forming a metal film on the polysilicon film, and a barrier metal on the metal film. Forming a metal silicide layer on the diffusion layer region, and embedding a conductive layer inside the contact hole to electrically connect to the diffusion layer region And a step of forming a contact plug.

  Further, the third invention of the present application includes a step of forming a gate insulating film on a silicon substrate, a step of forming a gate electrode on the gate insulating film, and an impurity in the silicon substrate using the gate electrode as a mask. The step of forming an extension region by ion implantation, the step of forming a sidewall on the side wall portion of the gate electrode, and the ion implantation of impurities into the silicon substrate using the gate electrode formed with the sidewall as a mask to form a diffusion layer region Forming a stopper film on the silicon substrate and the gate electrode on which the sidewall is formed, forming an interlayer insulating film on the stopper film, and using a predetermined mask Dry etching the interlayer insulating film to form an opening reaching the stopper film, and a stopper using the interlayer insulating film as a mask The contact hole that reaches the diffusion layer region is formed by dry etching of the step, and the process of recessing the bottom surface of the contact hole from the surface of the silicon substrate by overetching the stopper film, and the surface of the silicon substrate after the contact hole is formed A step of forming a polysilicon film on the interlayer insulating film so as to cover the inner surface of the contact hole after the cleaning, a step of forming a metal film on the polysilicon film, and the metal A step of forming a barrier metal film on the film, a step of siliciding the metal film by heat treatment to form a metal silicide layer on the diffusion layer region, and a conductive layer embedded in the contact hole to form a diffusion layer Forming a contact plug electrically connected to the region A method of manufacture of the device.

  As described above, according to the present invention, since the polysilicon film is formed after the formation of the contact hole and the subsequent cleaning process, the amount of silicon disappeared from the silicon substrate by overetching and silicidation is reduced. be able to. Therefore, it is possible to manufacture a semiconductor device that is fine and has excellent electrical characteristics.

Embodiment 1 FIG.
A method for manufacturing a semiconductor device according to the present embodiment will be described with reference to FIGS. In these drawings, parts using the same reference numerals are the same.

First, a silicon substrate 1 is prepared as a semiconductor substrate. Next, after an element isolation region 2 is formed by embedding an insulating film on the surface of the silicon substrate 1, an n-type or p-type impurity is implanted to form a diffusion layer 3. Thereafter, a gate insulating film 4 is formed on the silicon substrate 1 to obtain the structure shown in FIG. As the gate insulating film 4, for example, a silicon oxide film (SiO ₂ film) formed by a thermal oxidation method can be used.

  Next, a polysilicon film to be the gate electrode 5 is formed on the gate insulating film 4. Next, the polysilicon film and the gate insulating film 4 are processed using a photolithography method to obtain the structure shown in FIG.

  Next, the extension region 6 is formed using an ion implantation method. For example, for the p-type diffusion layer, As (arsenic) is implanted using the gate electrode 5 as a mask. Next, after forming a silicon nitride film (SiN film) to be the sidewall 7 on the entire surface, the silicon nitride film is removed by reactive ion etching except for the side wall portion of the gate electrode 5. Subsequently, the diffusion layer region 8 is formed using an ion implantation method. For example, As is selectively ion-implanted into the region of the p-type diffusion layer using the gate electrode 5 on which the sidewall 7 is formed as a mask. Thereafter, activation by heat treatment can be performed to form an n-type diffusion layer region. For example, when the implantation energy is 10 keV, the junction depth is about 30 nm to 40 nm. Through the above steps, the structure shown in FIG. 3 is obtained.

  Next, after forming a silicon nitride film as the stopper film 9, an interlayer insulating film 10 is formed on the stopper film 9 (FIG. 4). By forming the stopper film 9, the recess amount of the silicon substrate can be controlled with high accuracy by over-etching described later. For example, a silicon oxide film or the like can be used as the interlayer insulating film 10. After the interlayer insulating film 10 is formed, the surface is flattened by a CMP (Chemical Mechanical Polishing) method. As the stopper film 9, a film other than a silicon nitride film can be used, but a film made of a material having a high etching selection ratio with the interlayer insulating film 10 is used.

  Next, in order to form a contact plug that is electrically connected to the diffusion layer region, a contact hole 11 is provided in the interlayer insulating film 10 (FIG. 5).

  Specifically, a resist film (not shown) having a predetermined pattern is formed on the interlayer insulating film 10 using a photolithography method, and then the interlayer insulating film 10 is dry-etched using the resist film as a mask. An opening reaching the stopper film 9 is provided. Next, after removing the resist film, the stopper film 9 is dry-etched using the interlayer insulating film 10 as a mask to form a contact hole 11 reaching the silicon substrate 1. At this time, over-etching is performed so that the stopper film 9 does not remain so that the silicon substrate 1 is completely exposed on the surface.

  By over-etching the stopper film 9, the bottom surface of the contact hole 11 is recessed from the surface of the silicon substrate 1 by several nm to several tens nm as shown in FIG. 5.

  After the formation of the contact hole 11, cleaning for removing etching residues and the like is performed. Specifically, the surface is wet-etched using a chemical solution such as buffered hydrofluoric acid. Then, side etching is performed at the bottom of the contact hole 11 as shown in FIG. 6 due to over-etching of the stopper film 9 and isotropic wet etching in the cleaning process.

  In the present embodiment, a polysilicon film 12 is deposited on the inner surface of the contact hole 11 and the interlayer insulating film 10 in FIG. Here, the thickness of the polysilicon film 12 is set to be larger than the depth at which the bottom surface of the contact hole 11 is recessed with respect to the surface of the silicon substrate 1. For example, if the recess depth is about the same as the film thickness of the stopper film 9 (50 to 200 mm), the film thickness of the polysilicon film 12 is made larger than the film thickness of the stopper film 9. In this way, as shown in FIG. 7, the portion disappeared by overetching of the silicon substrate 1 can be completely replenished with the polysilicon film 12.

  The thickness of the polysilicon film 12 is made smaller than the thickness of silicon consumed by silicidation performed in a later process. As a result, the unreacted polysilicon film 12 does not remain after silicidation.

For example, the amount of Si consumed when forming TiSi ₂ is about 2.27 when Ti is 1. Therefore, when a titanium film having a thickness of about 300 mm is formed, the film thickness of silicon consumed for silicidation becomes 600 mm or more. Further, the amount of Si consumed when forming CoSi ₂ is about 3.64 when Co is 1. Therefore, when a cobalt film having a thickness of about 300 mm is formed, the amount of silicon consumed for silicidation becomes 950 mm or more.

  The thickness of silicon consumed by silicidation is generally larger than the depth at which the bottom surface of the contact hole 11 is recessed. Therefore, in order to prevent unreacted polysilicon film 12 from remaining after silicidation, the thickness of polysilicon film 12 is made smaller than the thickness of silicon consumed by silicidation. When a polysilicon film having a thickness substantially equal to the thickness is formed, the silicon substrate in the over-etched portion in FIG. Can be used. In other words, the thickness of the silicon substrate 1 consumed by silicidation can be limited to a part of the silicon substrate 1 consumed when the polysilicon film 12 is not provided.

  For example, if the thickness of silicon consumed by silicidation is a and the depth at which the bottom surface of the contact hole is recessed with respect to the surface of the silicon substrate is b, there is a relationship of a> b. According to the conventional method, since silicon consumed for silicidation is supplied only from the silicon substrate, the thickness of the silicon substrate that disappears after silicidation is (a + b). On the other hand, according to the present embodiment, by providing a polysilicon film having a film thickness c (where a> c> b), the silicon substrate that has disappeared due to overetching can be completely supplemented with the polysilicon film. The thickness of the silicon substrate consumed by silicidation can be kept at (ac). Here, (ac) is preferably set to be 300 mm or less. As a result, it is possible to manufacture a semiconductor device having excellent electrical characteristics even when the junction in the diffusion layer region becomes shallower.

  After the polysilicon film 12 is formed, ion species having the same polarity as the diffusion layer region 8 to be connected are ion-implanted into the polysilicon film 12 and the silicon substrate 1 (FIG. 8). Thereafter, heat treatment is performed to activate the implanted ion species. As a result, the contact resistance and the junction leakage current can be reduced.

  However, if the polysilicon film 12 is doped with an ion species having the same polarity as that of the diffusion layer region 8 to which the contact hole 11 is bonded, the above ion implantation step is not necessary. In this case, the contact resistance and the junction leakage current can be similarly reduced by performing a heat treatment after forming the polysilicon film 12 and diffusing the doped ionic species into the silicon substrate 1.

  In this embodiment, since the polysilicon film 12 is entirely consumed by the silicidation reaction, the polysilicon film 12 after film formation may be either doped or undoped.

  Next, in order to form a metal silicide film, a metal film 13 such as Ti and a barrier metal film 14 such as TiN are formed in this order by a CVD (Chemical Vapor Deposition) method (FIG. 9). According to the present embodiment, since the overetched portion is covered with the polysilicon film 12, the barrier metal film 14 can be formed with a uniform film thickness.

Next, heat treatment is performed at a temperature of about several hundred degrees to cause the metal film 13 to react with the polysilicon film 12 and the silicon substrate 1 to form a metal silicide layer 15 shown in FIG. When a Ti film is formed as the metal film 13, a TiSi ₂ layer is formed as the metal silicide layer 15. When a Co (cobalt) film is formed as the metal film 13, a CoSi ₂ layer is formed as the metal silicide layer 15. According to the present embodiment, since the consumption of the silicon substrate 1 can be reduced as compared with the conventional case, the contact hole 11 and the silicon substrate 1 can be joined at a shallow depth of the silicon substrate 1.

  In FIG. 10A, a metal silicide layer 15 and a barrier metal film 14 are formed on the side wall portion of the contact hole 11. On the other hand, when the metal film 13 and the barrier metal film 14 are formed by sputtering, they are formed with a thin film thickness on the side wall, so that the unreacted polysilicon film 12 remains on the side wall. 10 (b). Although any structure may be used in the present embodiment, the CVD method is preferable because the barrier metal film 14 may be locally thinned at the side wall in the sputtering method.

  After the silicidation reaction is completed, a conductive layer 16 such as W is formed so as to fill the inside of the contact hole 11. Thereafter, by using the CMP method, the unnecessary conductive layer 16 and the barrier metal film 14 are removed to form a contact plug. Subsequently, by forming a metal wiring 17 such as aluminum, the structure of FIG. 11 can be obtained.

According to the present embodiment, since the polysilicon film is formed after the formation of the contact hole and the subsequent cleaning process, the amount of silicon disappearing from the silicon substrate by overetching and silicidation can be reduced. . Therefore, since the contact hole can be bonded to the silicon substrate at a shallow depth of the silicon substrate, the contact resistance of the contact can be kept low, and junction leakage in the vertical direction of the silicon substrate can be suppressed. In addition, since the portion where side etching occurs due to overetching on the silicon substrate or wet etching in the cleaning process is covered with a polysilicon film, the barrier metal film is not locally thinned, and a desired film thickness can be obtained. Can be formed. Therefore, it becomes possible to prevent a defect from occurring in the silicon substrate by suppressing the reaction between F and Si in WF ₆ . Furthermore, since the portion where the side etching occurs is covered with the polysilicon film, it is possible to prevent junction leakage from occurring in the lateral direction of the silicon substrate.

Embodiment 2. FIG.
A method for manufacturing a semiconductor device according to the present embodiment will be described with reference to FIGS. In these drawings, parts using the same reference numerals are the same.

A silicon substrate 21 is prepared as a semiconductor substrate. Next, after an element isolation region 22 is formed by embedding an insulating film on the surface of the silicon substrate 21, an n-type or p-type impurity is implanted to form a diffusion layer 23. Thereafter, a gate insulating film 24 is formed on the silicon substrate 21 to obtain the structure shown in FIG. As the gate insulating film 24, for example, a silicon oxide film (SiO ₂ film) formed by a thermal oxidation method can be used.

  Next, a polysilicon film to be the gate electrode 25 is formed on the gate insulating film 24. Next, the polysilicon film and the gate insulating film 24 are processed using a photolithography method to obtain the structure shown in FIG.

  Next, the extension region 26 is formed using an ion implantation method. For example, for the p-type diffusion layer, As (arsenic) is implanted using the gate electrode 25 as a mask. Next, after forming a silicon nitride film (SiON film) to be the sidewall 27 on the entire surface, the silicon nitride film is removed by reactive ion etching except for the side wall portion of the gate electrode 25. Subsequently, the diffusion layer region 28 is formed by ion implantation. For example, As is selectively ion-implanted into the region of the p-type diffusion layer using the gate electrode 25 formed with the sidewall 27 as a mask. Thereafter, activation by heat treatment can be performed to form an n-type diffusion layer region. For example, when the implantation energy is 10 keV, the junction depth is about 30 nm to 40 nm. Through the above steps, the structure shown in FIG. 14 is obtained.

  Next, after forming a silicon nitride film as the stopper film 29, an interlayer insulating film 30 is formed on the stopper film 29 (FIG. 15). As the interlayer insulating film 30, for example, a silicon oxide film or the like can be used. After the interlayer insulating film 30 is formed, the surface is planarized by a CMP (Chemical Mechanical Polishing) method. As the stopper film 29, a film other than a silicon nitride film can be used, but a film made of a material having a high etching selectivity with respect to the interlayer insulating film 30 is used.

  Next, a contact hole is provided in the interlayer insulating film 30 in order to form a contact plug electrically connected to the diffusion layer region 28.

  Specifically, a resist film (not shown) having a predetermined pattern is formed on the interlayer insulating film 30 using a photolithography method, and then the interlayer insulating film 30 is dry-etched using the resist film as a mask. An opening reaching the stopper film 29 is provided. Next, after removing the resist film, the stopper film 29 is dry-etched using the interlayer insulating film 30 as a mask to form a contact hole 31 reaching the silicon substrate 21 (FIG. 16). At this time, over-etching is performed so that the stopper film 29 does not remain so that the silicon substrate 21 is completely exposed on the surface.

  By over-etching the stopper film 29, the bottom surface of the contact hole 31 is recessed from the surface of the silicon substrate 21 by several nm to several tens of nm as shown in FIG.

  After the formation of the contact hole 31, cleaning for removing etching residues and the like is performed. Specifically, the surface is wet-etched using a chemical solution such as buffered hydrofluoric acid. Thus, side etching is performed at the bottom of the contact hole 31 as shown in FIG. 17 due to over-etching of the stopper film 29 and isotropic wet etching in the cleaning process.

  Next, a polysilicon film 32 is deposited on the inner surface of the contact hole 31 and the interlayer insulating film 30 in FIG. The present embodiment is characterized in that the thickness of the polysilicon film 32 is made larger than the thickness of silicon consumed by silicidation performed in a later process. By doing so, the over-etched portion can be completely covered with the polysilicon film 32 as shown in FIG.

  In the present embodiment, since the polysilicon film 32 remains after silicidation, the conductive layer 36 formed in a later process is bonded to the polysilicon film 32. Therefore, unlike the first embodiment, the polysilicon film 32 needs to be doped with impurities. Specifically, when undoped polysilicon is used as the polysilicon film 32, ion species having the same polarity as the diffusion layer region 28 to be connected are formed in the polysilicon film 32 and the silicon substrate 21 after the polysilicon film 32 is formed. Ions are implanted (FIG. 19). Thereafter, heat treatment is performed to activate the doped ionic species. As a result, the contact resistance and the junction leakage current can be reduced.

  When the polysilicon film 32 is doped with an ion species having the same polarity as that of the diffusion layer region 28 to which the contact hole 31 is bonded, the above ion implantation process is not necessary. In this case, heat treatment is performed after the polysilicon film 32 is formed, and the doped ion species are diffused into the silicon substrate 21, whereby the contact resistance and the junction leakage current can be similarly reduced.

  Next, in order to form a metal silicide film, a metal film 33 such as Ti and a barrier metal film 34 such as TiN are formed in this order by a CVD (Chemical Vapor Deposition) method (FIG. 20). According to this embodiment, since the polysilicon film 32 covers the portion where the side etching has occurred, the barrier metal film 34 can be formed with a uniform film thickness.

Next, heat treatment is performed at a temperature of about several hundred degrees to cause the metal film 33 to react with the polysilicon film 32 to form a metal silicide layer 35 shown in FIG. When a Ti film is formed as the metal film 33, a TiSi ₂ layer is formed as the metal silicide layer 35. When a Co (cobalt) film is formed as the metal film 33, a CoSi ₂ layer is formed as the metal silicide layer 35. In this embodiment, since the thickness of the polysilicon film 32 is larger than the thickness of silicon consumed by silicidation, the unreacted polysilicon film 32 remains under the metal silicide layer 35. To do.

  In FIG. 21, a polysilicon film 32, a metal silicide layer 35, and a barrier metal film 34 are formed on the side wall portion of the contact hole 31. On the other hand, when the metal film 33 and the barrier metal film 34 are formed by the sputtering method, they are formed with a thin film thickness on the side wall, so that more unreacted polysilicon films 32 than in the example of FIG. It remains on the side wall. Although any structure may be used in the present embodiment, the CVD method is preferable because the barrier metal film 34 may be locally thinned at the side wall in the sputtering method.

  After the silicidation reaction is completed, a conductive layer 36 of W or the like is formed so as to fill the inside of the contact hole 31. Thereafter, by using a CMP (Chemical Mechanical Polishing) method, the unnecessary conductive layer 36 and the barrier metal film 34 are removed to form a contact plug. Subsequently, by forming a metal wiring 37 such as aluminum, the structure of FIG. 22 can be obtained.

According to the present embodiment, since the polysilicon film is formed with a film thickness equal to or larger than that of silicon consumed by silicidation, the over-etched portion of the silicon substrate can be complemented and consumed by silicidation. All of the silicon can be covered by the polysilicon film. Further, since the contact hole is bonded to the remaining polysilicon film, it is possible to suppress the junction leak in the vertical direction of the silicon substrate. In addition, since the portion where side etching occurs due to over-etching on the silicon substrate or wet etching in the cleaning step is covered with the polysilicon film, the barrier metal film can be formed with a desired film thickness. Therefore, it becomes possible to prevent a defect from occurring in the silicon substrate by suppressing the reaction between F and Si in WF ₆ . Furthermore, since the portion where the side etching occurs is covered with the polysilicon film, it is possible to prevent junction leakage from occurring in the lateral direction of the silicon substrate.

In the present embodiment, since the polysilicon film remains under the metal silicide layer, the resistance becomes higher than that in the first embodiment. However, since the thickness of the polysilicon film formed on the side wall portion of the contact hole is larger than that of the first embodiment, unreacted Ti does not remain on the side wall. Moreover, even if the barrier metal film has a thin part, it is caused by the reaction between F and Ti in WF ₆ , and the barrier metal film is more effectively peeled off due to the volume expansion of the hole side wall. It becomes possible to suppress. In particular, when the barrier metal film is formed by the sputtering method, the thickness of the barrier metal film on the side wall portion of the contact hole becomes thinner than that by the CVD method, but unreacted Ti remains. Since the fear is further reduced, the above problem can be suppressed.

FIG. 6 is a diagram for explaining the method for manufacturing the semiconductor device according to the first embodiment; FIG. 6 is a diagram for explaining the method for manufacturing the semiconductor device according to the first embodiment; FIG. 6 is a diagram for explaining the method for manufacturing the semiconductor device according to the first embodiment; FIG. 6 is a diagram for explaining the method for manufacturing the semiconductor device according to the first embodiment; FIG. 6 is a diagram for explaining the method for manufacturing the semiconductor device according to the first embodiment; FIG. 6 is a diagram for explaining the method for manufacturing the semiconductor device according to the first embodiment; FIG. 6 is a diagram for explaining the method for manufacturing the semiconductor device according to the first embodiment; FIG. 6 is a diagram for explaining the method for manufacturing the semiconductor device according to the first embodiment; FIG. 6 is a diagram for explaining the method for manufacturing the semiconductor device according to the first embodiment; 2A and 2B are diagrams illustrating a method for manufacturing the semiconductor device according to the first embodiment, in which FIG. 1A shows a case where a metal film and a barrier metal film are formed by a CVD method, and FIG. 2B shows a case where these films are formed by a sputtering method. It is. FIG. 6 is a diagram for explaining the method for manufacturing the semiconductor device according to the first embodiment; FIG. 10 is a diagram for explaining the method for manufacturing the semiconductor device according to the second embodiment; FIG. 10 is a diagram for explaining the method for manufacturing the semiconductor device according to the second embodiment; FIG. 10 is a diagram for explaining the method for manufacturing the semiconductor device according to the second embodiment; FIG. 10 is a diagram for explaining the method for manufacturing the semiconductor device according to the second embodiment; FIG. 10 is a diagram for explaining the method for manufacturing the semiconductor device according to the second embodiment; FIG. 10 is a diagram for explaining the method for manufacturing the semiconductor device according to the second embodiment; FIG. 10 is a diagram for explaining the method for manufacturing the semiconductor device according to the second embodiment; FIG. 10 is a diagram for explaining the method for manufacturing the semiconductor device according to the second embodiment; FIG. 10 is a diagram for explaining the method for manufacturing the semiconductor device according to the second embodiment; FIG. 10 is a diagram for explaining the method for manufacturing the semiconductor device according to the second embodiment; FIG. 10 is a diagram for explaining the method for manufacturing the semiconductor device according to the second embodiment;

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,21 Silicon substrate 2,22 Element isolation region 3,23 Diffusion layer 4,24 Gate insulating film 5,25 Gate electrode 6,26 Extension region 7,27 Side wall 8,28 Diffusion layer region 9,29 Stopper film 10, 30 Interlayer insulating film 11, 31 Contact hole 12, 32 Polysilicon film 13, 33 Metal film 14, 34 Barrier metal film 15, 35 Metal silicide layer 16, 36 Conductive layer 17, 37 Metal wiring

Claims (9)

A step of ion-implanting impurities into the silicon substrate to form a diffusion layer region;
Forming an interlayer insulating film on the silicon substrate;
The interlayer insulating film is dry-etched using a predetermined mask to form a contact hole reaching the diffusion layer region, and the bottom surface of the contact hole is recessed from the surface of the silicon substrate by over-etching the interlayer insulating film. And a process of
Forming a polysilicon film on the interlayer insulating film so as to cover the inner surface of the contact hole;
Forming a metal film on the polysilicon film;
Forming a barrier metal film on the metal film;
Siliciding the metal film by heat treatment to form a metal silicide layer on the diffusion layer region;
And a step of forming a contact plug which is embedded in the contact hole and electrically connected to the diffusion layer region. A step of ion-implanting impurities into the silicon substrate to form a diffusion layer region;
Forming a stopper film on the silicon substrate;
Forming an interlayer insulating film on the stopper film;
Dry etching the interlayer insulating film using a predetermined mask to form an opening reaching the stopper film;
A contact hole reaching the diffusion layer region is formed by dry etching of the stopper film using the interlayer insulating film as a mask, and a bottom surface of the contact hole is recessed from the surface of the silicon substrate by overetching of the stopper film. And a process of
Forming a polysilicon film on the interlayer insulating film so as to cover the inner surface of the contact hole;
Forming a metal film on the polysilicon film;
Forming a barrier metal film on the metal film;
Siliciding the metal film by heat treatment to form a metal silicide layer on the diffusion layer region;
And a step of forming a contact plug which is embedded in the contact hole and electrically connected to the diffusion layer region. Forming a gate insulating film on the silicon substrate;
Forming a gate electrode on the gate insulating film;
Using the gate electrode as a mask, implanting impurities into the silicon substrate to form an extension region;
Forming a sidewall on the sidewall of the gate electrode;
Using the gate electrode with the sidewall formed as a mask, ion-implanting impurities into the silicon substrate to form a diffusion layer region;
Forming a stopper film on the silicon substrate and the gate electrode on which the sidewall is formed;
Forming an interlayer insulating film on the stopper film;
Dry etching the interlayer insulating film using a predetermined mask to form an opening reaching the stopper film;
A contact hole reaching the diffusion layer region is formed by dry etching of the stopper film using the interlayer insulating film as a mask, and a bottom surface of the contact hole is recessed from the surface of the silicon substrate by overetching of the stopper film. And a process of
Cleaning the surface of the silicon substrate after forming the contact holes;
Forming a polysilicon film on the interlayer insulating film so as to cover the inner surface of the contact hole after the cleaning;
Forming a metal film on the polysilicon film;
Forming a barrier metal film on the metal film;
Siliciding the metal film by heat treatment to form a metal silicide layer on the diffusion layer region;
And a step of forming a contact plug which is embedded in the contact hole and electrically connected to the diffusion layer region. The step of forming the polysilicon film is a step of forming a non-doped polysilicon film,
After the step of forming the non-doped polysilicon film, a step of implanting ion species having the same polarity as the diffusion layer region into the non-doped polysilicon film and the silicon substrate under the non-doped polysilicon film. When,
The method for manufacturing a semiconductor device according to claim 1, further comprising a step of activating the implanted ion species by heat treatment. The step of forming the polysilicon film is a step of forming a doped polysilicon film containing ion species having the same polarity as the diffusion layer region,
The semiconductor device according to claim 1, further comprising, after the step of forming the doped polysilicon film, a step of diffusing the ion species into the silicon substrate under the doped polysilicon film by a heat treatment. Manufacturing method.   The method of manufacturing a semiconductor device according to claim 1, wherein a thickness of the polysilicon film is larger than a depth at which a bottom surface of the contact hole is recessed with respect to a surface of the silicon substrate. The thickness of the polysilicon film is smaller than the thickness of silicon consumed by silicidation of the metal film,
The method of manufacturing a semiconductor device according to claim 6, wherein the step of forming the metal silicide layer is a step in which the metal film reacts with the polysilicon film and the silicon substrate.   The method of manufacturing a semiconductor device according to claim 7, wherein a thickness of the silicon substrate that reacts with the metal film is 300 mm or less. The thickness of the polysilicon film is larger than the thickness of silicon consumed by silicidation of the metal film,
The method of manufacturing a semiconductor device according to claim 6, wherein the step of forming the metal silicide layer is a step in which the metal film reacts with a part of the polysilicon film.

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