JP2006108403A - Semiconductor device and manufacturing method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable high-voltage driving and increase speed while suppressing deterioration in reliability of a transistor.
A second single crystal semiconductor layer is formed on a first single crystal semiconductor layer by epitaxial growth using the antioxidant film as a mask, and a second single crystal semiconductor layer is formed using the antioxidant film as a mask. 5, the constituent components of the second single crystal semiconductor layer 5 are diffused into the first single crystal semiconductor layer 3, and a part of the first single crystal semiconductor layer 3 is formed in the third single crystal semiconductor layer 7. After the conversion, a fourth single crystal semiconductor layer 8 is formed on the first single crystal semiconductor layer 3 and the third single crystal semiconductor layer 7, and is disposed on the third single crystal semiconductor layer 7. A gate insulating film 11 is formed over the layer 8, and an offset gate layer 15 b and a drain layer 15 c are formed in the first single crystal semiconductor layer 3 and the fourth single crystal semiconductor layer 8.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and is particularly suitable for application to a method of forming a transistor with a strained semiconductor and an unstrained semiconductor.

In a conventional semiconductor device, there is a method of increasing the mobility of electrons and holes by applying a tensile stress to a semiconductor layer having a channel region, thereby increasing the speed of a field effect transistor formed in the semiconductor layer. Here, Non-Patent Document 1 discloses a method of applying strain to the entire Si thin film layer on a buried insulating layer (BOX layer) in an SOI (Silicon On Insulator) structure. Non-Patent Document 2 discloses a method of distorting the entire Si thin film layer in which a source / channel / drain is formed in a MOS (Metal Oxide Semiconductor) transistor formed in a bulk semiconductor.
K. Rim, K.M. Chan, D.C. Boyd, J .; Ott, N.M. Kiymko, F.M. Casdone, L.M. Tai, S .; Koester, M.C. Cobb, D.C. Canaperi, B.M. To, E .; Duch, I.D. Babich, R.A. Carruthers, P.M. Saunders, G.M. Walker, Y. et al. Zhang, M .; Steen, and M.M. Ieon “Fabrication and Mobility Characeristics of Ultra-thin Strained Si Dirty on Insulator (SSDOI) MOSFETs” 2003 IEEE 3.1.1-3.1.4. H. C. -H. Wang, Y .; -P. Wang, S.W. -J. Chen, C.I. -H. Ge, S.M. M.M. Ting, J .; -Y. Kung, R.A. -L. Hwang, H .; -K. Chiu, L. C. Sheu, P .; -Y. Tsai, L .; -G. Yao, S .; -C. Chen, H .; -J. Tao, Y .; -C. Yeo, W .; -C. Lee, and C.L. Hu “Substrate-Strained Silicon Technology: Process Integration” 2003 IEEE 3.4.1-3.4.4.

However, if tensile stress is applied to the entire Si thin film layer on which the source / channel / drain is formed, the band gap and the drain breakdown voltage are reduced. For this reason, there are problems in that the high voltage drive of the transistor is hindered and the reliability of the field effect transistor is deteriorated.
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor device and a method for manufacturing the semiconductor device that can be driven at a high voltage and can be increased in speed while suppressing deterioration in reliability.

In order to solve the above-described problem, according to a semiconductor device of one embodiment of the present invention, at least two of a source region, a channel region, and a drain region of a field effect transistor are formed of semiconductors having different strains. It is characterized by being.
As a result, the band gap can be made different for each of the source region, the channel region, and the drain region, and the mobility of electrons and holes in the channel region can be improved while suppressing a decrease in drain breakdown voltage. For this reason, it is possible to increase the speed of the transistor while enabling high-voltage driving, and to improve the reliability of the transistor.

In addition, according to the semiconductor device of one embodiment of the present invention, the source side of the channel region is configured by a tensile stressed semiconductor layer, and the drain side of the channel region is configured by an unstrained semiconductor layer. It is characterized by being.
Accordingly, it is possible to improve the mobility of electrons and holes in the channel region while suppressing a decrease in the breakdown voltage of the transistor, and to increase the speed of the transistor while enabling high voltage driving.

In the semiconductor device according to one embodiment of the present invention, the channel region is formed of a semiconductor layer subjected to tensile stress, and the drain region is formed of an unstrained semiconductor layer. .
As a result, tensile stress can be applied only to the portion that contributes to the high speed operation of the transistor, and the portion that contributes to the breakdown voltage of the transistor can be prevented from being distorted. Therefore, it is possible to increase the speed of the transistor while enabling high voltage driving.

According to the semiconductor device of one aspect of the present invention, the unstrained semiconductor layer is composed of a single layer of Si, and the semiconductor layer subjected to tensile stress is composed of Si stacked on SiGe. It is characterized by being.
As a result, a semiconductor layer subjected to tensile stress can be formed by epitaxial growth, and the semiconductor layer subjected to tensile stress can be formed of a single crystal semiconductor, and the surface of the semiconductor layer subjected to tensile stress can be formed. It is possible to provide a Si layer. Therefore, the gate insulating film can be formed by thermal oxidation of Si, and the interface order between the gate insulating film and the semiconductor region can be reduced. As a result, the semiconductor layer subjected to tensile stress and the unstrained semiconductor layer can be formed on the same substrate while reducing current leakage, and the channel region is formed in the semiconductor layer subjected to tensile stress. It is possible to form the drain region with the unstrained semiconductor layer.

According to the semiconductor device of one embodiment of the present invention, the channel region is configured by a semiconductor layer subjected to tensile stress, and the drain region is configured by a semiconductor layer subjected to compressive stress. Features.
As a result, tensile stress can be applied to the portion that contributes to the high speed operation of the transistor, and compressive stress can be applied to the portion that contributes to the breakdown voltage of the transistor. Therefore, it is possible to increase the speed of the transistor while enabling high voltage driving.

According to the semiconductor device of one embodiment of the present invention, the first insulating film embedded in the element isolation region on the source region side and the first insulating film embedded in the element isolation region on the drain region side And a second insulating film having a higher stress than that of the second insulating film.
Thereby, compressive stress can be applied to the drain region side while preventing compressive stress from being applied to the source region side. For this reason, it is possible to apply a tensile stress to a portion that contributes to the breakdown voltage of the transistor while allowing a tensile stress to be applied to a portion that contributes to the high-speed operation of the transistor. Can be achieved.

The semiconductor device according to one embodiment of the present invention further includes an offset gate region that changes from tensile stress to no strain or compressive stress from the channel region side toward the drain region side.
As a result, it is possible to improve the mobility of electrons and holes in the channel region while suppressing a decrease in the drain breakdown voltage, and to relax the electric field on the drain region side. Therefore, it is possible to further increase the breakdown voltage of the transistor while increasing the speed of the transistor.

In addition, according to the semiconductor device of one embodiment of the present invention, the thickness of the semiconductor layer on the drain region side is larger than the thickness of the semiconductor layer on the channel region side.
As a result, carriers on the drain region side can be increased, and the drain resistance can be reduced. For this reason, it becomes possible to improve the driving capability of the transistor, and even when the mobility of electrons and holes in the drain region is inferior to the mobility of electrons and holes in the channel region, the high speed of the transistor can be compensated. it can.

In addition, according to the method for manufacturing a semiconductor device of one embodiment of the present invention, a step of forming an antioxidant film over the first semiconductor layer formed over the support substrate, and selectively removing the antioxidant film Then, a second semiconductor layer is selectively formed on the exposed first semiconductor layer by exposing a part of the first semiconductor layer and performing epitaxial growth using the antioxidant film as a mask. And a step of thermally oxidizing the second semiconductor layer using the antioxidant film as a mask to diffuse constituent components of the second semiconductor layer into the first semiconductor layer, and to form a third layer on the first semiconductor layer. Forming a semiconductor layer; removing an anti-oxidation film on the first semiconductor layer; removing an oxide film formed on the third semiconductor layer; the third semiconductor layer and the first semiconductor layer; 4th semiconductor on one semiconductor layer Forming a layer; and a source region and a channel region are disposed in the fourth semiconductor layer on the third semiconductor layer, and a drain region is disposed in the fourth semiconductor layer on the first semiconductor layer. And a step of forming a field effect transistor.

  This makes it possible to form semiconductor layers of different materials on the same substrate by performing epitaxial growth and heat treatment, and selectively perform epitaxial growth and thermal oxidation by using the same antioxidant film. Can do. For this reason, it is possible to accurately form the unstrained semiconductor layer and the strained semiconductor layer on the same substrate while suppressing complication of the manufacturing process, and it is possible to maintain good crystal quality. For this reason, it is possible to accurately form the unstrained semiconductor layer and the strained semiconductor layer on the same substrate while suppressing complication of the manufacturing process, and it is possible to maintain good crystal quality. For this reason, the channel region can be formed by the semiconductor layer to which tensile stress is applied, and the drain region can be formed by the unstrained semiconductor layer.

  According to the method for manufacturing a semiconductor device of one embodiment of the present invention, a step of forming an insulating film over the semiconductor substrate, and a step of forming an opening in the insulating film exposing a part of the semiconductor substrate; Removing a part of the semiconductor substrate through the opening to form a recess in the semiconductor substrate; and performing epitaxial growth using the insulating film as a mask to form the first semiconductor layer in the recess Burying in step, removing the insulating film on the first semiconductor layer, forming a second semiconductor layer on the semiconductor substrate in which the first semiconductor layer is embedded, and on the first semiconductor layer Forming a field effect transistor having a channel region disposed in the second semiconductor layer and a drain region disposed in the second semiconductor layer on the semiconductor substrate.

  Thereby, it becomes possible to give distortion only to a partial region of the semiconductor layer while maintaining the crystal quality of the semiconductor layer. For this reason, it is possible to form a channel region with a semiconductor layer to which tensile stress is applied, and it is possible to form a drain region with an unstrained semiconductor layer. It is possible to increase the speed.

Hereinafter, a semiconductor device and a manufacturing method thereof according to embodiments of the present invention will be described with reference to the drawings.
1 and 2 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the first embodiment of the present invention.
In FIG. 1A, an insulating layer 2 is formed on a support substrate 1, and a first single crystal semiconductor layer 3 is formed on the insulating layer 2. Then, by patterning the first single crystal semiconductor layer 3 using a photolithography technique and an etching technique, the first single crystal semiconductor layer 3 is element-separated in a mesa shape. The support substrate 1 may be a semiconductor substrate such as Si, Ge, SiGe, GaAs, InP, GaP, GaN, SiC, or an insulating substrate such as glass, sapphire, or ceramic. Also good. Moreover, as a material of the 1st single crystal semiconductor layer 3, Si, Ge, SiGe, SiC, SiSn, PbS, GaAs, InP, GaP, GaN, ZnSe etc. can be used, for example, As the insulating layer 2, For example, an insulating layer such as SiO ₂ , SiON, or Si ₃ N ₄ or a buried insulating film can be used. In addition, as the semiconductor substrate in which the first single crystal semiconductor layer 3 is formed on the insulating layer 2, for example, an SOI substrate can be used. As the SOI substrate, a SIMOX (Separation by Implanted Oxgen) substrate, a bonded substrate is used. Alternatively, a laser annealing substrate or the like can be used.

  Next, as shown in FIG. 1B, an antioxidant film 4 is formed on the entire surface of the first single crystal semiconductor layer 3 by a method such as CVD. As the antioxidant film 4, for example, a silicon nitride film or a laminated structure of a silicon oxide film and a silicon nitride film can be used. Then, by patterning the antioxidant film 4 using a photolithography technique and an etching technique, a part of the first single crystal semiconductor layer 3 remains covered with the antioxidant film 4. The part is exposed from the antioxidant film 4. Then, the second single crystal semiconductor layer 5 is formed on part of the surface of the first single crystal semiconductor layer 3 by performing epitaxial growth using the antioxidant film 4 as a mask. Here, the second single crystal is formed on the first single crystal semiconductor layer 3 exposed from the antioxidant film 4 by performing epitaxial growth while covering a part of the first single crystal semiconductor layer 3 with the antioxidant film 4. The semiconductor layer 5 can be selectively formed.

  In addition, as a material of the 2nd single crystal semiconductor layer 5, Si, Ge, SiGe, SiC, SiSn, PbS, GaAs, InP, GaP, GaN, ZnSe etc. can be used, for example. Here, when Si is used as the material of the first single crystal semiconductor layer 3, it is preferable to use SiGe as the material of the second single crystal semiconductor layer 5. As a result, the lattice constants of the first single crystal semiconductor layer 3 and the second single crystal semiconductor layer 5 can be made closer to each other, and the second single crystal semiconductor layer 5 having good crystal quality can be formed on the first single crystal semiconductor layer 3. Can be formed stably.

  Next, as shown in FIG. 1C, the second single crystal semiconductor layer 5 is thermally oxidized using the antioxidant film 4 as a mask to thermally oxidize the second single crystal semiconductor layer 5, and the second single crystal semiconductor layer 5 is thermally oxidized. The constituent components of the crystalline semiconductor layer 5 are diffused into the first single crystal semiconductor layer 3 to convert a part of the first single crystal semiconductor layer 3 into the third single crystal semiconductor layer 7 and the third single crystal semiconductor layer 7. An oxide film 6 is formed thereon.

For example, when Si is used as the material of the first single crystal semiconductor layer 3 and SiGe is used as the material of the second single crystal semiconductor layer 5, when the second single crystal semiconductor layer 5 is thermally oxidized, Si among constituent components of SiGe. Is oxidized to become SiO ₂ , and an oxide film 6 is formed on the first single crystal semiconductor layer 3, and Ge is not oxidized, but diffuses into the first single crystal semiconductor layer 3, and the third single crystal semiconductor layer 7 As a result, Si _x Ge _1-x is formed. In the interface region between Si _x Ge _{1-x of} the third single crystal semiconductor layer 7 and Si of the first single crystal semiconductor layer 3, the Ge concentration gradient gently changes due to the diffusion of Ge.

  In addition, by performing epitaxial growth and heat treatment of the second single crystal semiconductor layer 5 using the antioxidant film 4 as a mask, the first single crystal semiconductor layer 3 and the third single crystal different in material are suppressed while suppressing the complexity of the manufacturing process. The crystal semiconductor layer 7 can be formed on the same support substrate 1 and the crystal quality of the first single crystal semiconductor layer 3 and the third single crystal semiconductor layer 7 can be maintained well.

When forming Si _x Ge _1-x as the third single crystal semiconductor layer 7 on the insulating layer 2, in addition to a method of diffusing Ge contained in SiGe into Si by thermal oxidation of SiGe, Ge may be selectively ion-implanted into the formed Si layer.
Next, as shown in FIG. 1D, the antioxidant film 4 on the first single crystal semiconductor layer 3 is removed, and the oxide film 6 on the third single crystal semiconductor layer 7 is removed. Then, by performing heat treatment on the third single crystal semiconductor layer 7, the third single crystal semiconductor layer 7 is relaxed and crystal defects in the third single crystal semiconductor layer 7 are recovered. Here, since the interface region between Si _x Ge _{1-x of} the third single crystal semiconductor layer 7 and Si of the first single crystal semiconductor layer 3 has a gentle Ge concentration gradient, the lattice constant changes sharply. Without the occurrence of defects. Furthermore, the interface between the insulating films 2, 4, 6 and the single crystal semiconductor layers 3, 7 plays the role of interstitial Si and vacancy suction ports, or the surface of the single crystal lattice, and suppresses the generation of defects. To do. Since Si _x Ge _{1-x of} the third single crystal semiconductor layer 7 and Si of the first single crystal semiconductor layer 3 are both thin films, the effect of the smooth surface to relieve stress is large, and crystal defects are recovered quickly. . Accordingly, Si _x Ge _{1-x of} the third single crystal semiconductor layer 7 and Si of the first single crystal semiconductor layer 3 having good crystallinity and different lattice constants can be formed on the insulating film 2. .

  Next, as shown in FIG. 2A, a fourth single crystal semiconductor layer 8 is formed on the first single crystal semiconductor layer 3 and the third single crystal semiconductor layer 7 by using epitaxial growth. Here, the material of the fourth single crystal semiconductor layer 8 is preferably the same as the material of the first single crystal semiconductor layer 3 and different from the material of the third single crystal semiconductor layer 7. Thus, on the first single crystal semiconductor layer 3, the lattice constants of the first single crystal semiconductor layer 3 and the fourth single crystal semiconductor layer 8 are matched so that the fourth single crystal semiconductor layer 8 is not distorted. On the third single crystal semiconductor layer 7, the third single crystal semiconductor layer 7 and the fourth single crystal semiconductor layer 8 have different lattice constants of the substances themselves, so that the fourth single crystal semiconductor It becomes possible to generate strain in the layer 8 and to form the strained semiconductor layer and the unstrained semiconductor layer on the same support substrate 1.

  For example, when Si is used as the material of the first single crystal semiconductor layer 3 and SiGe is used as the material of the second single crystal semiconductor layer 5, it is preferable to use Si as the material of the fourth single crystal semiconductor layer 8. Thereby, it is possible to prevent the fourth single crystal semiconductor layer 8 on the first single crystal semiconductor layer 3 from being distorted, and the fourth single crystal semiconductor layer 8 on the third single crystal semiconductor layer 7. It is possible to generate strain due to tensile stress. For this reason, on the first single crystal semiconductor layer 3, it is possible to suppress the reduction of the band gap of the fourth single crystal semiconductor layer 8 to ensure a breakdown voltage, and on the third single crystal semiconductor layer 7. The tensile stress can be applied to the fourth single crystal semiconductor layer 8, and the mobility of electrons and holes in the fourth single crystal semiconductor layer 8 can be improved.

  Next, as shown in FIG. 2B, by performing thermal oxidation of the fourth single crystal semiconductor layer 8, the gate is formed on the fourth single crystal semiconductor layer 8 disposed on the third single crystal semiconductor layer 7. An insulating film 11 is formed. Then, a polycrystalline silicon layer is formed on the fourth single crystal semiconductor layer 8 on which the gate insulating film 11 is formed by a method such as CVD. Then, the gate electrode 12 is formed on the fourth single crystal semiconductor layer 8 by patterning the polycrystalline silicon layer using a photolithography technique and an etching technique.

  Then, using the gate electrode 12 as a mask, impurities such as As, P, and B are ion-implanted into the first single crystal semiconductor layer 3, the third single crystal semiconductor layer 7, and the fourth single crystal semiconductor layer 8. An LDD layer 13 a made of a low concentration impurity introduction layer disposed on the source side of the electrode 12 is formed on the third single crystal semiconductor layer 7 and the fourth single crystal semiconductor layer 8 and disposed on the drain side of the gate electrode 12. An LDD layer 13 b made of a low concentration impurity introduction layer is formed on the first single crystal semiconductor layer 3 and the fourth single crystal semiconductor layer 8.

  Next, as shown in FIG. 2C, an insulating layer is formed on the fourth single crystal semiconductor layer 8 by a method such as CVD, and the insulating layer is etched back using anisotropic etching such as RIE. As a result, the side walls 14 a and 14 b are formed on the side walls of the gate electrode 12. Then, impurities are ion-implanted into the third single crystal semiconductor layer 7 and the fourth single crystal semiconductor layer 8 by using the gate electrode 12 and the side walls 14a and 14b as masks, thereby being arranged on the side of the side wall 14a. A source layer 15 a made of a high concentration impurity introduction layer is formed on the third single crystal semiconductor layer 7 and the fourth single crystal semiconductor layer 8. Further, by selectively ion-implanting impurities into the first single crystal semiconductor layer 3 and the fourth single crystal semiconductor layer 8, an offset gate layer comprising a medium concentration impurity introduction layer disposed on the side of the sidewall 14a. 15 b is formed in the first single crystal semiconductor layer 3 and the fourth single crystal semiconductor layer 8. Further, by selectively ion-implanting impurities into the first single crystal semiconductor layer 3 and the fourth single crystal semiconductor layer 8, a drain layer composed of a high concentration impurity introduction layer disposed on the side of the offset gate layer 15b. 15 c is formed in the first single crystal semiconductor layer 3 and the fourth single crystal semiconductor layer 8.

  Accordingly, the gate electrode 12 can be disposed on the fourth single crystal semiconductor layer 8 on the third single crystal semiconductor layer 7 and the fourth single crystal semiconductor layer 8 on the first single crystal semiconductor layer 3 can be provided. It is possible to dispose the offset gate layer 15b and the drain layer 15c on the fourth gate electrode, so that tensile stress can be applied to the fourth single crystal semiconductor layer 8 in the channel region, and the fourth of the offset gate layer 15b and the drain layer 15c can be applied. It is possible to prevent distortion from occurring in the single crystal semiconductor layer 8. As a result, tensile stress can be applied to the portion that contributes to the high-speed operation of the transistor, and compressive stress can be applied to the portion that contributes to the breakdown voltage of the transistor. The mobility of electrons and holes in the region can be improved. As a result, it is possible to increase the speed of the transistor while enabling high-voltage driving, and to improve the reliability of the transistor.

  Further, by using Si as the material of the fourth single crystal semiconductor layer 8, the gate insulating film 11 can be formed by thermal oxidation of Si, and the gate insulating film 11 and the fourth single crystal semiconductor layer 8 can be formed. The interface order can be reduced. As a result, the strained semiconductor layer and the unstrained semiconductor layer can be formed on the same support substrate 1 while reducing current leakage, and high speed driving of the transistor can be achieved while enabling high voltage driving. And deterioration of the reliability of the transistor can be suppressed.

  In addition, by oxidizing the first single crystal semiconductor layer 3 on which the second single crystal semiconductor layer 5 is stacked, a part of the film thickness of the first single crystal semiconductor layer 3 can be reduced. Therefore, the film thickness of the first single crystal semiconductor layer 3 on the drain region side can be made larger than the film thickness of the third single crystal semiconductor layer 7 on the channel region side. Can be increased, and the drain resistance can be reduced. For this reason, it becomes possible to improve the driving capability of the transistor, and even when the mobility of electrons and holes in the drain region is inferior to the mobility of electrons and holes in the channel region, the high speed of the transistor can be compensated. it can.

  In the above-described embodiment, the source layer 15a and the channel region are disposed in the fourth single crystal semiconductor layer 8 subjected to tensile stress, and the offset gate layer 15b and the drain layer 15c are disposed in the fourth single crystal semiconductor layer 8 without distortion. Although the method of disposing is described, compressive stress may be applied to the drain layer 15c. Further, the stress applied to the offset gate layer 15b may change from tensile stress to no strain or compressive stress from the channel region side toward the drain region side. Further, the source layer 15a is not necessarily constituted by a semiconductor layer subjected to tensile stress, and may be constituted by a semiconductor layer without distortion.

FIG. 3 is a cross-sectional view and a plan view showing a method for manufacturing a semiconductor device according to the second embodiment of the present invention.
In FIG. 3, it is assumed that the first single crystal semiconductor layer 3 is element-isolated by element isolation grooves M1 and M2. 2C, the thermal oxidation film 21 is formed on the surface of the fourth single crystal semiconductor layer 8 by performing thermal oxidation of the fourth single crystal semiconductor layer 8. Then, a low stress insulating film 22 and a high stress insulating film 23 are sequentially formed on the fourth single crystal semiconductor layer 8 on which the thermal oxide film 21 is formed. As the low stress insulating film 22, for example, a PSG film can be used, and as the high stress insulating film 23, for example, an HDP (High Density Plasma) oxide film can be used.

  Here, the width of the source-side element isolation trench M1 can be made narrower than the width of the drain-side element isolation trench M2. When the low-stress insulating film 22 is formed, the source-side element isolation groove M1 is completely filled with the low-stress insulating film 22, and the drain-side element isolation groove M2 is completely formed with the low-stress insulating film 22. Can be embedded in. When the high-stress insulating film 23 is formed, the high-stress insulating film 23 is not embedded in the source-side element isolation groove M1, and the drain-side element isolation groove M2 is formed by the high-stress insulating film 23. Can be completely embedded.

  Accordingly, the compressive stress F can be applied to the drain region side while preventing the compressive stress F from being applied to the source region side. For this reason, it is possible to apply a tensile stress to a portion that contributes to the breakdown voltage of the transistor while allowing a tensile stress to be applied to a portion that contributes to the high-speed operation of the transistor. It is possible to increase the speed.

FIG. 4 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a third embodiment of the present invention.
In FIG. 4A, an oxide film 32 is formed on the surface of the semiconductor substrate 31 by thermal oxidation of the semiconductor substrate 31. Then, by patterning the oxide film 32 using a photolithography technique and an etching technique, an opening for exposing a part of the semiconductor substrate 31 is formed in the oxide film 32. Then, the semiconductor substrate 31 is half-etched through the oxide film 32 in which the opening is formed, thereby forming the recess 33 in the semiconductor substrate 31.

  Next, as shown in FIG. 4B, the recess 33 is filled with the first single crystal semiconductor layer 34 by performing epitaxial growth using the oxide film 32 as a mask. Here, by performing epitaxial growth while the semiconductor substrate 31 is covered with the oxide film 32, the first single crystal semiconductor layer 34 can be selectively formed in the recess 33. Here, the material of the first single crystal semiconductor layer 34 can be selected so as to be different from that of the semiconductor substrate 31. For example, when Si is used as the material of the semiconductor substrate 31, it is preferable to use SiGe as the material of the first single crystal semiconductor layer 34. At this time, the Ge concentration of the SiGe layer of the first single crystal semiconductor layer 34 is gradually increased from the interface with the Si layer of the semiconductor substrate 31. This makes it possible to reduce the change in the lattice constant between the semiconductor substrate 31 and the first single crystal semiconductor layer 34, so that the first single crystal semiconductor layer 34 having a good crystal quality and a different lattice constant can be formed on the semiconductor substrate 31. Can be formed stably.

  Next, as shown in FIG. 4C, the second single crystal semiconductor layer 35 is formed on the semiconductor substrate 31 in which the first single crystal semiconductor layer 34 is embedded by using epitaxial growth. Here, the material of the second single crystal semiconductor layer 35 is preferably the same as the material of the semiconductor substrate 31 and is selected to be different from the material of the first single crystal semiconductor layer 34. For example, when Si is used as the material of the semiconductor substrate 31 and SiGe is used as the material of the first single crystal semiconductor layer 34, it is preferable to use Si as the material of the second single crystal semiconductor layer 35.

  Thereby, on the semiconductor substrate 31, it is possible to make the lattice constants of the semiconductor substrate 31 and the second single crystal semiconductor layer 35 coincide with each other so that the second single crystal semiconductor layer 35 is not distorted. On the first single crystal semiconductor layer 34, the first single crystal semiconductor layer 34 and the second single crystal semiconductor layer 35 are not matched in lattice constant so that the second single crystal semiconductor layer 35 is distorted. Is possible. For this reason, it is possible to form the strained semiconductor and the unstrained semiconductor on the same semiconductor substrate 31 while maintaining good crystal quality of the second single crystal semiconductor layer 35.

  For example, when Si is used as the material of the semiconductor substrate 31 and the second single crystal semiconductor layer 35 and SiGe is used as the material of the first single crystal semiconductor layer 34, the second single crystal semiconductor layer 35 is distorted on the semiconductor substrate 31. It becomes possible not to generate | occur | produce, and it becomes possible to generate | occur | produce distortion by tensile stress in the 2nd single crystal semiconductor layer 35 on the 1st single crystal semiconductor layer 34. FIG. Therefore, it is possible to suppress the reduction of the band gap of the second single crystal semiconductor layer 35 on the semiconductor substrate 31 to ensure a withstand voltage, and the second single crystal semiconductor on the first single crystal semiconductor layer 34. The mobility of electrons and holes in the layer 35 can be improved.

  Next, as illustrated in FIG. 4D, the gate insulating film 41 is formed on the second single crystal semiconductor layer 35 by performing thermal oxidation of the second single crystal semiconductor layer 35. Then, a polycrystalline silicon layer is formed on the second single crystal semiconductor layer 35 on which the gate insulating film 41 is formed by a method such as CVD. Then, the gate electrode 42 is formed on the second single crystal semiconductor layer 35 by patterning the polycrystalline silicon layer using a photolithography technique and an etching technique.

  Then, by using the gate electrode 42 as a mask, impurities such as As, P, and B are ion-implanted into the second single crystal semiconductor layer 35 and the semiconductor substrate 31, so that the low concentration respectively disposed on the side of the gate electrode 42 LDD layers 43 a and 43 b made of impurity introduction layers are formed on the semiconductor substrate 31. Then, an insulating layer is formed on the second single crystal semiconductor layer 35 by a method such as CVD, and the insulating layer is etched back using anisotropic etching such as RIE. 44a and 44b are formed. Then, impurities are ion-implanted into the second single crystal semiconductor layer 35 and the semiconductor substrate 31 using the gate electrode 42 and the sidewalls 44a and 44b as a mask, so that the high concentration disposed on the side of the sidewalls 44a and 44b. Source / drain layers 45 a and 45 b made of impurity introduction layers are formed on the second single crystal semiconductor layer 35 and the semiconductor substrate 31.

  As a result, it is possible to strain only a partial region of the second single crystal semiconductor layer 35 while maintaining the crystal quality of the second single crystal semiconductor layer 35. Therefore, a channel region can be formed in a portion of the second single crystal semiconductor layer 35 where tensile stress is applied, and a drain is formed in a portion of the second single crystal semiconductor layer 35 that is not strained. A region can be configured, and high-speed driving of the transistor can be achieved while enabling high-voltage driving.

Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 3rd Embodiment of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Support substrate, 2 Insulating layer, 3, 34 1st single crystal semiconductor layer, 4 Antioxidation film, 5, 35 2nd single crystal semiconductor layer, 6 Oxide film, 7 3rd single crystal semiconductor layer, 8 4th single crystal Semiconductor layer, 11, 41 Gate insulating film, 12, 42 Gate electrode, 13a, 13b, 43a, 43b LDD layer, 14a, 14b, 44a, 44b Side wall spacer, 15a, 45a Source layer, 15b Offset gate layer, 15c, 45b Drain layer, 21 Thermal oxide film, 22 Low stress insulating film, 23 High stress insulating film, M1, M2 Element isolation groove, 31 Semiconductor substrate, 32 Oxide film, 33 Recess

Claims (10)

  A semiconductor device, wherein at least two of a source region, a channel region, and a drain region of a field effect transistor are composed of semiconductors having different strains.   2. The semiconductor device according to claim 1, wherein a source side of the channel region is configured by a semiconductor layer subjected to tensile stress, and a drain side of the channel region is configured by an unstrained semiconductor layer.   2. The semiconductor device according to claim 1, wherein the channel region is composed of a semiconductor layer subjected to tensile stress, and the drain region is composed of an unstrained semiconductor layer.   4. The semiconductor device according to claim 2, wherein the unstrained semiconductor layer is composed of a single layer of Si, and the semiconductor layer subjected to the tensile stress is composed of Si laminated on SiGe. .   2. The semiconductor device according to claim 1, wherein the channel region is constituted by a semiconductor layer subjected to tensile stress, and the drain region is constituted by a semiconductor layer subjected to compressive stress. A first insulating film embedded in an element isolation region on the source region side;
6. The semiconductor device according to claim 5, further comprising a second insulating film buried in the element isolation region on the drain region side and having a larger stress than the first insulating film.   The semiconductor device according to claim 1, further comprising an offset gate region that changes from a tensile stress to an unstrained or compressive stress from the channel region side toward the drain region side.   8. The semiconductor device according to claim 1, wherein a film thickness of the semiconductor layer on the drain region side is larger than a film thickness of the semiconductor layer on the channel region side. Forming an antioxidant film on the first semiconductor layer formed on the support substrate;
Exposing the part of the first semiconductor layer by selectively removing the antioxidant film;
Selectively forming a second semiconductor layer on the exposed first semiconductor layer by performing epitaxial growth using the antioxidant film as a mask;
By thermally oxidizing the second semiconductor layer using the antioxidant film as a mask, the constituent components of the second semiconductor layer are diffused into the first semiconductor layer, and a third semiconductor layer is formed on the first semiconductor layer. And a process of
Removing an antioxidant film on the first semiconductor layer;
Removing an oxide film formed on the third semiconductor layer;
Forming a fourth semiconductor layer on the third semiconductor layer and the first semiconductor layer;
Forming a field effect transistor in which a source region and a channel region are disposed in a fourth semiconductor layer on the third semiconductor layer, and a drain region is disposed in the fourth semiconductor layer on the first semiconductor layer; A method for manufacturing a semiconductor device, comprising: Forming an insulating film on the semiconductor substrate;
Forming an opening in the insulating film to expose a part of the semiconductor substrate;
Forming a recess in the semiconductor substrate by removing a part of the semiconductor substrate through the opening;
Performing epitaxial growth using the insulating film as a mask to fill the recess with a first semiconductor layer;
Removing the insulating film on the first semiconductor layer;
Forming a second semiconductor layer on the semiconductor substrate in which the first semiconductor layer is embedded;
Forming a field effect transistor in which a channel region is disposed in the second semiconductor layer on the first semiconductor layer and a drain region is disposed in the second semiconductor layer on the semiconductor substrate. A method for manufacturing a semiconductor device.

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