JP2006086414A - Reverse blocking insulated gate semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a reverse blocking insulated gate semiconductor device which can reduce influence of flaws and stress applied to a collector layer on a reverse breakdown voltage after formation of the rear collector layer of a reverse blocking insulated-gate semiconductor device. <P>SOLUTION: The reverse blocking insulated gate semiconductor device has a p-base region 3 which is selectively formed in a first major surface 9 of an n-type semiconductor substrate 1, an n-type emitter region 4 which is selectively formed in the surface layer of the p-base region 3, a gate insulating film 5 which is applied to the first major surface 9 side of the p-base region 3 held between the remaining n-type drift layer 1 and the n-type emitter region 4, a gate electrode 6 applied via the insulating film 5, an isolation diffusion region 2 which surrounds the p-base region 3 via the n-type drift layer 1 and is formed from the first major surface 9 to the second major surface 10 of the substrate 1, and a p-type low implantation collector layer 8 which is formed in the second major surface 10 of the semiconductor substrate 1 and is connected to an isolation diffusion region 2 exposed to the second major surface 10. The low implantation collector layer 8 is formed by thermal diffusion of impurity atom whose diffusion coefficient is larger than that of impurity atom used for formation of the p-type base region 3. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a power semiconductor device used for a power conversion device or the like. More specifically, the present invention relates to a bidirectional device or a reverse blocking insulated gate bipolar transistor (hereinafter, abbreviated as a reverse blocking IGBT) having a separation diffusion layer and having a bidirectional breakdown voltage characteristic.

  Recently, in semiconductor power conversion devices, the adoption of bidirectional switching elements for matrix converter applications such as direct link conversion circuits such as AC (alternating current) / AC conversion, AC / DC (direct current) conversion, DC / AC conversion, etc. It has attracted attention from the viewpoints of circuit miniaturization, weight reduction, high efficiency, high speed response, and low cost. As such a bidirectional switching element, an element in which two reverse blocking IGBTs are connected in reverse parallel is known. As shown in FIG. 10, the reverse blocking IGBT includes a separation diffusion layer 111 formed by diffusion from the first main surface side 112, that is, from one side, and a MOS gate formed inside the separation diffusion layer 111. An active portion A having a structure, and a pressure-bonding termination structure 113 positioned between the active portion A and the isolation diffusion layer 111 are provided on the first main surface (front surface) side 112, and on the second main surface (back surface) side. Is a structure including a collector layer 103 having an impurity concentration controlled to low implantation.

When manufacturing the above-described low-injection reverse blocking IGBT, the back collector layer 103 is formed by forming a reverse breakdown voltage isolation diffusion region 111 and a MOS gate structure formed on the silicon substrate surface surrounded by the isolation diffusion region 111. After forming the silicon substrate, the back surface of the silicon substrate is ground and the separation diffusion region 111 is exposed on the back surface, and boron is dosed to the back surface at a dose of 1.2 × 10 ¹² cm ^{−2 to} 1.0 × 10 ¹⁶ cm ^{−. 2} is performed by activating boron as an acceptor having a concentration of about 5 × 10 ¹⁶ cm ^{−3 to} 5 × 10 ¹⁹ cm ⁻³ by annealing at 380 ° C. for 1 hour. The collector layer 103 has a thickness of about 0.3 μm to 1 μm because it has not undergone a thermal diffusion history. That is, since the annealing heat treatment is performed after the surface electrode is formed, it must be performed in a temperature region of 600 ° C. or less where the aluminum electrode on the surface does not melt, and the boron diffusion coefficient in silicon is very small. Boron atoms hardly move. If the acceleration energy at the time of ion implantation is increased to form the collector layer 103 having a thickness of 1 μm or more, the high-energy ions are greatly damaged by the silicon, and crystal defects in the silicon increase. Crystal defects are not preferred because they are difficult to recover by low-temperature annealing and cause an increase in reverse leakage current.

In the low-injection reverse blocking IGBT shown in FIG. 10, an NPT (Non Punch Through) wafer employing an FZ silicon substrate (the thickness of the substrate after forming the IGBT is, for example, 100 μm for 600 V withstand voltage and about 180 μm for 1200 V withstand voltage) Therefore, the collector layer 103 is thinned, its impurity concentration is appropriately controlled to control the minority carrier injection from the collector layer 103, and the on-voltage characteristics, which has been a problem in the past, can be obtained. The trade-off relationship regarding the turn-off loss can be improved and both can be reduced (Patent Document 1).
When a silicon substrate is doped, a method for manufacturing a power semiconductor element including forming a separation diffusion layer using selenium and sulfur as impurities having n conductivity type is known (Patent Document 2). Furthermore, it is well known to manufacture reverse blocking IGBTs by forming a separation diffusion layer (Patent Document 3).
JP 2002-319676 A Special table 2002-528913 gazette JP-A-7-307469

However, when manufacturing the above-described reverse blocking IGBT, after the formation of the back collector layer of the silicon substrate or during the chip and assembly, the substrate or the back surface of the chip may be damaged due to contact or abrasion as shown in FIG. There is. Since the thickness of the collector layer is as extremely thin as about 0.3 μm to 1 μm as described above, there is a possibility that the influence of scratches may extend to the pn junction between the back collector layer (p layer) and the drift layer (n layer). large. When the effect of the scratch B reaches the pn junction, the reverse breakdown voltage deteriorates and a characteristic failure occurs.
Furthermore, after the metal electrode film is coated on the back collector layer, the durability against the contact scratch and the scratch is increased. However, in the case of assembling work, the collector metal electrode film is interposed in the collector layer. There are cases where the pn junction is affected by scratches or the influence of stress due to the difference in thermal expansion coefficient. As a result, when the low injection reverse breakdown voltage IGBT chip is used as an element of the matrix converter module, 18 reverse blocking IGBTs are required. These chips are assembled to the matrix converter module by soldering. Later, when IGBTs having poor characteristics are mixed even with one chip, there is a problem that the whole becomes defective. In order to solve this problem, it is required to make a device that does not cause a breakdown voltage failure even if scratches or stress is applied to the back collector layer during handling or assembly of the silicon substrate or chip due to contact that is normally unavoidable. .

  The present invention has been made in view of the above-described problems, and an object of the present invention is to form a back collector layer of a reverse blocking insulated gate semiconductor device including a low-injection reverse blocking IGBT after the back collector layer is formed. An object of the present invention is to provide a reverse blocking insulated gate semiconductor device and a method for manufacturing the same, which can reduce the influence of applied scratches and stress on the reverse breakdown voltage.

  According to the first aspect of the present invention, the object is to select the second conductivity type base region selectively formed on the first main surface of the first conductivity type semiconductor substrate and the base region surface layer. A gate insulating film coated on the first main surface side surface of the base region sandwiched between the first conductivity type emitter region to be formed, the first conductivity type drift layer which is the remaining portion of the semiconductor substrate, and the emitter region And the gate electrode covered via the gate insulating film, and the second conductivity type base region are formed through the drift layer and formed from the first main surface to the second main surface of the substrate. Reverse blocking comprising a second conductivity type isolation diffusion region and a second conductivity type low injection collector layer formed on the second main surface of the semiconductor substrate and connected to the isolation diffusion region exposed to the second main surface Type insulated gate semiconductor device This is achieved by providing a reverse blocking insulated gate semiconductor device including a low injection collector layer formed by thermal diffusion of impurity atoms having a diffusion coefficient larger than that of the impurity atoms used for forming the second conductivity type base region. .

According to a second aspect of the present invention, the impurity atom used for forming the second conductivity type base region is boron, and the impurity atom used for forming the collector layer is aluminum or gallium. The reverse blocking insulated gate semiconductor device according to item 1 is preferable.
According to a third aspect of the present invention, the impurity atom used for forming the second conductivity type base region is phosphorus, and the impurity atom used for forming the collector layer is selenium or sulfur. The reverse blocking insulated gate semiconductor device according to Item 1 may be used.
According to the invention of claim 4, at least the step of forming the second conductivity type isolation diffusion region by thermal diffusion from the first main surface of the semiconductor substrate, the second conductivity type isolation diffusion region is surrounded. Forming a MOS gate structure excluding an aluminum electrode on the first main surface of the semiconductor substrate to be formed, grinding the second main surface side to expose the second conductivity type separation diffusion region to the second main surface side, aluminum Reverse blocking that includes ion implantation into the second main surface and thermal diffusion, formation of the emitter electrode and gate electrode pad on the first main surface, and deposition of a metal electrode on the second main surface in this order. The object is achieved by a method for manufacturing a type insulated gate semiconductor device.

  According to the present invention described above, the reverse blocking type insulated gate including the low injection reverse blocking IGBT that can reduce the influence of the scratches and stress applied to the collector layer on the reverse breakdown voltage after the back collector layer of the low injection reverse blocking IGBT is formed. A semiconductor device and a method for manufacturing the same can be provided.

FIG. 1 is a sectional view of a reverse blocking insulated gate bipolar transistor (reverse blocking IGBT) according to the present invention, FIG. 2 is an explanatory view of a scratch B entering the back collector layer of the reverse blocking IGBT, and FIGS. 3 to 9 FIG. 3 is a cross-sectional view for each process showing a method of manufacturing the reverse blocking IGBT of FIG. 1. It should be noted that the present invention is not limited to the description of the examples described below unless it exceeds the gist of the present invention.
The low injection reverse blocking IGBT having a breakdown voltage of 1200 V according to FIG. 1 will be described below. The low-injection reverse blocking IGBT according to the present invention includes a separation diffusion region 2 formed by selective diffusion of boron from the first main surface (surface) 9 side, and a surface layer of the silicon substrate 1 inside the separation diffusion region 2. And a p-type base region 3, an n-type emitter region 4, a gate oxide film 5, a gate electrode 6, and the like. 2 and a low injection collector layer 8 by thermal diffusion of aluminum which is conductively connected, and an aluminum emitter electrode 7 and a collector metal electrode 8-1 formed on both surfaces, respectively.

Next, a specific method for manufacturing the reverse blocking IGBT of FIG. 1 will be described.
FIGS. 3 to 9 are cross-sectional views of the main part of the IGBT showing the reverse blocking IGBT manufacturing method according to the embodiment of the present invention in the order of steps. This reverse blocking IGBT is an example of a reverse blocking IGBT having a withstand voltage of 1200V. A pattern surrounding an area where a 2.4 μm initial oxide film 11 is formed on a first main surface (surface) 9 of a FZ silicon substrate 101 having a thickness of 500 μm and a specific resistance of 80 Ωcm, and a p base region is formed in a later process. Thus, the separation diffusion opening 12 is formed by selective etching (FIG. 3).
Next, a boron source is applied to the surface and heat-treated to perform boron deposition, thereby forming a boron deposition region 13 (FIG. 4).
Next, boron glass etching is performed to remove boron in the oxide film, and then boron is driven and diffused to a depth of 180 μm in an oxygen atmosphere at a temperature of 1300 ° C. to form ap ⁺ isolation diffusion region 2. At this time, an oxide film 11-1 is also formed on the oxide film 11 (FIG. 5).

Next, a MOS gate structure including the p base region 3, the n ⁺ emitter region 4, the gate oxide film 5, the gate electrode 6 and the like is formed by a method similar to the conventional method (FIG. 6). Furthermore, in order to increase the speed, electron beam irradiation or helium irradiation may be performed as a lifetime killer.
Next, the second main surface 10 side is cut, and grinding distortion is removed by etching or the like, so that the thickness of the FZ silicon substrate 101 is about 180 μm (the silicon substrate after grinding is represented by reference numeral 1). The p ⁺ isolation diffusion region 2 is exposed on the back surface 10 (FIG. 7).
Next, in order to form the collector layer 8 on the back surface 10, aluminum with a dose of 1 × 10 ¹³ cm ⁻² is ion-implanted and thermal diffusion is performed at about 1000 ° C. for 6 hours. Aluminum has a diffusion coefficient of 1 × 10 ⁻¹¹ cm ² / sec, which is larger than that of boron, and therefore, a deep collector layer can be formed in a short time. As a result, the collector layer 8-1 has a thickness of 11 μm (FIG. 8). In addition to aluminum, gallium can also be used as an impurity atom having a diffusion coefficient larger than that of boron. The diffusion time of aluminum is 6 hours at 1000 ° C. as described above. However, in order to obtain the same collector layer thickness, 18 minutes may be used at 1300 ° C. Although the temperature can be lowered from 1000 ° C., it is 600 hours at 800 ° C., which is not practical. Since the diffusion coefficient of gallium is 10 times smaller than that of aluminum, it takes about 10 times as much time at the same temperature as in the case of aluminum to obtain an equivalent collector layer.

Since the diffusion coefficient of aluminum is considerably larger than that of boron, the fluctuation of the MOS gate structure on the front surface side received during the formation of the collector layer on the back surface side is not large, but the MOS gate is taken into account for the thermal history for forming the collector layer More preferably, the structure is formed.
In the above description, the first conductivity type is n-type and the second conductivity type is p-type. However, when the conductivity type is reversed and phosphorus is used as the n-type impurity atom of the second conductivity type base region, As the impurity atoms in the collector layer, selenium or sulfur having a diffusion coefficient larger than that of phosphorus can be used as the impurity atoms.
Next, an aluminum metal electrode film is formed on the surface side by sputtering and patterned to form an emitter electrode 7 and a gate electrode pad (not shown). After performing electron beam irradiation for lifetime adjustment, a back metal film is formed by vapor deposition to form a collector electrode 8-1, and dicing at the center of the separation diffusion region 2 of the silicon substrate. An injection reverse blocking IGBT chip is completed (FIG. 9).

This low injection reverse blocking IGBT chip has a thickness of 11 μm for the back collector layer 8 compared to the conventional low injection reverse blocking IGBT having a back collector layer thickness of 1 μm or less. Thus, even if an inevitable scratch or stress is applied in the wafer process or chip assembling process, the pn junction is hardly affected as much as it affects the withstand voltage characteristics. As a result, even when applied to the matrix converter described above, it is possible to prevent a decrease in the yield rate after assembly.
In Example 1 described above, the collector layer 8 has a thickness of 11 μm, but is preferably in the range of 1 μm to 20 μm. When the thickness of the collector layer 8 is less than 1 μm, the probability that the influence of scratches and stress on the back collector layer 8 reaches the pn junction becomes relatively large, and the reverse breakdown voltage defect increases. If it is 1 μm or more, the occurrence rate of breakdown voltage failure is considerably reduced. Further, if the thickness of the collector layer 8 is 20 μm, the influence of the scratches and stress is almost eliminated. However, even if the collector layer 8 has a thickness exceeding 20 μm, the voltage drop due to the collector layer 8 is not negligible, and disadvantages due to an increase in turn-off loss gradually increase.

In the above description, the effect of the depth of the scratch applied to the back collector layer on the reverse breakdown voltage has been described as having an influence on the reverse breakdown voltage when it reaches the pn junction of the collector layer for convenience. Whether or not the depletion layer extending from the pn junction of the collector layer to the drift layer and the collector layer affects the scratch. As shown in FIG. 2, the distance at which the electric field intensity at the tip of the depletion layer extending from the pn junction 14 toward the collector layer 8 at the time of reverse bias and the thickness Y of the collector layer is zero is x (that is, from the depletion layer junction). X), the average impurity concentration of the depletion layer width x in the collector layer is N, and the critical electric field intensity causing avalanche breakdown is 2 × 10 ⁵ V / cm, 2 × 10 ⁵ <xNq / ε (Q: elementary charge amount, ε: dielectric constant of silicon), the total impurity amount xN in the depletion layer width x in the collector layer is xN> 1.3 × 10 ¹² cm ⁻² . That is, if the tip of the scratch B is less than the distance (that is, (Y−x)) that reaches the depletion layer from the back surface, the scratch B does not contact the depletion layer, so that the breakdown voltage is not affected. Incidentally, when the average impurity concentration N of the depletion layer width x is 5 × 10 ¹⁶ cm ⁻³ and 5 × 10 ¹⁷ cm ⁻³ , respectively, the depletion layer x becomes 0.26 μm and 0.026 μm ( That is, when the thickness Y of the collector layer is 10 μm, (Y−x) is 9.74 μm and 9.97 μm from the back surface of the collector layer, respectively. Therefore, the depth of the scratch B is less than 9.74 μm and less than 9.97 μm from the back surface and does not affect the pressure resistance. Compared with the conventional permissible depth of scratches of 1 μm or less, it is possible to greatly reduce the breakdown voltage.

Cross-sectional view of reverse blocking IGBT of the present invention Explanatory drawing of the crack which enters into the back side collector layer of reverse blocking IGBT concerning the present invention Sectional drawing concerning the manufacturing process of reverse blocking IGBT of this invention (the 1) Sectional drawing concerning the manufacturing process of reverse blocking IGBT of this invention (the 2) Sectional drawing concerning the manufacturing process of reverse blocking IGBT of this invention (the 3) Sectional drawing concerning the manufacturing process of reverse blocking IGBT of this invention (the 4) Sectional drawing concerning the manufacturing process of reverse blocking IGBT of this invention (the 5) Sectional drawing concerning the manufacturing process of reverse blocking IGBT of this invention (the 6) Sectional drawing concerning the manufacturing process of reverse blocking IGBT of this invention (the 7) Cross-sectional view of a conventional reverse blocking IGBT

Explanation of symbols

1 n base region (silicon substrate)
2 separation diffusion region 3 p base region 4 n emitter region 5 gate oxide film 6 gate electrode
7 Emitter electrode 8 Collector layer 8-1 Collector electrode
9 First main surface 10 Second main surface.

Claims (4)

A second conductivity type base region selectively formed on a first main surface of the first conductivity type semiconductor substrate; a first conductivity type emitter region selectively formed on a surface layer of the base region; and a remaining portion of the semiconductor substrate. A gate insulating film coated on a first main surface side surface of the base region sandwiched between the first conductivity type drift layer and the emitter region, a gate electrode coated via the gate insulating film, and the second conductive A second base type separation diffusion region that surrounds the drift base layer and is formed from the first main surface to the second main surface of the substrate and the second main surface of the semiconductor substrate; And a second conductivity type low-injection collector layer connected to the isolation diffusion region exposed on the second main surface, and used for forming the second conductivity type base region. Than the impurity atoms Reverse blocking insulated gate semiconductor device, characterized in that it comprises a low injection collector layer formed by thermal diffusion of a large impurity atoms coefficients. 2. The reverse blocking insulated gate type according to claim 1, wherein the impurity atom used for forming the second conductivity type base region is boron, and the impurity atom used for forming the collector layer is aluminum or gallium. Semiconductor device. 2. The reverse-blocking insulated gate type according to claim 1, wherein the impurity atom used for forming the second conductivity type base region is phosphorus, and the impurity atom used for forming the collector layer is selenium or sulfur. Semiconductor device. At least a step of forming a second conductivity type isolation diffusion region by thermal diffusion from the first main surface of the semiconductor substrate, a MOS gate excluding an aluminum electrode on the first main surface of the semiconductor substrate surrounded by the second conductivity type isolation diffusion region A step of forming a structure, a step of grinding the second main surface side to expose the second conductivity type separation diffusion region to the second main surface side, a step of ion-implanting aluminum ions into the second main surface and thermally diffusing A method of manufacturing a reverse blocking insulated gate semiconductor device comprising the steps of: forming an emitter electrode and a gate electrode pad on a first main surface; and depositing a metal electrode on a second main surface in this order.

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