JP2006060079A - Semiconductor layer pattern forming method, electronic device, electronic device array, and display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for patterning a semiconductor layer of an element having an FET structure arbitrarily through simple production process at high speed with good maintainability without damaging an organic semiconductor material, and to provide an electronic element, an electronic element array, and a display. <P>SOLUTION: A source electrode 5 and a drain electrode 6 are formed on a substrate 1 directly or through a gate insulation layer 4 to face each other. Critical surface tension of the gate insulation layer or the substrate in the region other than the source electrode and drain electrode forming regions has surface energy lower than that of the critical surface tension in each electrode forming region, and a patterned semiconductor layer 3 is formed by imparting a solution containing a semiconductor material to between the source electrode and the drain electrode. Electronic elements thus produced are arrayed and employed for constituting a display. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a semiconductor device and related technology, and more particularly to a method for forming a semiconductor layer pattern of an element used for driving a flat panel display, an electronic element obtained thereby, and an electronic element obtained by arraying the same The present invention relates to an array and a display device including an electronic element array.

  When forming a transistor array, if the semiconductor layers of adjacent transistor elements are not electrically separated, mutual interference occurs due to leakage current from adjacent transistors during operation, and accurate operation cannot be performed. Therefore, patterning of the semiconductor layer is indispensable for producing a semiconductor element with good performance. For example, in the case of inorganic semiconductor materials that are currently widely used, a method of forming a fine pattern using photolithography is generally used.

  That is, in photolithography, patterning is generally performed by the following process. First, a material to be patterned (hereinafter referred to as material A) is formed on the entire surface of the substrate. Next, after a photoresist is coated on the formed material A and dried, a pattern to be formed is exposed using a photomask. Next, the resist is developed and rinsed to form a resist pattern. Thereafter, the material A is etched using an etching agent that dissolves the material A. After the etching, the resist is removed. By following the above process, the material A can be patterned into a desired shape. However, there are problems such as complicated manufacturing processes and time.

  On the other hand, devices using organic semiconductor materials have recently attracted attention. That is, when an organic semiconductor material is used, compared with an inorganic semiconductor device, (1) the manufacturing process such as film formation is simple, and (2) it is connected by a loose bond by van der Waals force. The material itself is flexible and can be easily applied to a flexible substrate. Therefore, various applications such as an insulating film, a dielectric film, a conductive film, a semiconductor element, a light emitting element, and a flexible and lightweight display device using them are expected, and research and development have been activated. For example, a field effect transistor (FET) using a material whose carrier mobility is changed by a physical external stimulus such as light or heat has been proposed (see, for example, Patent Document 1).

However, while research and development of materials and structures proceed, a processing method suitable for organic semiconductor materials has not yet been established. In addition, it is difficult to use the patterning method of an inorganic semiconductor material as it is for patterning of an organic semiconductor material for the following reasons.
(A) Organic materials are more susceptible to physical and chemical damage than inorganic materials. For this reason, it is easy to be damaged during etching or resist removal after etching, and it is difficult to suppress deterioration of the material.
(B) The resist agent used for patterning of the inorganic material is an organic material, and depending on the organic material to be patterned, there is a risk of being damaged by the solvent of the resist agent when the resist agent is applied.

As an example of manufacturing an organic EL element, a patterning method of an organic electroluminescence (EL) material has been proposed (for example, refer to Patent Document 2).
Schematic diagram of organic EL material patterning method in this proposal, that is, FIGS. 1 (A) and 1 (B) [(A): corresponds to FIG. 1 of Patent Document 2, and (B): corresponds to FIG. 2 of Patent Document 2]. According to the process shown in FIG. 1, first, the fine structure 20 including the drive circuit is embedded in the transparent substrate 10 to form the protective thin film 12, and then the lyophilic transparent electrode 14 is formed [(A)-(a ]]. Next, the entire surface of the transparent substrate 10 is covered with an insulating film made of a lyophilic material such as a silicon oxide film and then patterned to expose a region where the transparent electrode 14 is not formed, that is, the protective thin film 12 is exposed. The region being covered is covered with an insulating film 50. This is put in a sealed container together with heptadecafluorotetrahydrodecyltriethoxysilane and allowed to stand at room temperature for 96 hours, thereby forming a liquid-repellent film 51 on the entire surface of the transparent substrate 10 [(A)-(b). ]. Next, by selectively irradiating the surface of the transparent substrate 10 with ultraviolet rays through a mask, the liquid repellent film in the pixel forming region 40 of the liquid repellent film 51 is decomposed and removed [(A )-(C)]. Next, the hole injection material 41a is applied to the pixel formation region 40 by an inkjet method and dried to form the hole injection layer 41 [(B)-(a)]. Similarly, the organic EL layer 42 is formed to form the light emitting layer 43 [(B)-(b)]. Finally, the cathode layer 16 is formed to complete the organic EL element [(B)-(c)].

  According to the above method, the organic material can be patterned without causing damage, but it is not practical because it takes a long time to form the liquid repellent film. In addition, the fluorine-containing organic film is decomposed and removed at the time of patterning, but the fluorine-containing organic film generates a harmful decomposition gas due to the decomposition, which is disadvantageous in terms of safety and environment.

Another example of patterning using an organic semiconductor material has been proposed (see, for example, Patent Document 3).
In the patterning method of the organic semiconductor material in this proposal, that is, in the schematic diagrams of FIGS. 2A and 2B [(A): corresponds to FIG. 5 of the reference, and (B): corresponds to FIG. 6 of the reference] According to the process shown, semiconductor patterning is performed as follows.
(1) A CrMo film is formed on the glass substrate 101 by a sputtering method (step 201).
(2) The CrMo film is patterned by a photolithography process to form the gate electrode 102 (process 202).
(3) A gate insulating film 103 of a silicon oxide (SiO ₂ ) film is formed by CVD on the glass substrate 101 on which the gate electrode 102 is formed (step 203).
(4) A gate electrode extraction hole 109 is formed in the SiO ₂ film by a photolithography process (process 204).
(5) A CrMo film is formed thereon by sputtering and patterned by a photolithography process to form the source electrode 104 and the drain electrode 105 (steps 205 and 206).
(6) The Au film formed thereon by vapor deposition is patterned by a photolithography process to form the source electrode 104 and the drain electrode 105. Here, the CrMo film is used to improve the adhesion between the Au film and the SiO ₂ film (steps 207 and 208).
(7) A silicon nitride (SiNx) film 106 having a thickness of 500 nm is formed thereon using a CVD method (step 209).
(8) A part 110 of the SiNx film is removed by a photolithography process (process 210).
(9) Organic semiconductor films 107 and 108 are formed thereon by vacuum vapor deposition (step 211).

  However, according to the above method, it is possible to pattern an organic material without causing damage, but there is a problem that it takes time to form a silicon nitride (SiNx) film by a CVD method and is not practical.

JP-A-7-86600 JP 2002-15866 A JP 2000-269504 A

  The present invention has been made in view of the above-described prior art, and a semiconductor layer of an element having an FET structure can be arbitrarily formed by a simple manufacturing process, high speed, good maintainability, and without damaging an organic semiconductor material. It is an object of the present invention to provide a pattern forming method that can be formed in the pattern shape, an electronic element obtained thereby, an electronic element array in which the pattern is formed, and a display device including the electronic element array.

  As a result of intensive studies, the present inventors have controlled the critical surface tension other than the region to be lower than the critical surface tension in the formation region of the source electrode and the drain electrode formed opposite to each other on the substrate so as to have a low surface energy. When a solution containing a semiconductor material was applied between the electrodes to form a semiconductor layer, it was found that the desired pattern was obtained and the above-mentioned problems were solved, leading to the present invention. Hereinafter, the present invention will be specifically described.

That is, according to the present invention, a source electrode and a drain electrode are formed on a substrate directly or via a gate insulating layer at an appropriate interval, and a solution containing a semiconductor material is applied between the source electrode and the drain electrode to form a pattern. A method for forming a pattern of a semiconductor layer having an FET structure, comprising a step of forming an integrated semiconductor layer,
Each of the critical surface tensions of the gate insulating layer or substrate other than the source electrode and drain electrode formation regions has a low surface energy that is smaller than the respective critical surface tensions in the source electrode and drain electrode formation regions. This is a layer pattern forming method.

  In the present invention, a low-surface energy gate insulating layer having a low critical surface tension is provided on a substrate, and a high-surface energy source electrode and a drain electrode having a high critical surface tension are appropriately formed on a predetermined gate insulating layer. A method for forming a pattern of a semiconductor layer having an FET structure, comprising a step of forming a patterned semiconductor layer by applying a solution containing a semiconductor material between the source electrode and the drain electrode so as to face each other at intervals.

  Here, in any one of the pattern forming methods described above, the source electrode and drain electrode having a critical surface tension of 10 mN / m or more larger than the critical surface tension of the gate insulating layer or substrate other than the source electrode and drain electrode formation regions. It is preferable to include a step of forming.

  Further, in any one of the above pattern forming methods, each of the low surface energy gate insulating layers or the substrates sandwiched between the source electrode and the drain electrode is made smaller than the width of each of the source electrode and the drain electrode. It is preferable to include the process of forming an electrode.

  Further, in any one of the above pattern forming methods, the critical surface tension of the gate insulating layer or the substrate sandwiched between the source electrode and the drain electrode is less than the critical surface tension of the gate insulating layer or the substrate not sandwiched between the electrodes. It is desirable to include a step of making the layer to be larger than the value.

  In any one of the above pattern forming methods, the gate insulating layer is preferably made of a material whose critical surface tension changes with the addition of energy.

In any one of the above pattern forming methods, the gate insulating layer is composed of at least a first material and a second material, and the first material is critical by adding energy as compared with the second material. The material whose surface tension changes greatly, and the second material is a material having a function of complementing the performance different from that of the first material,
In addition, it is desirable that the first material and the second material have a concentration distribution in the thickness direction of the gate insulating layer, and the concentration of the first material in the outermost layer portion is higher than the concentration of the second material.

  In the pattern forming method, it is preferable that the second material is a material having higher electrical insulation than the first material.

  In the pattern forming method, the second material is preferably a material having a high relative dielectric constant as compared with the first material.

  In any one of the above pattern forming methods, it is preferable that the energy addition is performed by ultraviolet irradiation to change a critical surface tension of the gate insulating layer to form a low surface energy region.

  Furthermore, in any one of the pattern forming methods, the gate insulating layer is preferably made of a polymer material having a hydrophobic group in a side chain.

  In the pattern forming method, the polymer material having a hydrophobic group in the side chain is preferably made of a material having a polyimide structure.

  In any one of the pattern forming methods, the semiconductor layer is preferably made of an organic semiconductor.

  Furthermore, in any one of the pattern forming methods, it is preferable that a method of applying a solution containing a semiconductor material between the source electrode and the drain electrode is an ink jet method.

  The present invention also relates to an electronic device characterized in that a semiconductor layer is patterned by any one of the semiconductor layer pattern forming methods.

Furthermore, the present invention relates to an electronic element array, wherein a plurality of the electronic elements are formed on an insulating substrate.
Here, it is preferable that the insulating substrate also serves as a gate insulating layer having a low surface energy region having a small critical surface tension.

  The present invention also relates to a display device comprising any one of the electronic element arrays described above.

  According to the present invention, a semiconductor layer of an element having an FET structure can be easily and reliably formed in an arbitrary pattern shape without damaging an organic semiconductor material, with a simple manufacturing process, high speed and good maintainability. A pattern forming method that can be used can be provided. An electronic device having good performance such as electrical characteristics and dielectric characteristics can be easily obtained by this manufacturing method. If this electronic element is used, an electronic element array can be provided simply and easily at a low cost, and further, an inexpensive display device can be easily provided by using this electronic element array.

As described above, the present invention relates to a method for forming a pattern of a semiconductor layer in an element having a field effect transistor (FET) structure, and a semiconductor between a source electrode and a drain electrode formed to face each other at an appropriate interval on a substrate. A step of applying a solution containing the material to form a patterned semiconductor layer. At that time, the source electrode and the drain electrode are formed through the gate insulating layer or directly formed on the substrate, and each critical surface of the gate insulating layer or the substrate other than the source electrode and drain electrode forming regions is formed. The tension is controlled to have a low surface energy smaller than each critical surface tension in the region where the source electrode and the drain electrode are formed.
In the present invention, the magnitude of the critical surface tension, that is, the level of the surface energy is relative, and the difference is preferably 10 mN / m or more as described later.

The present invention also relates to a specific form of the semiconductor layer pattern forming method, wherein a low surface energy gate insulating layer having at least a small critical surface tension is provided on a substrate, and the critical surface tension is provided on the predetermined gate insulating layer. A high surface energy source electrode and a drain electrode facing each other at an appropriate interval, and a solution containing a semiconductor material is applied between the electrodes to form a patterned semiconductor layer. To do.
Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

FIG. 3 is a schematic cross-sectional view showing a configuration example of a transistor element suitable for carrying out the present invention. In FIG. 3, a gate electrode 2 is provided on a substrate 1, and a gate insulating layer 4 is formed thereon. A source electrode 5 and a drain electrode 6 are formed on the gate insulating layer 4 so as to face each other with a space therebetween.
In this configuration, the surfaces of the source electrode 5 and the drain electrode 6 are respectively high surface energy portions Sa and Da having a large critical surface tension, while the surface of the gate insulating layer 4 between the electrodes and the electrodes are formed. The surface of the gate insulating layer 4 other than the region that is formed is controlled so as to be low surface energy portions 4a and 4b having small critical surface tensions.

  When a solution containing a semiconductor material is applied between the source electrode 5 and the drain electrode 6 configured as described above, the source electrode 5 and the drain electrode 6 serve as banks, so-called dikes, and the low surface energy portion 4b of the gate insulating layer 4 In this case, the semiconductor layer is not formed, and an element having the patterned semiconductor layer 3 as shown in FIG. 3 can be obtained.

Further, another structural example of a transistor element suitable for carrying out the present invention is shown in a schematic sectional view of FIG.
In FIG. 4, a source electrode 5 and a drain electrode 6 are formed on a substrate 1 so as to face each other with a gap therebetween. The surfaces of the source electrode 5 and the drain electrode 6 are high surface energy portions Sa and Da having a large critical surface tension, respectively, while the surface of the substrate 1 between the electrodes and the substrate other than the region where the electrodes are formed. The surface of 1 is formed so as to be a low surface energy portion 1a, 1b having a small critical surface tension.

  When a solution containing a semiconductor material is applied between the source electrode 5 and the drain electrode 6 configured as described above, the source electrode 5 and the drain electrode 6 serve as banks, so-called dikes, and a semiconductor is formed on the low surface energy portion 1b of the substrate 1. No layer is formed, and a patterned semiconductor layer 3 as shown in FIG. 4 is formed. After the semiconductor layer 3 is formed, an element can be obtained by forming the gate insulating layer 4 and the gate electrode 2.

  Note that the shape of the semiconductor layer 3 does not have to be a cross-sectional shape as shown in FIG. 3 or FIG. 4, and the semiconductor layer is formed at a site where each pattern of the semiconductor layer 3 is separated and independent and a channel is formed. Any shape may be used. Another example of the shape of the semiconductor layer is shown in FIGS.

  According to the above invention, the semiconductor layer of the element having the FET structure can be easily formed in an arbitrary pattern shape without damaging the organic semiconductor material. Such a manufacturing method has a simple process, can be manufactured at high speed, and has good maintainability.

Further, the present invention provides a source having a critical surface tension of 10 mN / m or more larger than the critical surface tension of the gate insulating layer 4 or the substrate 1 other than the region where the source electrode 5 and the drain electrode 6 shown in FIG. The method includes a step of forming the electrode 5 and the drain electrode 6.
In order to reliably attach the liquid containing the semiconductor material only to the channel part, as described above, the high surface energy part of the source electrode 5 and the drain electrode 6 and the low surface energy part of the gate insulating layer 4 or the substrate 1 are used. Although a so-called critical surface tension difference is required to be large, by setting this difference to 10 mN / m or more, a solution containing a semiconductor material is surely adhered to a predetermined place to form a pattern of the semiconductor layer. be able to.

Furthermore, in the present invention, taking the configuration shown in the schematic cross-sectional view of FIG. 6 as an example, the distance Cw between the low-surface energy gate insulating layers 4 sandwiched between the source electrode 5 and the drain electrode 6 is the width of the source electrode Sw The method includes the step of forming each electrode so as to be smaller than the width Dw of the electrode.
Although FIG. 6 shows the case where the source electrode 5 and the drain electrode 6 are provided on the gate insulating layer 4, the source electrode 5 and the drain electrode 6 are formed directly on the substrate 1 as shown in FIG. The same applies to the case.

  When configured as described above, the distance Cw of the gate insulating layer 4, that is, the channel length is smaller than the width Sw of the source electrode and the width Dw of the drain electrode, and the low surface energy of the gate insulating layer 4 and the source electrode 5 and Since blocking works effectively based on the difference from the high surface energy of the drain electrode 6, the semiconductor layer is well patterned.

In the present invention, taking the configuration shown in the schematic cross-sectional view of FIG. 7 as an example, the critical surface tension of the low surface energy portion 7a of the gate insulating layer 4 sandwiched between the source electrode 5 and the drain electrode 6 is The method includes a step of manufacturing the gate insulating layer 4 not sandwiched between the drain electrodes 6 so as to be larger than the critical surface tension value in the low surface energy portion 7b.
By adopting such a configuration, the difference between the surface energy of the gate insulating layer 4 sandwiched between the electrodes and the surface energy of the source electrode 5 and the drain electrode 6 is reduced, and becomes a value close to the critical surface tension of each electrode. A semiconductor layer with good adhesion can be formed. Therefore, a continuous semiconductor layer is formed at each pattern formation location, and as a result, an electronic device with good performance is provided.

8A and 8B show the critical surface tension of the low surface energy portion 7a of the gate insulating layer 4 and the critical surfaces of the high surface energy portions Sa and Da of the source electrode 5 and the drain electrode 6 in FIG. It is a bird's-eye view which shows the external appearance at the time of changing the difference with tension | tensile_strength and forming a semiconductor layer.
FIG. 8A shows an overview of an element in which a semiconductor layer is formed by applying a liquid containing a semiconductor material between the electrodes when the difference between the low surface energy portion 7a and the high surface energy portions Sa and Da is large. FIG. It can be seen that the semiconductor layer is not attached and patterning is not possible.

  On the other hand, in FIG. 8B, in the case where the difference between the low surface energy portion 7a and the high surface energy portions Sa and Da is smaller, a semiconductor layer is formed by applying a liquid containing a semiconductor material between the electrodes. It is an overhead view of an element. It can be seen that the semiconductor layer is well patterned.

In the invention, it is preferable that the gate insulating layer is made of a material whose critical surface tension is changed by application of energy.
By using a material whose critical surface tension changes, it is possible to easily form the low surface energy portion as described above on the surface of the gate insulating layer by adding energy, and the pattern of the semiconductor layer can be surely formed.
Examples of such a gate insulating layer material that can be used in the present invention include, but are not limited to, paraxylylene, pullulan and derivatives thereof, and polyvinylphenol.

  In the present invention, the gate insulating layer comprises at least a first material and a second material. The first material is a material whose critical surface tension is greatly changed by the addition of energy as compared with the second material, and the second material has a function of complementing the performance different from that of the first material. The first material and the second material have a concentration distribution in the gate insulating layer thickness direction, and the concentration of the first material in the outermost layer portion is higher than the concentration of the second material. It is what.

More desirably, the first material concentration in the outermost layer is preferably close to 100%. In this way, it is possible to reliably control the critical surface tension, that is, to exhibit the wettability changing function.
With the above-described configuration, it is possible to reliably manufacture a low surface energy portion, and a semiconductor layer pattern can be easily formed.

The structural example of said 1st material and 2nd material is shown to the cross-sectional schematic diagram of Fig.9 (a), (b).
The structure shown in FIG. 9A can be manufactured by sequentially stacking layers made of the second material after forming layers made of the first material. As a manufacturing method of each layer, a vacuum process such as vacuum deposition can be used, or a coating process using a solution can be used.

On the other hand, FIG. 9B shows a configuration in which the first and second materials are mixed and have a concentration gradient without deviation in the thickness direction. As a process for obtaining such a structure, there is a method in which a solution in which a first material and a second material are mixed is applied to a substrate and dried.
This method is applied when the polarity of the first material is smaller than that of the second material, or when the molecular weight of the first material is small. That is, it is a case where the first material moves to the surface side before the solvent evaporates at the time of drying, and a layer can be formed with a high concentration distribution on the surface side.

When the coating process is used, as shown in FIG. 9B, the layer made of the first material and the layer made of the second material often cannot be clearly separated by the interface. The present invention can be applied if the first material concentration in the outermost layer is higher than the second material concentration.
Moreover, as shown in the schematic cross-sectional views of FIGS. 10C to 10E, the first and second materials may be mixed and unevenly distributed with a predetermined concentration distribution in the film thickness direction. In addition, when the gate insulating layer (wetting change material layer) configured to change the critical surface tension is composed of three or more kinds of materials, the gate insulating layer may be composed of three or more layers, Materials may be mixed with a predetermined concentration distribution in the film thickness direction without having a structure.

In addition, the present invention is characterized in that the second material is a material having higher electrical insulation than the first material.
With such a material structure, it is possible to provide a gate insulating layer that has high electrical insulation and can reliably manufacture a low surface energy portion, and a fine conductive layer pattern can be easily formed.

In the above, the composition ratio (second material / first material) of the first material in which the critical surface tension greatly changes due to the addition of energy and the second material excellent in electrical insulation is 50 / weight ratio. 50-99 / 1.
As the weight ratio of the first material in the composition ratio increases, the electrical insulation of the gate insulating layer (wetting change material layer) decreases, and if it exceeds 50, it becomes unsuitable as an insulating layer of an electronic device. On the other hand, when the weight ratio of the first material is reduced and the weight ratio is less than 1, the change in wettability becomes small, so that the patterning of the conductive layer is not good. Therefore, the mixing ratio of both is desirably 60/40 to 95/5, and more desirably 70/30 to 90/10. Further, the volume resistivity of the gate insulating layer (wetting change material layer) in the present invention is preferably about 1 × 10 ¹² Ω · cm or more.

Furthermore, the present invention is characterized in that the second material is a material having a higher relative dielectric constant than the first material.
With such a material structure, a gate insulating layer capable of reliably producing a low surface energy portion can be provided, and a semiconductor layer can be easily patterned, and the relative dielectric constant of the entire insulating layer can be provided. Therefore, an element that can be driven at a low voltage can be provided. The high dielectric constant in the present invention refers to a relative dielectric constant of 4.0 or more of silicon oxide used in inorganic semiconductors.

In the present invention, the gate insulating layer is made of a polymer material having a hydrophobic group in a side chain.
By using such a polymer material having a hydrophobic group in the side chain, the difference between the water-repellent part and the hydrophilic part formed by applying energy increases, so the gate insulating layer (wetting change material layer) In addition, it is possible to manufacture a laminated structure on which fine electrode patterning is performed, and it is possible to form a pattern of a delicate semiconductor layer. FIG. 11 is a conceptual diagram for explaining a polymer material having a hydrophobic group in a side chain.

  In FIG. 11, L represents a main chain of a polymer material having a skeleton such as polyimide or (meth) acrylate, and R1 to R4 are hydrophobic bonded to the main chain L directly or through a bonding group (not shown). The side chain which has a sex group is shown. R1 to R4 may be the same or different from each other.

Examples of the hydrophobic group include groups having a terminal structure of —CF ₂ CH ₃ , —CF ₂ CF ₃ , —CF (CF ₃ ) ₂ , —C (CF ₃ ) ₃ , —CF ₂ H, —CFH _2, etc. Can be mentioned.
Here, in order to facilitate the orientation of molecular chains, a group having a long carbon chain length is preferable, and a group having 4 or more carbon atoms is more preferable. Furthermore, a polyfluoroalkyl group in which two or more of the hydrogen atoms of the alkyl group are substituted with fluorine atoms (hereinafter referred to as “Rf group”) is preferable, and an Rf group having 4 to 20 carbon atoms is particularly preferable. The Rf group having 6 to 12 carbon atoms is preferred. The Rf group may have a linear structure or a branched structure, but a linear structure is preferred. Further, the hydrophobic group is preferably a perfluoroalkyl group in which substantially all of the hydrogen atoms of the alkyl group are substituted with fluorine atoms. The perfluoroalkyl group is preferably a group represented by C _n F _{2n + 1} — (where n is an integer of 4 to 16), particularly preferably when n is an integer of 6 to 12. The perfluoroalkyl group may have a linear structure or a branched structure, but a linear structure is preferred.

  The above materials are well known in detail in JP-A-3-178478 and the like, and become lyophilic when brought into contact with a liquid or solid in a heated state and become lyophobic when heated in air. Have. That is, the critical surface tension can be changed by the addition of thermal energy. The critical surface tension varies depending on the selection of the contact medium.

Furthermore, examples of the hydrophobic group include groups having a terminal structure such as —CH ₂ CH ₃ , —CH (CH ₃ ) ₂ , and —C (CH ₃ ) ₃ that do not contain a fluorine atom.
Also in this case, in order to facilitate the orientation of molecular chains, a group having a long carbon chain length is preferable, and a group having 4 or more carbon atoms is more preferable. The hydrophobic group may have a linear structure or a branched structure, but a linear structure is preferred. The alkyl group contains a phenyl group substituted with a halogen atom, a cyano group, a phenyl group, a hydroxyl group, a carboxyl group, or a linear, branched or cyclic alkyl group having 1 to 12 carbon atoms or an alkoxy group. Also good. It is considered that the more R bonding sites, the lower the surface energy (the smaller the critical surface tension) and the more lyophobic. In addition, it is speculated that a part of the bond is broken by energy addition such as ultraviolet irradiation, or the critical state tension increases due to the change of the orientation state and becomes lyophilic.

Further, the side chain having a hydrophobic group via a bonding group (not shown) in the main chain L of FIG. 11 having a skeleton such as polyimide or (meth) acrylate is described in the following documents A and B. It is also possible to use a block copolymer made of various types of polyimide or polymethyl methacrylate for the side chain.
Reference A: “Preparation of porous polyimides from self assembled graft copolymers” EYLebedeva, BSKesler, KRCarter, Polymer Preprint, vol.40 (1), pp494-495 (1999).
Reference B: “Nanoporous low-k polyimide films prepared from poly (amic acid) s with grafted poly (methylmethacrylate) / poly (acrylamide) side chains” GDFu, WCWang, S.Li, ETKang, KGNeoh, WTTseng, DJLiaw, Journal of Materials Chemistry, vol.13, pp2150-2156 (2003).

Furthermore, the present invention is characterized in that the polymer material having a hydrophobic group in the side chain is made of a material having a polyimide structure.
A polymer material composed of a polyimide structure is excellent in electrical insulation, chemical resistance, and heat resistance. Therefore, when an electrode layer or the like is formed on the gate insulation layer, it may swell due to temperature change due to solvent or baking. There is no such thing as a crack. Therefore, it is possible to provide a gate insulating layer capable of producing a low surface energy portion excellent in various performances, and to surely form a pattern of the semiconductor layer. Further, when the insulating layer is composed of two or more kinds of materials, considering heat resistance, solvent resistance, and affinity, materials other than the polymer material having a hydrophobic group in the side chain may be made of polyimide. desirable.

  Although it does not limit as a hydrophobic group of the high molecular material which has a polyimide structure which has a hydrophobic group in the side chain used by this invention, For example, following structural formula (1)-as an amine compound which comprises a polyimide. Any of the diamine compounds represented by (6) can be included.

In the structural formula (1), X is —CH ₂ — or —CH ₂ CH ₂ —, and A ¹ is substituted with 1,4-cyclohexylene, 1,4-phenylene or 1 to 4 fluorines. 1,4-phenylene, wherein A ² , A ³ and A ⁴ are each independently a single bond, 1,4-cyclohexylene, 1,4-phenylene or 1,4 substituted with 1 to 4 fluorines -Phenylene, B ¹ , B ² and B ³ are each independently a single bond or —CH ₂ CH ₂ —, B ⁴ is alkylene having 1 to 10 carbon atoms, R ³ , R ⁴ , R ⁵ , R ⁶ , and R ⁷ are each independently alkyl having 1 to 10 carbon atoms, and p is an integer of 1 or more.

  In the above structural formula (2), T, U and V are each independently a benzene ring or a cyclohexane ring, and any H on these rings is alkyl having 1 to 3 carbon atoms and fluorine substitution having 1 to 3 carbon atoms. Optionally substituted with alkyl, F, Cl or CN, m and n are each independently an integer from 0 to 2, h is an integer from 0 to 5, and R is H, F, Cl, CN Or it is a monovalent organic group, and two V when m is 2 or two V when n is 2 may be the same or different.

In the structural formula (3), the linking group Z is CH ₂ , CFH, CF ₂ , CH ₂ CH ₂ or CF ₂ O, and the ring Y is 1,4-cyclohexylene or 1 to 4 H atoms. 1,4-phenylene which may be replaced by F or CH3, A1 to A3 are each independently a single bond, 1,4-cyclohexylene or 1 to 4 Hs are replaced by F or CH3 1,4-phenylene, and B1 to B3 are each independently a single bond, alkylene having 1 to 4 carbon atoms, oxygen atom, oxyalkylene having 1 to 3 carbon atoms or alkyleneoxy having 1 to 3 carbon atoms. There, R represents H, any of the CH ₂ is CF ₂ at replaced with 1 to 10 carbon atoms which may alkyl or one CH ₂ may or alkoxy having 1 to 9 carbon atoms which may be replaced by CF _2, Is alkoxyalkyl The bonding position of the amino group to the benzene ring is an arbitrary position. However, when Z is CH ₂ , all of B1 to B3 are not simultaneously alkylene having 1 to 4 carbon atoms, Z is CH ₂ CH ₂ , and ring Y is 1,4-phenylene. , A ¹ and A ² are not both single bonds, and when Z is CF ₂ O, ring Y is not 1,4-cyclohexylene.

In the structural formula (4), R ² is a hydrogen atom or an alkyl group having 1 to 12 carbon atoms, Z ₁ is a CH ₂ group, m is 0 to 2, and ring A is a benzene ring or a cyclohexane ring. Wherein l is 0 or 1, each Y ₁ is independently an oxygen atom or a CH ₂ group, and each n ₁ is independently 0 or 1.

In the structural formula (5), each Y ₂ is independently an oxygen atom or a CH ₂ group, R ³ and R ⁴ are independently a hydrogen atom, an alkyl group having 1 to 12 carbon atoms or a perfluoroalkyl group, At least one is an alkyl group having 3 or more carbon atoms or a perfluoroalkyl group, and each n ₂ is independently 0 or 1.

  The diamine compound is not limited, but is described in detail, for example, in JP-A Nos. 2002-162630, 2003-96034, and 2003-267882.

In the structural formula (6), n represents an integer of 3 to 21. In view of solubility in a solvent, 5 to 15 is preferable.
This compound is described in detail, for example, in JP-A-5-43687.

  On the other hand, various materials such as aliphatic, alicyclic and aromatic materials can be used for the tetracarboxylic dianhydride used for constituting the main chain skeleton of polyimide together with these diamine compounds. .

  Specific examples include, but are not limited to, pyromellitic dianhydride, cyclobutane tetracarboxylic dianhydride, butane tetracarboxylic dianhydride, and the like. In addition, materials described in detail in JP-A-11-193345, JP-A-11-193346, JP-A-11-193347, and the like can also be used.

  Polyimides containing hydrophobic groups synthesized using the diamines of the structural formulas (1) to (6) and various acid dianhydrides may be used alone or in combination with other materials. However, when mixed and used, it is desirable that the material to be mixed has a polyimide structure in consideration of heat resistance, solvent resistance and affinity.

  Note that the thickness of the gate insulating layer in this embodiment is preferably 30 nm to 3 μm, and more preferably 50 nm to 1 μm. If it is thinner than 30 nm, the properties as a bulk body (insulating properties, gas barrier properties, moisture resistance, etc.) are impaired, and if it is thicker than 3 μm, the surface shape is deteriorated.

Further, the present invention is characterized in that the energy addition is performed by ultraviolet irradiation, and the critical surface tension of the gate insulating layer is changed to form a low surface energy region.
In this way, a fine pattern can be easily formed. The ultraviolet rays preferably include light having a relatively short wavelength of 100 nm to 300 nm.

In the present invention, the semiconductor layer is made of an organic semiconductor.
By using an organic semiconductor, the interface characteristics between the gate insulating layer and the semiconductor layer can be made extremely good, and the patterning of the semiconductor layer can be easily performed by a simple process such as a printing method. Become.

  Examples of the organic semiconductor material include, but are not limited to, organic low molecules such as pentacene, anthracene, tetracene, and phthalocyanine, polyacetylene conductive polymers, polyparaphenylene and derivatives thereof, polyphenylene vinylene and derivatives thereof, and the like. Use organic semiconductors such as polyphenylene-based conductive polymers, polypyrrole and derivatives thereof, polythiophene and derivatives thereof, heterocyclic conductive polymers such as polyfuran and derivatives thereof, and various ionic conductive polymers such as polyaniline and derivatives thereof be able to.

The present invention is characterized in that the method for applying a solution containing a semiconductor material between the source electrode and the drain electrode is an ink jet method.
That is, by using an ink jet method capable of supplying smaller droplets, it can be easily affected by surface energy, and a fine pattern of a semiconductor layer can be easily formed. In addition, since a method of supplying a necessary amount of small droplets is applied, it is possible to form a pattern of a semiconductor layer without using a semiconductor material wastefully.

Furthermore, the present invention provides an electronic device in which a semiconductor layer is patterned by any one of the semiconductor layer pattern forming methods described above.
According to the pattern forming method described above, since the manufacturing process is simple and high-definition patterning can be performed, it is possible to provide an electronic device having good characteristics.

The present invention also provides an electronic element array in which a plurality of the electronic elements are formed on an insulating substrate.
FIG. 12 is a schematic cross-sectional view showing a configuration example of an electronic element array (TFT array) in which a plurality of electronic elements in the present invention are installed on an insulating substrate via a gate insulating film.
As shown in FIG. 12, an electronic element array 19 includes an electronic element in which a gate electrode 12, a gate insulating film 14, a source electrode 15 and a drain electrode 16, a semiconductor layer 13, and an interlayer insulating film 17 are sequentially provided on a substrate 11. A plurality of 18 are two-dimensionally formed.
The electronic element array having such a structure can be manufactured easily and easily at low cost, and the semiconductor layer 13 including the channel region is formed in an island shape, so that current leakage to adjacent elements does not occur. Good device characteristics can be exhibited.

Furthermore, the invention is characterized in that the insulating substrate of the electronic element array also serves as a gate insulating layer having a low surface energy region having a small critical surface tension.
FIG. 13 is a schematic cross-sectional view showing a configuration example of a (TFT array) of an electronic element array in which a plurality of electronic elements according to the present invention are directly installed on an insulating substrate.
As shown in FIG. 13, the electronic element array 19 includes two electronic elements 18 each having a source electrode 15 and a drain electrode 16, a semiconductor layer 13, a gate insulating film 14, and a gate electrode 12 provided in this order on a substrate 11. A plurality of dimensions are formed.

  Similar to the case where a plurality of electronic elements are provided on an insulating substrate through the gate insulating film, the semiconductor layer 13 including the channel region is formed in an island shape, which can be easily and easily manufactured at low cost. Therefore, current leakage to adjacent elements does not occur and good element characteristics can be obtained.

And this invention provides the display apparatus provided with the said electronic element array.
If the electronic element array is used, a display device can be provided easily and inexpensively.
FIG. 14 is a schematic cross-sectional view illustrating a configuration example of a display device according to the present invention.
In FIG. 14, a display element 22 is provided between an electronic element (TFT) array substrate 11 configured as shown in FIG. 12 and a second substrate 24 having a transparent conductive film 23, and also serves as a pixel electrode by the TFT. The display element on the drain electrode 16 is switched.
As the second substrate 24, plastic such as glass, polyester, polycarbonate, polyarylate, or polyethersulfone can be used. As the display element 22, a method such as liquid crystal, electrophoresis, organic EL, or the like can be used.

  Since the liquid crystal display element is driven by an electric field, the power consumption is low, and the driving voltage is low, so that the driving frequency of the TFT can be increased, which is suitable for large-capacity display. Examples of the display method of the liquid crystal display element include TN, STN, guest-host type, and polymer-dispersed liquid crystal (PDLC). PDLC is preferable in that a bright white display can be obtained in a reflective type. .

  The electrophoretic display element is composed of a dispersion liquid in which particles exhibiting a first color (for example, white) are dispersed in a coloring dispersion medium exhibiting a second color. The particles exhibiting the first color are contained in the coloring dispersion medium. By being charged, the position in the dispersion medium can be changed by the action of an electric field, and the color to be exhibited thereby changes. According to this display method, it is possible to display brightly and with a wide viewing angle, and since it has a display memory property, it is preferably used particularly from the viewpoint of power consumption.

By using microcapsules in which the dispersion is wrapped with a polymer film, the display operation is stabilized and the display device can be easily manufactured.
Microcapsules can be produced by a known method such as a coacervation method, an In-Situ polymerization method, or an interfacial polymerization method. Titanium oxide is particularly preferably used as the white particles, and surface treatment or compounding with other materials is performed as necessary.

  Dispersion media include aromatic hydrocarbons such as benzene, toluene, xylene, naphthenic hydrocarbons, aliphatic hydrocarbons such as hexane, cyclohexane, kerosene, paraffinic hydrocarbons, trichloroethylene, tetrachloroethylene, trichlorofluoroethylene, odor It is preferable to use an organic solvent having high resistivity such as halogenated hydrocarbons such as ethyl halide, fluorine-containing ether compounds, fluorine-containing ester compounds, and silicone oil. In order to color the dispersion medium, oil-soluble dyes such as anthraquinones and azo compounds having desired absorption characteristics are used. A surfactant or the like may be added to the dispersion for stabilization of dispersion.

  Since the organic EL element is a self-luminous type, vivid full color display can be performed. Further, since the EL layer is a very thin organic thin film, it has a high flexibility and is particularly suitable for being formed on a flexible substrate.

  Hereinafter, the present invention will be described more specifically with reference to examples. However, the present invention is not limited to the following examples without departing from the gist thereof.

Example 1
A TFT element having the same configuration as that shown in FIG. 3 was prepared according to the following procedure.
(1): A 60 nm-thick Al film was vacuum-deposited on a glass substrate and processed to a width of 40 μm by photolithography to form a gate electrode.
(2): A gate insulating layer of polyparaxylylene was formed by chemical vapor deposition (CVD).
(3): Au was evaporated through a metal mask to form a source electrode layer and a drain electrode layer having an electrode width of 40 μm and an electrode interval of 5 μm.
(4): An inkjet apparatus was prepared as a pattern forming apparatus, and this inkjet apparatus was filled with a xylene mixed solution of poly-3-hexylthiophene.
(5): The substrate on which each of the electrodes was formed was set in a pattern forming apparatus.
(6): A signal is transmitted from the personal computer to the pattern forming apparatus, and a xylene mixed solution of poly (3-hexylthiophene) is discharged to a position where the space between the source electrode and the drain electrode (channel portion) is covered, and the area is about 64 μm square. The semiconductor pattern was formed.
(7): Finally, a semiconductor layer was formed by heating in an oven at 180 ° C. for 60 minutes to produce a TFT element.
The critical surface tension of the gate insulating layer other than the source electrode and drain electrode formation regions formed in the above process is controlled to a low surface energy smaller than the critical surface tension of each electrode as shown in FIG. Has been.

An overhead view of the TFT element obtained by the above procedure is shown in FIG. As shown in FIG. 15, a semiconductor layer having a predetermined pattern shape is formed without damaging the organic semiconductor material.
The mobility of this TFT was 9.8 × 10 ⁻³ cm ² / Vs, and the On / Off ratio was 650, which was inferior to that in the case where the semiconductor layer was formed by spin coating.

(Example 2)
An array having the same TFT element structure as that shown in FIG. 12 was prepared by the following procedure.
(1): A 60 nm-thick Al film was vacuum-deposited on a glass substrate and processed to a width of 40 μm by photolithography to form a gate electrode.
(2): After heat treatment, a mixed solution in which a polyimide precursor that becomes a polyimide structure represented by the following structural formula (7) and structural formula (8) is dissolved is applied by a spin coat method, and the heat treatment is performed at 250 ° C. Thus, a gate insulating layer was produced.
(3): A mask provided with a pattern having an opening width of 40 μm and a space between openings of 5 μm was pressure-bonded to the gate insulating layer, and irradiated with ultraviolet rays at 9 J / cm ² .

(4): An aqueous solution of PEDOT / PSS (polyethylenedioxythiophene / polyethylenesulfonic acid), which is a conductive polymer, was applied to the high surface energy part formed by ultraviolet irradiation of the gate insulating layer using an inkjet apparatus.
(5): The applied conductive polymer solution was baked at 200 ° C. to form a source and drain electrode layer.
(6): The substrate on which each of the electrodes was formed was set in a pattern forming apparatus.
(7): A signal is transmitted from the personal computer to the pattern forming apparatus, and a xylene mixed solution of poly (3-hexylthiophene) is discharged to a position where the space between the source electrode and the drain electrode (channel portion) is covered, and a semiconductor pattern of 64 μm square Formed.
(8): Finally, a semiconductor layer was formed by heating in an oven at 180 ° C. for 60 minutes to produce an array having a TFT element structure.
The critical surface tensions of the gate insulating layer other than the source electrode and drain electrode formation regions formed in the above process are low surface energy smaller than the critical surface tension of each electrode as shown in FIG. It is controlled.

Through the above steps, an electronic element array having 32 × 32 (inter-element pitch 500 μm) TFT elements on the substrate was produced. The average characteristics of the TFT were a mobility of 3.5 × 10 ⁻³ cm ² / Vs and an On / Off ratio of 2500.

It is a schematic diagram [(A): Corresponds to literature FIG. 1, (B): Corresponds to literature FIG. 2] for demonstrating the EL material patterning process in a prior art (patent document 2). It is the schematic diagram [(A): Corresponds to literature FIG. 5 and (B): corresponds to literature FIG. 6] for demonstrating the patterning process of the organic-semiconductor material in a prior art (patent document 3). It is a schematic sectional drawing which shows the structural example of the transistor element for describing embodiment in this invention. It is a schematic sectional drawing which shows another structural example of the transistor element for describing embodiment in this invention. It is a schematic sectional drawing which shows the other shape example of the semiconductor layer for describing embodiment in this invention. It is a schematic sectional drawing for demonstrating the relationship between the space | interval of the source electrode of a transistor element of this invention, and a drain electrode, and the width | variety of each electrode in embodiment. It is a schematic sectional drawing for demonstrating the relationship between the low surface energy part and high surface energy part of the transistor element of this invention in embodiment. FIG. 3 is an overhead view showing an appearance of a semiconductor layer formed by changing a difference in critical surface tension between a low surface energy part of a gate insulating layer and a high surface energy part of each electrode in an embodiment. It is a cross-sectional schematic diagram for demonstrating the example by which the gate insulating layer of this invention is comprised from a 1st and 2nd material (a: laminated structure, b: mixed structure) in embodiment. In embodiment, it is a cross-sectional schematic diagram for demonstrating the other example by which the gate insulating layer of this invention is comprised from the 1st and 2nd material (c: e: the structure mixed and unevenly distributed). The conceptual diagram for demonstrating the polymeric material which has a hydrophobic group in the side chain used as a gate insulating layer of this invention in embodiment is shown. It is a schematic sectional drawing which shows the structural example of the electronic element array (TFT array) by which multiple electronic elements in this invention are installed on an insulating substrate through a gate insulating film. It is a schematic sectional drawing which shows the structural example of (TFT array) of the electronic element array by which multiple electronic elements in this invention are directly installed on an insulating board | substrate. It is a schematic sectional drawing which shows the structural example of the display apparatus in this invention. 2 is an overhead view of a TFT element manufactured in Example 1. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Substrate 2 Gate electrode 3 Semiconductor layer 4 Gate insulating layer 4a Low surface energy part 4b Low surface energy part 5 Source electrode 6 Drain electrode Sa High surface energy part Da High surface energy part

Claims (18)

A patterned semiconductor layer is formed by forming a source electrode and a drain electrode facing each other at an appropriate interval directly on a substrate or via a gate insulating layer, and applying a solution containing a semiconductor material between the source electrode and the drain electrode. A method for forming a pattern of a semiconductor layer having an FET structure, the method comprising:
Each of the critical surface tensions of the gate insulating layer or substrate other than the source electrode and drain electrode formation regions has a low surface energy that is smaller than the respective critical surface tensions in the source electrode and drain electrode formation regions. Layer pattern formation method.   A low surface energy gate insulating layer having a small critical surface tension is provided on the substrate, and a high surface energy source electrode and a drain electrode having a large critical surface tension are formed on the predetermined gate insulating layer so as to face each other at an appropriate interval. A pattern formation method for a semiconductor layer having an FET structure, comprising a step of forming a patterned semiconductor layer by applying a solution containing a semiconductor material between the source electrode and the drain electrode.   And forming a source electrode and a drain electrode having a critical surface tension of 10 mN / m or more larger than a critical surface tension of a gate insulating layer or a substrate other than a region where the source electrode and the drain electrode are formed. Item 3. A method for forming a semiconductor layer pattern according to Item 1 or 2.   Forming each electrode so that a distance between a gate insulating layer or a substrate having a low surface energy sandwiched between the source electrode and the drain electrode is smaller than each width of the source electrode and the drain electrode. The semiconductor layer pattern forming method according to claim 1.   Producing a critical surface tension of the gate insulating layer or the substrate sandwiched between the source electrode and the drain electrode so as to be larger than a critical surface tension of the gate insulating layer or the substrate not sandwiched between the electrodes. The method for forming a pattern of a semiconductor layer according to claim 1, comprising:   6. The semiconductor layer pattern forming method according to claim 1, wherein the gate insulating layer is made of a material whose critical surface tension is changed by application of energy. The gate insulating layer is composed of at least a first material and a second material, and the first material is a material whose critical surface tension is greatly changed by the addition of energy as compared with the second material, The second material is a material having a function to complement the performance different from the first material,
The first material and the second material have a concentration distribution in the thickness direction of the gate insulating layer, and the concentration of the first material in the outermost layer is higher than the concentration of the second material. The pattern formation method of the semiconductor layer in any one of Claims 1-6.   The semiconductor layer pattern forming method according to claim 7, wherein the second material is a material having a higher electrical insulation than the first material.   The semiconductor layer pattern forming method according to claim 7, wherein the second material is a material having a higher relative dielectric constant than the first material.   10. The semiconductor layer pattern forming method according to claim 6, wherein the energy addition is performed by ultraviolet irradiation, and a low surface energy region is formed by changing a critical surface tension of the gate insulating layer. .   The method for forming a pattern of a semiconductor layer according to claim 1, wherein the gate insulating layer is made of a polymer material having a hydrophobic group in a side chain.   The method for forming a pattern of a semiconductor layer according to claim 11, wherein the polymer material having a hydrophobic group in the side chain is made of a material having a polyimide structure.   The semiconductor layer pattern forming method according to claim 1, wherein the semiconductor layer is made of an organic semiconductor.   The method for forming a pattern of a semiconductor layer according to claim 1, wherein the method of applying a solution containing a semiconductor material between the source electrode and the drain electrode is an inkjet method.   An electronic device, wherein the semiconductor layer is patterned by the semiconductor layer pattern forming method according to claim 1.   16. An electronic element array comprising a plurality of electronic elements according to claim 15 formed on an insulating substrate.   The electronic element array according to claim 16, wherein the insulating substrate also serves as a gate insulating layer having a low surface energy region having a small critical surface tension. A display device comprising the electronic element array according to claim 16.

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