JP2006059894A - Semiconductor integrated circuit layout method and layout program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a lay-out method and a lay-out program of a semiconductor integrated circuit, with which a situation where lay-out work becomes difficult since a region of signal wiring becomes narrow and a situation where manufacture cost and term of work increase due to addition of a wiring layer are avoided, an increase of a design period due to re-execution of lay-out is suppressed to a minimum, and a delay increase due to power voltage drop can be dissolved. <P>SOLUTION: A cell whose delay time becomes longer than permitted delay time due to power voltage drop by resistance of power wiring, namely, a cell whose speed becomes insufficient is automatically exchanged for a cell which is constituted of a transistor with low threshold and has the same function and the same size. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor integrated circuit layout method and a layout program. Specifically, the present invention relates to a layout method and a layout program for a semiconductor integrated circuit including a technique for eliminating a delay increase caused by a power supply voltage drop (IR-Drop) due to a resistance of a power supply wiring.

  FIG. 6 is a plan view schematically showing an example of the state of power supply voltage drop due to the resistance of the power supply wiring in the semiconductor integrated circuit chip. In FIG. 6, 1 is a semiconductor integrated circuit chip, 2 is a cell arrangement / wiring surface, and 3-6 are equivoltage lines schematically showing a portion of the power supply wiring layer surface where the power supply voltage is V3 to V6. In this example, V3> V4> V5> V6, and the power supply voltage drop is larger toward the center of the cell arrangement / wiring surface 2.

FIG. 7 is a diagram showing an example of the dependency of the gate delay time on the power supply voltage in the semiconductor integrated circuit, and shows that the gate delay time increases as the power supply voltage decreases. That is, the semiconductor integrated circuit has a problem that when the power consumption increases, the power supply voltage drop increases and the gate delay time increases. Therefore, conventionally, measures have been taken such as thickening the power supply wiring to suppress the power supply voltage drop, and buffering based on the result of timing analysis considering the power supply voltage drop.
JP-A-10-284612 JP 10-340292 A

  However, in the method of thickening the power supply wiring, the area of the signal wiring becomes narrow and the layout work becomes difficult. In some cases, it is necessary to add a wiring layer, resulting in an increase in manufacturing cost and an increase in work period. There was a problem. In addition, in the method of buffering based on the timing analysis result considering the power supply voltage drop, the increase in drive capability is the key to the countermeasure, so the cell size increases, the layout needs to be corrected, and the design period increases. There was a problem of inviting.

  In view of this point, the present invention avoids a situation in which the layout of the signal wiring becomes narrow and the layout work becomes difficult, a situation in which the manufacturing cost is increased due to the addition of the wiring layer, and the construction period is increased, and the design period of the layout is redesigned. It is an object of the present invention to provide a semiconductor integrated circuit layout method and layout program capable of minimizing an increase and eliminating an increase in delay due to a power supply voltage drop.

  According to a semiconductor integrated circuit layout method of the present invention, based on predetermined information, a cell is automatically placed and wired, a cell whose delay time is longer than an allowable delay time due to a power supply voltage drop is automatically extracted, and the cell is extracted. It includes a step of automatically exchanging with a cell having the same function and the same size constituted by a transistor having a low threshold value.

  According to the semiconductor integrated circuit layout program of the present invention, a cell automatic placement / wiring process based on predetermined information, and a cell having a delay time longer than an allowable delay time due to a power supply voltage drop are automatically extracted. Includes a program for causing a computer to execute a process of automatically replacing a cell having the same function and the same size configured by a transistor having a low threshold value.

  According to the present invention, a cell whose delay time is longer than the allowable delay time due to a power supply voltage drop is replaced with a cell having the same function constituted by a transistor having a low threshold, and an increase in delay due to the power supply voltage drop is eliminated. There is no need to thicken the power supply wiring as a measure against delay due to descent. As a result, it is possible to avoid a situation in which the area of the signal wiring becomes narrow and the layout work becomes difficult. Moreover, it is not necessary to add a wiring layer, and it is possible to avoid a situation in which the manufacturing cost increases and the construction period increases due to the addition of the wiring layer.

  In addition, cells whose delay time is longer than the allowable delay time due to a power supply voltage drop are replaced with cells of the same size. Therefore, the layout can be redone only by replacing the cells, and the increase in the design period required for the redo of the layout can be minimized.

  1 to 5, a semiconductor integrated circuit layout method according to an embodiment of the present invention will be described below including a semiconductor integrated circuit layout program according to an embodiment of the present invention.

  FIG. 1 is a diagram schematically showing an example of an apparatus for carrying out an embodiment of a semiconductor integrated circuit layout method of the present invention. One embodiment of the semiconductor integrated circuit layout method of the present invention can be implemented using a computer. In FIG. 1, reference numeral 7 denotes a CPU (central processing unit), 8 denotes a memory used by the CPU 7 for operations, and the like. Is an input means such as a keyboard and a mouse, and 10 is a display.

  11 is a net list storing means for storing a net list which is circuit information of the semiconductor integrated circuit, 12 is a cell library storing various information (size, power consumption, delay time, etc.) of the prepared cells, 13 Is a chip layout data storage means for storing chip layout data, 14 is a power supply voltage drop map storage means for storing a power supply voltage drop map, and 15 is a timing margin for storing information of a timing margin shortage path. This is a shortage path information storage means.

  16 is a cell initial placement program storage means for storing a cell initial placement program for initial placement of cells based on the netlist, 17 is a wiring program storage means for storing a wiring program for wiring, and 18 is power consumption. A power consumption estimation program storage means for storing a power consumption estimation program for estimating the power supply voltage drop, and a power supply voltage drop analysis program storage 19 for storing a power supply voltage drop analysis program for analyzing the power supply voltage drop due to the resistance of the power supply wiring Means.

  20 is a delay calculation / timing analysis program storage means for storing a delay calculation / timing analysis program for performing delay calculation / timing analysis, and 21 is a cell delay time suitability determination program for determining the suitability of the cell delay time. Cell delay time suitability determination program storage means 22, 22 is a cell exchange command creation program storage means for storing a cell exchange command creation program for creating a cell exchange command, and 23 is a cell exchange for storing a cell exchange program necessary for cell exchange. Program storage means.

  FIG. 2 is a flowchart showing an embodiment of a layout method of a semiconductor integrated circuit according to the present invention. In one embodiment of the semiconductor integrated circuit layout method of the present invention, first, based on the net list stored in the net list storage means 11 and the cell size information stored in the cell library 12, the chip layout is determined. Initial placement of cells on the surface is performed (step S1), followed by wiring (step S2).

  The initial cell placement is performed by using the cell initial placement program stored in the cell initial placement program storage means 16 and causing the CPU 7 to function as the cell initial placement means. The wiring is performed by using the wiring program stored in the wiring program storage means 17 and causing the CPU 7 to function as the wiring means.

  Chip layout data obtained by cell placement / wiring (steps S 1 and S 2) is stored in the chip layout data storage means 13. Further, based on the chip layout data and the power consumption information of each cell, the power consumption of the semiconductor integrated circuit is estimated (step S3). The estimation of the power consumption of the semiconductor integrated circuit is performed by using the power consumption estimation program stored in the power consumption estimation program storage means 18 and causing the CPU 7 to function as the power consumption estimation means.

  Next, the chip layout data stored in the chip layout data storage means 13 and the power consumption estimation result are used to analyze the power supply voltage drop due to the resistance of the power supply wiring, and the result is the power supply voltage drop. The map is stored in the power supply voltage drop map storage means 14 (step S4). The power supply voltage drop analysis is performed by using the power supply voltage drop analysis program stored in the power supply voltage drop analysis program storage means 19 and causing the CPU 7 to function as the power supply voltage drop analysis means.

  Next, delay calculation / timing analysis is performed based on the power supply voltage drop map stored in the power supply voltage drop map storage means 14 and the delay time information of the cells stored in the cell library 12 to obtain a timing margin. The shortage path is extracted and stored in the timing margin shortage path information storage means 15 (step S5). The delay calculation / timing analysis is performed by using the delay calculation / timing analysis program stored in the delay calculation / timing analysis program storage means 20 and causing the CPU 7 to function as the delay calculation / timing analysis means.

  Next, it is determined whether or not the delay time is appropriate for all the cells in the timing margin shortage path stored in the timing margin shortage path information storage means 15, that is, whether or not the delay time is longer than the allowable delay time. (Step S6). The suitability of the cell delay time is determined by using the cell delay time suitability judging program stored in the cell delay time suitability judging program storage means 21 and causing the CPU 7 to function as the cell delay time suitability judging means.

  If cells in the path with insufficient timing margin include cells with a delay time longer than the allowable delay time, the netlist, delay time information, A cell exchange command is created based on the chip layout data and the power supply voltage drop map (step S7). The cell exchange command is created by using the cell exchange command creation program stored in the cell exchange command creation program storage means 22 and causing the CPU 7 to function as the cell exchange command creation means.

  When the cell exchange command is created, a cell whose delay time is longer than the allowable delay time is exchanged (step S1). The cell exchange is performed by using the cell exchange program stored in the cell exchange program storage means 23 and causing the CPU 7 to function as the cell exchange means. In one embodiment of the semiconductor integrated circuit layout method of the present invention, as described later, it is replaced with a cell having the same function and the same size made of a transistor having a low threshold value.

  In step S6, steps S7 and S1 to S6 are repeated until the sum of the delay times of the cells in the timing margin shortage path becomes equal to or less than the allowable delay time, and the delay of the cells in the timing margin shortage path is reached. When the total time is equal to or less than the allowable delay time, the layout design is finished.

  FIG. 3 is a plan view showing a relative size of three 2-input NAND gates which are a kind of cells prepared in an embodiment of a semiconductor integrated circuit layout method of the present invention. In FIG. 3, 24 is a standard speed 2-input NAND gate, 24A and 24B are input terminals, and 24C is an output terminal. Reference numeral 25 denotes a two-input NAND gate having a relatively high speed (higher speed than the two-input NAND gate 24), 25A and 25B being input terminals, and 25C being an output terminal. Reference numeral 26 denotes a relatively high speed (higher speed than the 2-input NAND gate 25) 2-input NAND gate, 26A and 26B are input terminals, and 26C is an output terminal.

  Here, the 2-input NAND gate 25 is configured by a transistor having a lower threshold value than the transistors constituting the 2-input NAND gate 24, and the 2-input NAND gate 26 has a threshold value lower than that of the transistor configuring the 2-input NAND gate 25. It is composed of transistors and has the same size and terminal position.

  As described above, in one embodiment of the semiconductor integrated circuit layout method of the present invention, a cell having the same function and a cell having a standard speed with the same size and terminal position composed of transistors having different thresholds are used. A relatively high-speed cell composed of transistors with lower thresholds than the transistors that make up the cell, and a relatively super-high composed of transistors with lower thresholds than the transistors that make up relatively high-speed cells Three types of speed cells are prepared.

  Therefore, when a standard speed cell is arranged for a certain functional cell in the initial cell arrangement, if this standard speed cell is subject to replacement, a relatively high speed cell or a relatively super It will be replaced with a high speed cell. In addition, when a relatively high-speed cell is arranged for a certain functional cell in the initial cell arrangement, if this relatively high-speed cell is to be replaced, a relatively super-high speed Will be exchanged for other cells.

  FIG. 4 is a diagram showing the relationship between the gate delay time and the transistor threshold VTH in a semiconductor integrated circuit. Even if the transistors having a low threshold VTH have the same size, the on-resistance decreases and the gate delay time decreases. . Although not shown, current consumption increases when the threshold value VTH is lowered. Therefore, it is necessary to be aware that it is wasteful to collectively lower the threshold values VTH of all transistors in the semiconductor integrated circuit. is there.

  FIG. 5 is a diagram showing an example of a change in gate delay time due to cell replacement in a semiconductor integrated circuit. In FIG. 5, D1 to D3 indicate power supply voltage vs. delay time characteristics of a cell having the same function and the same size, D1 is a power supply voltage vs delay time characteristic of a standard speed cell, and D2 is a relatively high speed. The cell's power supply voltage versus delay time characteristic, D3, shows the power supply voltage versus delay time characteristic of a relatively high speed cell. Further, TD indicates an allowable delay time, VDD1 indicates a power supply voltage when there is no voltage drop, and VDD2 indicates a power supply voltage with a voltage drop.

  In this example, when the power supply voltage is VDD1, the delay time of each of the standard speed cell, the relatively high speed cell, and the relatively super high speed cell is equal to or shorter than the allowable delay time TD. However, when the power supply voltage drops to VDD2, the standard cell delay time exceeds the allowable delay time TD. Here, for example, when a standard speed cell is replaced with a relatively high speed cell, the delay time becomes smaller than the allowable delay time. However, in this case, the current consumption is slightly increased by cell replacement, so the power supply voltage is VDD3. This is highlighted in FIG.

  As described above, according to an embodiment of the semiconductor integrated circuit layout method of the present invention, the cells in the path whose delay time is longer than the allowable delay time due to the power supply voltage drop are configured by transistors having low thresholds. Since it can be automatically replaced with a functional cell, it is not necessary to make the power supply wiring thick as a countermeasure against a delay due to a power supply voltage drop. As a result, it is possible to avoid a situation in which the area of the signal wiring becomes narrow and the layout work becomes difficult. Further, it is not necessary to add a wiring layer for signal wiring, and it is possible to avoid a situation in which the manufacturing cost and the construction period increase due to the addition of the wiring layer.

  Further, according to an embodiment of the semiconductor integrated circuit layout method of the present invention, cells in a path whose delay time is longer than an allowable delay time due to a power supply voltage drop can be replaced with cells of the same size. Therefore, the layout can be redone only by replacing the cells, and the increase in the design period required for the redo of the layout can be minimized.

  Patent Documents 1 and 2 disclose a technique for replacing a cell having no or little delay time margin with a cell having a different driving capability. However, the techniques described in Patent Documents 1 and 2 are similar to those of the present invention. In addition, it is not intended to eliminate the delay caused by the power supply voltage drop due to the resistance of the power supply wiring, and is not a technique for exchanging cells with cells of the same size, and the effect obtained by the present invention cannot be obtained.

It is a figure which shows roughly an example of the apparatus for enforcing one Embodiment of the layout method of the semiconductor integrated circuit of this invention. 3 is a flowchart showing an embodiment of a layout method of a semiconductor integrated circuit according to the present invention. It is a top view which shows the relative size of three 2 input NAND gates which are 1 type of the cell prepared in one Embodiment of the layout method of the semiconductor integrated circuit of this invention. It is a figure which shows an example of the relationship between the gate delay time in a semiconductor integrated circuit, and the threshold value of a transistor. It is a figure which shows an example of the change of the gate delay time by the cell exchange in a semiconductor integrated circuit. It is a top view which shows roughly an example of the mode of the power supply voltage drop by the resistance of the power supply wiring in a semiconductor integrated circuit chip. It is a figure which shows an example of the power supply voltage dependence of the gate delay time in a semiconductor integrated circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Semiconductor integrated circuit chip 2 ... Cell arrangement | positioning and wiring surface 3-6 ... Isovoltage line 7 ... CPU
DESCRIPTION OF SYMBOLS 8 ... Memory 9 ... Input means 10 ... Display 11 ... Net list storage means 12 ... Cell library 13 ... Chip layout data storage means 14 ... Power supply voltage drop map storage means 15 ... Timing margin shortage path information storage means 16 ... Cell initial placement program storage means 17 ... Wiring program storage means 18 ... Power consumption estimation program storage means 19 ... Power supply voltage drop analysis program storage means 20 ... Delay calculation / timing analysis program storage means 21 ... Cell delay time suitability determination program storage means 22 ... Cell exchange command creation program storage means 23 ... Cell exchange program storage means

Claims (4)

A process of automatically placing and wiring cells based on predetermined information;
A semiconductor integrated circuit comprising a step of automatically extracting a cell having a delay time longer than an allowable delay time due to a power supply voltage drop and automatically replacing the cell with a cell having the same function and the same size configured by a transistor having a low threshold value. Circuit layout method. A step of estimating power consumption based on the result of automatic placement and wiring of the cells;
Performing a power supply voltage drop analysis using the result of the automatic placement and wiring of the cell and the result of the estimation of the power consumption;
Performing a timing analysis using the result of the power supply voltage drop analysis, and extracting a timing margin shortage path; and
2. The semiconductor integrated circuit according to claim 1, further comprising: automatically extracting a cell having a delay time longer than an allowable delay time due to the power supply voltage drop from the cells in the timing margin shortage path. Layout method. A process of automatically placing and wiring cells based on predetermined information;
A process of automatically extracting a cell whose delay time is longer than an allowable delay time due to a power supply voltage drop and automatically replacing the cell with a cell having the same function and the same size configured by a transistor having a low threshold value,
A layout program for a semiconductor integrated circuit, comprising a program to be executed by a computer. A step of estimating power consumption based on the result of automatic placement and wiring of the cells;
Performing a power supply voltage drop analysis using the result of the automatic placement and wiring of the cell and the result of the estimation of the power consumption;
Performing a timing analysis using the result of the power supply voltage drop analysis, and extracting a timing margin shortage path; and
A step of automatically extracting a cell having a delay time longer than an allowable delay time due to the power supply voltage drop from the cells in the timing margin shortage path,
4. The layout program for a semiconductor integrated circuit according to claim 3, further comprising a program to be executed by a computer.

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