JP2006050717A - DC motor control device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a control apparatus for a DC motor which reduces processing by a microcomputer to reduce firmware development and enables control at a low speed or a wide speed range from a low speed to a medium speed.
An internal rotation phase signal generation circuit that generates an internal rotation phase signal (REF_FG) based on an external reference signal (REF_CLK), an internal rotation phase signal (REF_FG), and an external rotation indicating a rotation phase of a DC motor A rotational speed control signal generation circuit 202 that generates a rotational speed control signal by obtaining a deviation from the phase signal (EXT_FG), and a phase control signal according to the phase difference between the external reference signal (REF_CLK) and the external index signal (INDEX) A phase control signal generation circuit 203 for generating the control signal, and a control signal generation circuit 204 for generating a control signal based on the rotation speed control signal and the phase control signal.
[Selection] Figure 1

Description

  The present invention relates to a control device for a DC motor, and more particularly, to constant speed rotation control and phase control by digital control.

  Conventionally, for a phase control method of a color wheel of a DLP projector, for example, “a motor control unit that synchronizes a color wheel with an incoming video signal and resynchronizes the color wheel after a channel change is provided. The control unit detects an out-of-phase condition and creates a color wheel sync signal from the pixel sample clock that is adjusted if there is a phase error, and a drive control unit provided in the motor control unit also provides this sync signal by the color wheel. In order to minimize the image effect at the time of channel change, a configuration has been proposed (for example, Patent Document 1).

  Further, regarding the control of the phase-synchronized DC motor, “the timer circuit measures the period of the timing signal and the relative phase between the timing signal and the rotational phase of the rotor of the motor, and the frequency command generator The motor speed command is generated to control the output phase of the motor driver circuit that drives the motor, with a small frequency synchronization error occurring between the timing signal and the rotational phase of the rotor. "Used to maintain phase relationship" has been proposed (for example, Patent Document 2).

  In addition, as the thing which realized complete digitalization, “the main digital signal processor which indicates the motor operation with the digital input command signal, the digital conversion signal for rotating the armature for each phase in response to the input command signal, And a drive controller that generates a digital pulse width modulation signal having a duty cycle determined by an input command signal, a switching unit that performs digital communication with the drive controller, and a motor monitoring unit that generates a digital tachometer signal representing an armature position. Have been proposed (for example, Patent Document 3).

JP 9-23444 A (Abstract) Japanese Patent Laid-Open No. 9-140177 (abstract) JP 7-163176 A (Abstract)

  The phase control methods described in Patent Documents 1 and 2 are good at a medium speed of 3600 rpm or higher, but have a problem that the pull-in time becomes long at a low speed. In addition, the control device disclosed in Patent Document 3 has a problem that the development of firmware is expensive because the microcomputer performs many processes.

  The present invention has been made in order to solve such a problem. The processing by the microcomputer is reduced to reduce the development of the firmware, and the control at a low speed or a wide range from a low speed to a medium speed. An object of the present invention is to provide a DC motor control device that enables control in a speed range.

  The control device for a DC motor according to the present invention is a control device that performs rotational speed control and phase control of a DC motor in synchronization with an external reference signal (REF_CLK), and an internal rotational phase signal based on the external reference signal (REF_CLK). An internal rotation phase signal generation circuit (201) for generating (REF_FG), the internal rotation phase signal (REF_FG), and an external rotation phase signal (EXT_FG) indicating the rotation phase of the DC motor in synchronization with the rotation of the DC motor. A rotation speed control signal generation circuit (202) for generating a rotation speed control signal by obtaining a deviation from the external reference signal (REF_CLK) and at least one pulse in synchronization with one rotation of the DC motor. A phase control signal generation circuit (203) for obtaining a phase difference from an applied external index signal (INDEX) and generating a phase control signal corresponding to the phase difference; and the rotational speed control signal It is obtained and a control signal generating circuit for generating a control signal based on the phase control signal of the rotational speed control signal from the phase control signal generating circuit from the adult circuit (204). In the present invention, the internal rotation phase signal (REF_FG) is generated based on the external reference signal (REF_CLK), and the deviation from the external rotation phase signal (EXT_FG) is obtained based on the internal rotation phase signal (REF_FG). Since the rotation speed control signal is generated, a situation in which the pull-in time becomes long at low speeds is avoided, and appropriate control is possible at low speeds. In addition, the processing by the microcomputer is reduced, and the development of firmware is no longer necessary. Or at least firmware development has been reduced. In addition, in this “means for solving the problems”, reference numerals corresponding to the configuration of the embodiment are added, but this is for clarifying the correspondence between the present invention and the embodiment. The configuration is not limited to that embodiment.

  The control device for a DC motor according to the present invention is a control device that performs rotational speed control and phase control of a DC motor in synchronization with an external reference signal (REF_CLK), and based on the external reference signal (REF_CLK) REF_FG) is input to the internal rotation phase signal generation circuit (201), the external reference signal (REF_CLK) and the internal rotation phase signal (REF_FG), and the frequency of the external reference signal (REF_CLK) is greater than a predetermined value. A first selection circuit (106) for outputting the period of the internal rotation phase signal (REF_FG) as a reference period when it is smaller, and outputting the period of the external reference signal (REF_CLK) as a reference period otherwise. An external rotation phase signal (EXT_FG) indicating the rotation phase of the DC motor in synchronization with the rotation of the DC motor, and at least one pulse in synchronization with one rotation of the DC motor. When an external index signal (INDEK) is input and the frequency of the external reference signal (REF_CLK) is lower than a predetermined value, the cycle of the external rotation phase signal (EXT_FG) is output as the target cycle, otherwise it is external A second selection circuit (113) that outputs the period of the index signal (INDEX) as a target period, and obtains a deviation between the reference period from the first selection circuit and the target period from the second selection circuit. A rotation speed control signal generation circuit (202) for generating a rotation control signal, a phase difference between the external reference signal (REF_CLK) and the external index signal (INDEX) is obtained, and a phase control signal corresponding to the phase difference is generated. A control signal is generated based on a phase control signal generation circuit (203), a rotation speed control signal from the rotation speed control signal generation circuit, and a phase control signal from the phase control signal generation circuit It is obtained by a control signal generating circuit (204).

  In the present invention, for example, control can be switched between a low speed and a medium speed. For example, when the speed is low, the external rotation phase signal (EXT_FG) is selected based on the internal rotation phase signal (REF_FG) generated based on the external reference signal (REF_CLK) by the selection of the first selection circuit and the second selection circuit. Since the rotation speed control signal is generated by obtaining the deviation, it is possible to avoid a situation in which the pull-in time becomes long at low speed, and appropriate control is possible at low speed. In the case of medium speed, the rotation speed control signal is generated by obtaining the deviation between the external reference signal (REF_CLK) and the external rotation phase signal (EXT_FG) by selecting the first selection circuit and the second selection circuit. As a result, control corresponding to medium speed is possible. Therefore, speed control corresponding to a wide speed range from low speed to medium speed is possible. In addition, the processing by the microcomputer is reduced and the development of firmware is no longer necessary, or at least the development of firmware is reduced.

  The control device for a DC motor according to the present invention obtains a moving average of the external rotation phase signal (EXT_FG), and uses the external rotation phase signal after the averaging process as the external rotation phase signal (EXT_FG) as the second selection. An averaging processing circuit (109) for outputting to the circuit is provided. In the present invention, since the moving average of the external rotation phase signal (EXT_FG) is obtained and the signal is used, for example, even if the external rotation phase signal (EXT_FG) includes jitter, it is canceled. This makes it possible to control rotation with high accuracy.

  In the control apparatus for a DC motor according to the present invention, the control signal generation circuit (204) outputs the minimum value as a control signal when the control signal is smaller than a predetermined minimum value, and the control signal is predetermined. When the control signal is larger than the maximum value, the maximum value is output as a control signal. When the control signal is a value between a predetermined minimum value and a predetermined maximum value, the control signal is output as it is. In the present invention, when the control signal is smaller than a minimum value, the minimum value is output as a control signal. When the control signal is larger than a predetermined maximum value, the maximum value is output as a control signal. The control amount is limited to stabilize the control.

  In the control apparatus for a DC motor according to the present invention, the rotation speed control signal generation circuit (202) compares the target period from the second selection circuit with a predetermined lower limit value and a predetermined upper limit value, respectively, When the speed is smaller than a predetermined lower limit value, a high speed signal (FAST) is output. When the speed is higher than the predetermined upper limit value, a low speed signal (SLOW) is output and output to the control signal generation circuit. The control signal generation circuit (204) outputs the maximum value as a control signal when the low speed signal (SLOW) is input, and outputs the minimum value as a control signal when the high speed signal (FAST) is input. As output. In the present invention, the control amount of the control signal is limited to stabilize the control.

  In the control apparatus for a DC motor according to the present invention, the control signal generation circuit (204) includes a PWM generation circuit (124) that generates a PWM signal based on the control signal, and outputs the PWM signal to a DC motor driver. To do. In the present invention, the PWM signal is generated and thereby the DC motor driver (20) is controlled to drive the DC motor.

  The control apparatus for a DC motor according to the present invention includes a first signal delay circuit (102) that delays the external reference signal (REF_CLK) for a predetermined time, and the external reference signal after delay processing is the external reference signal (REF_CLK). Output as. In the present invention, the phase of the DC motor relative to the external reference signal (REF_CLK) can be adjusted by appropriately delaying the external reference signal (REF_CLK).

  The control apparatus for a DC motor according to the present invention includes a second signal delay circuit (111) for delaying the external index signal (INDEX) for a predetermined time, and the external index signal after the delay processing is converted to the external index signal (INDEX). ). In the present invention, by appropriately delaying the external index signal (INDEX), the means for generating the external index signal (INDEX) does not require strict accuracy mechanically or electrically. .

  In the DC motor control device according to the present invention, each of the circuits is configured by hardware. In the present invention, each of the circuits is composed of a hardware circuit for processing a digital signal, so that the processing by the microcomputer is reduced and the development of firmware is unnecessary or at least reduced.

Embodiment 1. FIG.
FIG. 1 is a block diagram showing a control apparatus for a DC motor according to Embodiment 1 of the present invention. In the figure, the motor control means 10 inputs an external reference signal (REF_CLK), an external index signal (INDEX), an external rotation phase signal (EXT_FG), and a clock pulse (CLOCK), performs a predetermined process described later, and performs PWM processing. A signal is generated and output to the motor driver 20. The motor driver 20 controls the rotational speed and rotational phase of the DC motor 30 based on the PWM signal. As the external reference signal (REF_CLK) input to the motor control means 10, for example, when the control target is a projection monochrome wheel, VSYNC (vertical synchronization signal) representing the frame timing of the video signal is used. The external index signal (INDEX) is generated by the index generating means 31. For example, when the motor rotates, for example, x pulses are generated per rotation. For example, when one rotation is performed in synchronization with VSYNC (vertical synchronization signal), the external index signal (INDEX) generates one pulse. As a specific example of the index generation means 31, a reflection type photo reflector is used as an example. At this time, if the body (frame) of the DC motor 30 is made of a material that reflects the infrared rays of the photosensor, a process such as applying a black mark is performed. Further, the motor driver 20 is used for a DC brushless sensorless motor, and a motor driver capable of inputting / outputting a TTL level signal for digital control is used. Further, the motor driver 20 generates an external rotation phase signal (EXT_FG) from information based on the rotation angle of the rotor magnet inside the DC motor 30. In the first embodiment, the motor driver 20 and the DC motor 30 shown in FIG. 1 have been used in the past, and the configuration of the motor control means 10 has its characteristics, so the details will be described.

  FIG. 2 is an internal block diagram of the motor control means 10 of FIG. As shown in FIG. 2, the motor control means 10 includes an external reference signal normalization circuit 101, a signal delay circuit 102, a counter 103, an n frequency dividing circuit 104, an m multiplication circuit 105, a selection circuit 106, an external rotation phase signal normalization. Circuit 107, counter 108, averaging processing circuit 109, external index signal normalization circuit 110, signal delay circuit 111, counter 112, selection circuit 113, phase comparison circuit 114, filter 115, and deviation calculation circuit 120, a filter 121, an adder 122, a filter 123, and a PWM generation circuit 124. It is assumed that the counters 103, 108, and 112 have registers 103a, 108a, and 112a, respectively. These circuits are assumed to be composed of hardware.

  Further, the n frequency dividing circuit 104 and the m frequency multiplying circuit 105 correspond to the internal rotation phase generation circuit 201 of the present invention, the selection circuit 106 is the first selection circuit, the selection circuit 113 is the second selection circuit 113, and the deviation. The arithmetic circuit 120 and the filter 121 are included in the rotational speed control signal generation circuit 202 of the present invention, the phase comparison circuit 114 and the filter 115 are included in the phase control signal generation circuit 203 of the present invention, the adder 122, the filter 123, and the PWM generation circuit 124. This corresponds to the control signal generation circuit 204 of the present invention. Further, the signal delay circuit 102 corresponds to the first signal delay circuit of the present invention, and the signal delay circuit 111 corresponds to the second signal delay circuit of the present invention.

  FIG. 3 is a timing chart showing the output of each part of the external reference signal normalization circuit 101, the signal delay circuit 102, the counter 103, the n frequency dividing circuit 104, and the m multiplication circuit 105. The external reference signal normalization circuit 101 normalizes the external reference signal (REF_CLK) (FIG. 5A), and the signal delay circuit 102 delays the normalized external reference signal (REF_CLK) for a predetermined time to externally A reference signal delay signal (REF_CLK delay signal) is generated ((b) in the figure), and a delay signal (REF_CLK delay differential signal) is generated by differentiating the rising edge of the delay signal by a built-in differentiation circuit (not shown). (FIG. (C)). By thus delaying the external reference signal (REF_CLK) for a predetermined time, the phase adjustment of the DC motor 30 with respect to the external reference signal (REF_CLK) can be performed.

  When the delay differential signal (REF_CLK delay differential signal) is generated, the counter 103 starts counting the clock pulse (CLOCK), and the count value is stored in the internal register when the next delay differential signal (REF_CLK delay differential signal) is generated. 103 (a) and the count value (Ci) is reset ((d) (e) in the figure) The n divider circuit 104 multiplies the count value (Ci) by n times, that is, n (see (f) in FIG. )), The m multiplication circuit 105 multiplies the value by 1 / m, that is, m multiplication to obtain nCi / m, and thus the internal rotation phase signal (REF_FG) based on the period of the external reference signal (REF_CLK). The internal rotation phase signal (REF_FG) is a reference signal for speed control during low speed control.

The selection circuit 106 selects one of the count value (REF_CLK cycle) of the counter 103 and the output (internal rotation phase signal (REF_FG)) of the m multiplication circuit 105 and outputs it as a reference cycle. The selection circuit 106 sets, for example, a reference cycle = REF_CLK cycle (if REF_CLK> 40 Hz) and else REF_FG cycle. A cycle is selected, and when it is 40 Hz or less (when the speed is low), the cycle of the internal rotation phase signal (REF_FG) is selected and output to the deviation calculation circuit 120 as a reference cycle.

  FIG. 4 is a timing chart showing the output of each part of the external rotation phase signal normalization circuit 107, the counter 108, and the averaging processing circuit 109. The external rotation phase signal normalization circuit 107 normalizes the external rotation phase signal (EXT_FG) ((a) in the figure), differentiates the rise by a built-in differentiation circuit (not shown), and differentiates the external rotation phase signal (EXT_FG). ) Is obtained ((b) in the figure). The counter 108 counts the clock pulse (CLOCK). When the delayed differential signal (EXT_FG differential signal) is generated, the counter 108 starts counting the clock pulse (CLOCK) and generates the next delayed differential signal (EXT_FG differential signal). Thus, the count value is taken into the internal register 108a and stored, and the count value is reset (FIGS. 3C and 3D). The averaging processing circuit 109 obtains a moving average value of the count value of the register 108a of the counter 108. Since the external rotation phase signal (EXT_FG) is a signal generated from information based on the motor pole and rotor position, it is generated, for example, k times per rotation, but its frequency is not so accurate, so jitter (see FIG. 4 (a), which is black). Assuming that the external rotation phase signal (EXT_FG) is generated three times per rotation, the averaging processing circuit 109 averages the three counter values immediately before stored in the register 108a, and outputs them to the external rotation phase. The signal is output to the selection circuit 113 as a signal cycle (EXT_FG cycle) ((e) in the figure).

  FIG. 5 is a timing chart of the output of each part of the external index signal normalization circuit 110, the signal delay circuit 111, and the counter 112. The external index signal normalization circuit 110 normalizes the external index signal (INDEX), and the signal delay circuit 111 delays the normalized external index signal (INDEX) for a predetermined time and then incorporates a differentiation circuit (not shown). The differential signal (INDEX delayed differential signal) is generated by differentiating the rising edge of the delayed signal (FIG. 5A) (FIG. 5B). The counter 112 counts the clock pulse (CLOCK). When the differential signal ((INDEX delay differential signal) is generated, the counter 112 starts counting the clock pulse (CLOCK) and the next differential signal (INDEX delay differential signal) When the count value is generated, the count value is stored in the internal register 112a and output to the selection circuit 113, and the count value is reset ((c) and (d) in the figure). Although (INDEX) is delayed by a predetermined time, by performing such a process, the index generating means 31 is not required to be strictly accurate both mechanically and electrically.

The selection circuit 113 inputs the output of the averaging processing circuit 109 (external rotation phase signal cycle: EXT_FG cycle) and the output of the counter 112 (external index signal cycle: INDEX cycle), and sets the reference value to a preset value. One of them is selected based on the result and output to the deviation calculation circuit 120 as the target period. For example, the selection circuit 113 sets the target period = INDEX period (if REF_CLK> 40 Hz) else EXT_FG period, and selects the period of the external index signal (INDEX) when REF_CLK exceeds 40 Hz (medium speed), When REF_CLK is 40 Hz or less (low speed), the period of the external rotation phase signal (EXT_FG) is selected and output to the deviation calculation circuit 120 as the target period.

  FIG. 6 is a block diagram showing a part of the deviation calculation circuit 120, and FIG. 7 is a block diagram of the lower limit / upper limit generation block of FIG. The deviation calculation circuit 120 includes a lower limit value generation circuit 130, an upper limit value generation circuit 131, and comparators 132 and 133. As shown in FIG. 7, the lower limit value generation circuit 130 and the upper limit value generation circuit 131 include a set value register 135, a multiplier 136, and an adder / subtracter 137, and both have a common configuration. In the case of the lower limit generation circuit 130, the adder / subtracter 137 is a subtractor, and in the case of the upper limit generation circuit 131, the adder / subtracter 137 is an adder. Here, the lower limit generation circuit 130 will be described. For example, when 5% is set as the lower limit value in the set value register 135 via a data bus of a microcomputer (not shown), for example, the multiplier 136 When multiplied by a reference period (for example, the period is assumed to be 100), 100 × 5% = 5 is obtained, and the adder / subtracter 137 obtains a lower limit value of reference period−5 = 95. Similarly, when 8% is set as the upper limit, for example, an upper limit of “108” is obtained. The comparator 132 in FIG. 6 compares the lower limit value with the target period and outputs a signal FAST indicating that the speed is large when the lower limit value> the target period. The comparator 133 compares the upper limit value with the target period and outputs a signal SLOW indicating that the speed is small when the upper limit value <the target period. Since the periods are compared here, a large period means that the speed is slow. Note that the signal FAST and the signal SLOW are both inverted signals and are effective when they are “0”. However, the polarity of each signal described in the present embodiment depends on the circuit configuration in the present embodiment, and may be reversed when different circuit configurations are used.

  FIG. 8 is a block diagram showing a further part of the deviation calculation circuit 120. Here, the deviation between the reference period and the target period is obtained by the subtracter 138 and output. Therefore, the deviation calculation circuit 120 outputs the deviation output of FIG. 8 to the filter 121 and also outputs the signal FAST or the signal SLOW of FIG.

  FIG. 9 is a circuit diagram of the filter 121 of FIG. The filter 121 includes multipliers 140 and 141, adders 142 and 143, and a function multiplier 144 (this configuration itself has been used in the past). The filter 121 takes in the deviation output of the deviation calculation circuit 120 and generates a PI control signal.

  FIG. 10 is a circuit diagram of the phase comparison circuit 114 of FIG. The phase comparison circuit 114 includes flip-flop circuits (hereinafter referred to as FF circuits) 150 and 151, a NAND circuit 152, counters 153 and 154, falling detection circuits 155 and 156, and registers 157 and 158, and has a signal delay. The phase of the output (delayed REF_CLK) of the circuit 102 and the phase of the output (delayed EXT_FG) of the signal delay circuit 111 are compared to detect whether the phase is advanced or delayed, and the degree thereof is detected. .

  FIG. 11 is a timing chart showing the output of each part of the phase comparison circuit 114 when the phase of the reference signal (REF_CLK) is advanced. The FF circuit 150 receives the delayed external reference signal (REF_CLK) (FIG. (A)) as its output, and the FF circuit 151 sets the delayed index signal (INDEX) (FIG. (B)). ) To set the output to H level. The NAND circuit 152 takes these NAND logics and resets the output of the FF circuit 150, so that the output of the FF circuit 150 has a pulse (with a pulse width corresponding to the phase difference between the delayed REF_CLK and the delayed INDEX). Ph_fast) is obtained ((c) in the figure). The counter 153 counts the clock pulse (CLOCK) while the pulse Ph_fast is supplied ((d) in the figure). The falling edge detection circuit 155 detects the falling edge of the pulse (Ph_fast) and outputs it to the load terminal LD of the register 157. The register 157 fetches and outputs the output of the counter 153 at that timing ((e) in the figure). Therefore, the register 157 outputs a count value (phase advance information) corresponding to the phase difference between the delayed REF_CLK and the delayed index signal (INDEX) (the phase of the REF_CLK is ahead of the INDEX). It will be.

  FIG. 12 is a timing chart showing the output of each part of the phase comparison circuit 114 when the phase of the reference signal (REF_CLK) is delayed. The FF circuit 151 sets its output to the H level by the input of the delayed INDEX (FIG. 1A), and the FF circuit 150 receives the input of the delayed external reference signal (REF_CLK) (FIG. 1B). The output is set to H level. The NAND circuit 152 takes the NAND logic and resets the output of the FF circuit 151, so that the output of the FF circuit 151 includes a pulse (with a pulse width corresponding to the phase difference between the delayed INDEX and the delayed REF_CLK ( Ph_late) is obtained ((c) in the figure). While the pulse (Ph_late) is being supplied, the counter 154 counts the clock pulse (CLOCK) ((d) in the figure) The falling detection circuit 156 detects the falling of the pulse Ph_late, and the register 158 The register 158 captures and outputs the output of the counter 154 at that timing ((e) in the figure) Therefore, the register 158 has a delayed index signal (INDEX) and a delayed external reference signal. A count value (phase delay information) corresponding to (REF_CLK) and a phase difference (the phase of INDEX is advanced from that of REF_CLK) is output.

FIG. 13 is a circuit diagram of the phase control filter 115 of FIG. The filter 115 includes an inverter 160, an adder 161, a selector 162, and a multiplier 163. Here, the above phase advance information and phase lag information are
Phase advance information: P_fast [n-1: 0]
Phase lag information: P_late [n-1: 0]
And an n-bit configuration.

  For the phase delay information, 1 bit of P_late [n] (its value is 0) is added to P_late [n−1: 0], and information with n + 1 bits / sign is output to the selector 162. For the phase advance information, one bit of P_fast [n] (its value is 0) is added to P_fast [n−1: 0] and inverted by the inverter 160, and then the constant: “1” is added by the adder 161. Add and output to the selector 162. The selector 162 outputs any input information (n + 1 bit / signed), and the multiplier 163 sets the information to 1 / γ, for example. This is for adjusting the amount of data.

  If the phase is delayed, it is necessary to increase the rotation speed of the motor so that the phase is matched. For this reason, by performing the above processing, positive data is output to increase the control amount. ing. If the phase is advanced, it is necessary to slow down the rotation speed of the motor so that the phase is matched, and the amount of control is reduced, so that the amount of control is complemented by 2 by performing the above processing. Output as.

  The output (phase control signal) of the filter 115 for phase control in FIG. 13 is added to the output (rotational speed control signal) of the filter 121 by the adder 122 and input to the filter 123 as a control signal.

FIG. 14 is a circuit diagram of the filter 123 of FIG. The filter 123 includes registers 170 and 171, comparators 172 and 173, and a multiplexer 174. A minimum value is set in the register 170, and a maximum value is set in the register 171. The comparator 172 compares the control signal from the adder 122 with the minimum value set in the register 170, and outputs a signal (min) indicating the minimum value when the control signal is smaller than the minimum value of the register 170. However, since the comparator 172 outputs an inverted signal, it becomes “0” at that time. The comparator 173 compares the control signal from the adder 122 with the maximum value set in the register 171 and outputs a signal (max) indicating the maximum value when the control signal is larger than the maximum value of the register 171. . However, since the comparator 173 also outputs an inverted signal, it becomes “0” at that time. The multiplexer 174 takes in the outputs of the comparators 172 and 173, the control signal from the adder 122, the signals FAST and SLOW from the deviation calculation circuit 120, and performs the following calculation processing.
(Min, max) or (FAST, SLOW) = (0, 0) ... undefined (min, max) or (FAST, SLOW) = (0, 1) ... minimum value output (min, max) or (FAST, SLOW) = (1, 0)... Maximum value output (min, max) or (FAST, SLOW) = (1, 1)... Input is output as it is. Therefore, the multiplexer 174 has a control signal whose minimum value and maximum value. Is output as it is, and when the signal FAST is “0”, the minimum value is output. When the signal SLOW is “0”, the maximum value is output. The output is output and the control amount is limited.

  FIG. 15 is a circuit diagram of the PWM generation circuit 124 of FIG. The PWM generation circuit 124 includes a register 180, a counter 181, and comparators 182, 183 and an FF circuit 184. The PWM generation circuit 124 operates as shown in FIG. 16 to generate a PWM signal.

  FIG. 16 is a timing chart showing the operation of the PWM generation circuit 124. The output of the filter 123 (PWM_DATA, FIG. 5B) is set in the register 180. In this example, the counter 181 counts a clock pulse (CLOCK), and when it reaches a predetermined value, it is reset and restarts counting ((a) in the figure). The comparator 182 compares the output of the counter 181 with the set value “0”, and outputs a match signal to the set terminal S of the FF circuit 184 because they match. As a result, the output of the FF circuit 184 becomes H level. When the count of the counter 181 advances and the count value of the counter 181 coincides with the set value of the register 180, the comparator 183 detects this and outputs a coincidence signal to the reset terminal R of the FF circuit 184. The output of the circuit 184 becomes L level. By repeating such processing, the PWM signal is output from the FF circuit 184 ((d) in the figure).

  As described above, in the first embodiment, for example, at a low speed (in the above example, when REF_CLK is 4 Hz or less), the selection circuit 106 selects the period of the internal rotation phase signal (REF_FG period) and selects the deviation calculation circuit 120. The selection circuit 113 selects the period (EXT_FG period) of the external rotation phase signal and outputs it to the deviation calculation circuit 120. The deviation calculation circuit 120 determines the period of the internal rotation phase signal (REF_FG period) and the external rotation phase signal. The rotation speed control signal is obtained by obtaining a deviation from the period (EXT_FG period), and the pull-in time does not become long even at a low speed, and appropriate control is possible. For example, at a medium speed (when REF_CLK exceeds 4 Hz in the above example), the selection circuit 106 selects the period of the external reference signal (REF_CLK period) and outputs it to the deviation calculation circuit 120, and the selection circuit 113 outputs the external index. The signal cycle (INDEX cycle) is selected and output to the deviation calculation circuit 120. The deviation calculation circuit 120 calculates the deviation between the cycle of the external reference signal (REF_CLK cycle) and the cycle of the external index signal (INDEX cycle). A rotation speed control signal is obtained, and appropriate control corresponding to the medium speed is possible. For this reason, in the first embodiment, control in a wide speed range from a low speed to a medium speed is possible.

  Further, the filter 123 of FIG. 2 outputs the control signal as it is when the control signal is between the minimum value and the maximum value, and outputs the minimum value when the control signal is below the minimum value or when the signal FAST is “0”. When the signal exceeds the maximum value or when the signal SLOW is “0”, the output of the maximum value is output, and the control amount is limited (limiter), so that stable control is possible.

  2 is composed of hardware, for example, the signal delay circuits 102 and 111, the n frequency divider circuit 104, the m frequency multiplier circuit 105, the selection circuits 106 and 113, the deviation calculation circuit 120, the filter 121, and the like. The filter 123 only needs to be set once via the data bus in the initial stage, so that the processing by the microcomputer is reduced and the development of firmware is unnecessary or at least reduced.

Embodiment 2. FIG.
In the first embodiment, switching between the low speed and the medium speed has been described with reference to an external reference signal (REF_CLK) of 40 Hz. However, the present invention is not limited to this example, and It may be a value before or after. Further, in the first embodiment, the example in which the PWM signal is generated and output to the motor driver 20 has been described. However, if the motor driver 20 captures another type of control signal instead of the PWM signal, Outputs control signals in the corresponding format. The configurations of the circuits in FIGS. 6 to 10 and FIGS. 13 to 15 can be modified as appropriate without departing from the scope of the present invention. In addition, an example in which the external reference signal (REF_CLK) is obtained by dividing and multiplying the internal rotation phase signal (REF_FG) has been described. However, this is only a process of dividing or multiplying as necessary. May be.

  The present invention is applied to, for example, a motor control of a projection system that rotates a monochrome wheel to insert black and a projection system that rotates a prism at low speed and scans a light valve with light.

The block diagram of the control apparatus of the DC motor which concerns on Embodiment 1 of this invention. The circuit diagram of the motor control means of FIG. The timing chart which showed the output of each part of FIG. 2 (the 1). The timing chart which showed the output of each part of FIG. 2 (the 2). FIG. 3 is a timing chart (No. 3) showing an output of each unit in FIG. 2. The block diagram which shows a part of deviation operation circuit. The block diagram of a lower limit / upper limit generation circuit. The block diagram which shows a part of deviation operation circuit further. The circuit diagram of the filter for rotation speed control signals. The circuit diagram of a phase comparison circuit. 6 is a timing chart (No. 1) showing outputs of respective units of the phase comparison circuit. 6 is a timing chart (No. 2) showing the output of each part of the phase comparison circuit. The circuit diagram of the filter for phase control signals. The circuit diagram of the filter for control signals. The circuit diagram of a PWM generation circuit. The timing chart which shows the output of each part of a PWM generation circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Motor control means, 20 DC motor driver, 30 DC motor, 31 Index production | generation means, 101 External reference signal normalization circuit, 102 Signal delay circuit, 111 Signal delay circuit, 103 Counter, 104 n frequency dividing circuit, 105 m multiplication circuit , 106 selection circuit, 107 external rotation phase signal normalization circuit, 108 counter, 109 averaging processing circuit, 110 external index signal normalization circuit, 111 signal delay circuit, 112 counter, 113 selection circuit, 114 phase comparison circuit, 115 filter , 120 deviation calculation circuit, 121 filter, 122 adder, 123 filter, 123 filter, 124 PWM generation circuit.
201 internal rotation phase generation circuit, 202 rotation speed control signal generation circuit, 203 phase control signal generation circuit, 204 control signal generation circuit.

Claims (9)

In a control device that performs DC motor rotation speed control and phase control in synchronization with an external reference signal (REF_CLK),
An internal rotation phase signal generation circuit for generating an internal rotation phase signal (REF_FG) based on the external reference signal (REF_CLK);
A rotational speed control signal for generating a rotational speed control signal by obtaining a deviation between the internal rotational phase signal (REF_FG) and an external rotational phase signal (EXT_FG) indicating the rotational phase of the DC motor in synchronization with the rotation of the DC motor. A generation circuit;
A phase difference between the external reference signal (REF_CLK) and an external index signal (INDEX) given as at least one pulse in synchronization with one rotation of the DC motor is obtained, and a phase control signal corresponding to the phase difference A phase control signal generation circuit for generating
A control of a DC motor, comprising: a control signal generation circuit that generates a control signal based on a rotation speed control signal from the rotation control signal generation circuit and a phase control signal from the phase control signal generation circuit apparatus. In a control device that performs DC motor rotation speed control and phase control in synchronization with an external reference signal (REF_CLK),
Internal rotation phase signal generating means for generating an internal rotation phase signal (REF_FG) based on the external reference signal (REF_CLK);
When the external reference signal (REF_CLK) and the internal rotation phase signal (REF_FG) are input and the frequency of the external reference signal (REF_CLK) is smaller than a predetermined value, the cycle of the internal rotation phase signal (REF_FG) is set. A first selection circuit that outputs as a reference period, and otherwise outputs the period of the external reference signal (REF_CLK) as a reference period;
An external rotation phase signal (EXT_FG) indicating the rotation phase of the DC motor in synchronization with the rotation of the DC motor, and an external index signal (INDEK) provided as at least one pulse in synchronization with one rotation of the DC motor. ), And when the frequency of the external reference signal (REF_CLK) is lower than a predetermined value, the cycle of the external rotation phase signal (EXT_FG) is output as the target cycle, and otherwise, the external index signal (INDEX) A second selection circuit that outputs the period of
A rotation speed control signal generation circuit that generates a rotation control signal by obtaining a deviation between a reference period from the first selection circuit and a target period from the second selection circuit;
A phase control signal generation circuit for obtaining a phase difference between the external reference signal (REF_CLK) and the external index signal (INDEX) and generating a phase control signal according to the phase difference;
A DC motor comprising: a control signal generation circuit that generates a control signal based on a rotation speed control signal from the rotation speed control signal generation circuit and a phase control signal from the phase control signal generation circuit; Control device.   An averaging processing circuit is provided that calculates a moving average of the period of the external rotation phase signal (EXT_FG) and outputs the external rotation phase signal after the averaging process as the external rotation phase signal (EXT_FG). The control device for a DC motor according to claim 1 or 2.   The control signal generation circuit outputs the minimum value as a control signal when the value of the control signal is smaller than a predetermined minimum value, and when the value of the control signal is larger than a predetermined maximum value, The maximum value is output as a control signal, and when the value of the control signal is a value between a predetermined minimum value and a predetermined maximum value, the control signal is output as it is. The control apparatus of the DC motor in any one. The rotational speed control signal generation circuit compares the target cycle from the second selection circuit with a predetermined lower limit value and a predetermined upper limit value, respectively, and outputs a signal with a higher speed when the rotational speed control signal generation circuit is smaller than the predetermined lower limit value. Output, when the signal is larger than the predetermined upper limit value, output a low speed signal to the control signal generation circuit,
The control signal generation circuit outputs the maximum value as a control signal when the low speed signal is input, and outputs the minimum value as a control signal when the high speed signal is input. Item 5. The DC motor control device according to Item 4.   The said control signal generation circuit is provided with the PWM generation circuit which produces | generates a PWM signal based on the said control signal, The said PWM signal is output to a DC motor driver, The any one of Claims 1-5 characterized by the above-mentioned. Control device for DC motor.   7. The first signal delay circuit for delaying the external reference signal (REF_CLK) for a predetermined time, and outputting the external reference signal after delay processing as the external reference signal (REF_CLK). The control apparatus of the DC motor in any one.   The external index signal (INDEX) is provided with a second signal delay circuit that delays the external index signal (INDEX) for a predetermined time, and the external reference signal after delay processing is output as the external index signal (INDEX). A control device for a DC motor according to claim 1. 9. The DC motor control apparatus according to claim 1, wherein each of the circuits includes hardware that processes a digital signal.

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