JP2006048661A - Arithmetic processing device for controlling data transfer between processor and coprocessor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an arithmetic processing device capable of reducing the number of cycles required for data transfer between a main processor and a coprocessor.
An instruction interpretation control unit that sequentially interprets instructions and performs control based on instructions in a main processor specifies a type of arithmetic processing to be executed by the coprocessor in a field 22 in a single instruction. 24 designates the first register in which the subject of the arithmetic processing is stored, and designates the second register in which the result of the arithmetic processing by the coprocessor is to be stored in the field 23, and performs the operation on the coprocessor By obtaining and interpreting the requested coprocessor operation instruction, the coprocessor is caused to execute the operation processing of the type with the contents of the first register as the operation processing target, and further the operation processing performed by the coprocessor Control is performed to write the result to the second register.
[Selection] Figure 2

Description

  The present invention relates to an arithmetic processing device including a processor and a coprocessor, and more particularly, to a data transfer control technique for an operation target and an operation result between the processor and a coprocessor that performs a predetermined operation.

Conventionally, an arithmetic processing unit in a computer system includes a general-purpose processor (hereinafter referred to as “main processor”) and a processor for specific operation (hereinafter referred to as “coprocessor”), and these plural processors are coordinated. There is an arithmetic processing unit configured to operate as described above.
An arithmetic processing unit including such a main processor and a coprocessor is used for, for example, a moving picture encoding process in the MPEG (Moving Picture Experts Group) system.

In ME (Motion Estimation) processing, which occupies most of the calculation amount in this encoding processing, it is necessary to calculate the absolute value difference between pixel data of each image constituting the moving image to be processed and the sum thereof. Since a large amount of pixel data is subject to calculation, the difference absolute value calculation and the number of calculations related to the sum thereof are very large.
Therefore, the main processor performs the processing necessary for the encoding process in addition to the coprocessor having an arithmetic unit specialized in calculating the difference absolute value calculation and the sum thereof. The number of clock cycles (hereinafter simply referred to as “cycles”) required for the entire process is reduced.

In this way, the arithmetic processing unit in which the main processor and the coprocessor perform a cooperative operation, as a matter of course, completes the target processing in a smaller number of cycles than when the arithmetic processing unit consisting of a single processor performs processing. Therefore, even if the operating frequency of the arithmetic processing unit is kept relatively low, the intended processing can be completed.
In general, technology development for increasing the operating frequency of an arithmetic processing unit requires a large amount of cost. Therefore, reducing the number of cycles for completing a target process can be achieved by using a relatively low-cost arithmetic processing unit. This leads to the effect that the power consumption can be performed, and suppressing the operating frequency of the arithmetic processing device low leads to the effect that the power consumption can be suppressed low.

By the way, conventionally, coprocessor / data manipulation instructions and coprocessor / register transfer instructions are known as instructions for instructing operations to be performed by the coprocessor. A coprocessor register transfer instruction is known as an instruction for instructing data transfer of operation results (see Non-Patent Document 1).
This coprocessor register transfer instruction is an instruction for designating one-way data transfer between the main processor and the coprocessor.

More specifically, in this coprocessor / register transfer instruction, only one of the source data as the operation target and the destination data as the operation result can specify the register of the main processor.
FIG. 17 shows an example of a program that causes the coprocessor to perform an operation.
In the program shown in the figure, the instruction MCR in the row L1 is a coprocessor / register transfer instruction that instructs the coprocessor with data transfer to the coprocessor, and includes a first operand p0 for specifying the coprocessor, A second operand for specifying the processing contents, and a value of 0 indicates that a specific coprocessor operation requiring 3 cycles is to be performed, and a third for specifying a register in the main processor in which the source data to be calculated is stored It consists of an operand r1 and a fourth operand Cr1 and a fifth operand Cr2 that specify a register used for calculation in the coprocessor. Further, the instruction nop in the row L2 and the row L3 is an instruction that spends one cycle and does not perform any special processing, and the instruction MRC in the row L4 is a coprocessor register that instructs the coprocessor with data transfer from the coprocessor. A first instruction p0 that specifies a coprocessor, a second operand that specifies the processing contents of the coprocessor and indicates that no operation is performed if the value is 1, and a destination that is an operation result It comprises a third operand r0 for designating a register in the main processor in which data is to be stored, and a fourth operand Cr1 and a fifth operand Cr2 for designating registers used for operations in the coprocessor.

As described above, when the source data is stored in the main processor, the coprocessor performs an operation based on the source data, and the destination data generated as a result of the operation must be stored in the main processor. The coprocessor register transfer instruction is issued twice for the transfer of the source data and the transfer of the destination data.
Steve Furber, Arm Co., Ltd. (supervised), “Revised ARM Processor”, December 18, 2001 (first edition issued), CQ Publishing Co., Ltd. (issued), p. 122-126

  The present invention has been made to obtain a useful effect by reducing the number of cycles described above, and is an arithmetic processing unit capable of reducing the number of cycles required for data transfer between a main processor and a coprocessor as compared with the prior art. It is another object of the present invention to provide an instruction sequence generation device that generates an instruction sequence to be input to the arithmetic processing unit.

  In order to achieve the above object, an arithmetic processing unit according to the present invention is an arithmetic processing unit comprising a main processor and a coprocessor, wherein the main processor sequentially interprets instructions and performs control based on the instructions. An instruction control unit, wherein the instruction interpretation control unit includes a type of arithmetic processing to be executed by the coprocessor, a first storage area in which a target of the arithmetic processing is stored, and the coprocessor performs arithmetic processing. By interpreting a processing request instruction for designating a second storage area in which the result is to be stored, causing the coprocessor to execute the type of arithmetic processing with the contents of the first storage area as an arithmetic processing target; The control of writing a result of a certain arithmetic process performed by the coprocessor in the second storage area is performed.

  In the arithmetic processing unit configured as described above, the processing request instruction for requesting the coprocessor to perform arithmetic processing specifies the type of arithmetic processing to be executed by the coprocessor and becomes the source of transfer of source data to the coprocessor. In the case where both the designation of one storage area and the designation of the second storage area to which the destination data is transferred from the coprocessor are combined, it is possible to operate in response to this processing request instruction. The number of cycles required to complete can be kept relatively low. Basically, an arithmetic processing unit requires one or more cycles to execute one instruction. Therefore, if the number of instructions for achieving the same purpose is small, the number of cycles required for achieving the purpose is suppressed as compared with the case where the number of instructions is large. Because you get. In addition, there is an effect that the code size of a program for causing such an arithmetic processing device to execute a processing request instruction can be made smaller than that of the conventional one. This can lead to a reduction in the capacity of the instruction memory.

  Here, the main processor has a plurality of registers for storing an operation target or a result when performing an operation based on the operation instruction, and the processing request instruction specifies the first storage area Including: first data for identifying any one of the plurality of registers; and second data for identifying any one of the plurality of registers as designating a second storage area, , Causing the coprocessor to execute the arithmetic processing of the type specified by the processing request instruction with the contents of the register identified by the first data included in the processing request instruction as an arithmetic processing target. It is also possible to perform control to write a result of a certain arithmetic processing performed to a register identified by the second data included in the processing request instruction.

  As a result, one of the registers in the main processor register group is designated as a source data transfer source and a destination data transfer destination, and corresponds to one processing request instruction for causing the coprocessor to perform an operation. Therefore, the processing result of the main processor is handed over to the coprocessor to perform a specific operation, and the processing result of a certain coprocessor is processed by the main processor as one operation target. Since it can be described by an instruction, a program corresponding to a series of processes configured by stacking such processing procedures can be described by an instruction string with a small number of instructions, and as a result, execution of the series of processes is executed. The performance is improved than before.

  The processing request instruction is executed as a code format in the coprocessor in addition to a field for storing an instruction identification code for identifying the processing request instruction from other instructions in the instruction group executable by the main processor. The instruction interpretation control unit includes a field for storing a coprocessor instruction code indicating a type of arithmetic processing to be performed, a field for storing first data, and a field for storing second data. The instruction code for the coprocessor included in the instruction is controlled to be transmitted to the coprocessor, and the source data which is the content of the register identified by the first data included in the processing request instruction is transmitted to the coprocessor. In addition, the result data which is the result of a certain arithmetic processing sent from the coprocessor is acquired, Control is performed to write to the register identified by the second data included in the processing request instruction, and the coprocessor interprets the instruction code for the coprocessor sent from the main processor, and the source sent from the main processor It is also possible to acquire data and make it an arithmetic processing target, execute the type of arithmetic processing indicated by the instruction code for the coprocessor, and send result data as a result of the arithmetic processing to the main processor. Good.

  As a result, the operation result of the main processor is handed over to the coprocessor to perform a specific operation, and the operation result of the specific operation is further processed by the main processor. Specify the register of the main processor that is the transfer source, the type of arithmetic processing to be performed by the coprocessor, and the register of the main processor that is the transfer destination of data from the coprocessor in one instruction. become able to.

  Further, when the instruction interpretation control unit sends the coprocessor instruction code included in the processing request instruction to the coprocessor, the instruction interpretation control unit transmits the second data included in the processing request instruction together with the coprocessor instruction code. When sending the result data to the main processor, the coprocessor sends out the result data, which is the result of executing the type of arithmetic processing indicated by the coprocessor instruction code sent from the main processor. The second data sent from the main processor together with the instruction code for the coprocessor is sent to the main processor together with the result data, and the instruction interpretation control unit and the result data sent together from the coprocessor 2 data and the result data is written to the register identified by the second data. It is also possible to be.

  This allows the main processor to respond to the processing request instruction after several cycles have elapsed after sending a signal that triggers the start of computation to the coprocessor, that is, the instruction code for the coprocessor, in response to the processing request instruction. Until the calculation result by the coprocessor is returned, it is no longer necessary to store and hold which register should store the calculation result by the coprocessor. It is only necessary to store the operation result by the coprocessor in a register specified based on the information returned later.

  In addition, the result data that the instruction interpretation control unit controls to write to the register identified by the second data included in the processing request instruction is transmitted from the coprocessor, and the result data of the arithmetic processing specified by the processing request instruction is transmitted. The instruction interpretation control unit stores in advance time information indicating an operation processing time in association with each of the operation processes, and the coprocessor instruction code included in the process request instruction; After the source data is sent to the coprocessor, when the arithmetic processing time indicated by the stored time information corresponding to the type of arithmetic processing indicated by the coprocessor instruction code has elapsed, the coprocessor As a result, the result data sent from the control request is written to the register identified by the second data included in the processing request instruction. Good.

  As a result, the main processor must store the register to which the operation result by the coprocessor is to be returned after the coprocessor has started the operation in response to the processing request instruction. Even without receiving notification that the operation corresponding to the processing request command has been completed, the coprocessor can identify the timing at which the operation result output on the data transmission path should be acquired, and acquire the operation result. Thus, it can be stored in the previously stored register.

  The instruction interpretation control unit sends a predetermined signal to the coprocessor when the result data sent from the coprocessor is written to a register identified by the second data included in the processing request instruction. The coprocessor may continue sending the result data until detecting that the predetermined signal is sent by the main processor, and stop sending the result data after the detection. .

  As a result, after the main processor is executing a program including a processing request instruction, the coprocessor starts the operation in response to the processing request instruction, and then, for example, an interrupt handling process corresponding to an external interrupt signal Even when the main processor cannot immediately write the data output on the data transmission path as the result of the coprocessor operation at the end of the coprocessor operation, When it is written after it becomes ready to be written, that is, immediately before writing, when it is written, or immediately after writing, it is sent to the coprocessor. Since the output of the calculation result is continued, the main processor can reliably acquire the calculation result by the coprocessor.

  The coprocessor outputs the result data after the same time has elapsed from the start of the arithmetic processing for each type of arithmetic processing specified by the coprocessor instruction code. The result data that is controlled to be written to the register identified by the second data included in the request command is an operation specified by another processing request command that is sent from the coprocessor and interpreted prior to the processing request command. The processing result data, and the instruction interpretation control unit sends the coprocessor instruction code included in the processing request instruction together with the second data to the coprocessor, and then follows the processing request instruction. The result of the arithmetic processing specified by the processing request instruction preceding the processing request instruction by the coprocessor before interpreting another instruction The result data sent by, may be controlled to write into the register identified by the second data.

  As a result, for example, in the case where the arithmetic processing unit is supplied with a plurality of continuous processing request instructions and is interpreted and executed on the assumption that the operation requested by the coprocessor is processed in a pipeline manner, the continuous processing request In one processing request instruction of an instruction, not only a register for storing data to be given to a coprocessor but also a register for receiving a coprocessor operation result corresponding to a preceding processing request instruction can be specified. In other words, since the data storage position in the main processor related to data transfer from the main processor to the coprocessor and data transfer from the coprocessor to the main processor can be specified with one instruction, the number of instructions necessary to achieve some purpose is conventionally set. The number of cycles required to achieve the purpose can be suppressed.

Further, the control performed by the instruction interpretation control unit to write to the register identified by the second data included in the processing request instruction executes the type of arithmetic processing specified by the processing request instruction to the coprocessor. It is good also as control which writes the result made to the said register | resistor.
As a result, the processing request instruction can include the specification of a register for the main processor to receive the result of causing the coprocessor to execute the operation specified by the processing request instruction. It is now possible to define the instruction format of a processing request instruction that causes a coprocessor to perform an operation in an instruction format that includes the specification of a register that stores an operation result according to the instruction as an operand. For example, the program creator can understand the instruction It is useful for making it easier.

  The arithmetic processing unit includes first and second coprocessors, the second coprocessor has a plurality of registers, and the processing request instruction is an operation to be executed by the first coprocessor. The specification of the type of processing, the first data for identifying one of the plurality of registers of the second coprocessor as specifying the first storage area, and the second data as specifying the second storage area Second instruction for identifying any one of the plurality of registers of the processor, and the instruction interpretation control unit identifies the first coprocessor to the second data identified by the first data included in the processing request instruction. The contents of the register in the coprocessor are subject to arithmetic processing, the type of arithmetic processing specified by the processing request instruction is executed, and the result of certain arithmetic processing performed by the first coprocessor is Identified by second data contained in the processing request command may perform a control to write to registers in the second co-processor.

As a result, it is possible to instruct the other coprocessor to perform an operation based on data in a certain coprocessor and return the operation result to the original coprocessor with one instruction.
An instruction sequence generation device according to the present invention generates an instruction sequence in a machine language for causing a main processor included in the arithmetic processing unit of claim 1 to be executed together with a coprocessor based on input data. A column generation device, a storage unit, an input data acquisition unit for acquiring input data, a type of arithmetic processing to be executed by a coprocessor based on the input data, and a target of the arithmetic processing A processing request instruction for designating a first storage area outside the coprocessor and a second storage area outside the coprocessor in which the result of arithmetic processing performed by the coprocessor is to be stored And a command sequence generation unit for generating the command sequence in machine language including the command sequence and recording the command sequence in the storage unit.

When an instruction sequence that can be supplied to the above arithmetic processing unit and interpreted and executed is required, the instruction sequence generation device causes the coprocessor to perform an operation based on the contents of the storage area outside the coprocessor. Thus, it is possible to generate an instruction sequence including one processing request instruction specifying that the operation result is stored in a storage area outside the coprocessor.
Here, the process request instruction generated by the instruction sequence generation means stores, as a code format, an instruction identification code for identifying the process request instruction from other instructions in the instruction group executable by the main processor. A field for storing a coprocessor instruction code indicating the type of arithmetic processing to be executed by the coprocessor, and a first storage area. Each of a field for storing first data for identifying one of them, and a field for storing second data for identifying any one of a plurality of registers of the main processor as specifying a second storage area It is good also as including.

This instruction sequence generation device generates an instruction sequence including one processing request instruction that specifies that the coprocessor performs an operation using the contents of the main processor register and stores the operation result in the main processor register. Can be made.
The instruction sequence generation device further includes an operation time management unit that stores in advance time information indicating an operation processing time in association with various types of operation processing that can be executed by the coprocessor. The means generates a calculation instruction for calculating the contents of the register of the main processor identified by the second data included in the generated processing request instruction at a position subsequent to the processing request instruction in the instruction sequence. Specifies an operation processing time related to the operation processing of the type indicated by the instruction code for the coprocessor included in the process request instruction based on the time information stored by the operation time management means, and from the process request instruction The instruction sequence may be generated by placing the operation instruction at a position having an interval equal to or more than the number of instructions corresponding to the specified operation processing time.

  As a result, when an operation instruction for which the destination data specified by the process request instruction is an operation target follows the process request instruction, the coprocessor is operating according to the process request instruction at the time of execution of the operation instruction. Thus, an instruction sequence that prevents the occurrence of a situation in which the destination data has not been generated yet is generated.

<Embodiment 1>
Hereinafter, the arithmetic processing apparatus according to the first embodiment of the present invention will be described.
<Overview>
An arithmetic processing apparatus according to Embodiment 1 of the present invention includes a main processor and a coprocessor, and causes the coprocessor to perform an operation on an instruction set to be acquired, interpreted, and executed by the main processor. Arithmetic instructions are included. The xexec instruction corresponding to this coprocessor operation instruction is expressed in mnemonic notation as follows.

xexec OPn, dstRn, srcRn
Here, the coprocessor operation instruction, that is, the xexec instruction, is an instruction that requires specification of three operands OPn, dstRn, and srcRn. This OPn is the designation of the type of arithmetic processing in the coprocessor, srcRn is the designation of the register number on the main processor side that stores the source data used for the coprocessor computation, and dstRn is the computation by the coprocessor This is the designation of the register number on the main processor side for storing the result.

  When this coprocessor operation instruction is acquired and interpreted, the main processor requests the coprocessor to perform operation by transmitting the source data, which is the contents of the register designated by srcRn, and the type of operation processing to the coprocessor. . In response to this, the coprocessor performs arithmetic processing using the source data and transmits the destination data as the arithmetic result to the main processor. The main processor receives the destination data and stores it in the register specified by dstRn. To do.

  Thus, one coprocessor operation instruction specifies the type of operation processing to be executed by the coprocessor, specifies the source data transfer from the main processor to the coprocessor, and the destination from the coprocessor to the main processor. By combining the designation of data transfer, the arithmetic processing device that can use this coprocessor arithmetic instruction can keep the number of cycles required to complete the target processing relatively low. Basically, an arithmetic processing unit requires one or more cycles to execute one instruction. Therefore, if the number of instructions for achieving the same purpose is small, the number of cycles required for achieving the purpose is suppressed as compared with the case where the number of instructions is large. obtain.

FIG. 1 is a diagram illustrating a part of an assembler program including a xexec instruction.
The main processor can interpret and execute this program, actually the program code after being converted into machine language.
Line L11 is an xexec instruction that instructs the coprocessor to execute the arithmetic processing identified by OP0 using the contents of the register r1 and stores the arithmetic result in the register r0. Rows L12 and L13 are instructions that each spend a period of one cycle.

Assuming that 3 cycles are required for the execution of the arithmetic processing identified by OP0 by the coprocessor, in the instruction following line L13 in this program example, the execution result of the preceding xexec instruction is stored in register r0. The contents of the register r0 can be used.
Hereinafter, the arithmetic processing apparatus according to the first embodiment will be described in detail.

<Coprocessor operation instruction format>
First, the format of a coprocessor operation instruction (xexec instruction) that is one instruction belonging to the above-described instruction set of the main processor will be described.
FIG. 2 is a diagram illustrating a format of a coprocessor operation instruction (xexec instruction).
As shown in the figure, the xexec instruction has an instruction length of 16 bits, an instruction identification code field 21, a coprocessor instruction code field 22 for specifying an operand, a destination register specification field 23, and a source register. And a designation field 24.

Here, the instruction identification code field 21 is a field for setting a 6-bit instruction identification code for identifying an xexec instruction in an instruction group that can be decoded and executed by the main processor. 100010b and the like are predetermined.
The coprocessor instruction code field 22 corresponds to the operand OPn and is a field for setting a 2-bit code for identifying the type of arithmetic processing to be executed by the coprocessor. Here, this bit length is determined on the assumption that the coprocessor can perform four or less types of arithmetic processing.

The destination register designation field 23 is a field for setting 4-bit data for specifying one of the register groups in the main processor corresponding to the operand dstRn, and is a destination that is an operation result transmitted from the coprocessor. Used to specify a register to store data.
The source register specification field 24 is a field for setting 4-bit data for specifying one of the register groups in the main processor, corresponding to the operand srcRn, and is a source to be used for arithmetic processing in the coprocessor. Used to specify the register in which data is stored.

<Configuration of arithmetic processing unit>
FIG. 3 is a block diagram showing a configuration of the arithmetic processing apparatus according to the first embodiment.
As shown in the figure, the arithmetic processing unit 100 includes a main processor 3000, a coprocessor 4000, an instruction memory 5000 that stores an instruction sequence including coprocessor arithmetic instructions, and a data memory that is a target of data access by the main processor. 6000.

  Here, the main processor 3000 is a partial modification of the conventional processor, and includes an instruction interpretation control circuit 3100, an arithmetic unit 3200 that is a circuit group for performing arithmetic operations and logical operations, and an arithmetic unit 3200. And a register bank 3500 which is a register group configured so as to be able to transfer data between them. The main processor 3000 can perform another operation while causing the coprocessor 4000 to execute the operation.

  The instruction interpretation control circuit 3100 sequentially reads and interprets instructions from the instruction sequence stored in the instruction memory 5000, and controls or data related to access to the register bank 3500 and the data memory 6000 according to the interpretation target instruction. It has functions for performing transfer control, control for causing the arithmetic unit 3200 to execute an operation specified by an instruction, control of the coprocessor 4000, control related to reading of an instruction in the instruction memory 5000, and the like. Note that the control of the coprocessor 4000 is such that, when the instruction interpretation control circuit 3100 interprets the above-described coprocessor arithmetic instruction, the designation of the type of arithmetic processing included in the coprocessor arithmetic instruction is transmitted to the coprocessor 4000. Is done. The configuration of the register bank 3500 and the operation related to the data transfer will be described in detail later.

  The coprocessor 4000 is a partial modification of the conventional coprocessor, and transfers data between the logic control circuit 4100, the arithmetic unit 4200 that is a circuit that performs specific arithmetic processing, and the arithmetic unit 4200. And a register bank 4500 which is a register group configured to be able to perform the above. The coprocessor 4000 can sequentially execute the arithmetic processing of the arithmetic type designated by the main processor 3000 one by one. The operating frequency of the main processor 3000 and the coprocessor 4000 is the same.

  The logic control circuit 4100 receives the designation of the type of arithmetic processing transmitted from the main processor 3000, interprets it, and controls the data transfer to the register bank 4500 or the arithmetic unit 4200 according to the result. It has a function of performing control of processing, and notifying the main processor of completion of arithmetic processing. The logic control circuit 4100 stores data indicating the number of cycles required to execute the arithmetic processing of each arithmetic type. The number of cycles that elapse during execution of arithmetic processing by the arithmetic unit is counted and stored. It has a mechanism for detecting the end timing of the calculation by collating with data indicating the number of cycles being performed.

The arithmetic unit 4200 is an arithmetic unit specialized for a specific application, such as one that can perform parallel calculation of the differential absolute value calculation and the sum thereof used in the ME process constituting the encoding process in the MPEG system at a relatively high speed. It has a function.
In FIG. 3, a control signal transmission path (hereinafter referred to as “control signal line”) is represented by a thin arrow line, and a bus for transmitting data including instructions (hereinafter referred to as “data transmission path”). .) Is represented by a thick arrow line.

The control signal line 3010 transmits a signal sent from the command interpretation control circuit 3100 to control the command memory 5000. In response to this control signal, a command is sent from the command memory 5000 via the data transmission path 5010. It is sent to the interpretation control circuit 3100.
The control signal line 3020 controls the arithmetic unit 3200, the control signal line 3030 controls the register bank 3500, the control signal line 3050 controls the data memory 6000, and the control signal line 3040 is the coprocessor. In order to transmit the type of arithmetic processing, etc., signals transmitted from the instruction interpretation control circuit 3100 are transmitted.

  Data is transferred between the arithmetic unit 3200 and the register bank 3500 via the data transmission path 3060 and the data transmission path 3065, and between the register bank 3500 and the data memory 6000, the data transmission path 3080 and the data transmission path 3085. The data is transmitted between the arithmetic unit 4200 and the register bank 4500 via the data transmission path 4060 and the data transmission path 4065, and the register bank 3500 of the main processor 3000 and the register bank of the coprocessor 4000 are transmitted. Data is transmitted to and from 4500 via a data transmission path 3070 and a data transmission path 3075.

FIG. 4 is a configuration diagram showing the configuration of the register bank 3500 in detail.
The register bank 3500 includes a register 3600 (R0), a register 3601 (R1) to a register 3615 (R15), and a selector group that selects a data transmission path and a register in order to write data to the register, that is, a selector 3650 and a selector 3651-selector. 3665, a selector 3670, and a selector 3680 for selecting which register outputs data to be supplied to the data transmission path.

These register group and selector group are configured to operate in accordance with a control signal supplied from the instruction interpretation control circuit 3100 via the control signal line 3030.
Accordingly, the instruction interpretation control circuit 3100 switches the selector 3670, the selector 3650, and the selector 3651 to the selector 3665 by appropriately giving a control signal when certain data is to be written to a certain register according to the interpretation result of the instruction. Any of the data output from the data memory 6000 to the data transmission path 3080, the data output from the computing unit 3200 to the data transmission path 3060, and the data output from the coprocessor 4000 to the data transmission path 3070 Is supplied to a register to be written, and a control signal is given to the register to store data in the register. In addition, when the instruction interpretation control circuit 3100 is to supply data from a certain register to the data transmission path according to the interpretation result of the instruction, the instruction interpretation control circuit 3100 outputs a data by outputting a control signal to the register and appropriately controls the data. By supplying the signal to the selector 3680, the data output from the register is transferred to the data transmission path 3065 connected to the arithmetic unit 3200, the data transmission path 3085 connected to the data memory 6000, and the data transmission path 3075 connected to the coprocessor 4000. Control it to appear.

<Operations related to general operation instructions>
In the arithmetic processing unit 100 having the above-described configuration, arithmetic instructions other than the coprocessor arithmetic instructions are executed by the main processor 3000 mainly using the arithmetic unit 3200. The operation of the main processor 3000 in this case is the same as that of a general processor.
For example, when the instruction interpretation control circuit 3100 reads and interprets an operation instruction that executes a certain operation from the instruction memory 5000 based on the contents of the internal register R0 and stores the result in the internal register R1. Then, the selector 3680 is controlled to output the data as the contents of the register R0 to the data transmission line 3065, etc., and the arithmetic unit 3200 is controlled to perform the operation based on the output data, and the operation result is obtained. The data is transmitted to the data transmission path 3060, and the selector 3670, the selector 3651 and the register R1 are controlled to write the data on the data transmission path 3060 to the register R1.

It should be noted that the processing time from when the data used for the operation is read out from the register, the operation is performed and the result is written into the register is, for example, several cycles, and the number of cycles varies depending on the operation processing content.
The processing timing for the above-described calculation example includes a period T1 in which data transfer from the register R0 to the calculator is performed, a subsequent period T2 in which calculation is performed in the calculator, and a subsequent calculation result in the register R1. It includes a writing period T3. For example, the period T2 is included across one or more cycles subsequent to one cycle including the period T1, and the period T3 is included in one subsequent cycle. Considering an operation using two registers as inputs, for example, during a cycle, a period T1 during which data transfer from one register to the arithmetic unit is performed and a period during which data transfer from the other register to the arithmetic unit is performed. T1 ′ is included without duplication.

<Operations related to coprocessor operation instructions>
Hereinafter, the operation of each unit when the arithmetic processing unit 100 having the above-described configuration executes a coprocessor arithmetic instruction (xexec instruction) will be described.
When the instruction interpretation control circuit 3100 of the main processor 3000 interprets the instruction read from the instruction memory 5000 and determines that the instruction is the xexec instruction based on the instruction identification code, each field ( The following two processes are performed within one cycle based on the contents of FIG.

First, the instruction interpretation control circuit 3100 performs, as one process, the contents of the instruction code field for the coprocessor, that is, the operation type, and the contents of the destination register designation field, that is, the designation of the operation result storage register via the control signal line 3040. To the logic control circuit 4100 of the coprocessor 4000.
In addition, as another process, the instruction interpretation control circuit 3100 outputs each control signal for outputting data from one register designated by the contents of the source register designation field onto the data transmission path 3075. The signal is supplied to the register and selector 3680 via the control signal line 3030.

  In response to these processes, in the coprocessor 4000, the logic control circuit 4100 controls the register bank 4500 and the calculator 4200 in accordance with the received calculation type, and the source data provided on the data transmission path 3075. The arithmetic processing based on is executed. The number of cycles required for this calculation process is, for example, three cycles, and the number of cycles varies depending on the calculation type.

  Further, the logic control circuit 4100 holds the designation of the received arithmetic result storage register, and when the arithmetic processing ends, that is, based on the stored data indicating the number of cycles required to execute each arithmetic processing. In accordance with the end timing of the specified arithmetic processing, a signal indicating the end of the operation including designation of the operation result storage register is transmitted to the instruction interpretation control circuit 3100 of the main processor 3000 via the control signal line 4040. . At the end of the calculation, the calculation result data is output on the data transmission path 3070 by the calculator 4200. The calculation result is returned to the main processor 3000 through the data transmission path 3070.

  When the instruction interpretation control circuit 3100 receives from the logic control circuit 4100 a signal indicating the end of the operation including the specification of the operation result storage register, one register designated as the operation result storage register by that signal. Each control signal for causing the data on the data transmission path 3070 to be written to is supplied to the registers and selectors 3650 to 3665 via the control signal line 3030. As a result, the operation result of the coprocessor 4000 is stored in the register designated by the contents of the destination register designation field in the xexec instruction interpreted several cycles ago.

  The instruction interpretation control circuit 3100 has a data transfer period in which the operation result of the coprocessor 4000 corresponding to the xexec instruction is written to a certain register, and an internal corresponding to any general operation instruction following the xexec instruction. Control is performed so that the data transfer period in which the calculation result by the calculator is written to another register is included in one cycle without overlapping.

<Operation timing>
Hereinafter, the execution timing of each process related to the execution of the coprocessor operation instruction will be described in detail.
Here, (1) when the main processor 3000 sequentially reads, interprets and executes each instruction constituting the program stored in the instruction memory 5000, the main processor 3000 relates to the program when receiving an interrupt signal from the outside. The execution of the original program is resumed after temporarily interrupting the execution of the instruction, and the coprocessor 4000 is executing the interrupt handling process while the main processor 3000 is performing the interrupt handling process. (2) The coprocessor computing unit 4200 does not have a pipeline configuration and writes the previous computation result to a register in the main processor 3000. In the following description, it is assumed that the next coprocessor operation instruction is not accepted and two cycles are required to execute one operation process.

FIG. 5 is a timing chart for each process related to the coprocessor operation instruction. In this timing chart, the control signal is shown in two stages, upward or downward, and the upper part represents a state in which the signal that triggers the processing is active.
In cycle C1, instruction data acquisition processing 111 is executed. That is, the command interpretation control circuit 3100 sends a control signal via the control signal line 3010 to acquire a command from the command memory 5000.

In cycle C2, instruction decode processing 112 is executed. That is, the instruction interpretation control circuit 3100 interprets the acquired instruction and specifies each register specified by the operand of the xexec instruction.
In cycle C3, data transfer processing 113 to the coprocessor and control transfer processing 114 to the coprocessor are executed. That is, under the control of the instruction interpretation control circuit 3100 via the control signal line 3030, the register designated in the source register designation field outputs the data on the data transmission path 3075 and delivers the data to the coprocessor 4000. The interpretation control circuit 3100 outputs the operation type and the operation result storage register designation to the control signal line 3040 and passes them to the coprocessor 4000.

  In cycle C4 and cycle C5, coprocessor arithmetic processing 115 is executed. That is, the logic control circuit 4100 transmits a control signal via the control signal line 4020 in the cycle C4 according to the operation type acquired via the control signal line 3040, and sends the control signal to the arithmetic unit 4200 on the data transmission path 3075. An operation using data is started, and in cycle C5, a signal indicating the end of the operation including the designation of the operation result storage register that has already been acquired and held is sent via the control signal line 4040 to the main processor 3000. To send to. In cycle C5, arithmetic unit 4200 completes the operation and outputs the data of the operation result on data transmission path 3070.

  In cycle C6, data transfer processing 116 to the main processor is executed. That is, the instruction interpretation control circuit 3100 transmits a control signal to the register bank 3500 via the control signal line 3030 based on the designation of the register for storing the operation result included in the received signal indicating the end of the operation. The data on the data transmission path 3070 is written to the register.

The main processor 3000 performs processing related to the instruction subsequent to the coprocessor arithmetic instruction in parallel with the execution of the processing related to the coprocessor arithmetic instruction after the start of execution of the processing related to the coprocessor arithmetic instruction. Although not shown above, for example, in cycle C2, a general operation instruction A following the above-described xexec instruction is acquired from the instruction memory 5000, the operation instruction A is interpreted in cycle C3, and operation is performed in cycle C4. The calculation target data related to the instruction A is transferred from the register to the calculator 3200, the calculation according to the calculation instruction A is performed by the calculator 3200 in the cycle C5, and the calculation result is transferred to the register in the cycle C6. An operation instruction B subsequent to the operation instruction A is acquired from the instruction memory 5000 in C3, and the operation instruction B is acquired in cycle C4. Interpretation is performed, and the operation target data related to the operation instruction B is transferred from the register to the operation unit 3200 in the cycle C5, and the operation according to the operation instruction B is performed by the operation unit 3200 in the cycle C6. Transfer the result to a register.
<Modification 1>
Hereinafter, Modification 1 of the above-described arithmetic processing device 100 will be described. The original example described above with respect to the first modification will be referred to as a basic example.

  In the arithmetic processing device 100 according to the basic example described above, the coprocessor 4000 sequentially executes arithmetic processing of the arithmetic type designated by the main processor 3000 one by one. The apparatus differs from the arithmetic processing apparatus 100 according to the basic example in that the coprocessor executes each arithmetic processing in parallel in a pipeline manner. In addition, about each part of the arithmetic processing apparatus which concerns on the modification 1, it demonstrates using the same code | symbol as each corresponding part in the arithmetic processing apparatus 100 which concerns on the basic example mentioned above as needed for description.

The execution timing of each process related to the execution of the coprocessor arithmetic instruction (xexec instruction) in the arithmetic processing apparatus according to the first modification will be described.
Note that (1) While the main processor is performing interrupt handling processing, the coprocessor performs synchronous control that temporarily stops arithmetic processing. (2) The coprocessor's arithmetic unit Even if the previous operation result is not written to a register in the main processor, the next coprocessor operation instruction is accepted and the operation processing is executed in a pipeline system with two pipeline stages. In the following description, it is assumed that two cycles are required to execute one arithmetic process.

FIG. 6 is a timing chart for each process related to the coprocessor operation instruction in the first modification.
Here, description will be given focusing on the n-th instruction and the (n + 1) -th instruction, both of which are coprocessor operation instructions.
In cycle C1, instruction data acquisition processing 111 is executed for the nth coprocessor operation instruction.

  In cycle C2, the instruction data acquisition process 111 is executed for the (n + 1) th coprocessor operation instruction, and the instruction decode process 112 is executed for the nth coprocessor operation instruction. That is, the instruction interpretation control circuit sends out a control signal via the control signal line 3010 to acquire the (n + 1) th coprocessor operation instruction from the instruction memory, and the instruction interpretation control circuit acquires it in the cycle C1. The nth coprocessor operation instruction is interpreted.

Similarly, in the subsequent cycles, separate processing is performed corresponding to each of a plurality of coprocessor operation instructions in each cycle. In FIG. 6 and FIG. 7 and the like used thereafter, the contents of each process indicated by the same reference numerals as those in FIG. 5 are basically the same as the contents described above with reference to FIG. If there is a difference, it will be explained.
In cycle C3, a data transfer process 113 to the coprocessor and a control transfer process 114 to the coprocessor are executed corresponding to the nth coprocessor operation instruction, and an instruction corresponding to the (n + 1) th coprocessor operation instruction. A decoding process 112 is executed.

  In cycle C4, the first half process 115a of the coprocessor operation process divided into two stages is executed corresponding to the nth coprocessor operation instruction, and to the coprocessor corresponding to the n + 1th coprocessor operation instruction. Data transfer processing 113 and control transfer processing 114 to the coprocessor are executed. In the first half process 115a of the coprocessor arithmetic process, the logic control circuit continues to hold the designation of the register for storing the operation result that has already been acquired corresponding to the coprocessor arithmetic instruction that is the target of the first half process 115a. A control signal is transmitted via the control signal line 4020 according to the already obtained calculation type, and the calculator 4200 is caused to start calculation using data on the data transmission path 3075. Note that the logic control circuit has a storage area for holding the designation of registers for storing operation results, at least as many as the number of stages in the pipeline, and this set of storage areas is stored, for example, This is realized by a FIFO (First In First Out) buffer from which values can be sequentially extracted.

  In cycle C5, the second half process 115b of the coprocessor calculation process divided into two stages is executed corresponding to the nth coprocessor calculation instruction, and the first half process 115a corresponding to the n + 1th coprocessor calculation instruction. Is executed. In the second half process 115b of the coprocessor arithmetic process, the arithmetic unit 4200 takes over the result of the first half process 115a, performs further calculations to the end, and outputs the data of the calculation result on the data transmission path 3070. In response to the nth coprocessor operation instruction, the logic control circuit sends a signal indicating the end of the operation including the specification of the register for storing the operation result already held in the FIFO buffer, for example, to the control signal line 4040. To the main processor.

  In cycle C6, a data transfer process 116 to the main processor is executed corresponding to the nth coprocessor operation instruction, and a second half process 115b is executed corresponding to the n + 1th coprocessor operation instruction. In cycle C6, under the control of the instruction interpretation control circuit of the main processor, after the data on the data transmission path 3070 is written to the register indicated by the destination register designation field of the nth coprocessor operation instruction. Each operation timing is determined so that a calculation result corresponding to the (n + 1) th coprocessor calculation instruction by the calculator 4200 on the coprocessor side is output on the data transmission path 3070.

In cycle C7, data transfer processing 116 to the main processor is executed in response to the (n + 1) th coprocessor operation instruction.
<Modification 2>
Hereinafter, Modification 2 of the arithmetic processing device 100 according to the basic example will be described.
In the arithmetic processing unit 100 according to the basic example, the coprocessor 4000 performs synchronous control in which the arithmetic processing is temporarily stopped while the main processor 3000 performs the interrupt handling processing. The arithmetic processing device according to Example 2 differs from the arithmetic processing device 100 according to the basic example in that the coprocessor continues the arithmetic processing while the main processor performs the interrupt handling processing. In addition, about each part of the arithmetic processing apparatus which concerns on the modification 2, it demonstrates using the same code | symbol as each corresponding part in the arithmetic processing apparatus 100 which concerns on the basic example mentioned above as needed on description.

  In the arithmetic processing device according to the second modification, as in the arithmetic processing device 100 according to the basic example, the logic control circuit holds the designation of the received arithmetic result storage register, and performs an arithmetic operation on the arithmetic unit. The calculation result is output on the data transmission path 3070, and when the calculation process is completed, a signal indicating the completion of the calculation including the designation of the calculation result storage register is sent via the control signal line 4040. It is transmitted to the instruction interpretation control circuit of the main processor. The subsequent processing is unique to the arithmetic processing apparatus according to the second modification, and the instruction interpretation control circuit that has received the signal indicating the end of the operation indicates that the operation result can be received when ready to receive the operation result. The signal is transmitted to the logic control circuit via the control signal line 3040, and while the signal indicating that the signal can be received is not received on the logic control circuit side, a signal indicating the completion of the operation is repeatedly sent every cycle. The data on the data transmission path 3070 is maintained without executing a new calculation that outputs data to the data transmission path 3070.

Hereinafter, the execution timing of each process related to the execution of the coprocessor arithmetic instruction (xexec instruction) in the arithmetic processing apparatus according to the modified example 2 will be described.
The arithmetic unit of the coprocessor does not have a pipeline configuration, and does not accept the next coprocessor arithmetic instruction until the previous arithmetic result is written to a register in the main processor, and executes one arithmetic process. It is assumed that two cycles are required.

FIG. 7 is a timing chart for each process related to the coprocessor operation instruction in the second modification.
In cycles C1 to C3, the same operation as that of the arithmetic processing apparatus 100 according to the basic example shown in FIG. 5 is performed.
In cycle C4 and cycle C5, coprocessor arithmetic processing 115 is executed. That is, the logic control circuit transmits a control signal via the control signal line 4020 in cycle C4 in accordance with the computation type acquired via the control signal line 3040, and transmits data on the data transmission path 3075 to the computing unit 4200. In cycle C5, a signal indicating the end of the operation including the designation of the operation result storage register already acquired and held is transmitted to the main processor via the control signal line 4040. The operation unit 4200 outputs the operation result data after completion of the operation to the data transmission path 3070, and a signal indicating that reception is possible is sent via the control signal line 3040. wait.

FIG. 7 shows an example in which the main processor does not perform interrupt handling processing or the like and issues a signal indicating that it can be received without any particular delay.
In this example, since the logic control circuit has received a signal indicating that it can be received during cycle C5, the arithmetic unit 4200 is controlled to output data of the operation result to the data transmission line 3070 in cycle C6. Not performed.

  In cycle C6, data transfer processing 116 to the main processor is executed. That is, the instruction interpretation control circuit transmits the control signal to the register bank 3500 via the control signal line 3030 based on the designation of the register for storing the operation result included in the received signal indicating the end of the operation. Data on the data transmission path 3070 is written to the register.

FIG. 8 is a timing chart for each process related to the coprocessor operation instruction in the second modification, and shows an example in which a signal indicating that reception is possible is delayed.
In the example shown in the figure, the main processor interprets the coprocessor operation instruction, requests the coprocessor to perform the operation, performs interrupt handling processing, etc., and before the end, the operation by the coprocessor according to the request is performed. This is an example of completion.

In cycles C1 to C4, the same operation as in the example of FIG. 7 is performed.
In cycle C5, a signal indicating the end of the operation including the designation of the operation result storage register that has already been acquired and held is sent to the main processor via the control signal line 4040, and the operation unit 4200 receives the signal. Data of the calculation result after completion of the calculation is output on the data transmission path 3070 and waits for a signal indicating that it can be received via the control signal line 3040.

  In cycle C5, since the logic control circuit has not received a signal indicating that it can be received, the arithmetic unit 4200 outputs the operation result data to the data transmission path 3070 in cycle C6, and again stores the operation result. A signal indicating the end of the calculation including the register designation is sent to the main processor via the control signal line 4040. Then, in cycle C6, the logic control circuit receives a signal indicating that it can be received. Therefore, the arithmetic unit 4200 is not controlled to output the data of the operation result to the data transmission path 3070 in cycle C7.

In cycle C7, data transfer processing 116 to the main processor is executed. That is, the instruction interpretation control circuit transmits the control signal to the register bank 3500 via the control signal line 3030 based on the designation of the register for storing the operation result included in the received signal indicating the end of the operation. Data on the data transmission path 3070 is written to the register.
<Modification 3>
Hereinafter, Modification 3 of the arithmetic processing device 100 according to the basic example will be described.

  The arithmetic processing apparatus according to the third modification includes all the configurations necessary for the coprocessor to execute each arithmetic process in a pipeline manner as in the first modification described above, and includes the second modification described above. Similarly, the coprocessor continues arithmetic processing while the main processor is performing interrupt handling processing. In addition, about each part of the arithmetic processing apparatus which concerns on the modification 3, it demonstrates using the same code | symbol as each corresponding part in the arithmetic processing apparatus 100 which concerns on the basic example mentioned above as needed on description.

  In the arithmetic processing device according to the third modification, as in the second modification, the instruction interpretation control circuit that has received the signal indicating the completion of the operation can receive it when the operation result is ready to be received. Is transmitted to the logic control circuit via the control signal line 3040, and while the signal indicating that the signal can be received is not received on the logic control circuit side, the signal indicating the end of the calculation is repeatedly transmitted every cycle. In addition, the data transmission path 3070 is configured to maintain data on the data transmission path 3070 so as not to execute a new calculation that outputs data to the data transmission path 3070.

Hereinafter, the execution timing of each process related to the execution of the coprocessor arithmetic instruction (xexec instruction) in the arithmetic processing apparatus according to the modification 3 will be described.
The arithmetic unit of the coprocessor has a pipeline configuration, accepts the next coprocessor arithmetic instruction even before writing the previous arithmetic result into the register in the main processor, and performs arithmetic processing with two pipeline stages. In the following description, it is assumed that two cycles are required to execute one arithmetic processing.

FIG. 9 and FIG. 10 are timing chart examples for each process related to the coprocessor operation instruction in the third modification. In FIG. 10, a signal indicating that reception is possible is issued later than the example in FIG. An example of
Both the example of FIG. 9 and the example of FIG. 10 perform the same operations as those described in the first modification with reference to FIG. 6 in cycles C1 to C4.

  In both examples, in the cycle C5, the second half processing 115b of the coprocessor arithmetic processing divided into two stages is executed corresponding to the nth coprocessor arithmetic instruction, and the n + 1th coprocessor arithmetic instruction is corresponded. Then, the first half process 115a is executed. In the second half process 115b of the coprocessor arithmetic process, the arithmetic unit 4200 takes over the result of the first half process 115a, performs further calculations to the end, and outputs the data of the calculation result on the data transmission path 3070. In response to the nth coprocessor operation instruction, the logic control circuit sends a signal indicating the end of the operation including the specification of the register for storing the operation result already held in the FIFO buffer, for example, to the control signal line 4040. To the main processor, and waits for a signal indicating that it can be received via the control signal line 3040.

  In the example of FIG. 9, in cycle C5, a signal indicating that reception is possible corresponding to the nth coprocessor operation instruction is issued. Therefore, in cycle C6, the logic control circuit The operation completion signal corresponding to the coprocessor operation instruction is not repeatedly transmitted, but the operation completion signal corresponding to the (n + 1) th coprocessor operation instruction is transmitted, and the n + 1th coprocessor is supplied to the arithmetic unit 4200. The second half process 115b of the coprocessor arithmetic process corresponding to the arithmetic instruction is performed.

  On the other hand, in the example of FIG. 10, in cycle C5, the signal indicating that reception is possible corresponding to the nth coprocessor operation instruction is not issued. Therefore, in cycle C6, the logic control circuit Repeat sending of a signal indicating the end of the operation corresponding to the nth coprocessor operation instruction, and repeatedly outputting the operation result on the data transmission path 3070 by the operation unit 4200 corresponding to the nth coprocessor operation instruction. In addition, the start of the second half processing 115b of the coprocessor arithmetic processing corresponding to the (n + 1) th coprocessor arithmetic instruction is suppressed. Then, since a signal indicating that the signal can be received is issued in cycle C6, in cycle C7, the logic control circuit corresponds to the (n + 1) th coprocessor operation instruction, for example, an operation already held in the FIFO buffer. A signal indicating the end of the operation including the designation of the register for storing the result is transmitted, and the signal waiting for the reception is sent.

As described above, by performing various processes related to transmission of a signal indicating that reception is possible, the main processor and the coprocessor can appropriately cooperate in the arithmetic processing apparatus according to the third modification.
<Modification 4>
Hereinafter, Modification 4 of the arithmetic processing device 100 according to the basic example will be described.

The arithmetic processing apparatus according to the fourth modification has a functional configuration similar to that of the arithmetic processing apparatus according to the second modification described above, and is different only in that the operating frequency of the coprocessor is twice that of the main processor.
That is, the arithmetic unit of the coprocessor of the arithmetic processing unit according to the modified example 4 does not have a pipeline configuration and does not accept the next coprocessor arithmetic instruction until the previous arithmetic result is written to the register in the main processor. It is.

FIG. 11 is a timing chart for each process related to the coprocessor operation instruction in the fourth modification. This figure illustrates the case where one cycle is required to execute one arithmetic process in the coprocessor. Compared with FIG. 7, the time required for the coprocessor arithmetic processing 115 is different, and thus detailed description is omitted.
Also in the fourth modification, the main processor and the coprocessor can appropriately cooperate with each other by performing various processes related to the transmission of a signal indicating that reception is possible, as in the second modification.
<Modification 5>
Hereinafter, Modification 5 of the arithmetic processing device 100 according to the basic example will be described.

The arithmetic processing apparatus according to the modified example 5 has the same functional configuration as the arithmetic processing apparatus according to the modified example 3 described above, and is different only in that the operating frequency of the coprocessor is twice that of the main processor.
That is, the arithmetic unit of the coprocessor of the arithmetic processing device according to the modified example 5 has a pipeline configuration, and accepts the next coprocessor arithmetic instruction even before writing the previous arithmetic result into the register in the main processor, Arithmetic processing is executed in a pipeline system with two pipeline stages.

FIG. 12 is a timing chart for each process related to the coprocessor operation instruction in the fifth modification. This figure illustrates the case where one cycle is required to execute one arithmetic process in the coprocessor. Compared with FIG. 9, since the time required for the first half process 115a and the second half process 115b of the coprocessor arithmetic process is different, detailed description is omitted.
In this modified example 5, as in the modified example 3, the designation of the register for storing the operation result is held in the FIFO buffer or the like, and various processes relating to the transmission of the signal indicating that reception is possible are performed. The main processor and the coprocessor can operate appropriately.
<Modification 6>
Hereinafter, Modification 6 of the arithmetic processing device 100 according to the basic example will be described.

The arithmetic processing apparatus according to the sixth modification has the same functional configuration as the arithmetic processing apparatus according to the second modification described above, and is different in that the operating frequency of the coprocessor is ½ times that of the main processor.
In order to cope with this difference in operating frequency, the main processor of the arithmetic processing unit according to the modified example 6 further includes a buffer for storing the contents of the destination register designation field of the coprocessor arithmetic instruction. When interpreting the coprocessor operation instruction, the interpretation control circuit stores the operation result storage register specification, which is the contents of the destination register specification field, in the buffer, and then specifies the register that can be read from the buffer. It has a function of suppressing the execution of an arithmetic instruction that uses the designated register as an input until the designation of the register that is included in the signal indicating the completion of the computation from the coprocessor matches.

  That is, when the operating frequency of the coprocessor is lower than the operating frequency of the main processor, based on the coprocessor operation instruction, before the main processor asks the coprocessor to perform the operation and writes the operation result to the register, It is necessary to perform special control so that a general operation instruction that uses the operation result subsequent to the coprocessor operation instruction is not executed. For this reason, in the operation processing device according to the modified example 6, Holds the contents of the destination register specification field in the main processor, stores the processing result of the coprocessor operation instruction in the register specified by it, and then executes the subsequent operation instruction using that register as an input Therefore, a function for temporarily stopping the execution of the subsequent arithmetic instruction is provided.

Hereinafter, each process related to execution of a coprocessor operation instruction (xexec instruction) and a general operation instruction subsequent thereto in the operation processing apparatus according to the modification 6 will be described.
Note that the arithmetic unit of the coprocessor does not have a pipeline configuration, and does not accept the next coprocessor arithmetic instruction until the previous arithmetic result is written to a register in the main processor.

FIG. 13 is a timing chart for each process related to the coprocessor operation instruction in the sixth modification. Here, a case where four cycles are required to execute one arithmetic process in the coprocessor is illustrated.
In cycles C1 to C3, the same operation as that of the arithmetic processing apparatus 100 according to the modification 2 shown in FIG. 7 is performed. However, the instruction interpretation control circuit holds the contents of the destination register designation field of the coprocessor operation instruction in the buffer.

  In cycles C4 to C7, the coprocessor arithmetic processing 115 is executed. The coprocessor operates with two cycles as one unit. First, in the cycle C4 and the cycle C5, the logic control circuit transmits a control signal via the control signal line 4020 in the cycle C4 according to the calculation type acquired via the control signal line 3040, and outputs to the arithmetic unit 4200. An operation using data on the data transmission path 3075 is started, and in cycles C6 and C7, a signal indicating the end of the operation including the designation of the operation result storage register already acquired and held is controlled. The data is sent to the main processor via the signal line 4040, and the computing unit 4200 is made to output the data of the computation result after the computation is completed on the data transmission path 3070 and can be received via the control signal line 3040. Wait for a signal to be sent.

When the main processor receives a signal indicating the end of the calculation, it transmits a signal indicating that it can be received to the coprocessor via the control signal line 3040. Note that the main processor transmits a signal indicating that it can be received over a period of one cycle or more so that the coprocessor having a low operating frequency can recognize the signal indicating that it can be received.
When a signal indicating that reception is possible is received during the cycle C6 and cycle C7, the logic control circuit does not transmit a signal indicating the end of the calculation in the next cycle.

  Although not shown in FIG. 13 in cycle C2, the main processor can interpret the coprocessor arithmetic instruction and perform instruction data acquisition processing 111 for reading the arithmetic instruction subsequent to the instruction. For the subsequent operation instruction, instruction decode processing 112 is performed in cycle C3. However, the register specified for the operation input by the operation instruction matches the register for storing the operation result specified by the preceding coprocessor operation instruction, and the operation result by the coprocessor for the register still exists. When the storage is not performed, the start of the operation by the operation unit 3200 for the subsequent operation instruction is delayed until the storage is performed.

In cycle C8, data transfer processing 116 to the main processor is executed. That is, the instruction interpretation control circuit transmits the control signal to the register bank 3500 via the control signal line 3030 based on the designation of the register for storing the operation result included in the received signal indicating the end of the operation. The data on the data transmission path 3070 is written to the register, and thereafter, the designation of the register held in the buffer is deleted. If the buffer does not contain a register specification, the instruction interpretation control circuit, if there is an operation instruction that has been waiting for the register as an input, performs an operation of the operation instruction by the arithmetic unit 3200. Let it begin.
<Embodiment 2>
Hereinafter, the arithmetic processing apparatus according to the second embodiment of the present invention will be described.

  In the arithmetic processing apparatus according to the second embodiment, the coprocessor in the apparatus executes the calculation in a pipeline manner in the same manner as the first, third, and fifth modifications of the arithmetic processing apparatus according to the first embodiment. In the arithmetic processing apparatus according to the second embodiment, since the handling of the operand of the coprocessor arithmetic instruction (xexec instruction) is different, there is a slight difference in apparatus configuration from the arithmetic processing apparatus according to the first embodiment.

First, the xexec instruction is expressed in mnemonic notation as in the first embodiment.
xexec OPn, dstRn, srcRn
Here, the coprocessor operation instruction, that is, the xexec instruction, is an instruction that requires specification of three operands OPn, dstRn, and srcRn. This OPn is the designation of the type of arithmetic processing in the coprocessor, and srcRn is the designation of the register number on the main processor side that stores the source data used for the coprocessor computation. DstRn is not the result of the operation by the coprocessor, but corresponds to an xexec instruction that precedes the cycle corresponding to the number of pipeline stages of the coprocessor, and the coprocessor has received a request ahead of that cycle. This is the designation of the register number on the main processor side for storing the result of the operation.

When this coprocessor operation instruction is acquired and interpreted, the main processor requests the coprocessor to perform operation by transmitting the source data, which is the contents of the register specified by srcRn, and the type of operation processing to the coprocessor. Also, the result of the operation requested in advance by the coprocessor is received and stored in the register specified by dstRn.
Note that the data structure of the coprocessor operation instruction (xexec instruction) format is the same as that shown in the first embodiment with reference to FIG.

The configuration and operation of the arithmetic processing apparatus according to the second embodiment are basically the same as the configuration and operation of the arithmetic processing apparatus described in the first embodiment (see FIGS. 3 and 4), and are different here. Explain with emphasis on.
When the instruction interpretation control circuit of the main processor interprets the instruction read from the instruction memory and determines that the instruction is the xexec instruction by the instruction identification code, each field for specifying the operand of the instruction (see FIG. 2). The following three processes are performed within one cycle based on the contents of

  First, as the first process, the instruction interpretation control circuit transmits the contents of the instruction code field for the coprocessor, that is, the operation type, to the logic control circuit of the coprocessor via the control signal line 3040. At this time, the contents of the destination register designation field are not transmitted. Therefore, the logic control circuit does not have a configuration for holding the contents of the destination register designation field.

In addition, the instruction interpretation control circuit controls each control signal for causing data to be output on the data transmission path 3075 from one register designated by the contents of the source register designation field as a second process. The signal is supplied to the register bank 3500 through the signal line 3030.
The logic control circuit of the coprocessor performs data transfer control to the register bank 4500 and control for causing the arithmetic unit 4200 to execute specific arithmetic processing according to the designation of the type of arithmetic processing transmitted from the main processor. Even when the arithmetic processing is finished, the main processor is not notified of the signal indicating the end of the computation. Therefore, the control signal line 4040 is omitted. Note that the arithmetic unit 4200 outputs the data as the operation result onto the data transmission path 3070 when the arithmetic processing is completed.

  In addition, as the third process, the instruction interpretation control circuit performs each control for writing data on the data transmission path 3070 to one register designated by the contents of the destination register designation field for the xexec instruction. A signal is supplied to the registers and selectors 3650 to 3665 through a control signal line 3030. As a result, the operation result by the coprocessor corresponding to the xexec instruction interpreted several cycles before the xexec instruction is written into the register of the main processor.

Since the instruction interpretation control circuit only needs to write to one register within one cycle, in particular, a data transfer period in which the operation result of the coprocessor corresponding to the xexec instruction is written to a certain register, and the like. There is no need to adjust the data transfer period in which the operation result of the internal operation unit corresponding to the general operation instruction is written to another register.
Further, the instruction interpretation control circuit does not transmit a signal indicating that reception is possible via the control signal line 3040 as shown in some modified examples of the first embodiment. Therefore, the coprocessor side does not perform control to wait for a signal indicating that it can be received.

  According to the processing method of the arithmetic processing apparatus according to the second embodiment, when the program stored in the instruction memory includes a large number of consecutive coprocessor arithmetic instructions, the main processor also has a coprocessor. Even if the processor does not have a mechanism for holding a plurality of contents of the destination register designation field of each instruction, the process can be appropriately executed.

However, in the program, the register that should store the destination data specified by the operand of a certain coprocessor operation instruction has a coprocessor operation instruction that precedes the coprocessor operation instruction, and the preceding coprocessor operation instruction exists. If the operation result by the coprocessor corresponding to the processor operation instruction is not output on the data transmission path 3070, the effective value is not stored. For example, when the program creator directly describes the program With this in mind, it is necessary to describe the program after understanding the number of cycles required to execute coprocessor operations.
<Embodiment 3>
Hereinafter, an object code generation device according to Embodiment 3 of the present invention will be described.

The object code generation device according to the third embodiment is a so-called compiler realized by a computer and software, and is an object that is a program including an instruction sequence executed by the arithmetic processing device as described in the first embodiment. This is an instruction sequence generation device that generates code based on source code written in a high-level language.
FIG. 14 is a block diagram illustrating a configuration of the object code generation device according to the third embodiment. In the figure, source code 7001 and object code 7002 are also appended.

As shown in the figure, the object code generation device 7000 includes a source code acquisition unit 7010, an instruction code storage unit 7020, and an object code generation unit 7030 in terms of functional aspects.
Here, the source code acquisition unit 7010 has a function of reading and referencing a source code 7001 recorded in, for example, a hard disk device or the like into a memory.

  The instruction code storage unit 7020 stores information related to all instruction codes included in the instruction set of the main processor in the arithmetic processing apparatus serving as the execution environment of the object code, and further, according to the coprocessor arithmetic instruction, the arithmetic type For each coprocessor instruction code, cycle information indicating the number of cycles required for the coprocessor to execute an operation is stored. It should be noted that the information relating to all instruction codes includes information necessary for generating the coprocessor arithmetic instruction in the format shown in FIG. 2, and a function for designating the coprocessor arithmetic instruction in a high-level language. Definition information is also included.

  The object code generation unit 7030 refers to the source code via the source code acquisition unit 7010, and converts each sentence in the source code into an instruction sequence based on information related to the instruction code, as in a general compiler. To do. However, as a process different from a general compiler, the cycle information described above is referred to, the coprocessor operation instruction is interpreted, and then the destination data specified by the coprocessor operation instruction operand is stored in the register. The number of cycles until the calculation result by the processor is reflected is specified, and processing for adjusting the order of the converted instruction sequence is performed so that the register is not used for input of other instructions during the period.

FIG. 15 is a diagram illustrating an example of source code. Here, an example of C language is shown.
Line L51 is a declaration of a variable from data0 to data5, and line L52 indicates that a function predetermined as a function for coprocessor calculation called functionX01 is called with data3 as an argument and the calculation result is set to data0. It is a sentence.
Line L53 is a sentence indicating that the sum of data0 and data3 is set to data4, line L54 is a sentence indicating that the sum of data5 and data1 is set to data5, and line L55 is This is a statement indicating that the sum of data5 and data2 is set to data5.

  FIG. 16 is a diagram illustrating an example of object code generated based on the source code illustrated in FIG. For convenience of explanation, the object code is expressed in mnemonic notation. Here, the add instruction adds the contents of the register specified by the second operand and the contents of the register specified by the third operand, and the result is the register specified by the first operand. It is assumed that the instruction is stored in

  In this example, the object code generation device 7000 assigns the variables data0 to data5 to the registers R0 to R5, respectively. The object code generation device 7000 stores the function X01 in the line L52 of the source code and the instruction code for the coprocessor. It is converted into a coprocessor operation instruction which is OP01, and a row L21 is generated. The xexec instruction in line L21 designates OP01 as the type of arithmetic processing in the coprocessor, designates register R3 as a register on the main processor side that stores source data used for the coprocessor arithmetic, This is an instruction that designates the register R0 as a register on the main processor side for storing the operation result.

  That is, when the object code generation device 7000 finds the functionX01 function in the source code, the object code generation device 7000 replaces it with a xexec instruction whose coprocessor instruction code is OP01. The register allocated to the variable that is the argument of this function is converted to an operand that specifies the register on the main processor side that stores the source data, and the register allocated to the variable that is the return value of the function is Is converted into an operand that specifies a register on the main processor side for storing the result of the operation.

  Here, if the instruction code for the coprocessor is OP01, the number of cycles required for the operation is assumed to be 3 (see FIG. 14). Therefore, an add instruction “add R4, R0, R3” should be generated next to the line L21 as an instruction corresponding to the line L53 of the source code. Since the operation result of the coprocessor operation instruction is not stored in the register R0, the add instruction is generated at the position of the row L24. Instead, instructions corresponding to the statements in the lines L54 and L55 in FIG. 15 are generated at the positions of the lines L22 and L23.

Therefore, according to this object code generation device 7000, the program creator who describes the source code does not need to be aware of the number of cycles required for the coprocessor to complete the operation in response to the coprocessor operation instruction. Appropriate object code can be obtained. In the example of FIG. 15, the sentence in the line L54 and the sentence in the line L55 are eventually executed before the sentence in the line L53. It may not be possible to replace them. In that case, the object code generation device 7000 may add the necessary number of nop instructions after the coprocessor operation instruction and before another operation instruction to be executed using the operation result of the coprocessor operation instruction. , The object code is generated so as not to include an operation instruction that inputs a register in which an operation result corresponding to the coprocessor operation instruction is not stored.
<Supplement>
The embodiments of the arithmetic processing device and the object code generation device according to the present invention have been described above, but the present invention is not limited to the above-described embodiments themselves. That is, the arithmetic processing device or the object code generation device shown in each embodiment may be partially modified as described below.
(1) In the first embodiment, the main processor transmits the contents of the destination register designation field of the coprocessor operation instruction to the coprocessor, holds the content on the coprocessor, and ends the operation when the operation ends. However, the main processor does not transmit the contents of the destination register designation field of the coprocessor operation instruction, and stores and holds the contents of the coprocessor. When the operation result corresponding to the operation instruction is returned from the coprocessor and a signal indicating the end of the operation is received, the returned operation result is stored in a register designated by the content stored and held by itself. Also good. The contents of the destination register designation field may be stored in a FIFO buffer, for example.

  Furthermore, a method may be used in which a signal indicating the end of the operation is not transmitted from the coprocessor side. In this case, the instruction interpretation control circuit of the main processor displays the operation result corresponding to the coprocessor operation instruction as a coprocessor. The timing until the return is returned is stored in advance according to the operation type, and by counting the number of cycles, the timing for acquiring the returned operation result is detected, and the operation result is stored and held by itself. It may be stored in a register specified by the contents. As a control method related to the count, an appropriate count value is set according to the operation type when the coprocessor operation instruction is interpreted, and one counter value is subtracted every time one cycle elapses. Then, the data on the data transmission path 3070 may be controlled to be written in the register.

In addition, after interpreting the coprocessor operation instruction, the number of cycles in which the operation result by the coprocessor appears on the data transmission path 3070 is associated with the operation type that is the content of the coprocessor instruction code field of the coprocessor operation instruction. In order to store the instruction in the instruction interpretation control circuit in advance, the items to be considered in the design stage are the number of cycles until the register data in the main processor reaches the arithmetic unit 4200 of the coprocessor and the number of operations for each operation type. The number of cycles required for the calculation performed by the processor 4200 of the processor and the number of cycles in which the calculation result reaches the register bank of the main processor from the calculator 4200 of the coprocessor.
(2) In the modification of the first embodiment, the case where the operating frequency of the coprocessor is twice the operating frequency of the main processor has been described. However, the operating frequency is not limited to twice. In addition, although the case of ½ times has been described, it is not limited to ½ times, and may be ¼ times, for example.
(3) In each arithmetic processing unit according to the first and second embodiments, the instruction interpretation control circuit transmits the operation type that is the content of the coprocessor instruction code field of the coprocessor operation instruction to the logic control circuit of the coprocessor. The interpretation is performed by the logic control circuit of the coprocessor, but the sharing of the interpretation is not limited to this. For example, the instruction interpretation control circuit interprets the contents of the instruction code field for the coprocessor. Thus, the operation may be specified and a signal indicating that may be transmitted to the logic control circuit, and the logic control circuit may cause the calculator 4200 to execute the operation specified by the designated signal.
(4) In the coprocessor operation instructions shown in the first to third embodiments, only one register for storing source data and one register for storing destination data can be specified, but a plurality of these can be specified. You may do it. In this case, it is preferable to provide a plurality of data transmission paths from the main processor to the coprocessor and a data transmission path from the coprocessor to the main processor in the arithmetic processing unit, and control data transfer accordingly.
(5) Each process related to the coprocessor operation instruction described in Embodiment 1 with reference to FIGS. 5 to 13, for example, an instruction data acquisition process, an instruction decode process, a data transfer process to the coprocessor, etc. For example, the instruction data acquisition process and the instruction decode process may be executed in one cycle.
(6) In each arithmetic processing unit according to the first and second embodiments, the coprocessor does not directly access the data in the instruction memory 5000 or the data memory 6000, but can be accessed by providing a dedicated bus or instruction. You may comprise.
(7) In each arithmetic processing unit according to the first and second embodiments, the register for storing the source data and the register for storing the destination data specified by the coprocessor arithmetic instruction are both registers on the main processor side. The arithmetic processing unit has a plurality of coprocessors, and a register of another coprocessor B is used as a register for storing source data and destination data specified in a coprocessor arithmetic instruction for causing a certain coprocessor A to perform arithmetic operations. May be specified. In this case, the control contents to the register bank 3500 performed by the instruction interpretation control circuit of the main processor corresponding to the coprocessor operation instruction may be applied as the control contents to the register bank of the coprocessor B as it is. The control of the register bank of the coprocessor B may be executed by the logic control circuit in the coprocessor B in response to an instruction from the instruction interpretation control circuit.
(8) In some variations of the first embodiment, when the main processor is ready to receive the calculation result of the coprocessor, it sends a signal indicating that it can be received. Instead of this signal, the write completion signal is sent immediately after the coprocessor operation result is written to the register. On the coprocessor side, the calculation is completed until the write completion signal is received. You may make it continue the output on the data transmission path 3070 of a result.
(9) The arithmetic processing unit including the main processor and the coprocessor shown in the first and second embodiments may be configured on one semiconductor chip as a semiconductor integrated circuit, and further includes an instruction memory. May be included, and a data memory may be further included.
(10) In the third embodiment, the object code generation device is a so-called compiler that generates object code based on source code described in a high-level language such as C language. For example, a so-called assembler or assembler optimizer may be used, and the source code may be, for example, a code including an instruction sequence corresponding to the instruction set of the arithmetic processing apparatus described in the first embodiment, or an object code generation apparatus. Changes the order of the codes so that it does not include an operation instruction that inputs a register that does not store the operation result corresponding to the coprocessor operation instruction, that is, the operation result of the coprocessor operation instruction. The operation result of the coprocessor operation instruction is registered in the operation instruction to be used. The object code formed by staggered after the number of cycles by the coprocessor calculation instruction that should be stored, may be generated.

In addition, as a method for generating a program that can be executed by the arithmetic processing unit shown in the second embodiment and includes a coprocessor arithmetic instruction, the program creator directly describes the program in addition to describing the program. The object code generation apparatus shown in the third embodiment may be generated by a function in which the function of changing the instruction order in relation to the coprocessor operation instruction is omitted.
(11) Of the information stored in the instruction code storage unit 7020 of the object code generation device shown in the third embodiment, the cycle information may be switched to the content corresponding to another coprocessor. . Thus, the object code generation device can generate an object code corresponding to a case where the coprocessor in the arithmetic processing device is switched to another one.
(12) When the object code generation device shown in the third embodiment generates an object code including a coprocessor operation instruction, a register for storing source data designated by the coprocessor operation instruction and destination data are stored. The registers to be stored are all registers on the main processor side, but are not limited to the registers on the main processor side, and to generate object code for an arithmetic processing unit having a plurality of coprocessors Alternatively, a coprocessor operation instruction designating a register of another coprocessor B may be output as a register for storing source data and destination data of an operation for causing a certain coprocessor A to perform an operation.
(13) A computer program defining a process for generating an object code based on information stored in an instruction code storage unit and a source code, which is executed in the object code generation device shown in the third embodiment. It can also be recorded on a recording medium or distributed and distributed via various communication channels. Examples of such a recording medium include a flash memory, an IC card, an optical disk, a flexible disk, and a ROM. The computer program distributed and distributed is used by being stored in a memory or the like that can be read by the computer, and the computer executes the computer program to execute each of the object code generation apparatuses described in the third embodiment. The function will be realized.
(14) The coprocessors described in the first and second embodiments include a plurality of element calculators and selectors in the calculator 4200. The element calculator performs operations such as addition, subtraction, and multiplication, and the coprocessor The type of operation may be dynamically changed by setting an instruction or a register. In addition, the element arithmetic units are connected to each other, and the operation results of the registers in the main processor or the coprocessor and other element arithmetic units can be input to the element arithmetic unit via the selector. This setting may be used to dynamically change the input destination.
(15) The arithmetic processing units described in the first and second embodiments may be constituted by a plurality of coprocessors, and the contents of the main processor registers are used as source data input to the coprocessor arithmetic unit 4200. The register contents of the local coprocessor or another coprocessor may be used, and the storage location of the source data as the input destination is dynamically determined by the coprocessor instruction or register setting. It may be possible to change to

  In addition, the arithmetic unit 4200 of the coprocessor may perform operations such as addition, subtraction, and multiplication, and the operation of the arithmetic unit 4200 may be dynamically changed by setting the coprocessor instruction or register. Further, the coprocessor logic control circuit 4100 may be configured to dynamically change the format or the like of the coprocessor operation instruction by setting a special instruction or a register. In other words, the bit allocation mapping of the instruction code, input destination, output destination, operation, etc. may be dynamically changed.

  The arithmetic processing apparatus according to the present invention is installed and used in devices capable of executing programs such as various computers and various home appliances.

It is a figure which illustrates a part of assembler program containing a xexec instruction. It is a figure which shows the format of a coprocessor arithmetic instruction (xexec instruction). 1 is a block diagram illustrating a configuration of an arithmetic processing device according to a first embodiment. 3 is a configuration diagram showing a configuration of a register bank 3500 in detail. FIG. It is a timing chart about each processing concerning a coprocessor operation instruction. 10 is a timing chart for each process related to a coprocessor operation instruction in Modification 1; 10 is a timing chart for each process related to a coprocessor operation instruction in Modification 2; It is a timing chart about each process which concerns on the coprocessor arithmetic instruction in the modification 2, and shows the example when the signal which shows that it can receive is issued with a delay. 10 is a timing chart for each process related to a coprocessor operation instruction in Modification 3. It is a timing chart about each process which concerns on the coprocessor arithmetic instruction in the modification 3, and shows the example when the signal which shows that it can receive is issued late. 10 is a timing chart for each process related to a coprocessor operation instruction in Modification 4; 16 is a timing chart for each process related to a coprocessor operation instruction in Modification 5. 16 is a timing chart for each process related to a coprocessor operation instruction in Modification 6; FIG. 10 is a block diagram illustrating a configuration of an object code generation device according to a third embodiment. It is a figure which shows the example of a source code. It is a figure which shows the example of the object code produced | generated based on the source code illustrated in FIG. It is a figure which shows the example of the program which makes a coprocessor perform an operation.

Explanation of symbols

21 Instruction identification code field 22 Coprocessor instruction code field 23 Destination register designation field 24 Source register designation field 100 Arithmetic processing unit 3000 Main processor 3010, 3020, 3030, 3040, 3050, 4020, 4040 Control signal lines 3060, 3065, 3070, 3075, 3080, 3085, 4060, 4065, 5010 Data transmission path 3100 Instruction interpretation control circuit 3200 Arithmetic unit 3500, 4500 Register bank 3650, 3651, 3665, 3670, 3680 Selector 4000 Coprocessor 4100 Logic control circuit 4200 Arithmetic unit 5000 Instruction memory 6000 Data memory 7000 Object code generation device 7010 Source code acquisition unit 70 0 instruction code storage unit 7030 object code generator

Claims (12)

An arithmetic processing device comprising a main processor and a coprocessor,
The main processor has an instruction interpretation control unit that sequentially interprets instructions and performs control based on the instructions,
The instruction interpretation control unit should store a type of arithmetic processing to be executed by the coprocessor, a first storage area in which a target of the arithmetic processing is stored, and a result of arithmetic processing performed by the coprocessor By interpreting the processing request instruction designating the second storage area, the coprocessor is caused to execute the type of arithmetic processing with the contents of the first storage area as the arithmetic processing target, and is further performed by the coprocessor. An arithmetic processing device that performs control to write a result of a certain arithmetic processing into the second storage area. The main processor has a plurality of registers for storing an operation target or a result when performing an operation based on an operation instruction;
The processing request instruction identifies first data for identifying one of the plurality of registers as specifying the first storage area, and identifies any of the plurality of registers as specifying the second storage area. Second data,
The instruction interpretation control unit causes the coprocessor to execute the type of arithmetic processing specified by the processing request instruction, with the contents of the register identified by the first data included in the processing request instruction as an arithmetic processing target. The arithmetic processing apparatus according to claim 1, further comprising a control for writing a result of a certain arithmetic processing performed by the coprocessor to a register identified by the second data included in the processing request instruction. The processing request instruction should be executed by the coprocessor as a code format in addition to a field for storing an instruction identification code for identifying the processing request instruction from other instructions in the instruction group executable by the main processor. Each including a field for storing a coprocessor instruction code indicating a type of arithmetic processing, a field for storing first data, and a field for storing second data;
The instruction interpretation control unit controls to send a coprocessor instruction code included in a processing request instruction to the coprocessor, and is a source that is a content of a register identified by first data included in the processing request instruction Control to send data to the coprocessor, and obtain result data that is a result of a certain arithmetic processing sent from the coprocessor, and is identified by the second data included in the processing request instruction. Control to write to the register
The coprocessor interprets a coprocessor instruction code sent from the main processor, obtains source data sent from the main processor, and makes it an arithmetic processing target, which is indicated by the coprocessor instruction code. The arithmetic processing apparatus according to claim 2, further comprising: executing a certain type of arithmetic processing and sending result data as a result of the arithmetic processing to the main processor. When the instruction interpretation control unit sends the coprocessor instruction code included in the processing request instruction to the coprocessor, the instruction interpretation control unit sends the second data included in the processing request instruction to the coprocessor together with the coprocessor instruction code. Send out,
When the coprocessor sends to the main processor result data that is a result of executing the type of arithmetic processing indicated by the coprocessor instruction code sent from the main processor, the coprocessor instruction Sending the second data sent from the main processor together with the code to the main processor together with the result data;
The instruction interpretation control unit obtains result data and second data sent together from the coprocessor, and controls to write the result data in a register identified by the second data. The arithmetic processing apparatus according to claim 3. The result data for controlling the instruction interpretation control unit to write to the register identified by the second data included in the processing request instruction is the result of the arithmetic processing specified by the processing request instruction sent from the coprocessor. Yes,
The instruction interpretation control unit stores in advance time information indicating an operation processing time in association with each of the operation processes, the instruction code for the coprocessor included in the process request instruction, the source data, Is sent from the coprocessor when the computation processing time indicated by the time information stored corresponding to the type of computation processing indicated by the instruction code for the coprocessor has elapsed. 4. The arithmetic processing unit according to claim 3, wherein the result data is controlled to be written in a register identified by the second data included in the processing request instruction. 5. The instruction interpretation control unit controls to send a predetermined signal to the coprocessor when result data sent from the coprocessor is written to a register identified by second data included in the processing request instruction. And
The coprocessor continues sending the result data until it detects that the predetermined signal is sent by the main processor, and stops sending the result data after the detection. The arithmetic processing unit described. The coprocessor outputs the result data after the lapse of the same time from the start of the arithmetic processing for various types of arithmetic processing specified by the instruction code for the coprocessor,
The result data that the command interpretation control unit controls to write to the register identified by the second data included in the processing request command is another process that is sent from the coprocessor and interpreted prior to the processing request command. It is the result data of the arithmetic processing specified by the request instruction,
The instruction interpretation control unit sends the coprocessor instruction code included in the processing request instruction together with the second data to the coprocessor and then interprets another instruction following the processing request instruction. In addition, the coprocessor is controlled to write the result data sent as a result of performing the arithmetic processing designated by the processing request instruction preceding the processing request command to the register identified by the second data. The arithmetic processing device according to claim 3. The control performed by the instruction interpretation control unit, which writes to the register identified by the second data included in the processing request instruction, causes the coprocessor to execute the type of arithmetic processing specified by the processing request instruction. The arithmetic processing unit according to claim 2, wherein the result is control to write the result in the register. The arithmetic processing unit includes first and second coprocessors,
The second coprocessor has a plurality of registers,
The processing request instruction specifies a type of arithmetic processing to be executed by the first coprocessor, and identifies a first storage area as a first storage area that identifies one of a plurality of registers of the second coprocessor. Data and second data identifying any one of the plurality of registers of the second coprocessor as specifying the second storage area;
The instruction interpretation control unit designates the contents of the register in the second coprocessor identified by the first data included in the processing request instruction to the first coprocessor as an operation processing target by the processing request instruction. In the second coprocessor identified by the second data included in the processing request instruction, and the result of the certain arithmetic processing performed by the first coprocessor is further executed. The arithmetic processing unit according to claim 1, wherein control for writing to the register is performed. An instruction sequence generator for generating a machine language instruction sequence to be executed by a main processor provided with a coprocessor in an arithmetic processing unit of claim 1 based on input data,
Storage means;
Input data acquisition means for acquiring input data;
Based on the input data, the type of arithmetic processing to be executed by the coprocessor, a first storage area outside the coprocessor in which the target of the arithmetic processing is stored, and the coprocessor performs arithmetic processing. Generating a command sequence in machine language including a processing request command for designating a second storage area outside the coprocessor in which the result of the operation should be stored, and recording the command sequence in the storage means An instruction sequence generation device. The processing request instruction generated by the instruction sequence generation means is a code format of a field for storing an instruction identification code for identifying the processing request instruction from other instructions in an instruction group executable by the main processor. In addition, a field for storing a coprocessor instruction code indicating the type of arithmetic processing to be executed by the coprocessor, and one of a plurality of registers included in the main processor as a first storage area are designated. Including a field for storing first data to be identified, and a field for storing second data for identifying any one of the plurality of registers of the main processor as a second storage area. The instruction sequence generation device according to claim 10. The instruction sequence generation device further includes calculation time management means for preliminarily storing time information indicating calculation processing time in association with various types of calculation processing executable by the coprocessor,
The instruction sequence generation means is configured to place an operation instruction whose operation target is the content of the register of the main processor identified by the second data included in the generated process request instruction at a position subsequent to the process request instruction in the instruction sequence. When generating, specify the processing time for the type of calculation processing indicated by the coprocessor instruction code included in the processing request instruction based on the time information stored by the calculation time management means, 12. The instruction sequence according to claim 11, wherein the instruction sequence is generated by placing the operation instruction at a position spaced from the processing request instruction by an interval equal to or more than the number of instructions corresponding to the specified operation processing time. Column generator.

Images