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JP2006019465A - Semiconductor package and its manufacturing method - Google Patents

Semiconductor package and its manufacturing method Download PDF

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Publication number
JP2006019465A
JP2006019465A JP2004195146A JP2004195146A JP2006019465A JP 2006019465 A JP2006019465 A JP 2006019465A JP 2004195146 A JP2004195146 A JP 2004195146A JP 2004195146 A JP2004195146 A JP 2004195146A JP 2006019465 A JP2006019465 A JP 2006019465A
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package
external terminal
solder
semiconductor package
lead frame
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Daisuke Suzuki
大介 鈴木
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Mitsui Chemicals Inc
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Mitsui Chemicals Inc
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor package which can easily form a solder fillet in a surface mounting type package and can raise the solder adhering strength of a substrate to the package, and to provide a method of manufacturing the same. <P>SOLUTION: The semiconductor package 1 is a semiconductor package which seals leads except a terminal. The leads each has an external terminal 3 extended in parallel with a substrate surface to be mounted. The external terminal has a recess 4 passing the upper surface and the lower surface of the external terminal without including the side of a section in the section of the extending direction tip end. The recess is plated. The method of manufacturing the semiconductor package includes an inserting step of previously inserting a lead frame having a through hole into a mold at the external terminal of the lead, a molding step of injecting a resin and molding it, a plating step of plating the lead frame exposed part, and a cutting step of cutting the lead frame. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、リードが端子部を残して封止されている半導体パッケージおよびその製造方法に関する。さらに詳しくは半田フィレットを形成しやすくした表面実装型半導体パッケージおよびその製造方法に関する。   The present invention relates to a semiconductor package in which leads are sealed leaving a terminal portion and a method for manufacturing the same. More particularly, the present invention relates to a surface-mount type semiconductor package that can easily form a solder fillet and a method for manufacturing the same.

半導体素子は、周囲の温度や湿度の変化、あるいは微細なごみや埃に大きく影響され、その特性を劣化させてしまい、また機械的振動や衝撃を受けることにより破損しやすいことが知られている。これら外的要因から半導体素子を保護するために、セラミックス製の箱や樹脂で封止し、パッケージとして使用に供されていることは良く知られている。   It is known that a semiconductor element is greatly affected by changes in ambient temperature and humidity, or fine dust and dust, and its characteristics are deteriorated, and it is easily damaged due to mechanical vibration and impact. In order to protect the semiconductor element from these external factors, it is well known that the semiconductor element is sealed with a ceramic box or resin and used as a package.

中でも、CCD、CMOSを代表とする固体撮像素子や、LD、PDなどのレーザ素子、フォトダイオード素子などは、パッケージ外部と光の通路が必要であり、一般的なLSI素子のように、周囲を樹脂やセラミックスで封止することができない。これらの半導体素子は、一般に一方が開放された中空タイプのパッケージに実装され、その後開放部をガラスなど透明材料で封止することにより、パッケージングされている。   Above all, solid-state image sensors such as CCD and CMOS, laser elements such as LD and PD, and photodiode elements need a light path with the outside of the package. It cannot be sealed with resin or ceramics. These semiconductor elements are generally packaged by being mounted in a hollow type package in which one side is opened, and then the open part is sealed with a transparent material such as glass.

一方、近年では電子機器の小型化、薄型化が求められており、前述の封止タイプの半導体パッケージや中空タイプのパッケージにも、薄型化、小型化が求められる。その解決策の一つとして、外部端子をパッケージ底面から基板と平行方向に出す、表面実装型パッケージが実用化されている。このタイプのパッケージとしては、SON(Small Outline Non−Lead Package)や、QFN(Quad Flat Non−Lead Package)などが知られる。   On the other hand, in recent years, electronic devices are required to be reduced in size and thickness, and the above-described sealed type semiconductor package and hollow type package are also required to be reduced in thickness and size. As one of the solutions, a surface mount type package in which external terminals are provided in a direction parallel to the substrate from the bottom surface of the package has been put into practical use. As this type of package, SON (Small Outline Non-Lead Package), QFN (Quad Flat Non-Lead Package), and the like are known.

表面実装型パッケージは、DIP(Dual Inline Package)やSOP(Small Outline Package)と異なり実装する際の「足」(基板に垂直方向の外部端子)が無いため、手付け半田による実装は困難であり、一般的にフロー半田付け、リフロー半田付けの手法がとられることが多い。   Unlike the DIP (Dual Inline Package) and SOP (Small Outline Package), the surface mount type package does not have "foot" (external terminal in the direction perpendicular to the board) when mounting, so mounting by hand solder is difficult. In general, flow soldering and reflow soldering are often used.

例えばリフロー半田付けの場合、外部端子の下部だけではなく、端子の周辺のスペースにも半田が盛られるのが通常である。この端子の周辺に盛られた半田は半田フィレットと呼ばれ、半田接着面積を大きくし実装強度を高める働きをする。半田フィレットを形成させるため、半田濡れ性の高いめっき(金めっきなど)を、端子下部および側面に施すことで、該当部をより強固に半田と接着するよう工夫している。(非特許文献1参照)
樹脂製の半導体パッケージは、セラミックス製のパッケージと比較して、その製法上、外部端子の切断面には金めっきを施すことが出来ない。そのため、端子切断面には半田が乗らないため、この半田フィレットが形成しづらいという問題があった。
For example, in the case of reflow soldering, solder is usually deposited not only in the lower part of the external terminal but also in the space around the terminal. The solder piled up around the terminals is called a solder fillet and functions to increase the solder bonding area and the mounting strength. In order to form a solder fillet, a high solder wettability plating (gold plating or the like) is applied to the lower and side surfaces of the terminal so that the corresponding part is more firmly bonded to the solder. (See Non-Patent Document 1)
Compared with a ceramic package, a resin semiconductor package cannot be gold-plated on a cut surface of an external terminal because of its manufacturing method. Therefore, there is a problem that it is difficult to form the solder fillet because the solder does not get on the terminal cut surface.

さて、CCD、CMOSを代表とする固体撮像素子のパッケージの場合、これまではチップ自体やカラーフィルターなどの耐熱性の問題があり、パッケージ全体を加熱するフロー半田、リフロー半田実装は不具合を発生させることがあり、手付け半田実装が多く行われていた。しかし近年の薄型化要求に伴い、薄型の樹脂製SON、QFNを用いて固体撮像素子のパッケージを作製しようとした場合、手付け半田は困難であるため、リフロー半田付けによる実装方式、特に、素子にダメージを与えないよう低温半田を用いたリフロー実装方式が用いられようとしている。   Now, in the case of a solid-state imaging device package such as a CCD or CMOS, there has been a problem of heat resistance such as the chip itself or a color filter, and the flow solder and reflow solder mounting that heats the whole package causes a problem. In many cases, manual solder mounting was performed. However, in response to the recent demand for thinning, when trying to fabricate a solid-state imaging device package using thin resin SON, QFN, manual soldering is difficult, so mounting method by reflow soldering, especially for the device A reflow mounting method using low-temperature solder is being used so as not to cause damage.

このような低温半田を用いると、通常の半田と比較して半田接着強度が劣るため、半田フィレットが形成できない樹脂製のパッケージは、基板とパッケージとの接着強度が低くなってしまうという問題がある。さらに、CCD素子やカラーフィルターなども改良され、耐熱性が高まってきたこともあり、通常のリフロー半田実装(温度230℃程度で実装)や、将来的には低環境負荷である鉛フリー半田実装(温度260℃程度で実装)も行われようとしており、半田フィレットの形成で接着強度を高めることが課題となっている。   When such a low-temperature solder is used, since the solder adhesive strength is inferior to that of normal solder, a resin package in which a solder fillet cannot be formed has a problem that the adhesive strength between the substrate and the package is low. . In addition, CCD elements and color filters have been improved, and heat resistance has increased, so normal reflow solder mounting (mounting at a temperature of about 230 ° C) and lead-free solder mounting, which will be a low environmental load in the future (Mounting at a temperature of about 260 ° C.) is also being performed, and it is an issue to increase the adhesive strength by forming a solder fillet.

この課題に対し、特許文献1や特許文献2においては、半田フィレットの広がりを大きくするような提案がなされている。特許文献1ではアウターリードの厚みを増やすことで半田フィレットを広げようとしているが、パッケージ全体が厚くなったり、厚さの違うリードフレームを準備する必要があったりするため、どのパッケージにも適応できるわけではないという問題がある。また特許文献2では、アウターリードを斜め方向にカットする提案であるが、薄くカットされた部分が強度的に弱く曲がるという不具合が発生する可能性があったり、カット機器に特殊なものが必要となったりするため、現実的ではない。   In order to solve this problem, Patent Document 1 and Patent Document 2 make proposals to increase the spread of solder fillets. In Patent Document 1, an attempt is made to widen the solder fillet by increasing the thickness of the outer lead. However, since the entire package becomes thicker or a lead frame having a different thickness needs to be prepared, it can be applied to any package. There is a problem that does not mean. Patent Document 2 proposes to cut the outer lead in an oblique direction. However, there is a possibility that a thinly cut portion may be bent weakly in strength, or a special cutting device is required. Because it becomes, it is not realistic.

田中和吉著,「はんだ付け技術」,総合電子出版社,1974年7月20日初版Yoshikazu Tanaka, “Soldering Technology”, General Electronic Publishing Company, July 20, 1974, first edition 特開平10−270628号公報Japanese Patent Laid-Open No. 10-270628 特開2004−87998号公報JP 2004-87798 A

本発明の課題は表面実装型パッケージにおいて、半田フィレットを形成しやすくして、基板とパッケージの半田接着強度を高めることのできる半導体パッケージおよびその製造方法を提供しようとするものである。   SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor package and a method for manufacturing the same that can easily form a solder fillet in a surface-mount package and can increase the solder bond strength between the substrate and the package.

本発明の半導体パッケージは、リードが端子部を残して封止されている半導体パッケージであって、該リードは、実装する基板面に平行に延出する外部端子を有し、該外部端子はその延出方向先端部の断面に、断面の側辺を含むことなく外部端子の上面と下面を貫く凹部を有し、該凹部にめっきが施されていることを特徴とする。   The semiconductor package of the present invention is a semiconductor package in which leads are sealed leaving a terminal portion, and the leads have external terminals extending in parallel to a substrate surface to be mounted. The cross section of the front end portion in the extending direction has a concave portion penetrating the upper surface and the lower surface of the external terminal without including the side of the cross section, and the concave portion is plated.

本発明の半導体パッケージの製造方法は、リードが端子部を残して封止されている半導体パッケージの製造において、
リードの外部端子部に、予め貫通孔を有するリードフレームを金型にインサートするインサート工程、
樹脂を注入して成形するモールド工程、
リードフレーム露出部にめっきを施すめっき工程および
外部端子部の貫通孔を横断してリードフレームを切断する切断工程
を含むことを特徴とする。
The method of manufacturing a semiconductor package according to the present invention, in manufacturing a semiconductor package in which leads are sealed leaving a terminal portion,
Insert step of inserting a lead frame having a through hole in advance into a die in an external terminal portion of the lead,
A molding process in which resin is injected and molded;
It includes a plating step of plating the exposed portion of the lead frame and a cutting step of cutting the lead frame across the through hole of the external terminal portion.

本発明によれば、表面実装型半導体パッケージを基板に実装するにあたり、外部端子の先端部の断面にめっきが施された凹部を有しているため、半田実装する際に凹部内面が半田で濡れやすく、外部端子の先端部に半田フィレットの形成が容易になる。これにより、例えば低温半田を用いた実装においても、基板との接着強度に優れた実装が可能となる。   According to the present invention, when mounting a surface-mount type semiconductor package on a substrate, the inner surface of the recess has a recessed portion plated with solder, so that the inner surface of the recessed portion is wetted by solder when soldered. This facilitates the formation of a solder fillet at the tip of the external terminal. As a result, for example, even when mounting using low-temperature solder, mounting with excellent adhesion strength to the substrate is possible.

本発明の半導体パッケージは、封止材例えば樹脂組成物と導電性のリードからなり、基板との電気的接点となる外部端子が該リードから作製されており、該外部端子が実装する基板面に平行方向に延出されており、その先端部の断面には、断面の側辺を含むことなく外部端子の上面と下面を貫く、上面から見て半楕円形状、半円形状、U字形状、四角形状、三角形状、等の凹部を有し、外部端子の上面、下面、側面と該凹部壁面にめっきが施されていることを特徴とする、半導体パッケージである。   The semiconductor package of the present invention is made of a sealing material such as a resin composition and a conductive lead, and an external terminal serving as an electrical contact with the substrate is produced from the lead, and the external terminal is mounted on the surface of the substrate to be mounted. It extends in the parallel direction, and the cross section of the tip part penetrates the upper surface and the lower surface of the external terminal without including the side of the cross section, as viewed from the upper surface, a semi-elliptical shape, a semicircular shape, a U-shape, A semiconductor package having concave portions such as a quadrangular shape and a triangular shape, wherein the upper surface, the lower surface, and the side surfaces of the external terminals and the wall surfaces of the concave portions are plated.

半導体パッケージを封止する樹脂材料としては、エポキシ樹脂とフェノール樹脂に充填剤としてシリカを混練させた、いわゆる半導体封止材を好適に用いることができ、具体的には、三井化学製EPOXシリーズや、住友ベークライト製スミコンEMEシリーズなどが挙げられる。言うまでも無くこれは一例であり、リードフレームとの一体成形が可能であれば、樹脂の種類は問わないため、耐湿性の用途に応じて、必要な樹脂を用いることが出来る。   As a resin material for sealing a semiconductor package, a so-called semiconductor sealing material obtained by kneading silica as a filler in an epoxy resin and a phenol resin can be preferably used. And Sumitomo Bakelite's Sumicon EME series. Needless to say, this is only an example, and any type of resin can be used depending on the intended use of moisture resistance as long as it can be integrally formed with the lead frame.

本発明によるパッケージの一例の概略平面図を図1に示す。この例は、内部端子2と外部端子3を有する中空パッケージ1であり、外部端子先端の凹部4の壁面にめっきが施されている。そのために、半田実装を行う際、この部分も半田で濡れるため、凹部は基板と半田接続される。このために、従来は外部端子先端部断面には半田がつかなかったが、本手法により半田フィレットを形成させることが出来る。   A schematic plan view of an example of a package according to the present invention is shown in FIG. This example is a hollow package 1 having an internal terminal 2 and an external terminal 3, and the wall surface of the recess 4 at the tip of the external terminal is plated. Therefore, when solder mounting is performed, this portion is also wetted by the solder, so that the concave portion is soldered to the substrate. For this reason, conventionally, solder has not been applied to the cross section of the tip of the external terminal, but a solder fillet can be formed by this method.

ここで、凹部に施されるめっきの種類としては、用いるリードフレーム金属種類、半田の種類などにより、適宜選択することが出来る。通常、リードフレームには42アロイ、銅合金を用いることが多く、スズ/鉛系の半田で実装されることが多いため、めっきとしては下地ニッケルめっき、表面金めっきが選択される。また別途、半田めっき、パラジウムめっきなど用途に応じて採用することが可能である。めっき厚みは用途に応じて選択されるが、一般的には、下地がニッケルめっきの場合、ニッケル層が1μm〜20μm、好ましくは3μm〜10μm、表面の金めっきは0.1μm〜1μm、好ましくは0.1μm〜0.5μmが選択される。   Here, the type of plating applied to the recess can be appropriately selected depending on the type of lead frame metal used, the type of solder, and the like. Usually, a 42 alloy and a copper alloy are often used for the lead frame, and since it is often mounted with a tin / lead solder, a base nickel plating or a surface gold plating is selected as the plating. Separately, it can be employed according to applications such as solder plating and palladium plating. The plating thickness is selected according to the application. In general, when the base is nickel plating, the nickel layer is 1 μm to 20 μm, preferably 3 μm to 10 μm, and the gold plating on the surface is 0.1 μm to 1 μm, preferably 0.1 μm to 0.5 μm is selected.

本発明の半導体パッケージの製造方法としては、リードが端子部を残して封止されている半導体パッケージの製造に用いるリードフレームであって、外部端子に相当する部位の、リードフレームの切断位置に、予め円形状、楕円形状、長穴形状、菱形状、四角形状等の貫通孔を有するリードフレームを用いて、少なくとも
該リードフレームを金型にインサートするインサート工程、
樹脂を注入して成形するモールド工程、
リードフレーム露出部にめっきを施すめっき工程および
外部端子部の貫通孔を横断してリードフレームを切断する切断工程
を含むことを特徴とする。
As a method for manufacturing a semiconductor package of the present invention, a lead frame used for manufacturing a semiconductor package in which leads are sealed leaving a terminal portion, at a position corresponding to an external terminal, at a cutting position of the lead frame, Insert step of inserting at least the lead frame into a mold using a lead frame having a through-hole such as a circular shape, an elliptical shape, a long hole shape, a rhombus shape, a square shape in advance,
A molding process in which resin is injected and molded;
It includes a plating step of plating the exposed portion of the lead frame and a cutting step of cutting the lead frame across the through hole of the external terminal portion.

通常の表面実装型パッケージの製造方法では、めっき工程の後の切断工程で外部端子とリードフレームが切り離されるので、この切断面にはめっきが施されていないので半田フィレットが形成されにくい。一方、挿入型のパッケージ(例えば、DIPやSOP)では、「足」を有するために、切断後、めっきを施されたこの足で接合されるため半田フィレットが形成できる。   In an ordinary surface mount package manufacturing method, the external terminals and the lead frame are separated in a cutting step after the plating step. Therefore, since the cut surface is not plated, it is difficult to form a solder fillet. On the other hand, since the insert type package (for example, DIP or SOP) has “foot”, the soldered fillet can be formed because it is joined with the plated foot after cutting.

そこで、本発明の製造方法によると、外部端子先端面には凹部を設けることができ、この壁面にめっきを施すことが可能となる。図2に、パッケージを個片化する前の、リードフレームと接続されている状態の、本発明の製造方法で得られるパッケージの一例の概略平面図を示す。この例は、内部端子2と切断前の外部端子5を有する中空パッケージ1であり、外部端子の切断部7に貫通孔6が形成されており、この貫通孔の内壁面にめっきが施されることにより、切断後の外部端子先端部にめっきが施された凹部が形成される。   Therefore, according to the manufacturing method of the present invention, a concave portion can be provided on the end surface of the external terminal, and plating can be applied to this wall surface. FIG. 2 shows a schematic plan view of an example of a package obtained by the manufacturing method of the present invention in a state where it is connected to a lead frame before the package is singulated. This example is a hollow package 1 having an internal terminal 2 and an external terminal 5 before cutting, and a through hole 6 is formed in a cut portion 7 of the external terminal, and the inner wall surface of the through hole is plated. Thereby, the recessed part by which plating was given to the external terminal front-end | tip part after a cutting | disconnection is formed.

また、本発明は半導体実装用の中空パッケージについて述べたが、言うまでも無く同様の形状を持つパッケージであり、基板に半田実装を行うパッケージであれば、他のパッケージにも適応することが可能である。例えば、DRAMを代表とするフルモールドするタイプの表面実装型パッケージ、パワートランジスタのパッケージなど、また中空パッケージの例としてLD、LED素子を搭載する光パッケージ、圧力センサ、圧電センサ、ジャイロセンサ、温度センサ、キャパシタ、マイクロモータなどのMEMSパッケージなどにも適応することが出来る。   Although the present invention has been described with respect to a hollow package for semiconductor mounting, it is needless to say that the package has the same shape and can be applied to other packages as long as the package is solder-mounted on a substrate. It is. For example, full-mold type surface mount packages such as DRAM, power transistor packages, etc., and examples of hollow packages include LDs, optical packages with LED elements, pressure sensors, piezoelectric sensors, gyro sensors, temperature sensors It can also be applied to MEMS packages such as capacitors and micromotors.

以下に、本発明で得られる、半田実装性に優れるパッケージを具体的に述べるが、本発明は、以下に限られるものではない。
[実施例1]
外部端子に相当する部位の、リードフレームの切断位置に、予め円形状の貫通孔を有する厚さ0.15mmのリードフレームを金型に設置し、て樹脂パッケージを成形した。
エポキシ樹脂組成物(三井化学(株)製TM−250G)の顆粒を圧縮して得られた樹脂タブレットを、金型温度160℃、射出圧力1.5MPaの条件で金型に注入し、図3に示すSON(Small Outline Non−Lead Package)型の半導体パッケージを成形した。
Although the package excellent in solder mounting property obtained by the present invention will be specifically described below, the present invention is not limited to the following.
[Example 1]
A lead frame having a thickness of 0.15 mm having a circular through hole was previously placed in a mold at a position corresponding to the external terminal at the cutting position of the lead frame, and a resin package was molded.
A resin tablet obtained by compressing granules of an epoxy resin composition (TM-250G manufactured by Mitsui Chemicals, Inc.) was injected into a mold under the conditions of a mold temperature of 160 ° C. and an injection pressure of 1.5 MPa. A SON (Small Outline Non-Lead Package) type semiconductor package shown in FIG.

その後、貫通孔を含むリードフレーム全体を、ニッケルめっき(厚さ5μm)、金めっき(厚さ0.3μm)の順にめっきし、前述のリードフレームに予め形成してある貫通孔を横断してリードフレームを切断して、個片化されたパッケージを得た。
得られたパッケージを半田ペーストが塗られた基板上に乗せ、窒素気流下で230℃の半田リフロー実装を行った。
After that, the entire lead frame including the through hole is plated in the order of nickel plating (thickness 5 μm) and gold plating (thickness 0.3 μm), and the lead is crossed through the through holes previously formed in the lead frame. The frame was cut to obtain an individual package.
The obtained package was placed on a substrate coated with a solder paste, and solder reflow mounting at 230 ° C. was performed under a nitrogen stream.

実装後、半田フィレット高さを測定した。フィレット高さは、パッケージ外部端子(アウターリード)の高さをhとし、アウターリード先端のフィレット高さをfとした場合の、リード高さに対するフィレット高さの割合(f/h)×100(%)で表わした。結果を表1に示した。なお、フィレット高さfと外部端子の高さをhとの関係を示す外部端子部の側面拡大図を図4に示す。   After mounting, the solder fillet height was measured. The fillet height is the ratio of the fillet height to the lead height (f / h) × 100 (where h is the height of the package external terminal (outer lead) and f is the fillet height at the outer lead tip. %). The results are shown in Table 1. FIG. 4 is an enlarged side view of the external terminal portion showing the relationship between the fillet height f and the external terminal height h.

[実施例2]
用いたリードフレームの厚さを0.20mmとした以外は、実施例1と同様にパッケージを作製し、同様にフィレット高さ割合を求めた。
[Example 2]
A package was prepared in the same manner as in Example 1 except that the thickness of the lead frame used was 0.20 mm, and the fillet height ratio was similarly determined.

[比較例1]
切断位置に貫通孔を有していない厚さ0.15mmのリードフレームを用いた以外は、実施例1と同様にパッケージを作製し、同様にフィレット高さ割合求めた。
[Comparative Example 1]
A package was prepared in the same manner as in Example 1 except that a 0.15 mm thick lead frame having no through hole at the cutting position was used, and the fillet height ratio was similarly determined.

Figure 2006019465
Figure 2006019465

表1の結果の通り、本発明を用いることで、表面実装型パッケージに対して、効果的に半田フィレットを形成させることが出来ることが明らかとなった。   As shown in the results of Table 1, it was found that by using the present invention, a solder fillet can be effectively formed for a surface mount package.

本発明の表面実装型の半導体パッケージは、従来難しいとされていた外部端子先端部における半田フィレットを効果的に形成させることが可能であり、特に基板との接着強度の優れた半導体パッケージを作製することが出来、例えば半田強度の低い低温半田実装や、リフロー実装などにおいて、パッケージの信頼性を高めることが出来る。そのため、本発明は他のパッケージ、例えば、LD、LED素子を搭載する光パッケージ、圧力センサ、圧電センサ、ジャイロセンサ、温度センサ、キャパシタ、マイクロモータなどのMEMSパッケージなどにも適応することが出来る。   The surface-mount type semiconductor package of the present invention can effectively form a solder fillet at the tip of the external terminal, which has been considered difficult in the past, and in particular, a semiconductor package with excellent adhesion strength to the substrate is manufactured. For example, the reliability of the package can be improved in low-temperature solder mounting with low solder strength or reflow mounting. Therefore, the present invention can also be applied to other packages such as an optical package on which an LD or an LED element is mounted, a MEMS package such as a pressure sensor, a piezoelectric sensor, a gyro sensor, a temperature sensor, a capacitor, or a micromotor.

本発明によるパッケージの一例(SON型中空パッケージ)の概略平面図である。It is a schematic plan view of an example (SON type hollow package) of the package by this invention. 本発明の製造方法で得られるパッケージの一例の、個片化する前の状態を示す概略平面図である。It is a schematic plan view which shows the state before dividing into an example of the package obtained by the manufacturing method of this invention. 本発明の実施例で製造したパッケージ(SON型中空パッケージ)の平面図を示す。The top view of the package (SON type | mold hollow package) manufactured in the Example of this invention is shown. フィレット高さfと外部端子の高さをhとの関係を示す外部端子部の側面拡大図である。It is a side surface enlarged view of the external terminal part which shows the relationship between fillet height f and the height of an external terminal h.

符号の説明Explanation of symbols

1 パッケージ
2 内部端子(インナーリード)
3 外部端子(アウターリード)
4 凹部
5 外部端子(リードフレームとの切断前)
6 貫通孔
7 切断部
8 基板
9 外部端子
10 半田フィレット
1 Package 2 Internal terminal (Inner lead)
3 External terminal (outer lead)
4 Recess 5 External terminal (before cutting with lead frame)
6 Through-hole 7 Cutting part 8 Substrate 9 External terminal 10 Solder fillet

Claims (2)

リードが端子部を残して封止されている半導体パッケージであって、該リードは、実装する基板面に平行に延出する外部端子を有し、該外部端子はその延出方向先端部の断面に、断面の側辺を含むことなく外部端子の上面と下面を貫く凹部を有し、該凹部にめっきが施されていることを特徴とする半導体パッケージ。   A semiconductor package in which a lead is sealed leaving a terminal portion, and the lead has an external terminal extending in parallel to a substrate surface to be mounted, and the external terminal is a cross-section of a tip portion in the extending direction. And a recess that penetrates the upper surface and the lower surface of the external terminal without including the side of the cross section, and the recess is plated. リードが端子部を残して封止されている半導体パッケージの製造において、
リードの外部端子部に、予め貫通孔を有するリードフレームを金型にインサートするインサート工程、
樹脂を注入して成形するモールド工程、
リードフレーム露出部にめっきを施すめっき工程および
外部端子部の貫通孔を横断してリードフレームを切断する切断工程
を含むことを特徴とする半導体パッケージの製造方法。
In manufacturing a semiconductor package in which leads are sealed leaving a terminal portion,
Insert step of inserting a lead frame having a through hole in advance into a die in an external terminal portion of the lead,
A molding process in which resin is injected and molded;
A method of manufacturing a semiconductor package, comprising: a plating step of plating the exposed portion of the lead frame, and a cutting step of cutting the lead frame across the through hole of the external terminal portion.
JP2004195146A 2004-07-01 2004-07-01 Semiconductor package and its manufacturing method Pending JP2006019465A (en)

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JP2011151188A (en) * 2010-01-21 2011-08-04 Sharp Corp Terminal box for solar cell module, solar cell module using the same, and method of manufacturing the same
JP2011155088A (en) * 2010-01-27 2011-08-11 Mitsubishi Electric Corp Semiconductor device module
US8610263B2 (en) 2010-01-27 2013-12-17 Mitsubishi Electric Corporation Semiconductor device module
JP2013225595A (en) * 2012-04-20 2013-10-31 Shinko Electric Ind Co Ltd Lead frame, semiconductor package, and manufacturing methods of lead frame and semiconductor package
JP2015072947A (en) * 2013-10-01 2015-04-16 セイコーインスツル株式会社 Semiconductor device and manufacturing method of the same
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US11894281B2 (en) 2018-09-05 2024-02-06 Rohm Co., Ltd. Semiconductor device including lead with varying thickness
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