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JP2006013555A - Semiconductor device - Google Patents

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Publication number
JP2006013555A
JP2006013555A JP2005276525A JP2005276525A JP2006013555A JP 2006013555 A JP2006013555 A JP 2006013555A JP 2005276525 A JP2005276525 A JP 2005276525A JP 2005276525 A JP2005276525 A JP 2005276525A JP 2006013555 A JP2006013555 A JP 2006013555A
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Japan
Prior art keywords
semiconductor device
terminal
semiconductor
sealing resin
electrode
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JP2005276525A
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Japanese (ja)
Inventor
Nobuhito Oouchi
伸仁 大内
Shigeru Yamada
茂 山田
Yasushi Shiraishi
靖 白石
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Oki Electric Industry Co Ltd
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Oki Electric Industry Co Ltd
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Priority to JP2005276525A priority Critical patent/JP2006013555A/en
Publication of JP2006013555A publication Critical patent/JP2006013555A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA

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Abstract

<P>PROBLEM TO BE SOLVED: To provide semiconductor device which can restrain drop of the yield and can realize high density mounting. <P>SOLUTION: The semiconductor device 400 forms a first terminal electrically connected with a first electrode on a first semiconductor element including a first surface where a plurality of first electrodes are formed. Also, the device includes a first semiconductor device where a first sealing resin is formed to expose a first terminal; and a second semiconductor device where a second terminal electrically connected with a second electrode is formed on the second semiconductor element including the second surface where a plurality of second electrodes are formed, and the second sealing resin is formed to expose the second terminal. Meanwhile, a bump is formed on the first terminal and on the other hand, the second terminal is connected with the first terminal via a boding material. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、歩留まりの低下を抑えつつ、高密度実装化を図ることが可能な半導体装置に関するものである。   The present invention relates to a semiconductor device capable of achieving high-density mounting while suppressing a decrease in yield.

近年における携帯型電子機器の急速な普及には目覚ましいものがある。これに伴って携帯型電子機器に搭載される樹脂封止型半導体装置も薄型・小型・軽量のものが要求されるようになっている。かかる要求に応える高密度化の半導体装置としてチップサイズパッケージと称されるものがある。このチップサイズパッケージの構成の一例を、図１２を参照しながら説明する。   The rapid spread of portable electronic devices in recent years is remarkable. Accordingly, a resin-encapsulated semiconductor device mounted on a portable electronic device is required to be thin, small, and lightweight. As a high-density semiconductor device that meets such demands, there is one called a chip size package. An example of the configuration of this chip size package will be described with reference to FIG.

半導体装置８２０は、図１２に示したように、４００・ｍ程度の厚みを有する半導体素子１ｂ上に電極パッド６が形成され、電極パッド６に電気的に接続するＣｕ等による配線２が形成されている。半導体素子１ｂの表面及び配線２は、厚み１００・ｍ程度の封止樹脂５によって封止されている。封止樹脂５の表面に露出した配線２の上面にははんだ等によるバンプ３が形成されている。図中符号４は、電極パッド６と配線２とを電気的に接続するＣｕ等による再配線である。   In the semiconductor device 820, as shown in FIG. 12, the electrode pad 6 is formed on the semiconductor element 1b having a thickness of about 400 · m, and the wiring 2 made of Cu or the like electrically connected to the electrode pad 6 is formed. ing. The surface of the semiconductor element 1b and the wiring 2 are sealed with a sealing resin 5 having a thickness of about 100 m. Bumps 3 made of solder or the like are formed on the upper surface of the wiring 2 exposed on the surface of the sealing resin 5. Reference numeral 4 in the figure denotes rewiring with Cu or the like for electrically connecting the electrode pad 6 and the wiring 2.

この図１２に示した半導体装置８２０の製造方法を、図１３を参照しながら説明する。まず、図１３（Ａ）に示したように、半導体素子１ｂ上にＣｕ等による配線２が形成される。なお、図１３（Ａ）では、上記電極パッド６及び再配線４は図示していない。そして、図１３（Ｂ）に示したように、配線２を完全に覆う厚みで半導体素子１ｂの表面全体を封止樹脂５により封止する。次いで、図１３（Ｃ）に示したように、表面全体を研削して配線２を表面に露出させた後、図１３（Ｄ）に示したように、はんだ等によるバンプ３を形成する。さらに、半導体素子１ｂを個々の半導体装置に切断し分割することによって、半導体装置８２０が製造される。   A method for manufacturing the semiconductor device 820 shown in FIG. 12 will be described with reference to FIG. First, as shown in FIG. 13A, the wiring 2 made of Cu or the like is formed on the semiconductor element 1b. In FIG. 13A, the electrode pad 6 and the rewiring 4 are not shown. Then, as shown in FIG. 13B, the entire surface of the semiconductor element 1 b is sealed with a sealing resin 5 with a thickness that completely covers the wiring 2. Next, as shown in FIG. 13C, after the entire surface is ground to expose the wiring 2 on the surface, bumps 3 made of solder or the like are formed as shown in FIG. 13D. Furthermore, the semiconductor device 820 is manufactured by cutting and dividing the semiconductor element 1b into individual semiconductor devices.

なお、本件の親出願である特願平１１−１８７６５８号においては、拒絶理由通知の際に以下の８件の文献が挙げられている。
特開平１０−９３０１３号公報 特開平９−１８１２５６号公報 特開昭５９−１１７１４６号公報 特開平１０−１２８１０号公報 特開平７−２４０４９６号公報 実願平１−１４４０８９号（実開平３−８３９４０号）のマイクロフィルム 特願平１１−１４５８７０号（特開２０００−３４０７３６号公報） 特願平１０−１２１０４６号（特開平１１−３１２７８０号公報） In Japanese Patent Application No. 11-187658, which is the parent application of the present case, the following eight documents are cited at the time of notification of reasons for refusal.
Japanese Patent Laid-Open No. 10-93013 Japanese Patent Laid-Open No. 9-181256 JP 59-117146 A Japanese Patent Laid-Open No. 10-12810 Japanese Patent Laid-Open No. 7-240696 Microfilm of Japanese Utility Model Application No. 1-144089 (Japanese Utility Model Application No. 3-83940) Japanese Patent Application No. 11-145870 (Japanese Patent Laid-Open No. 2000-340736) Japanese Patent Application No. 10-121046 (Japanese Patent Laid-Open No. 11-31780)

ところで、例えばメモリプロセスとロジックプロセスのように、半導体素子製造のプロセス条件が異なる場合には、これらの異なる複数の機能を一の半導体素子上に形成することは難しい。かかる場合には、各機能の半導体装置を個別に製造しておき、それらをプリント基板上に実装することが行われる。
例えば、２つの半導体装置をプリント基板１３に実装する場合について説明する。ここで第１の半導体装置８１０は、半導体素子８１１及び金線８１５が設けられたエポキシ基板８１６の片面を封止樹脂８０５により封止し、裏面にはんだ等のバンプ８０３がエリア状に形成されたＢＧＡ（ｂａｌｌ ｇｒｉｄ ａｒｒａｙ）構造と称される半導体装置であり、第２の半導体装置は上述の半導体装置８２０であり、それぞれ個別に製造されたものである。これら個別に製造された２つの半導体装置８１０、８２０の実装を、図１４に示したように、プリント基板１３の同一平面上で行うと、高密度基板実装を図ることが難しいという問題があった。 By the way, when the process conditions for manufacturing a semiconductor element are different, such as a memory process and a logic process, it is difficult to form these different functions on one semiconductor element. In such a case, semiconductor devices having respective functions are individually manufactured and mounted on a printed board.
For example, a case where two semiconductor devices are mounted on the printed circuit board 13 will be described. Here, in the first semiconductor device 810, one surface of the epoxy substrate 816 provided with the semiconductor element 811 and the gold wire 815 is sealed with a sealing resin 805, and bumps 803 such as solder are formed in an area shape on the back surface. The semiconductor device is called a BGA (ball grid array) structure, and the second semiconductor device is the above-described semiconductor device 820, which are individually manufactured. When mounting these two individually manufactured semiconductor devices 810 and 820 on the same plane of the printed board 13 as shown in FIG. 14, there is a problem that it is difficult to achieve high-density board mounting. .

また、上記問題点を解決するために、図１５に示したように、半導体素子１ａ、１ｂを積み重ね、金属細線１５ａ、１５ｂを配線１４に接続した後に樹脂封止する構成がある。かかる構成によれば、基板実装面積を増加させることなく高密度実装を図ることができる。しかしながら、半導体装置全体の歩留まりの点においては、以下の問題点があった。すなわち、通常、半導体素子はウェハの状態で簡易的な特性チェックがされるが、最終テスト（出荷テスト）は、組立後の半導体装置としてのみ実施がされる。したがって、最終テストの済んでいない２つの半導体素子を搭載して半導体装置を製造すると、半導体装置全体としての歩留まりは２つの半導体素子の歩留まりの積となる。このため高密度実装化に反比例して歩留まりの低下が生じ、コストアップにつながるという課題があった。   In order to solve the above problem, as shown in FIG. 15, there is a configuration in which the semiconductor elements 1 a and 1 b are stacked and the metal thin wires 15 a and 15 b are connected to the wiring 14 and then resin-sealed. According to this configuration, high-density mounting can be achieved without increasing the board mounting area. However, there are the following problems in terms of the yield of the entire semiconductor device. That is, normally, a semiconductor device is subjected to a simple characteristic check in a wafer state, but a final test (shipment test) is performed only as a semiconductor device after assembly. Therefore, when a semiconductor device is manufactured by mounting two semiconductor elements that have not been final tested, the yield of the entire semiconductor device is the product of the yields of the two semiconductor elements. For this reason, there is a problem that the yield is reduced in inverse proportion to the high-density mounting, leading to an increase in cost.

上述の課題を解決するため、本発明によれば、複数の第１の電極が形成された第１の面を有する第１の半導体素子上に第１の電極と電気的に接続された第１の端子が形成されると共に、第１の端子が露出されるように第１の封止樹脂が形成された第１の半導体装置と、複数の第２の電極が形成された第２の面を有する第２の半導体素子上に第２の電極と電気的に接続された第２の端子が形成されると共に、第２の端子が露出されるように第２の封止樹脂が形成された第２の半導体装置とを有し、一方で第１の端子上にバンプが形成されており、他方では、第１の端子上に第２の端子が接合材とを介して接続されていることを特徴とする半導体装置が提供される。   In order to solve the above-described problem, according to the present invention, a first electrically connected to a first electrode on a first semiconductor element having a first surface on which a plurality of first electrodes are formed. A first semiconductor device in which a first sealing resin is formed so that the first terminal is exposed, and a second surface on which a plurality of second electrodes are formed. A second terminal electrically connected to the second electrode is formed on the second semiconductor element having the second sealing resin formed so that the second terminal is exposed. The bumps are formed on the first terminal on the one hand, and the second terminal is connected to the first terminal via a bonding material on the other hand. A semiconductor device is provided.

また、上述の課題を解決するため、本発明によれば、複数の第１の電極が形成された第１の面を有する第１の半導体素子上に第１の電極と電気的に接続された第１の端子が形成されると共に、第１の端子が露出されるように封止樹脂が形成された第１の半導体装置と、第１の端子の一部に接続されたバンプと、バンプが形成されていない第１の端子と電気的に接続される第２の電極を第２の面上に形成した第２の半導体素子と、を有することを特徴とする半導体装置が提供される。   Moreover, in order to solve the above-mentioned subject, according to this invention, it electrically connected with the 1st electrode on the 1st semiconductor element which has the 1st surface in which the several 1st electrode was formed. A first semiconductor device in which a sealing resin is formed so that the first terminal is exposed and the first terminal is exposed; a bump connected to a part of the first terminal; There is provided a semiconductor device comprising: a second semiconductor element formed on a second surface with a second electrode electrically connected to a first terminal that is not formed.

さらに、上述の課題を解決するため、本発明によれば、第１の半導体素子上に形成された第１の封止樹脂の側面には、切断によって形成された切断面を有することを特徴とする半導体装置が提供される。   Furthermore, in order to solve the above-mentioned problem, according to the present invention, the side surface of the first sealing resin formed on the first semiconductor element has a cut surface formed by cutting. A semiconductor device is provided.

本発明の効果として、半導体装置の製造における歩留まり低下の抑制しながら、高密度実装化を図ることが可能な半導体装置の提供が挙げられる。   As an effect of the present invention, provision of a semiconductor device capable of achieving high-density mounting while suppressing a decrease in yield in the manufacture of the semiconductor device can be given.

以下に添付図面を参照しながら、本発明にかかる半導体装置及びその製造方法の好適な実施の形態について詳細に説明する。なお、本明細書及び図面において、実質的に同一の機能構成を有する構成要素については、同一の符号を付することにより重複説明を省略する。   Exemplary embodiments of a semiconductor device and a manufacturing method thereof according to the present invention will be explained below in detail with reference to the accompanying drawings. In addition, in this specification and drawing, about the component which has the substantially same function structure, duplication description is abbreviate | omitted by attaching | subjecting the same code | symbol.

本実施の形態にかかる半導体装置１００を、図１を参照しながら説明する。半導体装置１００は、図１（Ａ）に示したように、表面にはんだ等のバンプ３が例えば格子状に形成された第１の半導体装置１１０と、複数の端子２を有し、第１の半導体装置１１０の表面のバンプ３が形成されていない領域に搭載される第２の半導体装置１２０とを含んでいる。第１の半導体装置１１０のバンプ３と第２の半導体装置１２０の端子２とは、後工程で半導体装置１００がプリント基板１３に実装される際に、プリント基板１３上の配線により、電気的に接続される。
第１の半導体装置１１０及び第２の半導体装置１２０の製造方法について、図２及び図３を参照しながら説明する。 A semiconductor device 100 according to the present embodiment will be described with reference to FIG. As shown in FIG. 1A, the semiconductor device 100 includes a first semiconductor device 110 having bumps 3 made of solder or the like formed on the surface thereof, for example, in a lattice shape, and a plurality of terminals 2. And a second semiconductor device 120 mounted on the surface of the semiconductor device 110 where the bumps 3 are not formed. The bump 3 of the first semiconductor device 110 and the terminal 2 of the second semiconductor device 120 are electrically connected by wiring on the printed circuit board 13 when the semiconductor device 100 is mounted on the printed circuit board 13 in a later process. Connected.
A method for manufacturing the first semiconductor device 110 and the second semiconductor device 120 will be described with reference to FIGS.

（第１の半導体装置１１０）まず、図２を参照しながら、第１の半導体装置１１０について説明する。まず、図２（Ａ）に示したように、エポキシ基板１６の表面に半導体素子１ａ及び配線１４を設ける。そして、図２（Ｂ）に示したように、半導体素子１ａ上の電極と配線１４とを金属細線１５ａにより接続する。その後、図２（Ｃ）に示したように、これらエポキシ基板１６上の各構成部材を覆うように封止樹脂５で封止する。さらに、エポキシ基板１６の裏面にバンプ３を形成する。このエポキシ基板１６にはスルーホール１７が形成されており、配線４は裏面のバンプ３と電気的に導通している。
バンプ３の高さは、後工程で第１の半導体装置１１０に搭載する第２の半導体装置１２０の高さと実質的に同じか、わずかに高い寸法となっている。また、バンプ３は、後工程で半導体装置１００がプリント基板１３に実装される際の熱処理により溶融する。 (First Semiconductor Device 110) First, the first semiconductor device 110 will be described with reference to FIG. First, as shown in FIG. 2A, the semiconductor element 1 a and the wiring 14 are provided on the surface of the epoxy substrate 16. Then, as shown in FIG. 2B, the electrode on the semiconductor element 1a and the wiring 14 are connected by a thin metal wire 15a. Thereafter, as shown in FIG. 2C, sealing is performed with a sealing resin 5 so as to cover the constituent members on the epoxy substrate 16. Further, bumps 3 are formed on the back surface of the epoxy substrate 16. A through hole 17 is formed in the epoxy substrate 16, and the wiring 4 is electrically connected to the bump 3 on the back surface.
The height of the bump 3 is substantially the same as or slightly higher than the height of the second semiconductor device 120 mounted on the first semiconductor device 110 in a later process. Further, the bump 3 is melted by heat treatment when the semiconductor device 100 is mounted on the printed board 13 in a later process.

（第２の半導体装置１２０）次いで、図３を参照しながら、第２の半導体装置１２０の製造方法について説明する。まず、図３（Ａ）に示したように、半導体素子１ｂ上に電気メッキ等により、高さ約５０・ｍのＣｕの配線２を形成する。次いで、図３（Ｂ）に示したように、配線２を完全に覆う厚みで半導体素子１ｂの表面全体を封止樹脂５ｂにより封止する。樹脂封止方法はトランスファーモールド法、ポッティング法、印刷法等が用いられる。次いで、図３（Ｃ）に示したように、表面全体を研削して配線２を表面に露出させる。
次いで、図３（Ｄ）に示したように、後工程で切断し分割する部分に所定の深さで溝９を形成する。溝９の深さは最終的に個々の半導体装置とした場合の半導体素子１ｂの厚みに基づいて決定する。半導体素子１ｂの厚みを１００・ｍとする場合、溝は約２０・ｍ深く形成し約１２０・ｍとする。そして、樹脂部５ｂの厚みも加えて合計で１７０・ｍの深さとなる。 (Second Semiconductor Device 120) Next, a method for manufacturing the second semiconductor device 120 will be described with reference to FIG. First, as shown in FIG. 3A, a Cu wiring 2 having a height of about 50 m is formed on the semiconductor element 1b by electroplating or the like. Next, as shown in FIG. 3B, the entire surface of the semiconductor element 1b is sealed with a sealing resin 5b with a thickness that completely covers the wiring 2. As the resin sealing method, a transfer molding method, a potting method, a printing method, or the like is used. Next, as shown in FIG. 3C, the entire surface is ground to expose the wiring 2 on the surface.
Next, as shown in FIG. 3D, a groove 9 is formed at a predetermined depth in a portion to be cut and divided in a subsequent process. The depth of the groove 9 is determined based on the thickness of the semiconductor element 1b when the semiconductor device is finally formed. When the thickness of the semiconductor element 1b is 100 · m, the groove is formed to be about 20 · m deep and about 120 · m. The total thickness is 170 · m including the thickness of the resin portion 5b.

次いで、裏面研削工程を行う。まず、図３（Ｅ）に示したように、溝９が形成された半導体素子１ｂの樹脂形成面に研削テープ２０を貼付する。この研削テープ２０は紫外線を照射することによって、粘着力が落ち、簡単に剥がせるものである。次いで、研削テープ２０を貼付した面を研削ステージ（図示しない）に吸着により固定する。裏面の研削は、図３（Ｆ）に示したように、上述の溝９の底部に達するまで行う。こうして研削テープ１２上に個々に分割された半導体装置（第２の半導体装置１２０）が並ぶ状態となる。
次いで、図３（Ｇ）に示したように、研削した面にマウントテープ２１が貼付される。そして、研削テープ２０は紫外線が照射されて除去される。この第２の半導体装置１２０がマウントテープ２１に並べられた状態で、第１の半導体装置１１０へと搭載される。 Next, a back grinding process is performed. First, as shown in FIG. 3E, the grinding tape 20 is attached to the resin-formed surface of the semiconductor element 1b in which the grooves 9 are formed. This grinding tape 20 can be easily peeled off by irradiating it with ultraviolet rays. Next, the surface to which the grinding tape 20 is affixed is fixed to a grinding stage (not shown) by suction. The grinding of the back surface is performed until the bottom of the groove 9 is reached as shown in FIG. In this way, the semiconductor devices (second semiconductor device 120) divided individually on the grinding tape 12 are arranged.
Next, as shown in FIG. 3G, the mount tape 21 is attached to the ground surface. Then, the grinding tape 20 is removed by irradiation with ultraviolet rays. The second semiconductor device 120 is mounted on the first semiconductor device 110 in a state of being arranged on the mount tape 21.

第２の半導体装置１２０の第１の半導体装置１２０への搭載は、第１の半導体装置１１０のバンプ３が形成されていない領域に第２の半導体装置１２０を接着剤１１５を用いて搭載する。この接着剤１１５は、第１の半導体装置１１０に供給しておくこともできるが、マウントテープ２１に接着剤１１５を設けることも可能である。以上の工程により、第１の実施の形態にかかる半導体装置１００が製造される。半導体装置１００は、後工程により、図１（Ｂ）に示したように、プリント基板１３に実装される。このとき、第２の半導体装置１２０の端子２は、プリント基板１３にはんだ１８により電気的に接続される。ここで、はんだ１８は、あらかじめプリント基板１３に塗布されているはんだペーストであり、このはんだペーストは、バンプ３及び端子２に対応してそれぞれ形成されている。
以上のように半導体装置１００によれば、第２の半導体装置１２０は、第１の半導体装置１１０の表面のバンプ３が形成されていない領域に搭載される。そして、第１の半導体装置１１０及び第２の半導体装置１２０がそれぞれ最終テスト済みであるため、歩留まりの低下を抑えつつ、高密度実装化を図ることが可能である。 The mounting of the second semiconductor device 120 on the first semiconductor device 120 is performed by mounting the second semiconductor device 120 on the region where the bumps 3 of the first semiconductor device 110 are not formed using the adhesive 115. The adhesive 115 can be supplied to the first semiconductor device 110, but the adhesive 115 can be provided on the mount tape 21. The semiconductor device 100 according to the first embodiment is manufactured through the above steps. The semiconductor device 100 is mounted on the printed circuit board 13 as shown in FIG. At this time, the terminal 2 of the second semiconductor device 120 is electrically connected to the printed circuit board 13 by the solder 18. Here, the solder 18 is a solder paste previously applied to the printed circuit board 13, and this solder paste is formed corresponding to the bump 3 and the terminal 2, respectively.
As described above, according to the semiconductor device 100, the second semiconductor device 120 is mounted on the surface of the first semiconductor device 110 where the bumps 3 are not formed. Since each of the first semiconductor device 110 and the second semiconductor device 120 has been subjected to a final test, high-density mounting can be achieved while suppressing a decrease in yield.

なお、本実施の形態においては、第１の半導体装置１１０にＢＧＡ構造の半導体装置を採用した場合の一例につき説明したが、本発明はこれに限定されない。例えば図４（Ａ）に示したように、第１の半導体装置として、第２の半導体装置１２０と同様のチップサイズパッケージの第１の半導体装置１１０'を採用し、半導体装置１００'を構成することも可能である。この第１の半導体装置１１０'は、図４（Ｂ）に示したように、上記第１の半導体装置１１０と同様、第２の半導体装置１２０を搭載する領域には、電極２及びバンプ３が形成されていない。なお、以下の実施の形態においても同様である。   Note that although an example in which a semiconductor device having a BGA structure is employed as the first semiconductor device 110 has been described in this embodiment, the present invention is not limited to this. For example, as shown in FIG. 4A, the first semiconductor device 110 ′ having the same chip size package as that of the second semiconductor device 120 is adopted as the first semiconductor device, thereby forming the semiconductor device 100 ′. It is also possible. As shown in FIG. 4B, the first semiconductor device 110 ′ has electrodes 2 and bumps 3 in the region where the second semiconductor device 120 is mounted, as in the first semiconductor device 110. Not formed. The same applies to the following embodiments.

本実施の形態にかかる半導体装置２００は、上記半導体装置１００を改良したものであり、第２の半導体装置２２０の端子が形成されていない面が第１の半導体装置２１０の表面と接着剤２１２により接合されることにより、第１の半導体装置２１０に搭載される点で上記半導体装置１００と共通する。以下に、半導体装置２００の改良点につき、図５を参照しながら説明する。なお、略同一の構成要素については同一符号を付すことで詳細な説明を省略する。   The semiconductor device 200 according to the present embodiment is an improvement of the semiconductor device 100, and the surface of the second semiconductor device 220 where the terminals are not formed is formed by the surface of the first semiconductor device 210 and the adhesive 212. By being bonded, it is common to the semiconductor device 100 in that it is mounted on the first semiconductor device 210. Hereinafter, improvements of the semiconductor device 200 will be described with reference to FIG. In addition, about the same component, the detailed description is abbreviate | omitted by attaching | subjecting the same code | symbol.

半導体装置２００においては、第１の半導体装置２１０のバンプ３が形成されていない所定の領域に、第２の半導体装置２２０の大きさに合わせて浅く平滑に削った凹部（座繰り部）２１５が形成されている。そして、第２の半導体装置２２０はこの座繰り部２１５に搭載される。
半導体装置２００は、後工程により、図５（Ｂ）に示したように、プリント基板１３に実装される。このとき、座繰り部２１５を形成したことにより第２の半導体装置２２０とプリント基板１３との間に広い空間をとることができるので、図５（Ｂ）に示したように、素子間の接続の信頼性を向上させるためのはんだ等のバンプ３ｂを形成することができる。
以上のように、半導体装置２００によれば、第２の半導体装置２２０を搭載する領域に厚み方向の広い空間を取ることができるので、第２の半導体装置２２０が多少厚みのあるものであっても搭載することができる。また、この空間にはんだ等のバンプ３ｂを形成することにより、素子間の接続の信頼性を向上させることが可能である。 In the semiconductor device 200, a recess (a countersink portion) 215 that is shallowly and smoothly cut according to the size of the second semiconductor device 220 is formed in a predetermined region where the bump 3 of the first semiconductor device 210 is not formed. Is formed. Then, the second semiconductor device 220 is mounted on the counterbore part 215.
The semiconductor device 200 is mounted on the printed circuit board 13 as shown in FIG. At this time, since the counterbored portion 215 is formed, a wide space can be provided between the second semiconductor device 220 and the printed circuit board 13, so that connection between elements is performed as shown in FIG. Bumps 3b made of solder or the like for improving the reliability can be formed.
As described above, according to the semiconductor device 200, since a wide space in the thickness direction can be provided in the region where the second semiconductor device 220 is mounted, the second semiconductor device 220 is somewhat thick. Can also be installed. Also, by forming bumps 3b such as solder in this space, it is possible to improve the reliability of connection between elements.

本実施の形態にかかる半導体装置３００は、上記半導体装置１００を改良したものであり、第２の半導体装置３２０の端子が形成されていない面が第１の半導体装置３１０の表面と接着剤により接合されることにより、第１の半導体装置３１０に搭載される点で上記半導体装置１００と共通する。以下に、半導体装置３００の改良点につき、図６を参照しながら説明する。なお、略同一の構成要素については同一符号を付すことで詳細な説明を省略する。   The semiconductor device 300 according to the present embodiment is an improvement of the semiconductor device 100, and the surface of the second semiconductor device 320 where the terminals are not formed is bonded to the surface of the first semiconductor device 310 with an adhesive. Thus, the semiconductor device 100 is common to the semiconductor device 100 in that it is mounted on the first semiconductor device 310. Hereinafter, improvements of the semiconductor device 300 will be described with reference to FIG. In addition, about the same component, the detailed description is abbreviate | omitted by attaching | subjecting the same code | symbol.

半導体装置３００は、図６（Ａ）に示したように、第２の半導体装置３２０の裏面と、第１の半導体装置３１０とを接合する接着剤に、所定の温度以上で接着性を失う低分子接着剤３１５を用いたことを特徴としている。ここで所定の温度とは、半導体装置３００をプリント基板１３に実装する際のリフロー等の熱処理時の温度であり、例えば２００℃以上で接着性を失う低分子接着剤を用いることができる。
半導体装置３００は、後工程により、図６（Ｂ）に示したように、プリント基板１３に実装される。このとき、低分子接着剤３１５は接着力を失い、第１の半導体装置３１０と第２の半導体装置３２０とは分離される。
以上のように半導体装置３００によれば、半導体装置３００をプリント基板１３に実装する際に、第１の半導体装置３１０と第２の半導体装置３２０とを分離して、個別に位置合わせすることができる。かかるセルフアライメント効果により、正確な位置に実装することが可能である。 As shown in FIG. 6A, the semiconductor device 300 is a low adhesive that bonds the back surface of the second semiconductor device 320 and the first semiconductor device 310 at a predetermined temperature or higher. A molecular adhesive 315 is used. Here, the predetermined temperature is a temperature at the time of heat treatment such as reflow when the semiconductor device 300 is mounted on the printed circuit board 13, and for example, a low molecular adhesive that loses adhesion at 200 ° C. or higher can be used.
The semiconductor device 300 is mounted on the printed circuit board 13 as shown in FIG. At this time, the low molecular adhesive 315 loses adhesive force, and the first semiconductor device 310 and the second semiconductor device 320 are separated.
As described above, according to the semiconductor device 300, when the semiconductor device 300 is mounted on the printed circuit board 13, the first semiconductor device 310 and the second semiconductor device 320 can be separated and individually aligned. it can. Due to such a self-alignment effect, mounting at an accurate position is possible.

本実施の形態にかかる半導体装置４００を、図７を参照しながら説明する。なお、第１の実施の形態にかかる半導体装置１００と略同一の構成要素については同一符号を付すことで詳細な説明を省略する。   A semiconductor device 400 according to the present embodiment will be described with reference to FIG. In addition, about the component substantially the same as the semiconductor device 100 concerning 1st Embodiment, detailed description is abbreviate | omitted by attaching | subjecting the same code | symbol.

上記半導体装置１００では、第２の半導体装置１２０の端子が形成されていない面が第１の半導体装置１１０の表面と接着剤１１５により接合されることにより、第１の半導体装置１１０に搭載されていた。本実施の形態にかかる半導体装置４００では、図７（Ａ）に示したように、第２の半導体装置４２０の端子２が第１の半導体装置４１０の表面とはんだ４１５により接合されることにより、第１の半導体装置４１０に搭載されることを特徴としている。
第１の半導体装置４１０のバンプ３が形成されたエポキシ基板１６の裏面には、バンプ３と第２の半導体装置４２０の端子２とを電気的に導通させるための配線パターンが形成されている。上記構成によれば、エポキシ基板１６の裏面で第１の半導体装置４１０と第２の半導体装置４２０とは電気的に接続される。
以上のように半導体装置４００によれば、図７（Ｂ）に示したように、後工程でプリント基板１３に実装する際に、装置全体の端子が増えていないため、容易に実装することが可能である。 The semiconductor device 100 is mounted on the first semiconductor device 110 by bonding the surface of the second semiconductor device 120 on which the terminals are not formed to the surface of the first semiconductor device 110 with an adhesive 115. It was. In the semiconductor device 400 according to the present embodiment, as shown in FIG. 7A, the terminal 2 of the second semiconductor device 420 is joined to the surface of the first semiconductor device 410 by the solder 415, It is mounted on the first semiconductor device 410.
A wiring pattern for electrically connecting the bumps 3 and the terminals 2 of the second semiconductor device 420 is formed on the back surface of the epoxy substrate 16 on which the bumps 3 of the first semiconductor device 410 are formed. According to the above configuration, the first semiconductor device 410 and the second semiconductor device 420 are electrically connected on the back surface of the epoxy substrate 16.
As described above, according to the semiconductor device 400, as shown in FIG. 7B, when the device is mounted on the printed circuit board 13 in a subsequent process, the number of terminals of the entire device is not increased. Is possible.

なお、本実施の形態においては、第１の半導体装置４１０にＢＧＡ構造の半導体装置を採用した場合の一例につき説明したが、本発明はこれに限定されない。例えば図８（Ａ）に示したように、第１の半導体装置として、第２の半導体装置４２０と同様のチップサイズパッケージの第１の半導体装置４１０'を採用し、半導体装置４００'を構成することも可能である。この第１の半導体装置４１０'は、図８（Ｂ）に示したように、上記第１の半導体装置４１０と同様、第２の半導体装置４２０を搭載する領域には、バンプ３が形成されておらず、端子２が露出している。そして、この第１の半導体装置４１０'の端子２と、第２の半導体装置４２０の端子２とが、はんだ４１５により電気的に接続される。なお、以下の実施の形態においても同様である。   Note that although an example in which a BGA structure semiconductor device is employed as the first semiconductor device 410 has been described in this embodiment mode, the present invention is not limited thereto. For example, as shown in FIG. 8A, a first semiconductor device 410 ′ having a chip size package similar to that of the second semiconductor device 420 is adopted as the first semiconductor device, thereby forming the semiconductor device 400 ′. It is also possible. As shown in FIG. 8B, the first semiconductor device 410 ′ has bumps 3 formed in the region where the second semiconductor device 420 is mounted, as in the first semiconductor device 410. The terminal 2 is exposed. The terminal 2 of the first semiconductor device 410 ′ and the terminal 2 of the second semiconductor device 420 are electrically connected by solder 415. The same applies to the following embodiments.

本実施の形態にかかる半導体装置５００は、上記半導体装置４００を改良したものであり、第２の半導体装置５２０の端子が第１の半導体装置５１０の表面とはんだ５１４により接合されることにより、第１の半導体装置５１０に搭載される点で上記半導体装置４００と共通する。以下に、半導体装置５００の改良点につき、図９を参照しながら説明する。なお、略同一の構成要素については同一符号を付すことで詳細な説明を省略する。   The semiconductor device 500 according to the present embodiment is an improvement of the semiconductor device 400, and the terminal of the second semiconductor device 520 is joined to the surface of the first semiconductor device 510 by the solder 514, so that the first It is common to the semiconductor device 400 in that it is mounted on one semiconductor device 510. Hereinafter, improvements of the semiconductor device 500 will be described with reference to FIG. In addition, about the same component, the detailed description is abbreviate | omitted by attaching | subjecting the same code | symbol.

半導体装置５００は、図９（Ａ）に示したように、第２の半導体装置５１０の裏面に、熱伝導性の高い接着部材５１５が貼付されることを特徴としている。この接着部材５１５は、図示した例では、所定厚みのシート状をしている。
半導体装置５００は、後工程により、図９（Ｂ）に示したように、プリント基板１３に実装される。このとき、第２の半導体装置５２０は、接着部材５１５の接着力によりプリント基板１３に安定して固定される。
以上のように半導体装置５００によれば、第２の半導体装置５２０は、熱伝導性の高い接着部材６１７を介してプリント基板１３に接続されているため、第２の半導体装置５２０の放熱性を向上させることが可能である。 As shown in FIG. 9A, the semiconductor device 500 is characterized in that an adhesive member 515 having high thermal conductivity is attached to the back surface of the second semiconductor device 510. In the illustrated example, the adhesive member 515 has a sheet shape with a predetermined thickness.
The semiconductor device 500 is mounted on the printed circuit board 13 as shown in FIG. At this time, the second semiconductor device 520 is stably fixed to the printed circuit board 13 by the adhesive force of the adhesive member 515.
As described above, according to the semiconductor device 500, since the second semiconductor device 520 is connected to the printed circuit board 13 through the adhesive member 617 having high thermal conductivity, the heat dissipation of the second semiconductor device 520 is improved. It is possible to improve.

本実施の形態にかかる半導体装置６００は、上記半導体装置４００を改良したものであり、第２の半導体装置６２０の端子が第１の半導体装置６１０の表面とはんだにより接合されることにより、第１の半導体装置６１０に搭載される点で上記半導体装置４００と共通する。以下に、半導体装置６００の改良点につき、図１０を参照しながら説明する。なお、略同一の構成要素については同一符号を付すことで詳細な説明を省略する。   The semiconductor device 600 according to the present embodiment is an improvement of the semiconductor device 400, and the first semiconductor device 620 is joined to the surface of the first semiconductor device 610 by soldering the first semiconductor device 610. This is common to the semiconductor device 400 in that it is mounted on the semiconductor device 610. Hereinafter, improvements of the semiconductor device 600 will be described with reference to FIG. In addition, about the same component, the detailed description is abbreviate | omitted by attaching | subjecting the same code | symbol.

半導体装置６００は、第２の半導体装置６２０の端子面と、第１の半導体装置６１０とを接合するはんだに、高融点はんだ６１５を用いたことを特徴としている。ここで高融点とは、後工程で半導体装置６００をプリント基板１３に実装する際の温度より高い融点であり、例えば２００℃以上の融点を持つ高融点はんだ６１５を用いることができる。
以上説明したように半導体装置６００によれば、プリント基板１３への実装時のリフロー等の熱処理を行っても、第２の半導体装置６２０は、第１の半導体装置６１０に高融点はんだで接合されているため、安定した基板実装が可能である。 The semiconductor device 600 is characterized in that a high melting point solder 615 is used as solder for joining the terminal surface of the second semiconductor device 620 and the first semiconductor device 610. Here, the high melting point is a melting point higher than the temperature at which the semiconductor device 600 is mounted on the printed circuit board 13 in a later step. For example, a high melting point solder 615 having a melting point of 200 ° C. or higher can be used.
As described above, according to the semiconductor device 600, the second semiconductor device 620 is bonded to the first semiconductor device 610 with the high melting point solder even if heat treatment such as reflow during mounting on the printed circuit board 13 is performed. Therefore, stable board mounting is possible.

本実施の形態にかかる半導体装置７００を、図１１を参照しながら説明する。なお、第１の実施の形態にかかる半導体装置１００と略同一の構成要素については同一符号を付すことで詳細な説明を省略する。   A semiconductor device 700 according to the present embodiment will be described with reference to FIG. In addition, about the component substantially the same as the semiconductor device 100 concerning 1st Embodiment, detailed description is abbreviate | omitted by attaching | subjecting the same code | symbol.

上記半導体装置１００では、第２の半導体装置１２０は、その裏面が第１の半導体装置１１０の表面と接着剤１１５により接合されることにより、第１の半導体装置１１０に搭載されていた。本実施の形態にかかる半導体装置７００では、図１１に示したように、第２の半導体装置７２０は、その裏面が第１の半導体装置７１０の表面と封止樹脂７１５により接合されることにより、第１の半導体装置７１０に搭載されることを特徴としている。   In the semiconductor device 100, the second semiconductor device 120 is mounted on the first semiconductor device 110 by bonding the back surface of the second semiconductor device 120 to the front surface of the first semiconductor device 110 with the adhesive 115. In the semiconductor device 700 according to the present embodiment, as shown in FIG. 11, the second semiconductor device 720 has its back surface bonded to the surface of the first semiconductor device 710 by the sealing resin 715. The semiconductor device is mounted on the first semiconductor device 710.

第１の半導体装置７１０は、所定のパターン加工が施され、必要に応じて放熱板７０２が設けられたエポキシ基板１６に、半導体素子１ａを接着剤により固着する。そして、半導体素子１ａ上の電極と、エポキシ基板１６とを金属細線１５ａで接続する。エポキシ基板１６はその表面で電気的に導通され、第１の半導体装置７１０の裏面に形成されたバンプ３と電気的に接続されている。   The first semiconductor device 710 is subjected to a predetermined pattern processing, and the semiconductor element 1a is fixed to the epoxy substrate 16 provided with the heat radiating plate 702 as necessary with an adhesive. And the electrode on the semiconductor element 1a and the epoxy board | substrate 16 are connected with the metal fine wire 15a. The epoxy substrate 16 is electrically connected on the front surface and is electrically connected to the bumps 3 formed on the back surface of the first semiconductor device 710.

第２の半導体装置７２０は、上記第１の半導体装置７１０の封止樹脂７１５の直後の封止樹脂７１５が凝固しないうちに、この封止樹脂７１５に接するように載置される。封止樹脂７１５が凝固すると、第１の半導体装置７１０と第２の半導体装置７２０とは、一体となって固着される。
以上のように半導体装置７００によれば、第２の半導体装置は、第１の半導体装置の樹脂封止部に直接接着されており、接着剤などの別の固着材は不要であるため、工程の簡略化、コスト低減が可能である。 The second semiconductor device 720 is placed in contact with the sealing resin 715 before the sealing resin 715 immediately after the sealing resin 715 of the first semiconductor device 710 is solidified. When the sealing resin 715 is solidified, the first semiconductor device 710 and the second semiconductor device 720 are integrally fixed.
As described above, according to the semiconductor device 700, the second semiconductor device is directly bonded to the resin sealing portion of the first semiconductor device, and another fixing material such as an adhesive is not necessary. Can be simplified and the cost can be reduced.

以上、添付図面を参照しながら本発明にかかる半導体装置及びその製造方法の好適な実施形態について説明したが、本発明はかかる例に限定されない。当業者であれば、特許請求の範囲に記載された技術的思想の範疇内において各種の変更例または修正例に想到し得ることは明らかであり、それらについても当然に本発明の技術的範囲に属するものと了解される。   The preferred embodiments of the semiconductor device and the manufacturing method thereof according to the present invention have been described above with reference to the accompanying drawings, but the present invention is not limited to such examples. It is obvious for those skilled in the art that various modifications or modifications can be conceived within the scope of the technical idea described in the claims, and these are naturally within the technical scope of the present invention. It is understood that it belongs.

実施例１にかかる半導体装置の説明図である。1 is an explanatory diagram of a semiconductor device according to Example 1. FIG. 第１の半導体装置の製造方法の説明図である。It is explanatory drawing of the manufacturing method of a 1st semiconductor device. 第２の半導体装置の製造方法の説明図である。It is explanatory drawing of the manufacturing method of a 2nd semiconductor device. 実施例１にかかる半導体装置の応用例の説明図である。FIG. 10 is an explanatory diagram of an application example of the semiconductor device according to Example 1; 実施例２にかかる半導体装置の説明図である。7 is an explanatory diagram of a semiconductor device according to Example 2. FIG. 実施例３にかかる半導体装置の説明図である。FIG. 10 is an explanatory diagram of a semiconductor device according to Example 3. 実施例４にかかる半導体装置の説明図である。FIG. 10 is an explanatory diagram of a semiconductor device according to Example 4; 実施例４にかかる半導体装置の応用例の説明図である。FIG. 10 is an explanatory diagram of an application example of the semiconductor device according to Example 4; 実施例５にかかる半導体装置の説明図である。FIG. 10 is an explanatory diagram of a semiconductor device according to Example 5; 実施例６にかかる半導体装置の説明図である。FIG. 10 is an explanatory diagram of a semiconductor device according to Example 6; 実施例７にかかる半導体装置の説明図である。FIG. 10 is an explanatory diagram of a semiconductor device according to Example 7. 従来の半導体装置の説明図である。It is explanatory drawing of the conventional semiconductor device. 従来の半導体装置の製造方法の説明図である。It is explanatory drawing of the manufacturing method of the conventional semiconductor device. 従来の半導体装置の問題点の説明図である。It is explanatory drawing of the problem of the conventional semiconductor device. 従来の半導体装置の問題点の説明図である。It is explanatory drawing of the problem of the conventional semiconductor device.

符号の説明Explanation of symbols

１ａ、１ｂ：半導体素子
２：配線
３、３ｂ：バンプ
５ａ、５ｂ：封止樹脂
１３：プリント基板
１４：配線
１５：金属配線
１６：エポキシ基板
１７：スルーホール
１００、２００、・・・、７００、１００'、４００'：半導体装置
１１０、２１０、・・・、７１０、１１０'、４１０'：第１の半導体装置
１２０、２２０、・・・、７２０：第２の半導体装置
１１５：接着剤
２１５：座繰り部
３１５：低分子接着剤
４１５：はんだ
５１５：熱伝導性接着部材
６１５：高融点はんだ
７１５：封止樹脂 DESCRIPTION OF SYMBOLS 1a, 1b: Semiconductor element 2: Wiring 3, 3b: Bump 5a, 5b: Sealing resin 13: Printed circuit board 14: Wiring 15: Metal wiring 16: Epoxy board 17: Through hole 100, 200, ..., 700, 100 ', 400': Semiconductor devices 110, 210, ..., 710, 110 ', 410': First semiconductor devices 120, 220, ..., 720: Second semiconductor devices 115: Adhesives 215: Countersink 315: Low molecular adhesive 415: Solder 515: Thermally conductive adhesive member 615: High melting point solder 715: Sealing resin

Claims (11)

複数の第１の電極が形成された第１の面を有する第１の半導体素子上に該第１の電極と電気的に接続された第１の端子が形成されると共に、前記第１の端子が露出されるように第１の封止樹脂が形成された第１の半導体装置と、
複数の第２の電極が形成された第２の面を有する第２の半導体素子上に該第２の電極と電気的に接続された第２の端子が形成されると共に、前記第２の端子が露出されるように第２の封止樹脂が形成された第２の半導体装置とを有し、
一方で前記第１の端子上にバンプが形成されており、他方では、前記第１の端子上に前記第２の端子が接合材とを介して接続されていることを特徴とする半導体装置。 A first terminal electrically connected to the first electrode is formed on a first semiconductor element having a first surface on which a plurality of first electrodes are formed, and the first terminal A first semiconductor device in which a first sealing resin is formed so as to be exposed;
A second terminal electrically connected to the second electrode is formed on a second semiconductor element having a second surface on which a plurality of second electrodes are formed, and the second terminal And a second semiconductor device in which a second sealing resin is formed so as to be exposed,
On the other hand, a bump is formed on the first terminal, and on the other hand, the second terminal is connected to the first terminal via a bonding material. 前記第１の半導体装置の前記第１の封止樹脂上から前記第２の半導体装置の前記第２の面と対向する面までの距離は、前記第１の半導体装置の前記第１の封止樹脂上から前記バンプの先端までの距離よりも短いことを特徴とする請求項１に記載の半導体装置。   The distance from the first sealing resin of the first semiconductor device to the surface facing the second surface of the second semiconductor device is the first sealing of the first semiconductor device. 2. The semiconductor device according to claim 1, wherein the distance is shorter than a distance from the top of the resin to the tip of the bump. 前記接合材の融点は、前記バンプの融点より高いことを特徴とする請求項１または請求項２のいずれかに記載の半導体装置。   The semiconductor device according to claim 1, wherein a melting point of the bonding material is higher than a melting point of the bump. 前記第２の電極が形成されていない面には、前記基板上に形成された前記バンプの搭載先と接着される接着部材が形成されていることを特徴とする請求項１〜３のいずれかに記載の半導体装置。   4. The adhesive member bonded to a mounting destination of the bump formed on the substrate is formed on a surface on which the second electrode is not formed. 5. A semiconductor device according to 1. 前記第１の半導体素子上に形成された前記第１の封止樹脂の側面には、切断によって形成された切断面を有することを特徴とする請求項１〜４のいずれかに記載の半導体装置。   5. The semiconductor device according to claim 1, wherein a side surface of the first sealing resin formed on the first semiconductor element has a cut surface formed by cutting. . 前記第２の半導体素子上に形成された前記第２の封止樹脂の側面には、切断によって形成された切断面を有することを特徴とする請求項１〜５のいずれかに記載の半導体装置。   6. The semiconductor device according to claim 1, wherein a side surface of the second sealing resin formed on the second semiconductor element has a cut surface formed by cutting. . 前記第１の電極と前記第１の端子の電気的接続は、第１の再配線により接続されていることを特徴とする請求項１〜６のいずれかに記載の半導体装置。   The semiconductor device according to claim 1, wherein the first electrode and the first terminal are electrically connected by a first rewiring. 前記第２の電極と前記第２の端子の電気的接続は、第２の再配線により接続されていることを特徴とする請求項１〜７のいずれかに記載の半導体装置。   The semiconductor device according to claim 1, wherein electrical connection between the second electrode and the second terminal is connected by a second rewiring. 複数の第１の電極が形成された第１の面を有する第１の半導体素子上に該第１の電極と電気的に接続された第１の端子が形成されると共に、前記第１の端子が露出されるように封止樹脂が形成された第１の半導体装置と、
前記第１の端子の一部に接続されたバンプと、
前記バンプが形成されていない前記第１の端子と電気的に接続される第２の電極を第２の面上に形成した第２の半導体素子と、
を有することを特徴とする半導体装置。 A first terminal electrically connected to the first electrode is formed on a first semiconductor element having a first surface on which a plurality of first electrodes are formed, and the first terminal A first semiconductor device in which a sealing resin is formed so as to be exposed;
A bump connected to a part of the first terminal;
A second semiconductor element formed on a second surface with a second electrode electrically connected to the first terminal on which the bump is not formed;
A semiconductor device comprising: 前記第１の電極と前記第１の端子の電気的接続は、第１の再配線により接続されていることを特徴とする請求項８に記載の半導体装置。   The semiconductor device according to claim 8, wherein the first electrode and the first terminal are electrically connected by a first rewiring. 前記第１の半導体素子上に形成された前記第１の封止樹脂の側面には、切断によって形成された切断面を有することを特徴とする請求項９または請求項１０のいずれかに記載の半導体装置。   11. The side surface of the first sealing resin formed on the first semiconductor element has a cut surface formed by cutting. 11. Semiconductor device.
JP2005276525A 2005-09-22 2005-09-22 Semiconductor device Pending JP2006013555A (en)

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Cited By (2)

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JP2014030042A (en) * 2008-09-08 2014-02-13 Intel Corp Computing system and method therefor
US8748229B2 (en) 2008-06-11 2014-06-10 Fujitsu Semiconductor Limited Manufacturing method including deformation of supporting board to accommodate semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
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US8748229B2 (en) 2008-06-11 2014-06-10 Fujitsu Semiconductor Limited Manufacturing method including deformation of supporting board to accommodate semiconductor device
JP2014030042A (en) * 2008-09-08 2014-02-13 Intel Corp Computing system and method therefor
US10251273B2 (en) 2008-09-08 2019-04-02 Intel Corporation Mainboard assembly including a package overlying a die directly attached to the mainboard
US10555417B2 (en) 2008-09-08 2020-02-04 Intel Corporation Mainboard assembly including a package overlying a die directly attached to the mainboard

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