JP2005353949A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To shorten the time required for wiring at automatic pattern layout design of a semiconductor integrated circuit, and to prevent an MOS transistor from being damaged by the effect of a process antenna. <P>SOLUTION: The semiconductor integrated circuit comprises a circuit block 10, and an MOS transistor M3 which is connected to the gate of an output terminal Pout of the circuit block through an external metal wiring 15. The internal metal wiring IM1 comprises a first wiring 11 connected to the output terminal Pout of an inverter INV1, a second wiring 12 connected to the output terminal Pout, and a third wiring 13 which is the wiring of upper layer than the first wiring 11 and the second wiring 12 and connects the first wiring 11 to the second wiring 12 through a via. It connects a diode D1 between the end of the second wiring 12 and a ground potential through two vias VIA6 and VIA7. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit in which damage to a MOS transistor due to a process antenna effect is suppressed.

  Conventionally, in a plasma process that realizes microfabrication of a semiconductor integrated circuit, a charge-up phenomenon that causes destruction of a semiconductor element and a decrease in reliability has been a problem. A process antenna effect is known as a kind of charge-up phenomenon.

  In the case of the conventional Al wiring process, this process antenna effect is obtained by patterning a resist on the metal layer, and etching the metal layer when processing the metal wiring by plasma etching the metal layer using the resist as a mask. The gate oxide film of the MOS transistor is damaged by the electric charge charged from the surface, and the destruction and reliability of the MOS transistor are deteriorated.

  In the case of a damascene process for Cu wiring used in recent miniaturization processes, during plasma CVD for forming an oxide film as a cap layer on the upper surface of the metal layer, charging is performed from the upper surface of the metal layer on which the oxide film is formed. Similarly, the gate oxide film of the MOS transistor is damaged by the generated charge.

Measures for preventing such process antenna effects include measures for pattern layout design in addition to measures for process technology. As a measure in designing the pattern layout, as shown in FIG. 3, the length L of the metal wiring 50 is set to a predetermined value or less according to the area of the diffusion layer D connected to the metal wiring 50 and the gate G of the MOS transistor 51. There are measures such as designing so as to satisfy the design rule to be regulated, or connecting the diode 52 to the metal wiring 50 to release the charge charged in the resist on the metal wiring to the semiconductor substrate 53.
JP 2000-150607 A JP 2003-209172 A

  However, with the miniaturization of the semiconductor integrated circuit process, it is effective to connect a diode to the end of the metal wiring or capture the design rule for the length of the metal wiring at only one layer level in the metal wiring forming process. There are many cases where process antenna effect countermeasures cannot be taken. In particular, when a circuit block called hard IP and its external circuit are connected by metal wiring through the input / output terminals of the circuit block, the metal wiring structure of the circuit block and its external circuit influences the process antenna effect. On the other hand, there is a problem that it is difficult to simply take effective measures, the wiring processing in the automatic pattern layout design becomes complicated, and the wiring work time becomes very long.

  Therefore, a semiconductor integrated circuit according to the present invention includes an output circuit, an output terminal, a circuit block including an internal wiring connecting the output circuit and the output terminal, and a MOS transistor outside the output terminal and the circuit block. The internal wiring includes a first wiring connected to the output circuit, a second wiring connected to the output terminal, the first wiring, and the first wiring. 2 wirings are connected via vias, and the first wiring and a third wiring that is a wiring higher than the second wiring, and a diode is connected between the second wiring and a fixed potential. It is characterized by connecting.

  According to another aspect of the present invention, there is provided a semiconductor integrated circuit comprising: an input circuit; an input terminal; a circuit block including an internal wiring connecting the input circuit and the input terminal; and an MOS transistor outside the input terminal and the circuit block. The internal wiring includes a first wiring connected to the input circuit, a second wiring connected to the input terminal, the first wiring, and the first wiring. 2 wirings are connected via vias, and the first wiring and a third wiring which is a wiring higher than the second wiring are formed, and a diode is connected between the first wiring and a fixed potential. It is characterized by connecting.

  According to the present invention, since the influence on the process antenna effect of the circuit block and the external metal wiring structure is separated, the design for preventing the process antenna effect at the time of designing the automatic pattern layout of the semiconductor integrated circuit. The rule can be easily fixed, the wiring work time can be shortened, and the damage to the MOS transistor due to the process antenna effect can be prevented at the time of manufacturing the semiconductor integrated circuit.

  Next, a semiconductor integrated circuit according to the first embodiment of the present invention will be described with reference to the layout diagram of FIG. This semiconductor integrated circuit includes a circuit block 10 called a circuit IP, and a MOS transistor M3 connected to a gate via an external metal wiring 15 at an output terminal Pout of the circuit block. The circuit block 10 is connected to an output terminal Pout via an internal metal wiring IM1 and an inverter INV1 (consisting of a P-channel MOS transistor M1 and an N-channel MOS transistor M2) as an output circuit, and the output of the inverter INV1. The

  The internal metal wiring IM1 connects the first wiring 11 connected to the output terminal Pout of the inverter INV1, the second wiring 12 connected to the output terminal Pout, the first wiring 11 and the second wiring 12 via. And is composed of a first wiring 11 and a third wiring 13 that is an upper layer wiring than the second wiring 12. Here, the end of the first wiring 11 is connected to the end of the third wiring 13 through three vias VIA1, VIA2, and VIA3 arranged in the vertical direction. The via is a connection electrode embedded in a via hole opened in an interlayer insulating film (not shown). In this embodiment, the third wiring 13 is a fourth layer metal wiring, but is preferably the uppermost layer wiring used in the circuit block 10.

  The other end of the third wiring 13 is connected to the end of the second wiring 12 which is a second-layer metal wiring lowered by two layers via two vias VIA4 and VIA5. Here, the other end of the third wiring 13 may be connected to the second wiring 12 through only one via VIA 4, that is, lowered by one layer. A diode D1 is connected between the end of the second wiring 12 and the ground potential via two vias VIA6 and VIA7.

  According to the layout configuration of the semiconductor integrated circuit described above, the influence of the circuit block 10 and the external metal wiring structure on the process antenna effect is separated. The prevention measures can be taken separately for the inside of the block 10 and the outside thereof.

  That is, when the external metal wiring 15 connected to the output terminal Pout is formed at the time of manufacturing the semiconductor integrated circuit, the external metal wiring 15 is connected to the diode D1 via the second metal wiring 12 in the circuit block 10. By being connected, measures to prevent the process antenna effect are taken. In this manufacturing stage, since the upper layer wiring is not formed, the external metal wiring 15 is separated from the inverter INV1. Therefore, the length of the external metal wiring 15 may be determined based on a design rule considering the gate area of the MOS transistor M3 connected thereto. The second wiring 12 and the third wiring 13 are preferably designed with a minimum design rule in order to minimize charge accumulation due to charge-up.

  Next, a semiconductor integrated circuit according to a second embodiment of the present invention will be described with reference to the layout diagram of FIG. This semiconductor integrated circuit includes a circuit block 20 called a circuit IP and a MOS transistor M6 connected to a gate via an external metal wiring 25 at an input terminal Pin of the circuit block. The circuit block 20 has an inverter INV2 (consisting of a P-channel MOS transistor M4 and an N-channel MOS transistor M5) as an input circuit, and an output of the inverter INV2 is connected to an output terminal Pout via an internal metal wiring IM. The

  The internal metal wiring IM2 connects the first wiring 21 connected to the input terminal Pin of the inverter INV2, the second wiring 22 connected to the input terminal Pin, the first wiring 21 and the second wiring 22 via. And is composed of a first wiring 21 and a third wiring 23, which is a wiring above the second wiring 22. Here, the end of the first wiring 11 is connected to the end of the third wiring 23 through three vias VIA11, VIA12, and VIA13 arranged in the vertical direction. A diode D2 is connected between the end of the first wiring 21 and the ground potential via the via VIA14.

  In this embodiment, the third wiring 23 is a fourth layer metal wiring, but is preferably the uppermost layer wiring used in the circuit block 20. The other end of the third wiring 23 is connected to the end of the second wiring 22 which is a second-layer metal wiring lowered by two layers via two vias VIA15 and VIA16. Here, the other end of the third wiring 23 may be connected to the second wiring 22 via only one via VIA 15, that is, lowered by one layer.

  According to the layout configuration of the semiconductor integrated circuit, the influence of the circuit block 20 and the external metal wiring structure on the process antenna effect is separated. The prevention measures can be taken separately for the inside of the block 20 and the outside thereof.

  That is, when the external metal wiring 25 connected to the input terminal Pout is formed at the time of manufacturing the semiconductor integrated circuit, the upper layer wiring is not formed, and thus the external metal wiring 25 is separated from the inverter INV2. Therefore, the length of the external metal wiring 25 may be determined based on a design rule considering the gate area of the MOS transistor M5 connected thereto. On the other hand, since the diode D2 is connected to the end of the first wiring 21 connected to the input terminal of the inverter INV2 in the circuit block 20, measures for preventing the process antenna effect are taken. Note that the second wiring 22 and the third wiring 23 are preferably designed with a minimum design rule as in the first embodiment.

1 is a layout diagram of a semiconductor integrated circuit according to a first embodiment of the present invention. FIG. 6 is a layout diagram of a semiconductor integrated circuit according to a second embodiment of the present invention. It is a figure for demonstrating the countermeasure which prevents the conventional process antenna effect.

Explanation of symbols

IM1, IM2 Internal wiring 15, 25 External wiring INV1, INV2 Inverter D1, D2 Diode

Claims (3)

A semiconductor comprising an output circuit, an output terminal, a circuit block comprising an internal wiring for connecting the output circuit and the output terminal, and an external wiring for connecting the output terminal and a MOS transistor outside the circuit block In integrated circuits,
The internal wiring connects the first wiring connected to the output circuit, the second wiring connected to the output terminal, the first wiring and the second wiring through vias, and the first wiring 1. A semiconductor integrated circuit comprising a first wiring and a third wiring that is a higher layer wiring than the second wiring, wherein a diode is connected between the second wiring and a fixed potential. A semiconductor comprising an input circuit, an input terminal, a circuit block comprising an internal wiring connecting the input circuit and the input terminal, and an external wiring connecting the input terminal and a MOS transistor outside the circuit block In integrated circuits,
The internal wiring connects the first wiring connected to the input circuit, the second wiring connected to the input terminal, the first wiring and the second wiring through vias, and the first wiring 1. A semiconductor integrated circuit comprising: a first wiring and a third wiring that is a higher layer wiring than the second wiring, wherein a diode is connected between the first wiring and a fixed potential. 3. The semiconductor integrated circuit according to claim 1, wherein the second wiring is an uppermost wiring used in the circuit block.

Images