JP2005353663A - Semiconductor device manufacturing method and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To manufacture a highly reliable semiconductor device that suppresses generation and growth of fluoride on a wiring layer and a pad surface, suppresses an increase in connection resistance, has a good appearance with respect to a pad, and does not reduce bonding or bump strength. A method and a semiconductor device are provided.
A contact hole is formed in an interlayer insulating film, a barrier metal is formed, and then a main wiring metal member is formed of Al. The surface of the main wiring metal member 152 is covered with a metal oxide layer (Al ₂ O ₃ film) 153. This suppresses the reaction between Al and fluoride. The metal oxide layer 153 also functions as an antireflection film. A via hole 18 is formed on the interlayer insulating film 132, and the metal oxide layer 153 is exposed at the bottom. The metal oxide layer 153 at the bottom of the via hole 18 is removed using an etching solution having a low Al erodibility. As a result, the resistance is reduced and the flat wiring connection portion 19 having a relatively small surface roughness is formed.
[Selection] Figure 1

Description

  The present invention relates to semiconductor device manufacturing, and more particularly to a method of manufacturing a semiconductor device that involves hole connection required for multilayer wiring of an integrated circuit and pad formation for external connection.

  Integrated circuit wiring in a semiconductor device is composed of multiple layers of Al wiring mainly composed of Al, and is accompanied by hole connection such as contact holes and via holes. This Al wiring is actually known to have an Al—Cu structure, an Al—Si structure, or an Al—Si—Cu structure containing a very small amount of Cu or Si. A pad for external connection is formed on the uppermost layer of these Al wiring layers. The pad is a connection area for bonding pads and metal bumps.

In forming the holes and pads, a photolithography process is performed on the insulating film. That is, after the resist coating, exposure, development, and a series of resist pattern forming steps, an etching step is performed. This etching process uses a parallel plate etching apparatus such as an RIE (reactive ion etching) apparatus. The reaction gas is a fluoride gas such as C ₄ F ₈ , CHF ₃ , SF ₆ , or CF ₄ and is processed under a reduced pressure of, for example, 1.3 Pa or more and less than 100 Pa.

Further, when an antireflection film for improving the lithography processing accuracy is formed on the Al wiring surface, it is necessary to remove the via connection portion and the pad surface. If the antireflection film is formed of a nitride film or the like, it is also etched away using a fluoride gas such as CF ₄ .

  As described above, a fluoride gas is used as a reaction gas for etching the insulating film and removing the antireflection film when forming holes and pads. Therefore, the fluoride gas remains as an atmosphere when forming holes and pads, and is also taken into the resist. Over time, the fluorine component easily reacts with Al, oxygen in the atmosphere, and moisture to generate crystalline foreign matters, that is, fluorides. This fluoride remains and grows even after an ashing process for removing the resist. As a result, fluoride on the Al surface at the bottom of the hole causes an increase in via hole connection resistance. Also in the pad, the appearance abnormalities caused by fluoride on the Al surface, bonding wire peeling (decrease in bond lift strength) or bump strength is caused.

Conventionally, as a countermeasure against fluoride on the Al surface, there is a method of removing the fluoride surface by sputter etching of Ar (see, for example, Patent Document 1).
Japanese Patent Laid-Open No. 5-82653 (FIG. 1)

  The physical etching of Ar to remove the fluoride on the Al surface forms an uneven surface. For this reason, there are still concerns about an increase in resistance that causes insufficient contact in the recesses and a problem of poor appearance with respect to the pads. Further, it may be possible to remove the fluoride by baking (heat treatment), but if the Al wiring contains Cu, there is a concern about precipitation of Cu. As a result, poor appearance, bonding and bump strength decrease.

  The present invention has been made in consideration of the above-mentioned circumstances, suppresses the generation and growth of fluoride on the wiring layer and the pad surface, suppresses an increase in connection resistance, and has a good appearance with respect to the pad. Another object of the present invention is to provide a highly reliable method of manufacturing a semiconductor device and a semiconductor device that do not reduce the bump strength.

  A method of manufacturing a semiconductor device according to the present invention includes a step of forming a metal member including a main wiring metal over an element provided on a semiconductor substrate via an interlayer insulating film, and covering the surface of the metal member with at least a metal oxide layer. A step of patterning the metal member, and a wet etching step of removing a predetermined region of the metal oxide layer to expose the surface of the metal member.

  According to the semiconductor device manufacturing method of the present invention, the metal member surface is coated with at least the metal oxide layer. As a result, the influence of fluoride generation at the time of etching the interlayer insulating film does not reach the surface of the connection portion to be formed later. In addition, the wet etching process does not induce a resistance increase factor (abnormality due to charge or reactive organisms) on the surface of the metal member.

  A method of manufacturing a semiconductor device according to the present invention includes a step of forming an interlayer insulating film covering a plurality of elements on a semiconductor substrate, a step of forming a conductive member mainly composed of aluminum on at least the interlayer insulating film, Introducing oxygen into the conductive member surface to form an amorphous metal oxide layer on the conductive member; patterning the conductive member coated with the metal oxide layer; and coating the metal oxide layer. Forming an insulating film on the conductive member; removing the insulating film in a predetermined region; exposing the metal oxide layer; selectively removing the metal oxide layer; And a wet etching process for exposing the surface of the conductive member.

  According to the method for manufacturing a semiconductor device according to the present invention, the metal oxide layer having an amorphous structure is formed on the conductive member before patterning the conductive member containing aluminum as a main component. Thereby, the influence of fluoride generation at the time of patterning the interlayer insulating film does not reach the surface of the connection portion to be formed later. In addition, the wet etching process does not induce an increase in resistance on the surface of the conductive member (abnormality due to charge or reactive organisms). The metal oxide layer having an amorphous structure is also useful as an antireflection film.

The semiconductor device according to the present invention preferably has the following characteristics.
The step of forming the metal oxide layer includes at least an O ₂ plasma treatment and a heat treatment.
Alternatively, the step of forming the metal oxide layer includes at least an O ₂ plasma treatment, a heat treatment, and an ion implantation treatment of an inert gas.
With respect to the above characteristics, when the conductive member contains a small amount of Cu, it is necessary to consider that the heat treatment should avoid the range of 250 to 350 ° C. in order to avoid Cu precipitation, or should not remain in this temperature range for a long time. In addition, the addition of an inert gas ion implantation process has the effect of making the surface of the metal oxide layer more completely amorphous.

  A method of manufacturing a semiconductor device according to the present invention includes a step of forming an interlayer insulating film covering a plurality of elements on a semiconductor substrate, a step of forming a conductive member mainly composed of aluminum on at least the interlayer insulating film, Forming a metal member having occlusion performance on the conductive member; introducing oxygen into the metal member to form a metal oxide layer on the conductive member; and the conductive member coated with the metal oxide layer. Patterning, forming an insulating film on the conductive member coated with the metal oxide layer, removing a predetermined area of the insulating film to expose the metal oxide layer, and the metal oxide layer A wet etching step of selectively removing the surface of the conductive member and exposing the surface of the conductive member to the bottom of the predetermined region.

  According to the semiconductor device manufacturing method of the present invention, the metal oxide layer is formed including the metal member occluded with oxygen on the conductive member before patterning the conductive member. Thereby, the influence of fluoride generation at the time of patterning the interlayer insulating film does not reach the surface of the connection portion to be formed later. In addition, the wet etching process does not induce an increase in resistance on the surface of the conductive member (abnormality due to charge or reactive organisms). In addition, it is preferable that the metal oxide layer as the uppermost layer of the conductive member also functions as an antireflection film.

The semiconductor device according to the present invention preferably has the following characteristics.
The step of forming the metal oxide layer includes at least an O ₂ plasma treatment and a hydrogen sintering treatment.
With respect to the above characteristics, when the conductive member contains a small amount of Cu, it is necessary to consider that the heat treatment should avoid the range of 250 to 350 ° C. in order to avoid Cu precipitation, or should not remain in this temperature range for a long time.

  In the semiconductor device manufacturing method according to the present invention, the surface of the conductive member is formed as a connection portion of a wiring layer. Alternatively, the surface of the conductive member is formed as a pad portion for connecting an external terminal. The manufacturing cost is low, the connection strength is high, and a highly reliable connection portion contributing to low resistance can be configured.

  A semiconductor device according to the present invention includes an interlayer insulating film, a hole that penetrates the insulating film and exposes a conductive member related to a lower layer wiring at a bottom, and a conductive member related to an upper layer wiring embedded in the hole , And at least an upper portion of the conductive member related to the lower layer wiring is covered with a metal oxide layer except for a connection portion with the conductive member related to the upper layer wiring.

  The semiconductor device according to the present invention includes a protective film and an opening that penetrates the protective film and exposes a conductive member related to the wiring at a bottom portion, and at least an upper portion of the conductive member is a region of the opening. It is coat | covered with the metal oxide layer except for.

  According to each of the semiconductor devices according to the present invention, the upper portion of the conductive member is covered with the metal oxide layer, and the metal oxide layer is removed only for the portion related to the connection in order to reduce the resistance. The metal oxide layer functions as a protective film that suppresses the formation of fluoride and as an antireflection film in the photolithography process. A highly reliable connection portion that contributes to high connection strength and low resistance is formed.

In each of the semiconductor devices according to the present invention, preferably, a low-resistance connection portion having a simple structure and high connection strength is provided, which has any of the following characteristics.
The conductive member is a metal member containing Al as a main component, and the metal oxide layer is an Al ₂ O ₃ film having an amorphous structure.
The conductive member is a metal member containing Al as a main component, and the metal oxide layer has a configuration in which a TiO ₂ layer is present as the uppermost layer of the Al ₃ Ti layer in which Al ₂ O ₃ is contained in the grain boundary.

BEST MODE FOR CARRYING OUT THE INVENTION

1A to 1E are cross-sectional views showing the main part of the method for manufacturing a semiconductor device according to the first embodiment of the present invention in the order of steps.
As shown in FIG. 1A, a first interlayer insulating film 131 is formed on an element 12 having an insulating gate provided on a semiconductor substrate 11. A necessary contact hole 14 for a diffusion layer (not shown) is formed in the interlayer insulating film 131 through a photolithography process. Next, after forming the barrier metal 151, the main wiring metal member 152 is formed. The barrier metal 151 has a Ti / TiN laminate or the like, and the main wiring metal member 152 has an Al—Cu structure containing a small amount of Cu (about 0.5%). The barrier metal 151 and the main wiring metal member 152 can be formed by using, for example, a sputtering method or a CVD (chemical vapor deposition) method.

Next, as shown in FIG. 1B, the surface of the main wiring metal member 152 is covered with a metal oxide layer 153. Various metal oxide layers 153 are conceivable. Here, an Al ₂ O ₃ film having an amorphous structure is formed. For example, oxygen is introduced into Al of the main wiring metal member 152 in an O ₂ plasma atmosphere. Thereafter, heat treatment is performed to form a thin metal oxide layer (Al ₂ O ₃ film) having a thickness of _{3 to 10} nm. The metal oxide layer 153 suppresses the reaction between Al and fluoride.

There are many conditions for the O ₂ plasma treatment for forming the metal oxide layer 153. For example, the conditions are set appropriately from the following condition ranges. Under a reduced pressure of 13 to 40 Pa, an O ₂ gas flow rate of 20 to 100 SCCM, an RF power of 100 to 250 W, and a processing time range from 30 seconds to 3 minutes.

  Moreover, heat processing shall be performed at 150 degrees C or less. Bake treatment for 30 minutes to 1 hour may be performed to promote oxidation into Al. Such heat treatment avoids the range of 250-350 ° C. to prevent Cu precipitation. Or it is important not to stay in this temperature range for a long time. As described above, the thin metal oxide layer 153 having a thickness of about 3 to 10 nm is an amorphized film.

Note that after the metal oxide layer 153 is formed, an inert gas ion implantation treatment may be further performed. For example, an ion implantation process of an inert gas such as Ar with an acceleration voltage of 5 to 10 keV is performed. Thereby, the metal oxide layer 153 has a more complete amorphous surface, and the reaction suppressing effect between Al and fluoride increases.
Through these steps, the conductive member 15 including the barrier metal 151, the main wiring metal member 152, and the metal oxide layer 153 is formed.

Next, as shown in FIG. 1C, a resist pattern 16 is formed on the conductive member 15 covered with the metal oxide layer 153 through a photolithography process. According to the resist pattern 16, the conductive member 15 is etched to form a wiring pattern. At this time, the Al ₂ O ₃ film of the metal oxide layer 153 also functions as an antireflection film. Thereby, favorable wiring patterning is achieved.

  Next, as shown in FIG. 1D, a second interlayer insulating film 132 that covers the patterned conductive member 15 is formed by CVD. Next, a resist pattern 17 is formed on the interlayer insulating film 132 by photolithography. In accordance with the resist pattern 17, the interlayer insulating film 132 is etched to form the via hole 18. The metal oxide layer 153 on the upper surface of the conductive member 15 is exposed at the bottom of the via hole 18. Here, the metal oxide layer 153 functions as an etching stopper.

A parallel plate etching apparatus such as an RIE (reactive ion etching) apparatus is used for the etching process of the interlayer insulating film 132 for forming the via hole 18. At this time, a fluoride gas such as C ₄ F ₈ , CHF ₃ , SF ₆ , or CF ₄ is used as the reaction gas. Therefore, the fluoride gas remains as an atmosphere and is taken into the resist (17). However, since the metal oxide layer 153 is coated on the conductive member 15, reaction generation between Al and fluoride on the wiring surface of the conductive member 15 can be suppressed almost.

Next, as shown in FIG. 1D, the resist pattern 17 is removed. Thereafter, the metal oxide layer 153 at the bottom of the via hole 18 is removed using an etching solution having a low Al erosion property. As a result, the resistance is reduced and the flat wiring connection portion 19 having a relatively small surface roughness is formed. As a specific example of the etching solution, a mixed solution of HF + NH ₄ F + CH ₃ COOHHF is used, and the amount ratio thereof is, for example, NH ₄ F: CH ₃ COOH = 1: 10: 5.

According to the method of the above embodiment, as the conductive member 15 mainly composed of aluminum, an extremely thin metal oxide layer (Al ₂ O ₃ film) 153 having an amorphous structure is formed on the upper surface thereof. Thereby, the influence of fluoride generation at the time of patterning of the interlayer insulating film 132 does not reach the surface of the wiring connection portion 19 to be formed later. Further, the wiring connection portion 19 is formed by wet etching without using dry etching. As a result, a resistance increase factor on the surface of the conductive member, that is, charging due to plasma and abnormality due to reactive organisms are not induced. Thereby, a highly reliable wiring connection part contributing to high connection strength and low resistance is formed.

The amorphous metal oxide layer (Al ₂ O ₃ film) 153 is also useful as an antireflection film, and contributes to the patterning accuracy of the conductive member 15. Further, a lamination process as an antireflection film such as a nitride film or titanium nitride can be omitted. For this reason, it is not necessary to consider the performance of the processing apparatus used for forming the antireflection film, which leads to simplification of the production of the wiring member.

2A and 2B are cross-sectional views showing the main part of the method of manufacturing a semiconductor device according to the second embodiment of the present invention in the order of steps.
In the first embodiment, as the conductive member 15 mainly composed of aluminum, the metal oxide layer 153 disposed on the upper surface of the conductive member 15 has been described to form an extremely thin Al ₂ O ₃ film having an amorphous structure.
In the second embodiment, the metal oxide layer 253 disposed on the upper surface of the conductive member 15 having aluminum as a main component is a TiO ₂ film as the uppermost layer. Hereinafter, FIG. 2 will be described with reference to FIG.
As shown in FIG. 2A, the surface of the main wiring metal member 152 is covered with the Ti film 21. The Ti film 21 is formed by a sputtering method or a CVD method to a thickness that will be oxidized later. The Ti film 21 is a film having a high occluding property, and is provided here for the purpose of occluding oxygen and supplying oxygen to the Al surface of the main wiring metal member 152.

Next, as shown in FIG. 2B, oxygen is introduced into Al of the main wiring metal member 152 through the Ti film 21 in an O ₂ plasma atmosphere. Although there are many conditions, for example, it is set appropriately from the following condition ranges. Under a reduced pressure of 13 to 40 Pa, an O ₂ gas flow rate of 20 to 100 sccm, an RF power of 100 to 250 W, and a processing time range from 30 seconds to 3 minutes. Thereafter, heat treatment is performed. In this heat treatment, sintering is performed at 400 to 450 ° C. for 30 minutes to 3 hours in an H ₂ / Ar atmosphere. In order to prevent Cu precipitation, it is important that the range of 250 to 350 ° C. passes only when the temperature rises and falls, and does not stay long. Thereby, an Al ₃ Ti layer 211 containing Al ₂ O ₃ in the grain boundary is formed at the boundary between the main wiring metal member 152 and Al. On the Al ₃ Ti layer 211, a TiO ₂ layer 212 is present as the uppermost layer.

That is, as the metal oxide layer 153 of FIG. 1B, as shown in FIG. 2, the metal oxide having an Al ₃ Ti layer 211 containing Al ₂ O ₃ in the grain boundary and a TiO ₂ layer 212 as the uppermost layer. Layer 253 is utilized. Even if such a metal oxide layer 253 is formed, the effect of suppressing the reaction between Al and fluoride can be obtained as in the first embodiment. The Al ₃ Ti layer 211 is hardly peeled off by the alloy reaction layer. The TiO ₂ layer 212 not only becomes a film excellent in crystallinity and etching resistance by heat treatment, but also becomes a good antireflection film having a high film density.

The selective wet etching process of the metal oxide layer 253 corresponding to FIG. 1E is as follows. Similar to the first embodiment, the metal oxide layer 253 is removed by using an etching solution having low Al erodibility. For example, an etching solution made of a mixed solution of HF + NH ₄ F + CH ₃ COOHHF is used, and the amount ratio thereof is, for example, NH ₄ F: CH ₃ COOH = 1: 10: 5.

According to the method of the above embodiment, as the conductive member 15 mainly composed of aluminum, the metal oxide layer (Al ₃ Ti layer containing Al ₂ O ₃ / TiO ₂ containing Al ₂ O ₃₎ is included on the upper surface of the conductive member 15. Top layer) 253 is formed. Thereby, the influence of fluoride generation at the time of patterning the interlayer insulating film does not reach the surface of the wiring connection portion to be formed later. Further, the wiring connection portion is formed by wet etching without using dry etching. As a result, a resistance increase factor on the surface of the conductive member, that is, charging due to plasma and abnormality due to reactive organisms are not induced. Thereby, a highly reliable wiring connection part contributing to high connection strength and low resistance is formed.

Note that the TiO ₂ layer 212 becomes a film excellent in crystallinity and etching resistance by heat treatment, and acts as an excellent etching stopper. Furthermore, it becomes a good antireflection film having a high film density. This contributes to the patterning accuracy of the conductive member 15. Further, a lamination process as an antireflection film such as a nitride film or titanium nitride can be omitted. For this reason, it is not necessary to consider the performance of the processing apparatus used for forming the antireflection film, which leads to simplification of the production of the wiring member.

3A and 3B are cross-sectional views showing the main part of the method of manufacturing a semiconductor device according to the third embodiment of the present invention in the order of steps. The conductive member 15 shown in the first embodiment or the second embodiment can also be applied to a configuration including an interlayer insulating film and a wiring plug that have undergone a planarization step.
As shown in FIG. 3A, the first interlayer insulating film 311 is planarized by using a CMP (Chemical Mechanical Polishing) technique. A necessary contact hole 34 for a diffusion layer (not shown) is formed in the interlayer insulating film 311 through a photolithography process. Next, after forming the barrier metal 351, the wiring plug 352 is formed. The barrier metal 351 is a Ti / TiN stack or the like, and the wiring plug 352 is a W (tungsten) plug. In any case, film formation is possible using a sputtering method or a CVD method. Thereafter, the contact hole 34 is buried through a CMP process. Next, the conductive member 15 described in the first embodiment or the second embodiment is formed. That is, the metal oxide layer 153 (or 253) is provided as the uppermost layer.

  As shown in FIG. 3B, a wiring pattern is formed on the conductive member 15 covered with the metal oxide layer 153 (or 253) using photolithography and etching techniques. At this time, the metal oxide layer 153 (or 253) also functions as an antireflection film. Thereby, favorable wiring patterning is achieved.

  Next, a second interlayer insulating film 312 covering the patterned conductive member 15 is formed by CVD. Next, via holes 36 are formed in the interlayer insulating film 312 using photolithography and etching techniques. The upper surface of the conductive member 15, that is, the metal oxide layer 153 (or 253) remains as an etching stopper at the bottom of the via hole 36 (see the broken line). When etching the interlayer insulating film 312 for forming the via hole 36, a reactive gas of fluoride is used. Therefore, the fluoride gas remains as an atmosphere and is taken into a resist (not shown). However, since the metal oxide layer 153 (or 253) is coated on the conductive member 15, the reaction generation of Al and fluoride on the wiring surface of the conductive member 15 can be hardly suppressed.

  After the resist is removed, the metal oxide layer 153 (or 253) at the bottom of the via hole 36 is removed using an etching solution having a low Al erosion property, as in the first or second embodiment. As a result, the resistance is reduced and the flat wiring connection portion 37 having a relatively small surface roughness is formed. The wiring connection portion 37 is formed by a wet etching process without performing dry etching with plasma. This does not induce a resistance increase factor (abnormality due to charge or reactive organisms) on the surface of the wiring connection portion 37.

4A to 4C are cross-sectional views showing the main part of the method for manufacturing a semiconductor device according to the fourth embodiment of the present invention in the order of steps. The conductive member 15 shown in the first embodiment or the second embodiment can also be applied to a configuration including pad formation that opens the uppermost protective film (passivation film) of the semiconductor device.
As shown in FIG. 4A, the conductive member 15 described in the first embodiment or the second embodiment is formed on the interlayer insulating film 41 and patterned into a pad shape. The uppermost layer is provided with a metal oxide layer 153 (or 253) that also functions as an antireflection film. Next, a protective film 42 that covers the patterned conductive member 15 is formed by CVD. The protective film 42 is composed of, for example, an oxide film / plasma silicon nitride film stack.

  Next, as shown in FIG. 4B, a pad opening 43 is formed in the protective film 42 using photolithography and etching techniques. At the bottom of the opening 43, the upper surface of the conductive member 15, that is, the metal oxide layer 153 (or 253) remains as an etching stopper. At the time of etching the protective film 42 that forms the opening 43, a reactive gas of fluoride is used. Therefore, the fluoride gas remains as an atmosphere and is taken into a resist (not shown). However, since the metal oxide layer 153 (or 253) is coated on the conductive member 15, the reaction generation of Al and fluoride on the wiring surface of the conductive member 15 can be hardly suppressed.

  After the resist is removed, the metal oxide layer 153 (or 253) at the bottom of the opening 43 is removed using an etching solution having a low Al erosion property, as in the first or second embodiment. As a result, the resistance is reduced and the flat wiring connection portion 45 having a relatively small surface roughness is formed. The wiring connection portion 45 is formed through a wet etching process without performing dry etching with plasma. This does not induce a resistance increase factor (abnormality due to charge or reactive organisms) on the surface of the wiring connection portion 45. The wiring connection portion 45 is the basis of various configurations such as wiring to the outside using bonding wires as pads and wiring to the outside via bump formation. The wiring connection portion 45 has no appearance of fluoride and has a good appearance as a pad. As a result, a highly reliable pad that does not reduce bonding or bump strength can be obtained.

  As mentioned above, according to the method of each embodiment and the structure accompanying it, the metal member surface relevant to wiring is coat | covered with a metal oxide layer at least. Thereby, the influence of fluoride generation at the time of etching of the insulating film covering the metal member does not reach the surface of the wiring connection portion to be formed later. The metal oxide layer is removed by a wet etching process to reduce the resistance of the wiring connection portion. The wet etching process does not induce abnormalities due to charge or reactive organisms unlike plasma etching. Thereby, a highly reliable wiring connection part contributing to high connection strength and low resistance is formed. As a result, the generation and growth of fluoride on the wiring layer and the pad surface are suppressed, the increase in connection resistance is suppressed, and the appearance of the pad is good, and the manufacture of a highly reliable semiconductor device that does not reduce the bonding or bump strength A method and a semiconductor device can be provided.

Sectional drawing which shows the principal part of the manufacturing method of the semiconductor device which concerns on 1st Embodiment to process order. Sectional drawing which shows the principal part of the manufacturing method of the semiconductor device which concerns on 2nd Embodiment in process order. Sectional drawing which shows the principal part of the manufacturing method of the semiconductor device which concerns on 3rd Embodiment in order of a process. Sectional drawing which shows the principal part of the manufacturing method of the semiconductor device which concerns on 4th Embodiment in order of a process.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 ... Semiconductor substrate, 12 ... Element, 131, 132, 311, 312, 41 ... Interlayer insulating film, 14, 34 ... Contact hole, 15 ... Conductive member, 151, 351 ... Barrier metal, 152 ... Main wiring metal member, 153 , 253 ... Metal oxide layer, 16, 17 ... Resist pattern, 18, 36 ... Via hole, 19, 37, 45 ... Wiring connection part, 21 ... Ti film, 221 ... Al ₃ Ti layer, 212 ... TiO ₂ layer, 352 ... Wiring plug, 42 ... protective film, 43 ... opening.

Claims (12)

Forming a metal member including a main wiring metal via an interlayer insulating film above an element provided on a semiconductor substrate;
Coating the metal member surface with at least a metal oxide layer;
Patterning the metal member;
A wet etching step of exposing the metal member surface by removing the metal oxide layer in a predetermined region;
A method of manufacturing a semiconductor device including: Forming an interlayer insulating film covering a plurality of elements on a semiconductor substrate;
Forming a conductive member mainly composed of aluminum on at least the interlayer insulating film;
Introducing oxygen into the conductive member surface to form an amorphous metal oxide layer on the conductive member;
Patterning the conductive member coated with the metal oxide layer;
Forming an insulating film on the conductive member coated with the metal oxide layer;
Removing the insulating film in a predetermined region and exposing the metal oxide layer;
A wet etching step of selectively removing the metal oxide layer and exposing the surface of the conductive member at the bottom of the predetermined region;
A method of manufacturing a semiconductor device including: The method for manufacturing a semiconductor device according to claim ₂ , wherein the step of forming the metal oxide layer includes at least an O ₂ plasma treatment and a heat treatment. The method of manufacturing a semiconductor device according to claim 2, wherein the step of forming the metal oxide layer includes at least an O ₂ plasma treatment, a heat treatment, and an ion implantation treatment of an inert gas. Forming an interlayer insulating film covering a plurality of elements on a semiconductor substrate;
Forming a conductive member mainly composed of aluminum on at least the interlayer insulating film;
Forming a metal member having occlusion performance on the conductive member;
Introducing oxygen into the metal member to form a metal oxide layer on the conductive member;
Patterning the conductive member coated with the metal oxide layer;
Forming an insulating film on the conductive member coated with the metal oxide layer;
Removing the insulating film in a predetermined region and exposing the metal oxide layer;
A wet etching step of selectively removing the metal oxide layer and exposing the surface of the conductive member at the bottom of the predetermined region;
A method of manufacturing a semiconductor device including: 6. The method of manufacturing a semiconductor device according to claim 5, wherein the step of forming the metal oxide layer includes at least an O ₂ plasma treatment and a hydrogen sintering treatment. The method for manufacturing a semiconductor device according to claim 2, wherein the conductive member surface is formed as a connection portion of a wiring layer. The method for manufacturing a semiconductor device according to claim 2, wherein the surface of the conductive member is formed as a pad portion for connecting an external terminal. An insulating film between the layers;
A hole that penetrates the insulating film and exposes a conductive member related to the lower layer wiring at the bottom;
A conductive member related to the upper layer wiring embedded in the hole;
Including
A semiconductor device in which at least an upper portion of a conductive member related to the lower layer wiring is covered with a metal oxide layer except for a connection portion with the conductive member related to the upper layer wiring. A protective film;
An opening that penetrates the protective film and exposes a conductive member related to the wiring at the bottom;
Including
A semiconductor device in which at least an upper portion of the conductive member is covered with a metal oxide layer except for the region of the opening. 11. The semiconductor device according to claim 9, wherein the conductive member is a metal member containing Al as a main component, and the metal oxide layer is an Al ₂ O ₃ film having an amorphous structure. The conductive member is a metal member containing Al as a main component, and the metal oxide layer has a structure in which a TiO ₂ layer is present as an uppermost layer of an Al ₃ Ti layer in which Al ₂ O ₃ is contained in a grain boundary. Item 11. The semiconductor device according to Item 9 or 10.

Images