JP2005340475A - Solid state imaging device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the sensitivity of a photoelectric conversion device by separately producing a salicide process and a non-salicide process in the manufacturing process of an image sensor. <P>SOLUTION: As an insulation film provided on the photodiode of a silicone substrate 1, an insulation film of four layer structure consists of an SiO<SB>2</SB>film M1, an SiO<SB>2</SB>film M2, a low voltage CVD-SiN film M3 and a plasma CVD-SiN film M4, or an insulation film of two layer structure consists of an SiO<SB>2</SB>film and a plasma CVD-SiN film. At the side wall of the gate part of an MOS transistor, a low reflection film consisting of insulation films M2, M3 and 9 of a three-layer structure using a part of the insulation film in common is realized when the insulation film has the 4 layer structure. Thus, improvement of a transistor characteristic is compatible with the improvement of the sensitivity of the photodiode. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention employs a CCD image sensor that employs both a manufacturing process that does not use silicide (non-salicide process) and a manufacturing process that uses silicide (salicide process) to reduce dark current and contact resistance. The present invention relates to a solid-state imaging device such as a CMOS image sensor, and more particularly to a structure of an insulating film formed on a photoelectric conversion element.

In recent semiconductor devices, miniaturization has progressed to follow the scaling law, and as the miniaturization progresses, salicide technology using silicide, which is a compound of silicon with cobalt, titanium, etc., is used in the semiconductor manufacturing process. ing. That is, in order to reduce parasitic resistance such as contact resistance, a method of forming contact parts in the source / drain regions of a MOS transistor with silicide is generally employed.
On the other hand, for example, in the manufacturing process of a solid-state imaging device of the 0.18 μm generation and later, both a manufacturing technique that does not use silicide (non-salicide process) and a manufacturing technique that uses silicide (salicide process) are adopted (so-called separate creation). By creating a composite function device in which a system such as an imaging unit and a circuit unit having other functions (for example, an optical communication function and a light detection function) is integrated on the same silicon substrate.
That is, a non-salicide process is applied to the production of a photodiode (photoelectric conversion element), and a salicide process is applied to the production of other parts to reduce both dark current and contact resistance. Yes.
When such a separate process is used, a method of using a laminated film of SiO / SiN as an insulating film on a silicon substrate or an insulating film for a sidewall of a gate portion of a transistor has been proposed (for example, a patent) Reference 1).
Further, it has been proposed to achieve good transistor characteristics by using a sidewall having a three-layer film of SiO / LP-SiN / SiO at the gate portion of the transistor (see, for example, Patent Document 2).
JP 2002-83949 A Public 2001-111022A

However, in the above-described conventional method using a laminated film of SiO / SiN for the insulating film, it is necessary to use thick SiO as a sidewall, and therefore the amount of etchback cannot be controlled accurately. Therefore, there is a problem that good transistor characteristics cannot be maintained.
Further, the method using a three-layer film of SiO / LP-SiN / SiO as a sidewall has a problem that the sensitivity of the photoelectric conversion element cannot be optimized.

  In view of the above, an object of the present invention is to provide a solid-state imaging device capable of making a salicide process and a non-salicide process separately and improving the sensitivity of a photoelectric conversion element.

  In order to achieve the above-described object, a solid-state imaging device of the present invention includes an imaging including a plurality of photoelectric conversion elements that generate signal charges corresponding to the amount of received light on a semiconductor substrate having both a silicide formation region and a silicide non-formation region. And an insulating film having a laminated structure including at least a SiO film and a plasma CVD-SiN film is provided on the photoelectric conversion element.

  According to the solid-state imaging device of the present invention, an SiO film and a plasma CVD-SiN film are formed on a photoelectric conversion element in a structure in which an imaging unit including a photoelectric conversion element and other circuit units are created by separately forming a salicide process and a non-salicide process. By providing an insulating film having a stacked structure including a film, it is possible to optimize the control of the film thickness of the insulating film, and to improve the sensitivity of the photoelectric conversion element while maintaining a favorable sidewall structure of the transistor. There is an effect.

In the embodiment of the present invention, as an insulating film provided on a photodiode on a silicon substrate, an insulating film having a four-layer structure of an SiO ₂ film, an SiO ₂ film, a low-pressure CVD-SiN film, and a plasma CVD-SiN film, an SiO ₂ film a three-layer structure of SiO ₂ film and a plasma CVD-SiN film, a two-layer structure of SiO ₂ film and a plasma CVD-SiN film, an insulating film of any of the structures used.
Further, when the insulating film has a four-layer structure on the side wall of the gate portion of the MOS transistor, a low-reflection film having a three-layer structure that also serves as a part of the insulating film is realized to improve the transistor characteristics and the photodiode. Both improved sensitivity.

1 is a cross-sectional view showing a laminated structure of an insulating film on a photodiode according to Embodiment 1 of the present invention, and FIG. 2 is a cross-sectional view showing an element structure of an image pickup unit of a solid-state image pickup device to which the insulating film shown in FIG. 1 is applied. FIG.
In this embodiment, a CMOS image sensor having a transistor using a three-layer film (optimum low reflection film structure) capable of obtaining good characteristics using a salicide process and a non-salicide process is used. By using the above-described four-layered film as an insulating film on a photodiode, a solid-state imaging device with good transistor characteristics and high photoelectric conversion efficiency is provided.
That is, since the structure of the surface insulating film is limited in the separate process using the three-layer sidewall, an insulating film for preventing the formation of silicide must be stacked in the silicide non-formation region (the upper surface of the photodiode).
Therefore, as shown in FIG. 1, the insulating film on the photodiode of the semiconductor substrate 1 is formed in order from the bottom, the gate insulating film (SiO ₂ film) M1 of the MOS transistor, and the first insulating film (side wall). SiO ₂ film) M 2, second insulating film (LP-SiN film, silicon nitride layer formed by low-pressure CVD) M 3 for forming sidewalls, and interlayer insulating film (P-SiN film, formed by plasma CVD) The silicon nitride layer (M4) is laminated.
Among these, the insulating films M2 and M3 are insulating films for preventing metal silicide formation. Further, the interlayer insulating film M4 also plays a role as an etching stopper when forming a contact part.
If these film thicknesses are not optimized, the sensitivity of the solid-state imaging device is lowered due to the difference in reflectance between the plurality of films stacked on the silicon substrate. Therefore, in this embodiment, this sensitivity reduction is solved by optimizing the film thickness of the interlayer insulating film M4.

Next, the element structure of the solid-state imaging device of the present embodiment shown in FIG. 2 will be described.
The solid-state imaging device of this example is formed in a well region (impurity implantation region) 3 provided on the silicon substrate 1. First, an element isolation insulating film 2 is formed above the well region 3, and a photodiode formation region 4 and a pixel transistor formation region 5 are provided in the region isolated by the element isolation insulating film 2. Yes.
The photodiode formation region 4 is provided with impurity implantation regions 7 and 11 constituting an embedded photodiode, and the pixel transistor formation region 5 is provided with an impurity implantation region 8 for LDD formation and source / drain formation. The impurity implantation region 10 is provided.
Further, the above-described insulating films M1 to M4 are disposed on the upper surface of the silicon substrate 1, the gate electrode 6 of the MOS transistor is formed on the gate insulating film M1, and a side wall serves as a sidewall. Insulating films M2 and M3 are disposed.
A planarizing film 12 is disposed on the interlayer insulating film M4, and a color filter and an on-chip microlens (not shown) are disposed on the planarizing film 12.

3 and 4 are explanatory diagrams showing the relationship between the film thicknesses of the insulating films M1 to M4 and the transmittance. The horizontal axis represents the film thickness value (nm) of M4, and the vertical axis represents the transmittance (%). .
First, as shown in FIG. 3, for example, when the total thickness of the insulating film M1 and the insulating film M2 is about 10 nm and the thickness of the insulating film M3 is about 10 nm, the optimal thickness of the insulating film M4 is About 40-45 nm. At this time, the light transmittance increases to about 95%.
Further, since the planarizing film 12 is laminated when the contact part is formed, it is necessary to perform different amounts of etching. Therefore, an etching stopper is necessary, and the insulating film M4 is used as this stopper. Therefore, when the planarization film thickness 12 is increased, the insulating film M4 must also be increased. In this case, the thickness of the insulating film M4 can be increased by stacking the insulating film M4 after the insulating film M3 is removed by etching in advance. FIG. 4 shows an example in this case. When the sum of the insulating film M1 and the insulating film M2 is 10 nm, the film thickness of the insulating film M4 is about 45 to 55 nm.

Next, FIGS. 5 to 26 are cross-sectional views showing the manufacturing process of the solid-state imaging device of the present embodiment.
First, in step 1, an element isolation insulating film 2 is formed on the semiconductor substrate 1. FIG. 5 shows a cross section of a logic circuit portion (including a signal processing circuit, a control drive circuit, and the like) using MOS transistors. The first MOS transistor region 13, the second MOS transistor region 14, A state is shown in which the third MOS transistor region 15 and the fourth MOS transistor region 16 are separated (FIG. 5).
Next, in step 2, a screen oxide film 17 for ion implantation is formed on the semiconductor substrate 1 created in step 1, and a well impurity implantation region 3 is formed by ion implantation (FIG. 6).
The well impurity implantation region 3 may be arranged so that impurities to be implanted using a photoresist method and implantation conditions (energy, impurity concentration, etc.) are assigned to each transistor region.
Next, FIG. 7 shows a cross section of the imaging unit (corresponding to the region shown in FIG. 2) when Step 1 and Step 2 are performed. Here, as step 3, the element isolation insulating film 2 is formed on the semiconductor substrate 1, and the well impurity implantation region 3 is formed by ion implantation. In FIG. 7, a photodiode formation region 4 and a pixel transistor formation region 5 are shown.
In the well impurity implantation region 3, the impurity to be implanted and the implantation conditions (energy, impurity concentration, etc.) may be determined in each element region by using a photoresist method.

Next, in step 4, the gate insulating film M1, the gate insulating film 18, and the gate electrode 6 made of polysilicon are formed on the semiconductor substrate 1 in the above step 2 (FIG. 8). FIG. 8 shows a cross section of the logic circuit portion as in FIG. In each transistor region, for example, the gate insulating film 18 may be formed to have a thickness of 3 nm, for example, the gate insulating film M1 may be formed to have a thickness of 5 nm. The film thickness of the gate electrode 6 is set to 200 nm, for example.
Next, in step 5, the gate electrode 6 in the above step 4 is shaped using, for example, a photoresist method or a dry etching method (FIG. 9).
Next, FIG. 10 shows a cross section of the imaging unit after the steps 4 and 5 described above. In step 6, in the photodiode formation region 4, the impurity implantation region 7 is formed in the photodiode region 4 by the ion implantation method using the photoresist method and the gate electrode 6 shaped in the above step 5 as a mask.

Next, in step 7, an impurity implantation region 8 for forming LDD is formed by ion implantation using the gate electrode 6 shaped in step 5 as a mask (FIG. 11). FIG. 11 is a cross-sectional view of the logic circuit portion. Impurities to be implanted and implantation conditions (energy, impurity concentration, etc.) may be determined in each transistor region by using a photoresist method.
Next, in step 8, a first insulating film M2 for forming a sidewall made of, for example, 5 nm of SiO and a sidewall made of 15 nm of LP-SiN are formed on the semiconductor substrate 1 in the above step 7. A second insulating film M3 is formed (FIG. 12).
Next, in step 9, the insulating films M2 and M3 in the above step 8 are etched by using an etch back method, and insulating films M2 and M3 serving as sidewall spacers are formed only on the side walls of the gate electrode 6. (FIG. 13).
Next, in step 10, following step 9, a third insulating film 9 for forming a sidewall is formed, and an insulating film 9 serving as a sidewall spacer is formed only on the gate sidewall using an etch-back method. Is formed (FIG. 14). The film thickness of the insulating film 9 is set to 100 nm, for example.

Next, FIG. 15 shows a cross section of the imaging unit when the above steps 7 and 8 are performed. In step 11, as in the logic circuit portion, an impurity implantation region 8 for forming an LDD is formed by ion implantation in the pixel transistor formation region 5 of the imaging portion using the gate electrode 6 as a mask.
Subsequently, insulating films M2 and M3 are formed.
Next, FIG. 16 shows a cross-sectional view of the imaging unit when the above step 9 is performed. Here, as step 12, a photoresist is formed only on the image pickup unit using the photoresist method immediately before step 9, and a sidewall is formed on the image pickup unit at the time of forming the side wall of the logic circuit unit in step 9. I'm trying not to be. Thus, the insulating film M2 and the insulating film M3 are not removed by etching.
Next, FIG. 17 shows a cross-sectional view of the imaging unit when the above step 10 is performed. Here, as the process 13, the third insulating film 9 for forming the sidewall is formed also in the pixel transistor formation region of the image pickup unit, similarly to the logic circuit unit.

Next, in step 14, following step 10, the source / drain regions 10 are formed by ion implantation using the gate electrode 6 and the side wall spacers (insulating films) M2, M3, 9 as a mask (FIG. 18).
FIG. 18 shows a cross-sectional view of the logic circuit portion, and the impurity to be implanted and the implantation conditions (energy, impurity concentration, etc.) may be determined in each transistor region by using a photoresist method.
Next, FIG. 19 is a cross-sectional view of the imaging unit when step 14 is performed. In step 15, as in the logic circuit portion, the source / drain regions are formed in the pixel transistor formation region 5 of the imaging portion by ion implantation using the gate electrode 6 and the sidewall spacers (insulating films) M2, M3, and 9 as a mask. Region 10 is formed.
At this time, the first insulating film M2 and the second insulating film M3 are formed on the source / drain of the imaging unit pixel transistor. The thickness of the first insulating film M2 is 10 nm, By setting the film thickness of the insulating film M3 to 30 nm and setting the energy of ion implantation for forming the source / drain regions to 20 keV or higher when the implanted ions are Phos +, for example, Source / drain regions can also be formed in the pixel transistor. Note that when the thickness of the second insulating film M3 is set to 30 nm, the remaining film of the second insulating film M3 in the etching process of the above step 13 becomes about 10 nm.
Furthermore, as in the example shown in FIG. 2, an impurity implantation region 7 for forming a buried photodiode may be formed on the substrate surface of the photodiode region 4 for the purpose of further reducing the junction leakage current.

Next, in Step 16, following the Step 14, the silicide layer 21 is formed on the gate electrode 6 made of polysilicon and the source / drain regions by the salicide method (FIG. 20). FIG. 20 is a cross-sectional view of the logic circuit portion.
FIG. 21 is a cross-sectional view of the imaging unit when the above step 16 is performed. Since the first insulating film M2 and the second insulating film M3 are formed on the entire surface of the imaging unit, no refractory metal silicide layer is formed on the imaging unit. This is designated as step 17.
Next, in step 18, after step 17, the interlayer insulating film M4 is formed. Here, the film thickness of the interlayer insulating film M4 is about 40 to 45 nm (FIG. 22).
Next, in step 19, the planarizing film 12 is formed after step 18 (FIG. 23). In step 20, the planarizing film 12 formed in step 19 is removed by etching (first contact hole 22). At this time, a resist is used as a mask. Etching of the planarizing film 12 ends with M4. That is, the interlayer insulating film M4 plays a role as an etching stopper. The film thickness of the interlayer insulating film M4 necessary as an etching stopper is about 40 nm or more (FIG. 24).
Next, in step 21, after step 20, contact portions are formed in the gate region, source / drain region, well region, photodiode region, and the like of the transistor (second contact hole 23). At this time, each region may be etched separately using a resist method (FIG. 25).

Next, as Example 2, the steps after Step 18 of Example 1 may be modified as follows.
First, in step 18 ′, the third insulating film 38 is removed by etching after step 17 of Example 1 (FIG. 26).
Next, in step 19 ′, after the step 18 ′, the second insulating film M3 for forming the sidewall is removed by etching (FIG. 27).
Next, in Step 20 ′, an interlayer insulating film M4 is formed after Step 17 of Example 1. The film thickness of the interlayer insulating film M4 is about 50 nm (FIG. 28).
Next, in step 21 ′, a planarizing film 12 is formed after step 20 ′ (FIG. 29).
Next, in step 22 ′, the planarizing film 12 formed in step 21 ′ is removed by etching using the resist as a mask and the interlayer insulating film M4 as a stopper (first contact hole 21). At this time, the film thickness of the interlayer insulating film M4 required as a stopper is required to be about 40 nm or more (FIG. 30).
Next, in step 23 ′, after step 22, contact portions are formed in the gate region, source / drain region, well region, photodiode region, etc. of the transistor (second contact hole 22). At this time, each may be etched separately using a resist (FIG. 31).

As described above, according to the first and second embodiments described above, it is possible to optimize the insulating film on the photodiode in the structure in which the imaging unit including the photodiode and the other circuit unit are created by separately forming the salicide process and the non-salicide process. , Quantum efficiency (photoelectric conversion efficiency) can be increased. Specifically, the quantum efficiency of a CCD image sensor or a CMOS image sensor can be increased to about 25%, light received by a photodiode can be efficiently converted to electrons, and the sensitivity of the image sensor can be improved. It becomes.
In addition, since each of the insulating films M1, M2, and M3 uses a film of a separate process, an element having a small junction leak and a MOS transistor having a high operating speed can be compatible.

In the first and second embodiments, the insulating film on the photodiode is the gate insulating film (SiO film) M1, the first insulating film (SiO film) M2 for forming the sidewall, and the sidewall forming. Although the four-layer structure of the second insulating film (LP-SiN film) M3 and the interlayer insulating film (P-SiN film) M4 is adopted, the two-layer structure is formed by removing the insulating films M2 and M3 for forming the sidewalls. Also good.
Although omitted in the description of the embodiments, for example, a circuit unit having a specific function other than an imaging function such as a MOS transistor is mounted on the logic circuit unit, for example, a circuit unit such as an optical communication device unit or an infrared detection device unit, A system integrating a plurality of functions may be configured.
Further, the specific configuration of the present invention is not limited to the above-described embodiments, and various modifications are possible. For example, a PIN photodiode or an avalanche photodiode is applied to the photodiode. Thus, responsiveness can be improved and sensitivity can be increased.

It is sectional drawing which shows the laminated structure of the insulating film provided on the photodiode of the solid-state imaging device by Example 1 of this invention. It is sectional drawing which shows the element structure of the imaging part in the solid-state imaging device of Example 1 shown in FIG. It is explanatory drawing which shows the characteristic example of the insulating film thickness and the transmittance | permeability in the solid-state imaging device of Example 1 shown in FIG. It is explanatory drawing which shows the characteristic example of the insulating film thickness and the transmittance | permeability in the solid-state imaging device of Example 1 shown in FIG. It is sectional drawing which shows the manufacturing process of the solid-state imaging device of Example 1 shown in FIG. It is sectional drawing which shows the manufacturing process of the solid-state imaging device of Example 1 shown in FIG. It is sectional drawing which shows the manufacturing process of the solid-state imaging device of Example 1 shown in FIG. It is sectional drawing which shows the manufacturing process of the solid-state imaging device of Example 1 shown in FIG. It is sectional drawing which shows the manufacturing process of the solid-state imaging device of Example 1 shown in FIG. It is sectional drawing which shows the manufacturing process of the solid-state imaging device of Example 1 shown in FIG. It is sectional drawing which shows the manufacturing process of the solid-state imaging device of Example 1 shown in FIG. It is sectional drawing which shows the manufacturing process of the solid-state imaging device of Example 1 shown in FIG. It is sectional drawing which shows the manufacturing process of the solid-state imaging device of Example 1 shown in FIG. It is sectional drawing which shows the manufacturing process of the solid-state imaging device of Example 1 shown in FIG. It is sectional drawing which shows the manufacturing process of the solid-state imaging device of Example 1 shown in FIG. It is sectional drawing which shows the manufacturing process of the solid-state imaging device of Example 1 shown in FIG. It is sectional drawing which shows the manufacturing process of the solid-state imaging device of Example 1 shown in FIG. It is sectional drawing which shows the manufacturing process of the solid-state imaging device of Example 1 shown in FIG. It is sectional drawing which shows the manufacturing process of the solid-state imaging device of Example 1 shown in FIG. It is sectional drawing which shows the manufacturing process of the solid-state imaging device of Example 1 shown in FIG. It is sectional drawing which shows the manufacturing process of the solid-state imaging device of Example 1 shown in FIG. It is sectional drawing which shows the manufacturing process of the solid-state imaging device of Example 1 shown in FIG. It is sectional drawing which shows the manufacturing process of the solid-state imaging device of Example 1 shown in FIG. It is sectional drawing which shows the manufacturing process of the solid-state imaging device of Example 1 shown in FIG. It is sectional drawing which shows the manufacturing process of the solid-state imaging device of Example 1 shown in FIG. It is sectional drawing which shows the manufacturing process of the solid-state imaging device of Example 2 of this invention. It is sectional drawing which shows the manufacturing process of the solid-state imaging device of Example 2 shown in FIG. It is sectional drawing which shows the manufacturing process of the solid-state imaging device of Example 2 shown in FIG. It is sectional drawing which shows the manufacturing process of the solid-state imaging device of Example 2 shown in FIG. It is sectional drawing which shows the manufacturing process of the solid-state imaging device of Example 2 shown in FIG. It is sectional drawing which shows the manufacturing process of the solid-state imaging device of Example 2 shown in FIG.

Explanation of symbols

  M1... Gate insulating film, M2... First insulating film for forming sidewall (SiO film), M3... Second insulating film for forming sidewall (LP-SiN film), M4. Film (P-SiN film), 1 ... silicon substrate, 2 ... element isolation insulating film, 3 ... well region, 4 ... photodiode formation region, 5 ... pixel transistor formation region, 6 ... gate electrode, 7, 8, 10, 11... Impurity implantation region, 12.

Claims (10)

An imaging unit including a plurality of photoelectric conversion elements that generate a signal charge according to the amount of received light is formed on a semiconductor substrate having both a silicide formation region and a silicide non-formation region, and at least a SiO film and a photoelectric conversion element are formed on the photoelectric conversion element. An insulating film having a laminated structure including a plasma CVD-SiN film was provided.
A solid-state imaging device.   The solid-state imaging device according to claim 1, wherein a gate portion of a transistor formed on the semiconductor substrate has a sidewall structure. _2. The solid-state imaging device according to claim 1, wherein the insulating film has a four-layer structure of a SiO ₂ film, a SiO ₂ film, a low-pressure CVD-SiN film, and a plasma CVD-SiN film. The solid-state imaging device according to claim 1, wherein the insulating film has a three-layer structure of a SiO ₂ film, a SiO ₂ film, and a plasma CVD-SiN film. The solid-state imaging device according to claim 1, wherein the insulating film has a two-layer structure of a SiO ₂ film and a plasma CVD-SiN film.   The imaging unit includes a CCD transfer unit that sequentially transfers signal charges generated by a plurality of photoelectric conversion elements, a charge detection unit that sequentially detects signal charges transferred by the CCD transfer unit, and a detection potential of the charge detection unit The solid-state imaging device according to claim 1, wherein the solid-state imaging device is configured as a CCD image sensor having a transistor circuit portion for converting the signal into an electric signal.   The imaging unit is a CMOS image sensor having a plurality of charge detection units that detect signal charges generated by a plurality of photoelectric conversion elements, and a plurality of transistor circuit units that convert detection potentials of the charge detection units into electric signals. The solid-state imaging device according to claim 1, wherein the solid-state imaging device is configured.   2. The solid-state imaging device according to claim 1, wherein a circuit device unit having a specific function other than the imaging function is formed on the semiconductor substrate to constitute a system in which a plurality of functions are integrated.   The solid-state imaging device according to claim 1, wherein the circuit device unit is an optical communication device unit.   The solid-state imaging device according to claim 1, wherein the circuit device unit is an infrared detection device unit.

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