JP2005340465A - Semiconductor device manufacturing method and semiconductor device - Google Patents

Abstract

A deep diffusion layer such as a field stop layer is formed using phosphorus or boron used in a normal silicon process as a dopant, and a trench gate structure having good characteristics is formed.
A trench is formed on a silicon wafer having a (110) plane as a main surface so that a (001) plane perpendicular to the (110) plane is exposed on a trench sidewall, and gate oxidation is performed in the trench. A gate electrode 24 is formed through the film 25. Then, phosphorus ions are implanted perpendicularly to the (110) plane on the backside of the wafer to form a deep diffusion layer that becomes the field stop layer 31.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device manufacturing method and a semiconductor device, and more particularly, to a semiconductor device manufacturing method and a semiconductor device that constitute an insulated gate bipolar transistor having a trench gate structure and a deep diffusion layer serving as a field stop layer.

  In recent years, trench gate structures have been put into practical use in power MOSFETs, insulated gate bipolar transistors (hereinafter referred to as IGBTs), thyristors, diodes, and the like used in power converters. The trench gate structure is a structure in which a gate electrode is provided in the trench on the substrate surface via a gate oxide film, and has an advantage that the channel density is remarkably improved.

7 and 8 are cross-sectional views showing the structure of a field stop type IGBT (hereinafter referred to as FS-IGBT) having a trench gate structure and a planar gate structure, respectively. As shown in FIG. 7, in the trench gate type FS-IGBT, a trench 3 penetrating the p base region 2 is provided on the surface side of the n ⁻ drift layer 1. The gate electrode 4 is provided in the trench 3 via a gate oxide film 5.

The n ⁺ emitter region 6 is provided in contact with the trench 3 in the p base region 2. Emitter electrode 7 is in contact with p base region 2 and n ⁺ emitter region 6 and is insulated from gate electrode 4 by interlayer insulating film 8.

On the back surface side of the n ⁻ drift layer 1, a p ⁺ collector layer 9 serving as a hole injection layer and a collector electrode 10 in contact therewith are provided. An n ⁺ field stop layer 11 is provided between the p ⁺ collector layer 9 and the n ⁻ drift layer 1.

As shown in FIG. 8, in the planar gate type FS-IGBT, the gate electrode 4 is provided on the surface of the n ⁻ drift layer 1 via the gate oxide film 5. The other configuration is the same as that of the trench gate type FS-IGBT described above.

  As is clear from a comparison between the configuration shown in FIG. 7 and the configuration shown in FIG. 8, the channel density can be improved by using the trench gate structure. In addition, since the carrier accumulation effect is improved, the loss can be reduced in a high breakdown voltage device in which the contribution of the channel resistance component is small.

  FIG. 9 is a cross-sectional view showing the main parts of the FS-IGBT having a planar gate structure and a non-punch through type IGBT (hereinafter referred to as NPT-IGBT) for comparison. a) shows the FS-IGBT, and FIG. 5B shows the NPT-IGBT. In FIG. 9, the interlayer insulating film, the emitter electrode, and the collector electrode are omitted.

  As shown in FIG. 9B, the NPT-IGBT has no field stop layer. Therefore, it is necessary to make the drift layer 1 thicker than the FS-IGBT so that the depletion layer does not contact the collector side at the time of off. In other words, since the field stop layer 11 for stopping the depletion layer is provided in the FS-IGBT, the drift layer 1 can be made thinner than the NPT-IGBT.

For this reason, the FS-IGBT has an advantage that the collector-emitter saturation voltage V _{CE (sat)} can be reduced. In addition, since there are few excess carriers and the remaining width of the neutral region in a state where the depletion layer is fully extended, there is an advantage that turn-off loss can be reduced. In FIG. 9B, the two-dot chain line indicates the position of the depletion layer that has been extended in the NPT-IGBT.

  By the way, the field stop layer 11 is formed on the back side of the substrate. As for the field stop layer 11, it is known that better characteristics can be obtained as the profile spreads deeper. For this reason, it is necessary to form a deep diffusion layer as the field stop layer 11.

  However, among the n-type dopants used in the normal silicon process, even if phosphorus (P) having the largest projected range and a large diffusion coefficient in silicon is used, a deep diffusion layer that becomes the field stop layer 11 Can not form. Therefore, it has been proposed to use selenium (Se) or sulfur (S) having a larger diffusion coefficient than phosphorus as a dopant (see, for example, Patent Document 1 and Patent Document 2).

Japanese translation of PCT publication No. 2002-52085 Special Table 2002-520886

  However, since selenium and sulfur are not used as dopants in a normal silicon process, it is necessary to prevent deterioration in device characteristics and reduction in yield rate due to contamination. For that purpose, it is necessary to prepare a dedicated ion implantation apparatus, a diffusion furnace, a cleaning apparatus, and the like, resulting in an increase in cost. In addition, when phosphorus is used as a dopant or when large diffusion cannot be obtained due to heat treatment temperature and heat treatment time limitations, an expensive and special ion implantation apparatus that can perform ion implantation at high acceleration is prepared. There is a need to.

  In order to solve the above-mentioned problems caused by the prior art, the present invention optimizes the crystal plane orientation of a silicon wafer, and uses phosphorus or boron used in a normal silicon process as a dopant to form a field stop layer or the like. It is an object of the present invention to provide a method for manufacturing a semiconductor device capable of forming a deep diffusion layer and forming a trench gate structure having good characteristics. Another object of the present invention is to provide a semiconductor device having a deep diffusion layer such as a field stop layer containing phosphorus or boron as a dopant used in a normal silicon process and a trench gate structure having good characteristics. .

  In order to solve the above-described problems and achieve the object, a method of manufacturing a semiconductor device according to claim 1 includes a trench gate structure formed on the substrate surface side, and a deep diffusion layer formed on the substrate back side. Forming a trench so that a (001) plane perpendicular to the (110) plane is exposed on the trench side wall in a silicon wafer having a (110) plane as a main surface, Forming a gate oxide film inside the trench; forming a gate electrode inside the gate oxide film; and implanting a dopant perpendicular to the (110) plane of the wafer. It is characterized by.

According to the first aspect of the present invention, a diffusion layer having a deep dopant profile is formed by utilizing <110> axis channeling by implanting a dopant perpendicular to the (110) plane of the wafer by ion implantation. Can be formed. Further, in the trench sidewalls, since SiO ₂ is a gate oxide film is in contact with the (001) plane of silicon, the fixed charge density and surface charge density in the SiO ₂ is small, good SiO ₂ high mobility of carriers / Si interface is obtained.

  According to a second aspect of the present invention, there is provided a method for manufacturing a semiconductor device according to the first aspect, wherein the dopant is phosphorus or boron.

  According to the second aspect of the present invention, it is possible to form a deep diffusion layer using phosphorus or boron used in a normal silicon process as a dopant.

  In order to solve the above-described problems and achieve the object, a semiconductor device manufacturing method according to claim 3 includes a trench gate structure formed on the substrate surface side and a field stop formed on the substrate back side. In manufacturing a semiconductor device comprising an insulated gate bipolar transistor having a structure, a (001) plane perpendicular to the (110) plane is exposed on a trench sidewall on a silicon wafer having a (110) plane as a main surface. Forming a trench in the trench, forming a gate oxide film inside the trench, forming a gate electrode inside the gate oxide film, and a dopant perpendicular to the (110) plane of the wafer And forming a deep diffusion layer to be a field stop layer by implanting.

According to the third aspect of the present invention, a field stop layer having a deep dopant profile using <110> axis channeling by implanting a dopant perpendicular to the (110) plane of the wafer by ion implantation. Can be formed. In addition, since the SiO ₂ that is the gate oxide film is in contact with the (001) surface of silicon on the trench side wall, there is a good interface in which the fixed charge density and the interface charge density in SiO ₂ are small and the carrier mobility is large. can get.

  According to a fourth aspect of the present invention, there is provided a method for manufacturing a semiconductor device according to the third aspect, wherein the dopant is phosphorus.

  According to the fourth aspect of the present invention, a deep field stop layer can be formed using phosphorus used in a normal silicon process as a dopant.

  In order to solve the above-described problems and achieve the object, a semiconductor device according to a fifth aspect of the present invention is directed to a surface side of a silicon semiconductor substrate having a (110) plane as a main surface and perpendicular to the (110) plane. A trench gate structure in which a trench having a (001) plane as a trench sidewall is formed, and a gate electrode is provided in the trench via a gate oxide film, and phosphorus or boron formed on the back side of the silicon semiconductor substrate And a deep diffusion layer containing as a dopant.

According to the fifth aspect of the present invention, the SiO _{2 as} the gate oxide film contacts the (001) surface of silicon on the trench sidewall, so that the fixed charge density and the interface charge density in SiO ₂ are small, and the carrier A good interface with high mobility can be obtained. Further, if phosphorus or boron is implanted as a dopant perpendicularly to the (110) plane of the wafer by ion implantation, a diffusion layer having a deep dopant profile can be obtained by <110> axis channeling.

  In order to solve the above-described problems and achieve the object, a semiconductor device according to a sixth aspect of the present invention is directed to a surface side of a silicon semiconductor substrate having a (110) plane as a main surface and perpendicular to the (110) plane. A trench having a (001) plane as a trench sidewall, a trench gate structure in which a gate electrode is provided via a gate oxide film in the trench, and phosphorus formed on the back side of the silicon semiconductor substrate as a dopant An insulated gate bipolar transistor having a deep diffusion layer serving as a field stop layer is included.

According to the sixth aspect of the present invention, since the SiO _{2 as} the gate oxide film contacts the (001) surface of silicon on the trench sidewall, the fixed charge density and the interface charge density in the SiO ₂ are small, and the carrier A good interface with high mobility can be obtained. If phosphorus is implanted as a dopant perpendicularly to the (110) plane of the wafer by ion implantation, a field stop layer having a deep dopant profile is obtained by <110> axis channeling.

  According to the method for manufacturing a semiconductor device and the semiconductor device according to the present invention, a semiconductor device having a deep diffusion layer such as a field stop layer using phosphorus or boron as a dopant used in a normal silicon process can be obtained. In addition, a semiconductor device having a good trench gate structure with few interface states and high carrier mobility can be obtained. Therefore, a semiconductor device having both a deep diffusion layer such as a field stop layer and a trench gate structure with good characteristics can be obtained without preparing a special device.

  Exemplary embodiments of a method for manufacturing a semiconductor device and a semiconductor device according to the present invention will be explained below in detail with reference to the accompanying drawings.

FIG. 2 is a cross-sectional view showing a configuration of an FS-IGBT having a trench gate structure according to an embodiment of the present invention. As shown in FIG. 2, a trench 23 penetrating the p base region 22 is provided on the surface side of the n ⁻ drift layer 21. The gate electrode 24 is provided in the trench 23 via a gate oxide film 25. In FIG. 2, the gate electrode 24 is made of polysilicon, and the reference numeral 32 above the gate electrode 24 is a metal gate electrode in contact with the gate electrode 24.

The n ⁺ emitter region 26 is provided in contact with the trench 23 in the p base region 22. Emitter electrode 27 is in contact with p base region 22 and n ⁺ emitter region 26 and insulated from gate electrode 24 by an interlayer insulating film (not shown).

On the back side of the n ⁻ drift layer 21, a p ⁺ collector layer 29 serving as a hole injection layer and a collector electrode 30 in contact therewith are provided. The n ⁺ field stop layer 31 is provided between the p ⁺ collector layer 29 and the n ⁻ drift layer 21.

Here, the crystal plane orientation of the silicon wafer to be the n ⁻ drift layer 21 is the (110) plane. Therefore, the crystal plane orientation of the interface of the p base region 22 and the n ⁺ emitter region 26 contacting the emitter electrode 27 and the interlayer insulating film (not shown) is the (110) plane. Further, by forming the trench 23 perpendicular to the wafer surface, the crystal plane orientation of the interface of the p base region 22 and the n ⁺ emitter region 26 in contact with the gate oxide film 25 on the sidewall of the trench 23 is ( The (001) plane is perpendicular to the (110) plane.

In forming the gate trench structure, a gate oxide film 25 is formed in the trench 23, and further, doped polysilicon serving as the gate electrode 24 is buried therein. When a silicon wafer having a principal plane crystal plane orientation of (110) is used, if a normal planar gate structure is formed on the principal plane, SiO _{2 as} a gate oxide film contacts the (110) plane of silicon. For this reason, the fixed charge density and the interface charge density in SiO ₂ increase, and the carrier mobility decreases.

On the other hand, in the embodiment, since the trench 23 is formed in the silicon wafer having the (110) plane as the main surface so that the (001) plane is exposed on the trench side wall, it has a normal planar gate structure. Similar to the IGBT or the like, the SiO ₂ that is the gate oxide film 25 comes into contact with the (001) plane of silicon. Therefore, the interface between the gate oxide film and silicon is a good interface with low fixed charge density and interface charge density in SiO ₂ and high carrier mobility.

FIG. 1 is a cross-sectional view for explaining a method of forming a field stop layer of the FS-IGBT having the configuration shown in FIG. In forming the n ⁺ field stop layer 31, phosphorus is ion-implanted as a dopant from the back side of the wafer. The crystal plane orientation on the backside of the wafer is the (110) plane. The ion implantation conditions at this time are such that the wafer implantation angle (tilt angle) is 0 °, that is, perpendicular to the (110) plane, and <110> axis channeling occurs.

  FIG. 3 is a diagram schematically showing a silicon lattice when the (110) plane of a silicon wafer is viewed from the <110> axis direction. In FIG. 3, reference numeral 41 denotes silicon atoms, and reference numeral 42 denotes silicon. A channel (gap) formed by an array of atomic crystals. Channeling is a phenomenon in which implanted ions enter deeply along this channel.

  For comparison, FIG. 5 shows a schematic diagram of a silicon lattice when the (100) plane of a silicon wafer is viewed from the <100> axis direction. In FIG. 5, reference numeral 51 is a silicon atom, and reference numeral 52 is a channel. As is clear from the comparison between FIGS. 3 and 5, the channel 42 generated in the (110) plane is much larger than the channel 52 generated in the (100) plane. For this reason, when a dopant such as phosphorus is implanted at a tilt angle of 0 ° in the same manner on the (110) plane and the (100) plane, channeling is more effective when a silicon wafer having the (110) plane as the main surface is used. The spread of the dopant profile is much larger, which is advantageous for the formation of deep diffusion layers.

An example of a profile when P ⁺ (phosphorus ion) is ion-implanted with an implantation energy of 1 MeV is shown in FIGS. FIG. 4 shows a profile for the (110) plane, and FIG. 6 shows a profile for the (100) plane. From the comparison of both figures, it can be seen that P ⁺ diffuses deeper when ion implantation is performed on the (110) plane.

  In addition, when performing ion implantation for forming the field stop layer 31, it is desirable to use a parallel scan type implantation apparatus. By doing so, it is possible to prevent profile variation due to the difference in implantation angle between the wafer central portion and the outer peripheral portion.

  Further, at the same time as the ion implantation, it is desirable to heat the wafer so that the temperature of the wafer becomes 150 ° C. or higher when phosphorus is used as the dopant, and the temperature of the wafer becomes 50 ° C. or higher when boron is used as the dopant. . By doing so, it is possible to recover the implantation damage introduced during the ion implantation and maintain the increase in the range due to channeling. If the implantation damage is integrated and exceeds a certain implantation amount, the crystalline structure of silicon does not have a regular arrangement, and an amorphous layer is formed. When this amorphous layer is formed, channeling does not occur, so the range becomes small. In order to maintain the increase in the range, it is necessary to suppress the formation of the amorphous layer.

As described above, according to the embodiment, the field stop layer 31 having phosphorus as a dopant used in a normal silicon process is provided, the fixed charge density and the interface charge density in SiO ₂ are small, and the carrier moves. An FS-IGBT having a good and excellent trench gate structure can be obtained.

  As described above, the present invention is not limited to the above-described embodiment, and various modifications can be made. For example, the semiconductor layer and the semiconductor region may have a reversed conductivity type. Further, as a dopant, not only phosphorus but also boron or the like can be used. Furthermore, the present invention is not limited to the FS-IGBT but can be applied to a semiconductor device having both a trench gate structure and a deep diffusion layer.

  As described above, the method for manufacturing a semiconductor device and the semiconductor device according to the present invention include industrial fields such as general-purpose inverters, AC servos, uninterruptible power supplies (UPS), and switching power supplies, and consumer products such as microwave ovens, rice cookers, and strobes. This is useful for power semiconductor devices such as IGBTs used in the field of equipment.

It is sectional drawing for demonstrating the formation method of the field stop layer of FS-IGBT which has a trench gate structure concerning embodiment of this invention. It is sectional drawing which shows the structure of FS-IGBT which has a trench gate structure concerning embodiment of this invention. It is a schematic diagram which shows a silicon | silicone lattice when the (110) plane of a silicon wafer is seen from the <110> axis direction. It is a figure which shows an example of a profile when P ^<+> ion implantation is carried out to the (110) plane of a silicon wafer. It is a schematic diagram which shows a silicon lattice when the (100) plane of a silicon wafer is viewed from the <100> axis direction. It is a figure which shows an example of a profile when P ^<+> ion implantation is carried out to the (100) plane of a silicon wafer. It is sectional drawing which shows the structure of FS-IGBT which has a trench gate structure. It is sectional drawing which shows the structure of FS-IGBT which has a planar gate structure. It is sectional drawing which shows the structure of the principal part of FS-IGBT and NPT-IGBT which have a planar gate structure.

Explanation of symbols

23 trench 24 gate electrode 25 gate oxide film 31 field stop layer (deep diffusion layer)

Claims (6)

In manufacturing a semiconductor device having a trench gate structure formed on the substrate surface side and a deep diffusion layer formed on the substrate back side,
Forming a trench in a silicon wafer having a (110) plane as a main surface so that a (001) plane perpendicular to the (110) plane is exposed on the trench sidewall;
Forming a gate oxide film inside the trench;
Forming a gate electrode inside the gate oxide film;
Implanting a dopant perpendicular to the (110) plane of the wafer;
A method for manufacturing a semiconductor device, comprising:   The method for manufacturing a semiconductor device according to claim 1, wherein the dopant is phosphorus or boron. In manufacturing a semiconductor device composed of an insulated gate bipolar transistor having a trench gate structure formed on the substrate front surface side and a field stop structure formed on the substrate back surface side,
Forming a trench in a silicon wafer having a (110) plane as a main surface so that a (001) plane perpendicular to the (110) plane is exposed on the trench sidewall;
Forming a gate oxide film inside the trench;
Forming a gate electrode inside the gate oxide film;
A step of implanting a dopant perpendicular to the (110) plane of the wafer to form a deep diffusion layer to be a field stop layer;
A method for manufacturing a semiconductor device, comprising:   The method for manufacturing a semiconductor device according to claim 3, wherein the dopant is phosphorus. A trench having a (001) plane perpendicular to the (110) plane as a trench sidewall is formed on the surface side of the silicon semiconductor substrate having the (110) plane as a main surface, and a gate electrode is formed in the trench via a gate oxide film. A trench gate structure provided with
A deep diffusion layer formed on the back side of the silicon semiconductor substrate and containing phosphorus or boron as a dopant;
A semiconductor device comprising: A trench having a (001) plane perpendicular to the (110) plane as a trench sidewall is formed on the surface side of the silicon semiconductor substrate having the (110) plane as a main surface, and a gate electrode is formed in the trench via a gate oxide film. A trench gate structure provided with
A deep diffusion layer formed on the back side of the silicon semiconductor substrate and serving as a field stop layer containing phosphorus as a dopant;
A semiconductor device comprising an insulated gate bipolar transistor having

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