JP2005340267A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a lead-free semiconductor device having heat fatigue reliability using a lead-free bonding material having heat resistance and die bonding property of 400 ° C. or less.
SOLUTION: An alloy obtained by adding one or more of Ag and Cu and an amount of 5 to 30 wt% to an Sn-Sb alloy having a composition ratio of 43 wt% ≦ Sb / (Sn + Sb) weight ratio <53 wt%. 6, 7, 8, and 9, the semiconductor element 1, the base electrode 2, and the lead electrode 3 are joined with a low thermal expansion member 4 having a thermal expansion coefficient of 10 ppm or less interposed therebetween. The joint surface of each member was Ni metallized to ensure heat resistance and die bonding properties. The semiconductor element 1 can be prevented from being damaged and the thermal fatigue life can be improved at the same time. It is possible to provide a semiconductor device A that does not use lead and can ensure a heat resistance reliability of 250 ° C. and a thermal fatigue reliability of 7000 times or more. The present invention can be effectively applied as a large-capacity semiconductor device for automobile applications in which it is required not to use lead as a bonding material without reducing heat resistance and thermal fatigue life.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device used for automobiles, and more particularly to a high heat-resistant semiconductor device having a junction structure in which lead-free semiconductor devices, thermal fatigue life and heat resistance are improved.

  Conventionally, high-melting-point solder materials containing Pb of 90% or more and several percent of Sn, Ag, etc. have been used for semiconductor element bonding of semiconductor devices. The structure is a structure in which a Cu base electrode, a Cu / Fe-Ni alloy / Cu low thermal expansion member for stress buffering, a semiconductor element, and a Cu lead electrode are stacked, and each member is joined with a high melting point solder containing lead. It is. Ni plating is applied to the upper and lower electrodes of each member and the semiconductor element.

On the other hand, in recent years, it has become important to protect the environment from contamination with harmful substances, and it is required to remove lead from the assembly members of electronic devices. However, at present, a high-temperature solder material that does not use lead that can be directly replaced with a conventional high-temperature solder material containing lead has not been developed. It has various problems in practical use and is difficult to apply to semiconductor devices. Patent Document 1 discloses an invention in which a ZnAl eutectic alloy is used as a solder material. Patent Document 2 discloses an invention using a Sn—Sb alloy as a solder material.
JP 2000-61686 A JP 2001-237252 A

  In semiconductor devices for automobiles, it is required to increase the current capacity per semiconductor device. When the energization current is increased in a conventional semiconductor device element, heat generation from the element increases, and the operating temperature of the semiconductor device increases. For this reason, improvement in heat resistance of semiconductor devices has become a major technical issue. Another problem is the prohibition of the use of lead in automobile equipment or electronic equipment, which is going to be regulated mainly in Europe from the viewpoint of environmental protection.

  In conventional semiconductor devices using high-temperature lead-containing solder materials, the solder material is soft, so most of the thermal strain between the semiconductor element and the Cu lead electrode or between the semiconductor element and the low thermal expansion member of Cu / Fe-Ni / Cu is absorbed by the solder part. If the operating temperature rises, cracks develop in the solder in a short period of time, or the NiSn compound that grows at the bonding interface causes cracks at the compound-solder interface or the compound-Ni plating interface, resulting in a long life. There is a problem of shortening.

  ZnAl refractory solder, one of the conventional high-temperature solder materials that do not use lead, has a chemically stable and mechanically strong Al oxide film formed on the surface of the solder pellet, and a hydrogen atmosphere There is a problem that it is not reduced even under, and the wet spreadability is poor.

  On the other hand, SnSb high-melting-point solder has good wettability, but in the case of a composition with a solid phase temperature of 300 ° C or higher, the liquidus temperature is as high as 400 ° C or higher, and the solder joint temperature must be 400 ° C or higher. There are problems that the semiconductor element is cracked in the cooling process after joining because the material is inferior and hard, and the semiconductor element is cracked in the temperature cycle test.

  An object of the present invention is to provide a technique related to a semiconductor device that does not use lead, which is excellent in solderability during assembly and can be used in a high temperature environment up to 250 ° C.

  Another object of the present invention is to provide a technology relating to a semiconductor device that prevents cracking of a semiconductor element in a cooling process after temperature assembly and a temperature cycle test, and has an excellent thermal fatigue life due to repeated energization and interruption of the element. There is.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  That is, in order to achieve the first object of providing a technique related to a semiconductor device that does not use lead, which is excellent in solderability at the time of assembly and can be used in a high temperature environment up to 250 ° C., a semiconductor element and both electrode terminal members An Ni plating film is formed on the surface of the material, and the main constituent element is 43 wt% ≦ Sb / (Sn + Sb) weight ratio <53 wt%. A joining structure using a joining material having a composition with an amount of% added was conceived.

  As a result of examining the temperature of the solid phase and the liquid phase by making various trial manufactures of the alloy of the above composition, the solidus temperature is determined by the composition ratio of Sn and Sb, and the composition range is 300 ° C or higher, and Ag and Cu are added. Then, it was found that the solidus temperature could not be lowered but only the liquidus temperature could be lowered, and the above composition would be 400 ° C. or lower, and the present invention was achieved.

  FIG. 9 shows a phase diagram of the Sn—Sb binary alloy, and FIGS. 10, 11 and 12 show the measurement results of the solidus temperature and the liquidus temperature in alloys of various compositions. Each figure shows the solidus temperature and liquidus temperature when the ratio of a specific element is changed in the Sn—Sb—Ag—Cu quaternary alloy.

  Fig. 10 shows the Sb / (Sn + Sb) parameter dependence of the solid-phase / liquidus temperature characteristics of Sn-Sb-Ag-Cu-based alloys, with 43 wt% ≤ Sb / (Sn + Sb). It can be seen that the solidus temperature is 300 ° C. or higher. Fig. 11 shows the Ag concentration dependence of the solid phase / liquidus temperature characteristics of Sn-Sb-Ag-Cu solder, and Fig. 12 shows the solid phase / liquidus temperature characteristics of Sn-Sb-Ag-Cu solder. This shows the Cu concentration dependence. As shown in FIGS. 11 and 12, the liquidus temperature is greatly lowered by the addition of Ag or Cu, but the solidus temperature remains at 300 ° C. or more and the change is small. For this reason, the solid-liquid coexistence temperature region is narrow.

  In assembly by soldering, it is important to be able to prevent workability determined by working temperature and wettability and the occurrence of joint defects. The Sn-Sb solder used in the present invention can be soldered at a heating temperature of 360 ° C to 400 ° C, and the bonding temperature can be greatly reduced compared to the conventional Sn-Sb binary solder. There is an advantage that the equipment and process of the solder can be used as it is.

  In addition, since it does not contain an easily oxidizable element, it has excellent wettability with respect to Ni and Cu, and bonding with good wettability in a reducing atmosphere is possible without using a flux or the like. In addition, since it can be joined cleanly in a clean environment, cleaning and other processes are unnecessary, and workability is excellent.

  Further, since the temperature range of the solidus line and the liquidus line is small, the segregation of the composition during the solidification process is small. Therefore, the volume shrinkage at the time of solidification is small, shrinkage-like defects are suppressed, and irregularities on the fillet surface are suppressed, so that bonding with few bonding defects becomes possible. Furthermore, it was found that the solidus temperature is as high as 300 ° C. or higher, and high temperature reliability at 250 ° C. to 1500 h can be secured by plating the joint surface of the member with Ni to form a solder / Ni interface.

  To achieve the second object of providing a technology relating to a semiconductor device that prevents cracking of a semiconductor element in a cooling process or temperature cycle test after joining and assembly and has an excellent thermal fatigue life due to repeated energization and interruption of the element. In addition, a thin plate-like low thermal expansion member having a coefficient of thermal expansion of 10 ppm or less is inserted as a stress buffer between the semiconductor element and both electrode terminals, and the outer dimensions of the thin plate-like low thermal expansion member are defined as the electrode of the semiconductor element on the lead electrode terminal side. A structure was devised that is smaller than the outer dimension of the surface and larger than the outer dimension of the semiconductor element on the base electrode terminal side.

  Addition of one or more of Ag and Cu to the SnSb alloy with a composition ratio of 43 wt% ≤ Sb / (Sn + Sb) weight ratio <54 wt% and a total of 5 to 30 wt% of the main constituent elements The composition was as follows. When the thermal expansion coefficient exceeds 10 ppm above and below the semiconductor element, for example, 11.0 ppm of Cu / Fe-Ni alloy / Cu low thermal expansion member is placed, and the solder cracking occurs when the semiconductor element is soldered. It has been found that if the ratio of the Fe-Ni alloy, which is a low thermal expansion material, is increased and the coefficient of thermal expansion is reduced to 10 ppm or less, no cracking occurs in the semiconductor element.

  In addition, as a result of conducting detailed examination by conducting a thermal fatigue test, the external dimensions of the thin plate-like low thermal expansion member on the lead electrode side are made smaller than the external dimensions of the electrode surface of the semiconductor element, and further, the thin plate-like low thermal expansion on the base electrode side It has also been found that the thermal fatigue life is improved when the outer dimension of the member is made larger than the outer dimension of the electrode surface of the semiconductor element. If the outer dimension of the thin plate-like low thermal expansion member on the lead electrode side is made smaller than the outer dimension of the electrode surface of the semiconductor element, the tensile stress generated on the outer peripheral side wall of the semiconductor element can be reduced, and the outer shape of the thin plate-like low thermal expansion member on the base electrode side It has been elucidated by analysis that if the dimension is made larger than the outer dimension of the electrode surface of the semiconductor element, the heat dissipation from the element is improved and the life is improved.

  Furthermore, lowering the elastic modulus and yield strength of the low thermal expansion member at this time will increase the fatigue life of the solder, and increasing the thermal conductivity of the low thermal expansion member and lowering the solder joint thickness will improve heat dissipation. It was also confirmed that the thermal fatigue life was extended.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  That is, according to the present invention, the bonding material is 43 wt% ≦ Sb / (Sn + Sb) weight ratio <53 wt% in a Sn—Sb alloy having a composition ratio of one or more of Ag and Cu and an amount of 5 to 30 wt%. To provide a semiconductor device that does not use lead, which can ensure die bonding property of 400 ° C or less and high temperature reliability up to 250 ° C by Ni metallization treatment of the joining surface of each member to be joined as an added alloy it can.

  In addition, the thin plate member that is directly bonded to the semiconductor element is configured with a member having a coefficient of thermal expansion of 10 ppm or less, and the outer dimension of the thin plate member that is directly bonded to the semiconductor element on the base electrode side is greater than the outer dimension of the electrode surface of the semiconductor element. Thermal stress that occurs during the cooling process and temperature cycle after joining and assembly by making the outer dimensions of the thin plate member directly bonded to the semiconductor element on the lead electrode side smaller than the outer dimensions of the electrode surface of the semiconductor element. The thermal fatigue life associated with repeated energization and interruption of the semiconductor element due to the use of high-strength SnSbAgCu solder and the placement of low thermal expansion members above and below the semiconductor element It is possible to provide a semiconductor device that has been improved dramatically.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof may be omitted.

(Embodiment 1)
In this embodiment mode, a semiconductor device according to the present invention will be described. FIG. 1 is a cross-sectional view showing an embodiment of a semiconductor device mounting structure according to the present invention. FIG. 2 is a cross-sectional view showing in more detail the structure of the junction of the semiconductor device shown in FIG. 1 and 2, a semiconductor device A includes thin plate-like low thermal expansion members 4a (4) and 4b (4) arranged above and below a semiconductor element 1 having a rectifying action, and a Cu lead electrode 3; Below that, a Cu base electrode 2 is arranged. Between the lead electrode 3, the low thermal expansion member 4b, the semiconductor element 1, the low thermal expansion member 4a, and the base electrode 2, solder materials 6, 7, 8, having a composition of Sn-35Sb-11Ag-8Cu (wt%), 9 is used as a bonding material.

  The average thickness of the upper and lower solder materials 6 and 8 of the semiconductor element 1 is 20 to 60 μm, and the average thickness of the solder materials 7 and 9 joining the electrode members such as the base electrode 2 and the lead electrode 3 is 30. It is set to ~ 100 μm. As shown in FIG. 2, the entire surface of the electrode member such as the base electrode 2 and the lead electrode 3 and the low thermal expansion members 4a and 4b has matte electric Ni platings 12 and 13 in which impurities are hardly mixed into the plating film. 14 and 15 are applied with a thickness of 2 to 10 μm, and electroless Ni—P plating 11 is applied with a thickness of 0.5 to 3 μm on the upper and lower surfaces of the semiconductor element. In such a configuration, the metal material configuration of the bonding portion is Ni / the bonding material / Ni.

  The dish-like base electrode 2 in which the semiconductor element 1 is housed is filled with a resin 10 to a height that covers a part of the lead electrode 3 as shown in FIG. The low thermal expansion members 4a and 4b used here are Cu / Fe—Ni alloy / Cu composite materials having a cross-sectional structure shown in FIG. 3, and are materials whose thermal expansion coefficient α is adjusted to 6.0 ppm. It has a laminated structure of Fe—Ni alloy as the low thermal expansion material 21 and Cu as the good conductor material 22. The periphery of such a laminated structure is covered with Ni plating 23.

  The upper thin plate-like low thermal expansion member 4 b interposed between the lead electrode 3 and the semiconductor element 1 is smaller than the outer dimension of the electrode surface of the semiconductor element 1, and is interposed between the semiconductor element 1 and the base electrode 2. The outer dimension of the lower thin plate-like low thermal expansion member 4 a to be made is larger than the outer dimension of the electrode surface of the semiconductor element 1. In the joining and assembling method, the components and solder pellets are aligned and laminated with a jig, and are soldered by heating to 380 ° C. in a hydrogen atmosphere. The heating was held at 380 ° C. for 2 minutes and cooled to room temperature at a cooling rate of about 20 ° C./min.

  According to this example, SnSbAgCu solder has excellent wettability to Ni, so it has excellent solder joint properties during assembly, and compound growth at the joint interface between AnSbAgCu solder and electroless Ni plating or matte electric Ni plating occurs. Because it is small even under a high temperature environment of 250 ° C and stable without the occurrence of Kirkendall voids or cracks at the interface, it can provide lead-free semiconductor device parts with high temperature reliability up to 250 ° C. .

  As shown in FIGS. 1 and 2, low thermal expansion members 4 a (4) and 4 b (4) having a thermal expansion coefficient of 6.0 ppm are comparatively small and high strength at a thermal expansion coefficient of 18 ppm above and below the semiconductor element 1. Since the SnSbAgCu solder materials 6 and 8 are joined, the thermal stress generated in the semiconductor element 1 is reduced. Further, since the outer dimensions of the upper and lower low thermal expansion members 4a (4) and 4b (4) are different from those of the semiconductor element 1, the tensile thermal stress generated in the semiconductor element 1 during cooling is dispersed. be able to.

  Therefore, the problem that the semiconductor element 1 is cracked by thermal stress when a temperature cycle or a power cycle is applied due to these effects can be completely avoided. At the same time, since SnSbAgCu solder materials 6 and 8 are high in strength, thermal strain is dispersed in the low thermal expansion members 4a and 4b and the semiconductor element 1, and the high temperature creep strain of the solder materials 6 and 8 is small. The fatigue life of the solder part when a thermal stress is applied by a cycle or the like is dramatically improved.

  In the configuration shown in this embodiment, the electroless Ni-P plating on the semiconductor element 1 and the surface of the electrode members such as the low thermal expansion members 4a and 4b, the base electrode 2 and the lead electrode 3 are matte electric Ni. Although plated, all may be electroless Ni-P plating. In electroless Ni-P plating, the growth of the compound formed at the interface with the solder is slower, and the high temperature reliability is higher than that of electric Ni plating.

(Embodiment 2)
In the above embodiment, the low thermal expansion member 4 is configured to sandwich the upper and lower surfaces of the low thermal expansion material 21 with the good conductor material 22 and cover the entire circumference with the Ni plating 23. However, a configuration other than this configuration may be used.

  For example, FIG. 4 shows an embodiment of the low thermal expansion member 4 (4a, 4b) used in the semiconductor device A according to the present invention, where (a) is a plan sectional view taken along line BB shown in (b). (B) is sectional drawing in the AA line of the low thermal expansion member 4 shown to (a). In the low thermal expansion member 4 of FIG. 4, the central member is Cu or Cu alloy which is a good conductor material 22 having a high coefficient of thermal expansion and conducts heat and electricity well, and the surrounding members are Fe-Ni having low heat and electric conductivity. It is composed of a low thermal expansion material 21 such as an alloy. The good conductor material 22 and the low thermal expansion material 21 are firmly metal-bonded by a pressure welding method by hot rolling or a friction stir welding method. The entire periphery of the low thermal expansion member 4 is covered with the Ni plating 23.

  According to this configuration of the present embodiment, the thermal expansion coefficient in the horizontal direction is low thermal expansion material 23 arranged on the outer periphery, and the expansion and contraction of good conductor material 22 are suppressed, and the behavior of low thermal expansion as a member is exhibited. The thermal strain generated when 1 is soldered can be reduced to improve the mechanical breakdown of the semiconductor element 1 and the thermal fatigue life of the solder portion.

  At the same time, since the good conductor material 22 is arranged in the plate thickness direction, the heat generated in the semiconductor element 1 can be efficiently transmitted to the base electrode 2 and the temperature rise of the semiconductor element 1 can be suppressed. Can reduce the loss.

  Further, since the good electrical conductor made of the good conductor material 22 is disposed in the low thermal expansion member 4 so as to penetrate in the energizing direction, the electrical resistance as the low thermal expansion member 4 is suppressed to be small and is generated from the low thermal expansion member 4. Heat can be suppressed, energy loss can be reduced, and as a result, the efficiency of the semiconductor device A can be improved. Moreover, since the temperature rise of the semiconductor element 1 can be suppressed, the thermal fatigue life can be further improved.

(Embodiment 3)
In the present embodiment, a configuration of a modified example of the low thermal expansion member 4 described in the above embodiment will be described. FIG. 5 shows an embodiment of the low thermal expansion member 4 used in the semiconductor device A according to the present invention. (A) is a plan sectional view taken along the line DD shown in (b). It is sectional drawing in CC line of the low thermal expansion member 4 shown to (a). In FIG. 5, a plurality of members arranged inside are Cu or Cu alloy as a good conductor material 22 having a high coefficient of thermal expansion and heat and electricity, and surrounding members are Fe-Ni alloys having a low heat and electricity conductivity. Of the low thermal expansion material 21. The good conductor material 22 and the low thermal expansion material 21 are firmly metal-bonded. The entire periphery of the low thermal expansion member 4 is covered with the Ni plating 23.

  According to the present embodiment, the same effect as in FIG. 4 can be obtained. In addition, the good conductor material 22 having a large thermal expansion coefficient is dispersed and arranged in a small size, so that one large good conductor material 22 is arranged. Unlike the case of the configuration shown in FIG. 2, the strain amount of the good conductor material 22 generated due to the difference in thermal expansion is reduced in proportion to the size, and the maximum value of the local thermal stress can be reduced. The thermal fatigue life of the solder portion can be further improved.

  FIG. 6 is a sectional view showing another modification of the low thermal expansion member 4 used in the semiconductor device A according to the present invention. In FIG. 6, the low thermal expansion material 21 inferior in heat and electricity conduction is finely dispersed in the good conductor matrix 22a of the good conductor material 22 made of Cu or Cu alloy. The interface between the low thermal expansion material 21 and the good conductor material 22 is loosely bonded, in other words, in close contact, but bonded in a weak state. The entire surface of the low thermal expansion member 4 is covered with Ni plating 23.

  According to the configuration shown in FIG. 6 of this embodiment, in addition to the same effects as in FIG. 4, the thermal strain generated between the solder and the low thermal expansion member 4 is reduced by the low thermal expansion material 21 of the good conductor matrix 22a. Since the thermal fatigue life of the solder portion is greatly improved and the thermal fatigue reliability of the semiconductor device A is drastically improved. It is done.

(Embodiment 4)
The low thermal expansion member 4 described in the above embodiment is formed in a thin plate shape and is assumed to be disposed between the semiconductor element 1 and the electrode member such as the base electrode 2 and the lead electrode 3. By providing, the semiconductor element 1 and the electrode member have a configuration for ensuring conduction.

  The low thermal expansion member 4 according to the present embodiment is not disposed between the semiconductor element 1 and the electrode member, but is disposed around the electrode member joined to the semiconductor element 1 by soldering to reduce thermal stress. This is a configuration premised on what to do.

  FIG. 7 shows one embodiment of the low thermal expansion member 4 used in the semiconductor device A according to the present invention. (A) is a plan sectional view taken along line FF shown in (b). It is sectional drawing in the EE line of the low thermal expansion member 4 shown to a). The low thermal expansion member 5 shown in FIG. 7 has a configuration in which a Ni plating 23 is applied to the surface of a low thermal expansion material 21 formed on a ring.

  FIG. 8 is a cross-sectional view showing an embodiment of the mounting structure of the semiconductor device A to which the low thermal expansion member 5 of FIG. 7 is applied. In FIG. 8, the low thermal expansion member 4 shown in FIG. 5 is disposed below the semiconductor element 1, and the base electrode 2 is further disposed below the low thermal expansion member 4. On the semiconductor element 1, the same ring-shaped low thermal expansion member 5 as in FIG. 7 is disposed, and the lead electrode 3 is disposed inside thereof.

  Between the base electrode 2 and the low thermal expansion member 4, between the low thermal expansion member 4 and the semiconductor element 1, and between the semiconductor element 1 and the ring-shaped low thermal expansion member 5 and the lead electrode 3, Sn45Sb9Ag5Cu (wt%) solder material 6a, 7a, 8a Is used as a bonding material. Electroless Ni-P plating is applied to all surfaces of the bonding surfaces of the members.

  According to this embodiment, the lower side of the semiconductor element 1 can reduce the thermal stress generated in the semiconductor element 1 and the solder part for the same reason as described in the configuration shown in FIG. The lead electrode 3 is directly solder-bonded, but at the same time is also solder-bonded to the ring-shaped low thermal expansion member 5, the thermal strain of the lead electrode 3 is restrained by the ring-shaped low thermal expansion member 5, and the semiconductor element 1. It is possible to prevent excessive stress from being generated in the semiconductor device 1 and to prevent the semiconductor element 1 from being damaged due to these effects.

  In the configuration shown in FIG. 8, since the lead electrode 3 and the semiconductor element 1 are directly solder-bonded, an increase in electric resistance and thermal resistance can be suppressed, and an effect of improving power loss and thermal fatigue life can be achieved. is there. Further, since the low thermal expansion member 5 is not configured to be interposed between the semiconductor element 1 and the lead electrode 3, the overall structure of the semiconductor device A can be reduced by suppressing the bonding structure of the semiconductor device A to be low. .

(Embodiment 5)
In the present embodiment, the electrode member is formed of a low thermal expansion material so that the electrode member has a function of reducing the thermal strain. FIG. 13 is a cross-sectional view showing an embodiment of the mounting structure of the semiconductor device A according to the present invention.

  A semiconductor element 1 having electroless Ni-P plating applied to the upper and lower electrode surfaces is disposed between a base electrode 52 and a lead electrode 53 having a matte electric Ni applied to the entire surface, and a space between them is Sn-35Sb-10Ag -8Cu alloy solder materials 54 and 55 are used as bonding materials. The dish-like base electrode 52 in which such a joining structure is stored is filled with a resin 56 to a height that covers a part of the lead electrode 53. Here, the base electrode 52 and the lead electrode 53 are made of a low thermal expansion material formed by press-bonding Fe—Ni alloy particles and Cu particles. The volume ratio of Fe—Ni alloy and Cu of both electrode members is 3: 2, and the coefficient of thermal expansion is adjusted to 7 ppm.

  According to the present embodiment, the electrode member is made of a low thermal expansion material, so that the semiconductor element 1 can be prevented from being damaged due to thermal stress, and the SnSbAgCu-based high yield strength bonding material is used to significantly improve the fatigue life of the solder part. Thus, the semiconductor device A having a long thermal fatigue life can be realized. In such a configuration, the number of components can be reduced to the minimum of three, ie, the semiconductor element 1, the base electrode 52, and the lead electrode 53, so that there is an effect that the number of joints is minimized and the assembly yield can be improved.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the above-described embodiment, the case where the low thermal expansion member is formed in a flat circular shape has been described as an example. However, it is not necessary to limit to such a circular shape, and a rectangular shape or the like is appropriately used according to the shape of the semiconductor element to be used. The shape may be adopted.

  In the description of the low thermal expansion member formed in the ring, the case where the ring is formed in an annular shape is illustrated, but it is not necessary to be limited to such an annular shape. For example, the ring may be appropriately modified into a square ring or the like.

  When the size of the low thermal expansion member is interposed between the semiconductor element and the base electrode, in the description of the above embodiment, the shape larger than the semiconductor element is shown as a preferred example. If not, the thermal stress relaxation effect is inferior, but it is confirmed that a certain degree of effect can be expected in the case of the isomorphic size.

  When the size of the low thermal expansion member is interposed between the semiconductor element and the lead electrode, in the description of the embodiment, the shape larger than the lead electrode surface is shown as a preferred example. If it is not small, the thermal stress relaxation effect is inferior, but it has been confirmed that a certain degree of effect can be expected even in the case of the same shape size.

  INDUSTRIAL APPLICABILITY The present invention can be effectively used in the field of a high heat-resistant semiconductor device having a junction structure in which the semiconductor device is made lead-free, improved in thermal fatigue life, and improved in heat resistance.

It is sectional drawing which shows one Example of the mounting structure of the semiconductor device by this invention. FIG. 2 is a partial cross-sectional view showing in detail a structure of a joint portion of the semiconductor device shown in FIG. 1. It is sectional drawing which shows the structure of one Example of the low thermal expansion member used for the semiconductor device by this invention. An example of the low thermal expansion member used for the semiconductor device by this invention is shown, (a) is a plane sectional view in the BB line shown to (b), (b) is the low heat shown to (a). It is sectional drawing in the AA of an expansion | swelling member. An example of the low thermal expansion member used for the semiconductor device by this invention is shown, (a) is a plane sectional view in the DD line | wire shown to (b), (b) is the low heat | fever shown to (a). It is sectional drawing in the CC line of an expansion member. It is sectional drawing which shows the modification of the low thermal expansion member used for the semiconductor device by this invention. An example of the low thermal expansion member used for the semiconductor device by this invention is shown, (a) is a plane sectional view in the FF line | wire shown to (b), (b) is the low heat | fever shown to (a). It is sectional drawing in the EE line of an expansion member. It is sectional drawing which shows one Example of the mounting structure of the semiconductor device to which the low thermal expansion member of FIG. 7 is applied. It is a phase diagram of the binary alloy of Sn-Sb. It is a graph which shows the Sb / (Sn + Sb) parameter dependence of the solid-phase / liquidus temperature characteristic of a Sn-Sb-Ag-Cu-type alloy. It is a graph which shows the Ag density | concentration dependence of the solid-phase / liquidus temperature characteristic of Sn-Sb-Ag-Cu-type solder. It is a graph which shows Cu concentration dependence of the solid-phase / liquidus temperature characteristic of Sn-Sb-Ag-Cu-type solder. It is sectional drawing which shows one Example of the mounting structure of the semiconductor device by this invention using the electrode member formed with the low thermal expansion material.

Explanation of symbols

  1: Semiconductor element, 2: Base electrode, 3: Lead electrode, 4a, 4b, 4, 5: Low thermal expansion member, 6, 6a, 7, 7a, 8, 8a, 9: Solder material, 10: Resin, 11: Electroless Ni-P plating, 12, 13, 14, 15: Electric Ni plating, 21: Low thermal expansion material, 22: Good conductor material, 22a: Good conductor matrix, 23: Ni plating, low thermal expansion material, 52: Base electrode, 53 : Lead electrode, 54, 55: Solder material, 56: Resin, A: Semiconductor device.

Claims (7)

A semiconductor element having a rectifying action; a lead electrode terminal electrically connected to one electrode surface of the semiconductor element by a bonding material; and a base electrode terminal connected to the other electrode surface of the semiconductor element by a bonding material; A semiconductor device comprising an insulating member that insulates and seals a joint portion between the semiconductor element and both the electrode terminals,
The bonding material is composed of an alloy material having a solidus temperature of 300 ° C. or higher and a liquidus temperature of 400 ° C. or lower, not containing Pb, and Sn and Sb as main constituent elements. Semiconductor device. A semiconductor element having a rectifying action; a lead electrode terminal electrically connected to one electrode surface of the semiconductor element by a bonding material; and a base electrode terminal connected to the other electrode surface of the semiconductor element by a bonding material; A semiconductor device comprising an insulating member that insulates and seals a joint portion between the semiconductor element and both the electrode terminals,
Between the lead electrode terminal and the electrode surface of the semiconductor element, the coefficient of thermal expansion is 10 ppm or less, and the outer dimension of the surface joined to the semiconductor element is smaller than the outer dimension of the electrode surface of the semiconductor element. 1 low thermal expansion member is disposed,
Between the base electrode terminal and the electrode surface of the semiconductor element, the coefficient of thermal expansion is 10 ppm or less, and the outer dimension of the surface joined to the semiconductor element is larger than the outer dimension of the electrode surface of the semiconductor element. 2 low thermal expansion members are arranged,
Between the base electrode terminal and the second low thermal expansion member, between the second low thermal expansion member and the semiconductor element, between the semiconductor element and the first low thermal expansion member, the first Between the low thermal expansion member and the lead electrode terminal, a solidus temperature of 300 ° C. or higher, and a liquidus temperature of 400 ° C. or lower, joining Pb-free alloys containing Sn and Sb as main constituent elements A semiconductor device characterized by being electrically connected by a material. The semiconductor device according to claim 1 or 2,
The bonding material includes 43 wt% ≦ Sb / (Sn + Sb) weight ratio <53 wt% in a composition ratio of Sn and Sb containing one or more of Ag and Cu and an amount of 5 to 30 wt%. Semiconductor device. The semiconductor device according to claim 3.
The semiconductor device is characterized in that the bonding material is an alloy containing at least one of 0.01 to 5 wt% of Ni, Ge, Zn, Ga and 0.005 to 0.5 wt% of P. The semiconductor device according to claim 1 or 2,
The semiconductor device according to claim 1, wherein the joining portion joined by the joining material has a metal material configuration of Ni / the joining material / Ni. The semiconductor device according to claim 2,
The first low thermal expansion member and / or the second low thermal expansion member have a structure in which a material having a coefficient of thermal expansion of 4 ppm or less and a highly conductive material are laminated,
The outer dimension of the first low thermal expansion member on the lead electrode terminal side is smaller than the outer dimension of the electrode surface of the semiconductor element;
A semiconductor device, wherein an outer dimension of the second low thermal expansion member on a base electrode terminal side is larger than an outer dimension of an electrode surface of the semiconductor element. The semiconductor device according to claim 2,
The first low thermal expansion member and / or the second low thermal expansion member are formed in a ring and joined to the semiconductor element,
The semiconductor device, wherein the lead electrode terminal and / or the base electrode terminal are joined to the semiconductor element inside the ring.

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