JP2005338482A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To significantly reduce the area occupied by an MLS arithmetic circuit in a semiconductor substrate in a semiconductor integrated circuit for driving a display device by using an MLS (multiline drive) method.
The semiconductor integrated circuit includes first latch circuits 20a to 20c for latching RGB image data for a plurality of lines, and RGB image data for a plurality of lines latched in the first latch circuit. A selector circuit 30 that sequentially selects one of them, an arithmetic circuit 40 that sequentially performs MLS arithmetic processing on the image data for a plurality of lines selected by the selector circuit, and image data that has been arithmetically operated by the arithmetic circuit. Second latch circuits 60a to 60c and 70 for latching, and a pulse width modulation circuit 80 for generating a plurality of display signals by performing pulse width modulation based on image data latched by the second latch circuit. To do.
[Selection] Figure 2

Description

  The present invention relates to a semiconductor integrated circuit (driver IC) for driving a display device such as an LCD (liquid crystal display), and in particular, a display device using an MLS (multi line selection) system. The present invention relates to a semiconductor integrated circuit which drives

  Liquid crystal panels are widely used in display units of small devices such as watches and mobile phones. The color tone (hue and brightness) of the image displayed on the liquid crystal panel is determined by the brightness of each color displayed based on the image data of R (red), G (green), and B (blue).

For example, when 16-bit image data is used, 5 bits are generally assigned to R (red), 6 bits are assigned to G (green), and 5 bits are assigned to B (blue), and 2 ⁶ = 64 for G (green). The brightness of the gradation can be displayed, and a total of 2 ¹⁶ = about 65k colors can be expressed. The R (red) and B (blue) image data are also used by converting the unit bit length from 5 bits to 6 bits in order to make the circuit common.

On the other hand, in the case of using 12-bit image data, the unit bit length of the image data of each color is 4 bits, and the brightness of 2 ⁴ = 16 gradations is displayed for each color, for a total of 2 ¹² = 4096 colors. Can be expressed. When the unit bit length of the image data of each color corresponds to both 4-bit and 6-bit image data, the 4-bit unit bit length is converted to 6 bits.

  By the way, a display signal to be supplied to a liquid crystal panel in order to determine the brightness of each color is generated using a PWM (pulse width modulation) system. For example, the display with the brightness of 64 gradations compares the image data having a unit bit length of 6 bits with the 6-bit data counted up and output at every predetermined timing, and until the two match, the liquid crystal is displayed. This is realized by causing the pixels of the panel to emit light and not causing the pixels of the liquid crystal panel to emit light after matching.

  When a simple matrix type liquid crystal panel is used, an MLS method in which a plurality of scanning electrodes are simultaneously selected may be used in order to improve the response speed of the liquid crystal panel. In the MLS method, MLS calculation for a plurality of fields is performed using a scanning pattern of a plurality of scanning electrodes selected simultaneously and gradation data for a plurality of lines corresponding to the scanning pattern, and the result is obtained. The combination of output voltages is supplied to the plurality of signal electrodes. Thereby, power consumption can be reduced while improving the response speed of the liquid crystal panel.

  As a related technique, the following Patent Document 1 discloses a display driving circuit that performs display driving while omitting unnecessary reading of gradation data when a plurality of reading operations are performed. In the display data RAM (random access memory) of this display drive circuit, memory cells holding gradation data for two lines are arranged in the output pad arrangement direction within the pitch of the output pads of the display drive circuit. Yes. The latch circuit latches the gradation data for four lines read from the display data RAM based on the first and second clock signals. The selector circuit selectively outputs gradation data for three consecutive lines from the gradation data latched by the latch circuit. The MLS signal conversion circuit generates an MLS calculation result of the simultaneous selection of three lines based on the gradation data for the three lines selected and output. The signal electrode drive circuit outputs a drive voltage to the output pad based on the MLS calculation result.

  Patent Document 2 below discloses a display drive circuit that can suppress deterioration of contrast ratio with a simple configuration that reduces the number of voltage levels when performing display drive by MLS. In this display drive circuit, the first to fourth bits of the gradation data corresponding to the display pattern for three lines are supplied to four ROMs (decode circuits). These ROMs use the orthogonal function defined by the combination of the scanning pattern and the dummy scanning pattern of the virtual electrode, and display patterns specified by the first to fourth bits of the gradation data and the corresponding dummy. The four-line simultaneous MLS calculation results performed on the display pattern are decoded and output based on the field signals f1 to f4.

However, in the display drive circuit described in Patent Document 1 or Patent Document 2, an MLS operation circuit (decode circuit) is required for each color of RGB (red, green, blue). The area occupied by the circuit becomes large.
JP 2003-173170 A (first page, FIG. 5) JP 2003-173168 A (first page, FIG. 2)

  Accordingly, in view of the above points, an object of the present invention is to significantly reduce the area occupied by an MLS arithmetic circuit in a semiconductor substrate in a semiconductor integrated circuit (driver IC) that drives a display device using the MLS method. .

  In order to solve the above problems, the semiconductor integrated circuit according to the present invention is based on RGB (red, green, blue) image data in accordance with a multi-line driving method that simultaneously selects a plurality of scanning electrodes of an image display device. A semiconductor integrated circuit for supplying RGB display signals to a plurality of signal electrodes of an image display device, wherein R image data for a plurality of lines, G image data for a plurality of lines, and B image data for a plurality of lines, Of a plurality of lines of R image data, a plurality of lines of G image data, and a plurality of lines of B image data latched in the first latch circuit. A selector circuit that sequentially selects one, and an operation that sequentially performs arithmetic processing according to a multiline driving method on image data for a plurality of lines selected by the selector circuit And a second latch circuit that latches image data that has been subjected to computation by the computation circuit, and generates a display signal of RGB by performing pulse width modulation based on the image data latched by the second latch circuit A pulse width modulation circuit.

  The semiconductor integrated circuit according to the present invention sequentially outputs RGB image data by performing processing for inverting the arrangement on the time axis for each display period in accordance with the control signal for the image data that has been subjected to the calculation by the arithmetic circuit. A left / right inverting circuit may be further provided.

  In that case, the second latch circuit sequentially outputs the R image data latched at the first timing from the RGB image data sequentially output from the left / right inversion circuit, and the left / right inversion circuit sequentially. Among the RGB image data to be outputted, the G latch circuit for latching the G image data at the second timing, and the RGB image data sequentially outputted from the left-right inversion circuit from the RGB image data at the third timing. A B latch circuit that latches image data, and an RGB latch circuit that latches RGB image data output from the R latch circuit, the G latch circuit, and the B latch circuit at the same timing may be included.

  In the above, the pulse width modulation circuit generates comparison data based on the count value output from the counter, compares the unit bit length image data with the comparison data, and based on the comparison result, the pulse of the display signal The width may be determined.

  The semiconductor integrated circuit according to the present invention may further include a plurality of output circuits that shift and output the levels of RGB display signals generated by the pulse width modulation circuit.

  According to the present invention, the arithmetic circuit sequentially performs arithmetic processing according to the multiline driving method on the image data sequentially selected by the selector circuit from among the RGB image data. The occupation area of the MLS arithmetic circuit can be greatly reduced. As a result, the area balance with the RAM circuit is improved, and the invalid area can be reduced. Further, it is possible to reduce the area of the semiconductor chip and increase the number of effective chips that can be taken out from one wafer.

Hereinafter, the best mode for carrying out the present invention will be described in detail with reference to the drawings.
FIG. 1 shows a configuration of an image display device using a semiconductor integrated circuit according to an embodiment of the present invention. In the present embodiment, a liquid crystal display device will be described as an example. In the present application, the substrate means a transparent insulating substrate, a printed substrate, a flexible substrate, or the like that can be electrically wired by mounting a liquid crystal display panel and a driver IC. A glass substrate is used.

  As shown in FIG. 1, the image display device includes a substrate 5, driver ICs 1 and 2 mounted on the substrate 5, and a liquid crystal panel 3. The driver IC (Y driver) 1 outputs a scanning signal for driving the liquid crystal panel 3 in synchronization with the line pulse. On the other hand, the driver IC (X driver) 2 has a RAM (Random Access Memory) 10 for storing image data representing image information to be displayed on the liquid crystal panel 3, and a display signal for driving the liquid crystal panel 3. And a line pulse is supplied to the Y driver 1. Here, an MPU (microprocessor unit) 4 is connected to the X driver 2, and the image data output from the MPU 4, the address used for designating the storage area of the image data in the RAM 10, A control signal is input to the X driver 2.

  The liquid crystal panel 3 has a plurality of regions in the segment direction and also has a plurality of regions in the common direction. Here, by specifying one region in the segment direction and one region in the common direction, one dot, that is, a pixel is specified. In the case of a color image display device, three dots of RGB (red, green, blue) are used to represent image information of one pixel.

  In order to apply a voltage to these regions, the liquid crystal panel 3 has a plurality of signal electrodes arranged in the segment direction and a plurality of scanning electrodes arranged in the common direction. The plurality of signal electrodes are respectively connected to a plurality of output terminals provided in the X driver 2, and the plurality of scanning electrodes are respectively connected to a plurality of output terminals provided in the Y driver 1.

  The X driver 2 generates display signals S1, S2,... For supplying to a plurality of signal electrodes arranged in the segment direction of the liquid crystal panel 3 based on the image data stored in the RAM 10. Here, if i = 1, 2,..., The display signal S (3i-2) is an R (red) display signal, and the display signal S (3i-1) is an G (green) signal. This is a display signal, and the display signal S (3i) is a B (blue) display signal.

  The Y driver 1 generates scanning signals C1, C2,... For scanning the liquid crystal panel 3 in accordance with the line pulse supplied from the X driver 2, and a plurality of Y signals arranged in the common direction of the liquid crystal panel 3. Are respectively supplied to the scanning electrodes.

  In the present invention, the liquid crystal panel 3 is driven by an MLS (multi-line drive) system that simultaneously selects a plurality of scanning electrodes. In the MLS method, when the number of simultaneously selected scan electrodes is m, the Y driver 1 scans the scan electrodes in units of m lines, and the X driver 2 generates a segment waveform based on the display pattern in units of n lines. A display signal having the same is supplied to the signal electrode. Here, n and m are natural numbers, and n = m may be set. This segment waveform is specified by the MLS calculation performed on the display pattern using an orthogonal function corresponding to the scan pattern of the scan electrode.

  In general, in the MLS method of m-line simultaneous selection, the number of voltage levels required for driving the scan electrodes is 3, and the number of voltage levels required for driving the signal electrodes is (m + 1). These voltage levels are generated by the power supply circuit and supplied to the Y driver 1 and the X driver 2.

  FIG. 2 is a block diagram showing a configuration of the X driver shown in FIG. The X driver uses a plurality of lines of the image display device based on RGB image data in accordance with a multi-line driving method that simultaneously selects scan electrodes of a plurality of lines (in this embodiment, three lines) of the image display device. RGB display signals are supplied to the signal electrodes.

  As shown in FIG. 2, the X driver has a RAM 10 that stores RGB image data supplied from the MPU 4 shown in FIG. 1, a latch circuit 20 that latches RGB image data for three lines, and a latch circuit 20. A selector circuit 30 that sequentially selects one of the latched RGB image data, and an MLS operation that sequentially performs MLS operation processing according to the multiline driving method on the image data selected by the selector circuit 30 Circuit 40. Here, the RAM 10 includes an R data RAM 10a for storing R data, a G data RAM 10b for storing G data, and a B data RAM 10c for storing B data. The latch circuit 20 includes an R latch circuit 20a that latches R data for three lines, a G latch circuit 20b that latches G data for three lines, and a B latch circuit 20c that latches B data for three lines. Including.

  Further, the X driver performs processing for inverting the arrangement on the time axis for each display period in accordance with the control signal for the image data that has been calculated by the MLS arithmetic circuit 40, and sequentially outputs RGB image data. The left / right inversion circuit 50, an R latch circuit 60a for latching R data at a first timing out of RGB image data sequentially output from the left / right inversion circuit 50, and a G for latching G data at a second timing A latch circuit 60b, a B latch circuit 60c that latches B data at a third timing, an RGB latch circuit 70 that latches RGB image data output from the latch circuits 60a to 60c at the same timing, and an RGB latch RGB display signals by performing pulse width modulation based on the image data latched in the circuit 70 And generating PWM circuit 80 which has the R output circuit 90a that outputs by shifting the level of the RGB of the display signal generated by the PWM circuit 80, G output circuit 90b, and a B output circuit 90c.

Next, the operation of the X driver shown in FIG. 2 will be described with reference to FIGS.
FIG. 3 is a timing chart for explaining the operation of the X driver shown in FIG. As shown in FIG. 3, a clock signal CLK having a period of 1/16 of the reference clock signal CL is generated in synchronization with the reference clock signal CL representing one image display period. Based on the clock signal CLK, three clock signals CLK1 to CLK3 having different timings, a signal PRC used for reading out image data for three lines from the RAM 10, and a signal used for generating a read address of the RAM 10 are used. LCDRDAD is generated. Based on the signal LCDRDAD, the read addresses of the RAM 10 are calculated as “0”, “1”, “2”,.

  In synchronization with the clock signals CLK1 to CLK3, the R latch circuit 20a latches R data for three lines, the G latch circuit 20b latches G data for three lines, and the B latch circuit 20c has three lines. Latch the minute B data.

  Further, selection signals RSEL, GSEL, and BSEL are generated based on the clock signal CLK. The selector circuit 30 selects R data for three lines latched in the R latch circuit 20a when the selection signal RSEL is at a low level, and the G latch circuit 20b when the selection signal GSEL is at a low level. When the selection signal BSEL is at a low level, the B data for three lines latched in the B latch circuit 20c is selected. Note that one of the selection signals RSEL, GSEL, and BSEL is always set to a low level so that the output signal level of the selector circuit 30 does not become unstable.

  The MLS arithmetic circuit 40 sequentially performs MLS arithmetic processing on the image data selected by the selector circuit 30 in accordance with signals FX1 to FX4 indicating the order of four fields constituting one frame. The MLS arithmetic circuit 40 performs orthogonal arithmetic processing corresponding to each field in each field, and an image of one frame is displayed by making a round of these four fields.

  The left / right reversing circuit 50 performs left / right reversing processing for reversing the arrangement on the time axis for each display period in accordance with the control signal L / R with respect to the image data that has been calculated by the MLS calculating circuit 40. Thereby, the waveform of the display signal in two consecutive display periods can be made symmetrical (in the case of a still image), and the level change of the display signal at the edge of the screen can be reduced.

  Further, three clock signals RCLK, GCLK, and BCLK having different timings are generated based on the clock signal CLK. The R latch circuit 60 a latches R data among the RGB image data sequentially output from the left / right inversion circuit 50 in synchronization with the clock signal RCLK, and the G latch circuit 60 b is sequentially output from the left / right inversion circuit 50. The RGB data is latched in synchronization with the clock signal GCLK, and the B latch circuit 60c is synchronized with the clock signal BCLK from the RGB image data sequentially output from the left / right inversion circuit 50. The B data is latched.

  The RGB latch circuit 70 latches RGB image data output from the latch circuits 60a to 60c in synchronization with the reference clock signal CL. The PWM circuit 80 generates comparison data based on the count value output from the counter that counts the clock signal for generating comparison data, compares the unit bit length image data with the comparison data, and outputs the comparison result. Based on this, the pulse width of the display signal is determined. The RGB display signals generated by the PWM circuit 80 are output to the output pad via the R output circuit 90a, the G output circuit 90b, and the B output circuit 90c.

  The present invention can be used in a semiconductor integrated circuit (driver IC) for driving a display device such as an LCD.

1 is a diagram showing an image display device using a semiconductor integrated circuit according to an embodiment of the present invention. The block diagram which shows the structure of X driver shown in FIG. The timing chart for demonstrating operation | movement of the X driver shown in FIG.

Explanation of symbols

  1 Y driver, 2 X driver, 3 liquid crystal panel, 4 MPU (microprocessor unit), 5 substrate, 10 RAM (random access memory), 10a R data RAM, 10b G data RAM, 10c B data RAM, 20 latch circuit, 20a R latch circuit, 20b G latch circuit, 20c B latch circuit, 30 selector circuit, 40 MLS arithmetic circuit, 50 horizontal inversion circuit, 60a R latch circuit, 60b G latch circuit, 60c B latch circuit, 70 RGB latch circuit, 80 PWM circuit, 90a R output circuit, 90b G output circuit, 90c B output circuit

Claims (5)

RGB display signals are supplied to the plurality of signal electrodes of the image display device based on RGB (red, green, blue) image data in accordance with a multi-line driving method that simultaneously selects a plurality of scan electrodes of the image display device. A semiconductor integrated circuit,
A first latch circuit for latching R image data for a plurality of lines, G image data for a plurality of lines, and B image data for a plurality of lines;
A selector circuit for sequentially selecting one of a plurality of lines of R image data, a plurality of lines of G image data, and a plurality of lines of B image data latched in the first latch circuit; ,
An arithmetic circuit that sequentially performs arithmetic processing according to a multi-line driving method on image data for a plurality of lines selected by the selector circuit;
A second latch circuit that latches image data that has been subjected to computation by the arithmetic circuit;
A pulse width modulation circuit for generating RGB display signals by performing pulse width modulation based on the image data latched by the second latch circuit;
A semiconductor integrated circuit comprising:   The image processing apparatus further includes a left / right reversing circuit for sequentially outputting the RGB image data by performing processing for reversing the arrangement on the time axis for each display period in accordance with the control signal with respect to the image data calculated by the arithmetic circuit. The semiconductor integrated circuit according to claim 1. The second latch circuit comprises:
An R latch circuit that latches R image data at a first timing out of RGB image data sequentially output from the left-right inversion circuit;
A G latch circuit that latches G image data at a second timing from among RGB image data sequentially output from the left-right inversion circuit;
A B latch circuit that latches B image data at a third timing from among RGB image data sequentially output from the left-right inversion circuit;
An RGB latch circuit that latches RGB image data respectively output from the R latch circuit, the G latch circuit, and the B latch circuit at the same timing;
The semiconductor integrated circuit according to claim 2, comprising:   The pulse width modulation circuit generates comparison data based on the count value output from the counter, compares the unit bit length image data with the comparison data, and determines the pulse width of the display signal based on the comparison result. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is determined.   5. The semiconductor integrated circuit according to claim 1, further comprising a plurality of output circuits that shift and output levels of RGB display signals generated by the pulse width modulation circuit.

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