JP2005331949A - Power supply voltage removal sensing circuit and display device - Google Patents

Abstract

A power supply voltage removal sensing circuit and a display device are provided.
A power supply voltage removal sensing circuit according to an embodiment of the present invention includes a detection unit and an output unit. The detection unit detects that one voltage level of the first power supply voltage and the second power supply voltage becomes the second level, and outputs a detection signal at the first level. The output unit prevents malfunction of the detection unit, inverts the detection signal in response to the operation activation signal, and outputs it as a detection control signal. The detection unit outputs a detection signal at the second level while the voltage levels of the first power supply voltage and the second power supply voltage are maintained at the first level. The first power supply voltage and the second power supply voltage are If the battery is removed, the voltage levels of the first power supply voltage and the second power supply voltage become the second level with different time differences.
[Selection] Figure 1

Description

  The present invention relates to a power supply voltage removal sensing circuit and a display device including a power supply voltage removal sensing circuit, and more particularly, to a display device and method for removing a panel afterimage at the time of battery removal by using the power supply voltage removal sensing circuit.

  If a battery that generates a power supply voltage is removed from a display device (for example, a TFT-LCD) using an active matrix system, an image remains on the liquid crystal panel for a certain period of time and gradually disappears.

  In the display device using the passive matrix method, if the battery is removed, a method of discharging the panel driving voltage using a discharge circuit to eliminate the image is used. That is, when the battery is removed, the drive voltage applied to the panel is forcibly discharged, and the image remaining on the panel is forcibly lost.

  More specifically, when the battery is removed, the driving voltage (VGH, VGL, AVDD, etc.) for driving the liquid crystal panel is forcibly discharged. VGH and VGL are voltages for controlling the gate lines of the panel, and AVDD is an output voltage of the source driver. VGH and AVDD are voltages obtained by stepping up the power supply voltage, and VGL is a voltage obtained by stepping down the power supply voltage and has a negative voltage level.

  The forced discharge method utilizes the fact that the voltage VGOFF for turning off the gate line of the panel is a negative voltage, and if the VGOFF voltage is not a negative voltage but becomes a ground voltage level by discharge, Even if the gate line of the panel is not completely turned on, a constant current can flow.

  Therefore, when the output voltage AVDD of the source driver is discharged to the ground voltage level in a state in which the gate line of the panel can flow a constant current, the charge stored in the capacitor of the panel is removed, and the image disappears. Depending on the characteristics of the panel, the panel may be white or black.

  However, unlike the display device using the passive matrix method, the display device using the active matrix method does not use the forced discharge method, so it takes time for the image to disappear on the panel when the battery is removed, and the screen is displayed at once. There is a problem that is not removed cleanly.

An object of the present invention is to provide a power supply voltage removal sensing circuit that recognizes battery removal.
Another problem to be solved by the present invention is to provide a display device that includes a power supply voltage removal sensing circuit and removes a panel afterimage at the time of battery removal.
Another problem to be solved by the present invention is to provide a method for removing an afterimage that appears on a panel when a battery of a display device having a power supply voltage removal sensing circuit is removed.

In order to solve the above problems, a power supply voltage removal sensing circuit according to an embodiment of the present invention includes a detection unit and an output unit.
The detection unit detects that one voltage level of the first power supply voltage and the second power supply voltage becomes the second level, and outputs a detection signal at the first level.
The output unit prevents malfunction of the detection unit, inverts the detection signal in response to an operation activation signal, and outputs the inverted detection signal.
The detection unit outputs the detection signal at a second level while the voltage levels of the first power supply voltage and the second power supply voltage are maintained at the first level, and the first power supply voltage and the second power supply voltage are output. The second power supply voltage is a voltage generated from the battery. When the battery is removed, the voltage levels of the first power supply voltage and the second power supply voltage become the second level with different time differences.
The detection unit includes a voltage level control unit and a comparison unit.

  The voltage level controller controls the voltage level of the first node to be higher than the voltage level of the second node while the first power supply voltage and the second power supply voltage are maintained at the first level. If one voltage level of the first power supply voltage and the second power supply voltage is a second level, the voltage level of the first node is controlled to be lower than the voltage level of the second node.

  The comparator operates in response to the boosted voltage, compares the voltage levels of the first node and the second node, and generates the detection signal.

The voltage level controller includes a first transistor, a first resistor, a second resistor, a second transistor, a third resistor, and a third transistor.
The first transistor receives the second power supply voltage at a gate, and has a first end connected to the first node. The first resistor has one end connected to the second end of the first transistor and the other end connected to the first voltage.
The second resistor is connected between the first node and the second node. The second transistor receives the second power supply voltage at its gate, has a first end connected to the second node, and a second end connected to the comparison unit.
The third resistor has one end connected to the second node. The third transistor has a first end connected to the other end of the third resistor, a first control signal applied to the gate, and a second end connected to the ground voltage.

  The first control signal is generated at the first level when the generation of the boosted voltage is completed. The comparison unit includes a comparator, a capacitor, and a fourth transistor. The comparator operates in response to the boosted voltage, and a negative terminal is connected to the first node, and a positive terminal is connected to the second terminal of the second transistor, and outputs the detection signal.

  A capacitor is coupled between the positive terminal of the comparator and a ground voltage. The fourth transistor is connected in parallel with the capacitor between the positive terminal of the comparator and the ground voltage, and receives a reset pulse at the gate.

  The reset pulse discharges the charge charged in the capacitor in the initial operation of the power supply voltage removal sensing circuit.

  The output unit includes a down-shifting unit that lowers the voltage level of the detection signal, a delay unit that delays the output of the down-shifting unit, a logical product that ANDs the output of the delay unit and the output of the down-shifting unit And a latch unit that inverts the output of the AND means and outputs it as the detection control signal when the operation activation signal is activated.

  The downshifting unit includes n inverters connected in series, and the inverter operates in response to the first power supply voltage, where n is an even number.

  According to an embodiment of the present invention for solving the other problems, a display device for removing a panel afterimage when removing a battery at a time includes a panel and a drive driver for controlling the panel to display an image on the panel. Prepare.

The driving driver includes a power supply voltage removal sensing unit, a voltage boosting unit, a microprocessor, a source driver, and a gate driver.
The power supply voltage removal sensing unit generates a detection control signal at a second level when the battery for supplying the power supply voltage to the driver and the panel is removed. The voltage booster cuts off the boosted voltage applied to the panel in response to the detection control signal.

  The microprocessor blocks the control signal received by the drive driver in response to the detection control signal. The source driver and the gate driver control the source line and the gate line of the panel in response to the detection control signal.

  The gate driver activates every gate line of the panel in response to the second level detection control signal, and the source driver responds to the second level detection control signal in response to the second level detection control signal. The voltage level at the output end of every source line is set to the ground voltage level.

  In response to the second level detection control signal, the panel sets a voltage level of a reference voltage connected to a capacitor in the panel to a ground voltage level. The panel is an active matrix type panel.

  An afterimage removal method according to an embodiment of the present invention for solving the other problems includes a panel and a panel at the time of battery removal of a display device including a drive driver that controls the panel and displays an image on the panel. The present invention relates to an afterimage removal method that appears.

  Recognizing the removal of the battery and generating a detection control signal at a second level; in response to the detection control signal, blocking a boosted voltage applied to the panel; Severing a control signal received by the drive driver in response to a detection control signal, and discharging all charges charged in a capacitor of the panel at a time in response to the detection control signal.

  The step of discharging all the charges at one time includes the step of activating all the gate lines of the panel in response to the detection control signal, and the output terminal of every source line of the panel in response to the detection control signal. And setting the voltage level of the reference voltage connected to the capacitor in the panel to the ground voltage level in response to the detection control signal.

  The step of generating the detection control signal detects that one voltage level of the first power supply voltage and the second power supply voltage generated from the battery is the second level, and sets the detection signal at the first level. And a step of inverting the detection signal in response to an operation activation signal and outputting it as the detection control signal.

  According to another aspect of the present invention, there is provided a power supply voltage removal sensing method according to an embodiment of the present invention, wherein one voltage level of a first power supply voltage and a second power supply voltage generated from a battery is a second level. Detecting and outputting a detection signal at a first level, and inverting the detection signal in response to an operation activation signal and outputting it as a detection control signal.

  The step of outputting the detection signal includes outputting the detection signal at a second level while the voltage levels of the first power supply voltage and the second power supply voltage are maintained at the first level, and the battery is removed. Then, the voltage levels of the first power supply voltage and the second power supply voltage become the second level with different time differences.

  The power supply voltage removal sensing circuit according to the present invention, the display device including the power supply voltage removal sensing circuit, and the afterimage removal method that appears on the panel when the battery of the display device is removed use an active matrix method when the battery is forcibly removed. The image remaining on the panel can be removed quickly.

  For a full understanding of the invention and the operational advantages of the invention and the objects achieved by the practice of the invention, reference should be made to the accompanying drawings illustrating preferred embodiments of the invention and the contents described in the accompanying drawings. You must refer to it.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same reference numerals provided in each drawing denote the same members.
FIG. 1 is a circuit diagram illustrating a power supply voltage removal sensing circuit according to an embodiment of the present invention.
As shown in FIG. 1, the power supply voltage removal sensing circuit 100 according to the embodiment of the present invention includes a detection unit 110 and an output unit 140. The detection unit 110 detects that one voltage level of the first power supply voltage VDD and the second power supply voltage VCI becomes the second level, and outputs the detection signal DETS at the first level.

  The detection unit 110 outputs the detection signal DETS at the second level while the voltage levels of the first power supply voltage VDD and the second power supply voltage VCI are maintained at the first level. For convenience of explanation, it is assumed that the first level is a high level and the second level is a low level.

  The output unit 140 prevents malfunction of the detection unit 110, inverts the detection signal DETS in response to the operation activation signal S2, and outputs it as the detection control signal DETCTRLS.

  In the battery, two power supply voltages, the first power supply voltage VDD and the second power supply voltage VCI, are generated. The first power supply voltage VDD is a voltage that controls the logic level of the power supply voltage removal sensing circuit 100, and the second power supply voltage VCI is an analog voltage and has a higher voltage level than the first power supply voltage VDD.

When the battery is removed, the voltage levels of the first power supply voltage VDD and the second power supply voltage VCI become the second level with different time differences. That is, if the battery is removed, one of the first power supply voltage VDD and the second power supply voltage VCI first falls to the second level, and the other falls to the second level later.
Accordingly, the power supply voltage removal sensing circuit 100 senses a voltage that falls first to the second level among the first power supply voltage VDD and the second power supply voltage VCI.

The detection unit 110 includes a voltage level control unit 120 and a comparison unit 130. The voltage level controller 120 causes the voltage level of the first node N1 to be higher than the voltage level of the second node N2 while the first power supply voltage VDD and the second power supply voltage VCI are maintained at the first level. To control.
When the voltage level of one of the first power supply voltage VDD and the second power supply voltage VCI becomes the second level, the detection unit 110 causes the voltage level of the first node N1 to be higher than the voltage level of the second node N2. Control to lower.
More specifically, the voltage level controller 120 includes a first transistor TR1, a second transistor TR2, a third transistor TR3, a first resistor R1, a second resistor R2, and a third resistor R3.

The first transistor TR1 receives the second power supply voltage VCI at its gate, and has a first end connected to the first node N1. The first resistor R1 has one end connected to the second end of the first transistor TR1 and the other end connected to the first power supply voltage VDD.
The second resistor R2 is connected between the first node N1 and the second node N2. The second transistor TR2 receives the second power supply voltage VCI at its gate, and has a first end connected to the second node N2 and a second end connected to the comparison unit 130.
The third resistor R3 has one end connected to the second node N2. The third transistor TR3 has a first end connected to the other end of the third resistor R3, a first control signal S1 applied to the gate, and a second end connected to the ground voltage VSS.

The first control signal S1 is generated at the first level when the generation of the boosted voltage AVDD is completed.
The comparator 130 operates in response to the boosted voltage AVDD, compares the voltage levels of the first node N1 and the second node N2, and generates the detection signal DETS.

  The comparison unit 130 includes a comparator COMP, a capacitor C, and a fourth transistor TR4. The comparator COMP operates in response to the boosted voltage AVDD, the negative terminal is connected to the first node N1, the positive terminal is connected to the second terminal of the second transistor TR2, and the detection signal DETS is output. .

Capacitor C is connected between the positive terminal of comparator COMP and ground voltage VSS. The fourth transistor TR4 is connected in parallel with the capacitor C between the positive terminal of the comparator COMP and the ground voltage VSS, and receives the reset pulse RST_PULSE at the gate.
The reset pulse RST_PULSE discharges the charge charged in the capacitor C in the initial operation of the power supply voltage removal sensing circuit 100.

The operation of the detection unit 110 will be described. First, the reset pulse RST_PULSE discharges charges that may be stored in the capacitor C to prevent the comparator COMP from malfunctioning. The reset pulse RST_PULSE is a rectangular wave having a short high level period. During the high level period of the reset pulse RST_PULSE, the fourth transistor TR4 is turned on to discharge the charge stored in the capacitor C.
The first control signal S1 is generated at the first level when the generation of the boosted voltage AVDD is completed.

  The boosted voltage AVDD is a driving voltage for driving the display device when the power supply voltage removal sensing circuit 100 is mounted on a display device (not shown) including a panel. The boosted voltage AVDD has a voltage level obtained by boosting the power supply voltage by a voltage booster (not shown) of a display device (not shown).

  In the standby mode or sleep mode of the display device (not shown), the first control signal S1 is generated at the second level, that is, the low level, and turns off the third transistor TR3. As a result, the power supply voltage removal sensing circuit 100 does not operate and current consumption can be reduced.

  Completion of generation of the boosted voltage AVDD means that the display device operates normally. When the generation of the boosted voltage AVDD is completed, the first control signal S1 is generated at a high level to turn on the third transistor TR3. Thereby, the detection unit 110 is in a state where it can recognize the removal of the battery.

  When the battery is mounted and the first power supply voltage VDD and the second power supply voltage VCI operate normally, the first transistor TR1 and the second transistor TR2 are turned on, and the first resistor R1, the second resistor R2, and the second resistor The voltage level of the first node N1 and the second node N2 is determined by the resistance value of the three resistor R3, and the voltage level of the first node N1 is higher than the voltage level of the second node N2.

Therefore, the comparator COMP generates a low level detection signal DETS.
The first to third resistors R1, R2, and R3 distribute the first power supply voltage VDD according to the resistance ratio, and set a threshold voltage Vth condition of the first and second transistors TR1 and TR2 that detect the second power supply voltage VCI. By satisfying and adjusting the voltage across the comparator COMP, a faster detection level when removing the battery can be determined.

  If the resistance value of the first resistor R1 is 0, the voltage determination of the first node N1 varies depending on the relationship between the first power supply voltage VDD and the second power supply voltage VCI. That is, when the second power supply voltage VCI is higher than the first power supply voltage VDD as much as the threshold voltage Vth of the first transistor TR1 that receives the second power supply voltage VCI at the gate, it is in the vicinity of the level of the first power supply voltage VDD. The voltage level of the first node N1 is determined.

  The output unit 140 ANDs the downshifting unit 150 that lowers the voltage level of the detection signal DETS, the delay unit 160 that delays the output of the downshifting unit 150, the output of the delay unit 160, and the output of the downshifting unit 150. When the logical product 170 and the operation activation signal S2 are activated, a latch unit 180 that inverts the output of the logical product 170 and outputs the inverted signal as the detection control signal DETCTRLS is provided.

The downshifting unit 150 includes n inverters I1 and I2 connected in series. The inverters I1 and I2 operate in response to the first power supply voltage VDD, and n is an even number.
Since the comparator COMP operates in response to the boost voltage AVDD, the level of the detection signal DETS output from the comparator COMP is also the voltage level of the first power supply voltage VDD which is the logic power supply voltage level of the power supply voltage removal sensing circuit 100. taller than.
Accordingly, the downshifting unit 150 serves to lower the level of the detection signal DETS to the first power supply voltage VDD level that allows logic operation.

The delay unit 160 functions to prevent malfunction when the first power supply voltage VDD and the second power supply voltage VCI fluctuate and the output of the comparator COMP instantaneously becomes a high level to cause malfunction.
That is, while the first power supply voltage VDD and the second power supply voltage VCI operate normally and the detection signal DETS is generated at the low level, the comparator COMP instantaneously malfunctions and the detection signal DETS is generated for a certain time. If the signal level is high, the signal directly input to the logical product unit 170 is high level, but the signal input to the logical product unit 170 after passing through the delay unit 160 is low level. The means 170 continues to output a low level signal.
Therefore, using the delay unit 160 and the logical product means 170, it is possible to prevent malfunction due to an instantaneous glitch of the first power supply voltage VDD or the second power supply voltage VCI. The malfunction prevention function can be adjusted by selectively setting the delay time of the delay unit 160.

  When the operation activation signal S2 is activated, the latch unit 180 inverts the output of the AND unit 170 and outputs the inverted signal as the detection control signal DETCTRLS. When the power supply voltage removal sensing circuit 100 is mounted on a display device (not shown), the operation activation signal S2 is activated to the first level when an image is displayed on the panel of the display device (not shown). The

  Since the removal of the battery has no effect on the panel before the image is displayed on the panel, the operation activation signal S2 is detected in order to detect the removal of the battery only after the image is actually displayed on the panel. Is used.

FIG. 2 is a flowchart for explaining the operation of the power supply voltage removal sensing circuit of FIG.
FIG. 3A is a flowchart illustrating step 210 of FIG.
FIG. 3B is a flowchart illustrating step 220 of FIG.
Hereinafter, the operation of the power supply voltage removal sensing circuit 100 will be described in detail with reference to FIGS.
The power supply voltage removal sensing method 200 detects that one voltage level of the first power supply voltage VDD and the second power supply voltage VCI generated from the battery is the second level, and sets the detection signal DETS at the first level. Output (step 210). Step 210 is performed by the detection unit 110 of FIG.

Further explaining step 210, the voltage level of the first node N1 is higher than the voltage level of the second node N2 while the first power supply voltage VDD and the second power supply voltage VCI are maintained at the first level. Control.
Then, if one of the first power supply voltage VDD and the second power supply voltage VCI becomes the second level, the voltage level of the first node N1 is controlled to be lower than the voltage level of the second node N2. (Step 310a). Step 310a is performed by the voltage level controller 120 of FIG.
The voltage levels of the first node N1 and the second node N2 are compared to generate the detection signal DETS (step 310b). Step 310b is performed by the comparison unit 130 of FIG.

When the battery is forcibly removed and the second power supply voltage VCI falls to the low level before the first power supply voltage VDD, the power supply voltage removal sensing circuit 100 operates as follows.
If the second power supply voltage VCI goes low while the first node N1 and the second node N2 are maintained at a constant voltage level, the first and second transistors TR1 and TR2 are turned off.
Thus, the voltage level of the positive terminal of the comparator COMP is maintained as it is by the turned off second transistor TR2, and only the voltage level of the negative terminal, that is, the voltage level of the first node N1 continues to decrease.
Therefore, the voltage level of the positive terminal of the comparator COMP is higher than the voltage level of the negative terminal, and the comparator COMP outputs the detection signal DETS at a high level. When the level of the detection signal DETS becomes a high level, the power supply voltage removal sensing circuit 100 senses forced removal of the battery.

Conversely, when the first power supply voltage VDD falls to the low level before the second power supply voltage VCI, the voltage level of the positive terminal of the comparator COMP is changed by the capacitor C to the voltage level of the negative terminal (that is, the first power supply voltage VCI). The voltage level of the positive terminal of the comparator COMP becomes higher than the voltage level of the negative terminal, and the comparator COMP sets the detection signal DETS to high. Output by level.
When the first power supply voltage VDD falls to the low level before the second power supply voltage VCI, the removal of the battery can be detected as the capacity of the capacitor C increases.

  The output detection signal DETS is logically ANDed if the detection signal DETS is delayed 320a, the detection signal DETS is ANDed with the delayed detection signal 320b, and the operation activation signal S2 is activated. The signal is inverted and output as the detection control signal DETCTRLS through step 320c which outputs the detection control signal DETCTRLS.

  Steps 320a to 320c are performed by the output unit 140 of FIG. The high level detection signal DETS is input to the latch unit 180 through the downshifting unit 150 and the delay unit 160.

  In response to the operation activation signal S2, the latch unit 180 inverts the logic level of the detection signal DETS and outputs the inverted signal as the detection control signal DETCTRLS. That is, when the battery is removed, the detection control signal DETCTRLS is output at a low level.

  As described above, if the battery is forcibly removed, the power supply voltage removal sensing circuit 100 inverts the logic level of the detection control signal DETCCTRLS from the high level to the low level and outputs it, thereby removing the battery. It can be perceived.

FIG. 4 is a circuit diagram of a power supply voltage removal sensing circuit according to another embodiment of the present invention.
The detection unit 410 of the power supply voltage removal sensing circuit 400 of FIG. 4 has the same configuration as the detection unit 110 of the power supply voltage removal sensing circuit 100 of FIG. However, the structure of the output unit 440 is different.
The output unit 440 of the power supply voltage removal sensing circuit 400 of FIG. 4 includes a downshifting unit 450, a delay unit 460, an inverted OR unit 470, an AND unit 480, and an inverter I2.
The downshifting unit 450 lowers the voltage level of the detection signal DETS. The delay unit 460 delays the output of the downshifting unit 450. The inverting OR unit 470 performs inverting OR of the output of the delay unit 460 and the output of the downshifting unit 450.

The logical product means 480 logically ANDs the operation activation signal S2 and the output of the inverted logical sum means 470. The inverter I2 inverts the output of the logical product means 480 and outputs it as the detection control signal DETCTRLS.
The downshifting unit 450 includes an inverter I1 that inverts the detection signal DETS, and the inverter I1 operates in response to the first power supply voltage VDD.

  The output unit 440 of FIG. 4 outputs the detection control signal DETCRLS using the inverted OR means 470 instead of the latch unit 180 of the output unit 140 of FIG. 1, and the operation principle of the output unit 440 of FIG. Since it is the same as the operation principle of the output unit 140 in FIG. 1, detailed description thereof is omitted.

FIG. 5 is a circuit diagram of a power supply voltage removal sensing circuit according to still another embodiment of the present invention.
The output unit 540 of the power supply voltage removal sensing circuit 500 of FIG. 5 has the same configuration as the output unit 440 of the power supply voltage removal sensing circuit 400 of FIG. However, the structure of the detection unit 510 is different.
5 includes a first resistor R1, first transistors TR11, TR12 to TR1n, a second resistor R2, second transistors TR21, TR22 to TR2n, a third resistor R3, and a third transistor TR3. .
The first resistor R1 has one end connected to the first power supply voltage VDD. The plurality of first transistors TR11 and TR12 to TR1n are connected in series between the other end of the first resistor R1 and the first node N1, and gate the corresponding second power supply voltages VCI1 and VCI2 to VCIn. Receive at.
The second resistor R2 is connected between the first node N1 and the second node N2. The second transistors TR21 and TR22 to TR2n are connected in series between the second node N2 and the comparison unit 530, and receive a plurality of corresponding second power supply voltages VCI1 and VCI2 to VCIn at their gates. The third resistor R3 has one end connected to the second node N2.
The third transistor TR3 has a first end connected to the other end of the third resistor R3, a first control signal S1 applied to the gate, and a second end connected to the ground voltage VSS.

The voltage level control unit 520 of the power supply voltage removal sensing circuit 500 of FIG. 5 is described as being capable of a circuit that senses a plurality of power supply voltages. The operation of the voltage level control unit 520 is the same as the operation of detecting two power supply voltages by the voltage level control unit 120 of FIG.
That is, if any one of the first power supply voltage VDD or the plurality of second power supply voltages VCI1, VCI2 to VCIn falls to a low level, the voltage levels of the first node N1 and the second node N2 are reversed.
Therefore, the logic level of the detection control signal DETCCTRLS changes from the high level to the low level. Here, the plurality of second power supply voltages VCI1, VCI2 to VCIn can be generated from a plurality of batteries.

FIG. 6 is a block diagram illustrating a display apparatus according to an embodiment of the present invention.
FIG. 7 is a diagram illustrating the internal structure of the panel of FIG.
As shown in FIG. 6, the display device 600 that removes the panel afterimage at the time of removing the battery at a time includes a panel 610 and a drive driver 620 that controls the panel 610 and displays an image on the panel 610.
The driving driver 620 includes a power supply voltage removal sensing unit 630, a voltage boosting unit 640, a microprocessor 650, a source driver 660, and a gate driver 670. The panel 610 is an active matrix type panel.

  The voltage booster 640 generates a boosted voltage and applies it to the inside of the drive driver 620 and the panel 610. The source driver 660 and the gate driver 670 control the source line and the gate line of the panel 610. The operations of the source driver 660 and the gate driver 670 are controlled by the microprocessor 650.

FIG. 8 is a flowchart illustrating a method for removing an afterimage of a panel when removing a battery from a display device according to another embodiment of the present invention.
FIG. 9 is a flowchart illustrating step 840 of FIG. Hereinafter, based on FIGS. 6 to 9, a display device and a method for removing an afterimage of a panel when the battery of the display device is removed will be described.
First, the removal of the battery is recognized and a detection control signal is generated at the second level (step 810). Step 810 is performed by the power supply voltage removal sensing unit 630 of FIG.
The power supply voltage removal sensing unit 630 has the same configuration as the power supply voltage removal sensing circuit 100 of FIG. 1, and the operation principle is the same.
That is, if the battery is removed, the voltage level of the first power supply voltage VDD or the second power supply voltage VCI decreases, and the power supply voltage removal sensing circuit 100 senses it and generates the detection signal DETS. Is generated as a detection control signal DETCCTRLS. If the battery is removed, the detection control signal DETCTRLS is generated at a second level, that is, a low level.

Since the circuit configuration and operation of the power supply voltage removal sensing circuit 100 in FIG. 1 have been described above, detailed description thereof will be omitted.
In response to the detection control signal DETCCTRLS, the boosted voltage applied to the panel 610 is cut off (step 820). Step 820 is performed by the voltage booster 640. The voltage booster 640 generates a boosted voltage while the detection control signal DETCTRLS is generated at the first level, that is, the high level.

However, if the detection control signal DETCTRLS is generated at the second level, the voltage booster 640 blocks the boosted voltage applied to the panel 610.
If the battery is removed, the supply of the power supply voltage is interrupted, so that the voltage booster 640 interrupts the generation of the boosted voltage. The boosted voltage that has already been generated is used to perform the subsequent operations of the display apparatus 600, that is, the operations of Step 830 and Step 840.
In response to the detection control signal DETCCTRLS, the control signal received by the drive driver 620 is blocked (step 830). Step 830 is performed by the microprocessor 650. The microprocessor 650 receives control signals (not shown) from the outside and controls the operations of the drive driver 620 and the panel 610.

  However, if the detection control signal DETCCTRLS is generated at a low level, the microprocessor 650 blocks a control signal (not shown) received by the drive driver 620. This is to prevent the display device 600 from performing any operation other than the operation of removing the image of the panel 610 since the battery has been removed.

  In response to the detection control signal DETCCTRLS, all the charges charged in the capacitor of the panel 610 are discharged at a time (step 840). Step 840 is performed by source driver 660, gate driver 670 and panel 610.

  As shown in FIG. 7, when the gate lines G1 and G2 are activated and the transistors TFT11, TFT12, TFT21, and TFT22 are turned on, hue data (not shown) is transferred to the transistor TFT11 through the source lines SL1 and SL2. Images are displayed on the panel 610 by being stored in the capacitors C11, C12, C21, and C22 connected to the TFT12, TFT21, and TFT22.

  However, if the battery is removed, the hue data stored in the capacitors C11, C12, C21, and C22, that is, the charge, must be discharged quickly in order to quickly remove the image on the panel 610.

To further explain step 840, all gate lines of panel 610 are activated in response to detection control signal DETCTRLS (step 910). Step 910 is performed by the gate driver 670.
That is, the gate driver 670 activates all the gate lines G1 and G2 of the panel 610 in response to the second level detection control signal DETCCTRLS. Thereby, all the transistors TFT11, TFT12, TFT21, and TFT22 are turned on.

In response to the detection control signal DETCCTRLS, the voltage levels of the output terminals of all the source lines SL1 and SL2 of the panel 610 are set to the ground voltage VSS level (step 920). Step 920 is performed by the source driver 660.
That is, the source driver 660 sets the voltage level of the output terminals of all the source lines SL1 and SL2 of the panel 610 to the ground voltage VSS level in response to the second level detection control signal DETCCTRLS.

In response to the detection control signal DETCCTRLS, the voltage level of the reference voltage VCOM connected to the capacitors C11, C12, C21, and C22 in the panel 610 is set to the ground voltage VSS level (step 930).
That is, in response to the second level detection control signal DETCCTRLS, the panel 610 sets the voltage level of the reference voltage VCOM connected to the capacitors C11, C12, C21, and C22 in the panel 610 to the ground voltage VSS level.

Through this process, all the transistors TFT11, TFT12, TFT21 and TFT22 inside the panel 610 are turned on, and the voltage levels of the source lines SL1 and SL2 connected to the transistors TFT11, TFT12, TFT21 and TFT22 are This is the ground voltage level, and the voltage level of the reference voltage VCOM is also the ground voltage level.
In such a state, the charges stored in the capacitors C11, C12, C21, and C22 of the panel 610 are instantaneously discharged through the source lines SL1 and SL2. Therefore, after the battery is removed, the image remaining on the panel 610 can be removed at once.

As described above, the optimal embodiment has been disclosed in the drawings and specification. Although specific terms are used herein, they are merely used to describe the present invention and limit the scope of the invention as defined in the meaning and claims. It was not used for that purpose.
Accordingly, those skilled in the art will appreciate that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention must be determined by the technical idea of the claims.

  The present invention can be used for a display device, and in particular, can be used in the field of controlling a panel of a display device.

FIG. 3 is a circuit diagram illustrating a power supply voltage removal sensing circuit according to an embodiment of the present invention. 3 is a flowchart for explaining the operation of the power supply voltage removal sensing circuit of FIG. 1. It is a flowchart explaining step 210 of FIG. It is a flowchart explaining step 230 of FIG. FIG. 6 is a circuit diagram of a power supply voltage removal sensing circuit according to another embodiment of the present invention. FIG. 6 is a circuit diagram of a power supply voltage removal sensing circuit according to still another embodiment of the present invention. 1 is a block diagram illustrating a display device according to an embodiment of the present invention. It is drawing explaining the internal structure of the panel of FIG. 6 is a flowchart illustrating a method for removing an afterimage of a panel when removing a battery from a display device according to another exemplary embodiment of the present invention. It is a flowchart explaining step 840 of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Power supply voltage removal detection circuit 110 Detection part 120 Voltage level control part 130 Comparison part 140 Output part 150 Downshifting part 160 Delay part 170 AND means

Claims (44)

A detection unit that detects that one of the first power supply voltage and the second power supply voltage becomes the second level and outputs a detection signal at the first level;
A power supply voltage removal sensing circuit, comprising: an output unit that prevents malfunction of the detection unit and inverts the detection signal and outputs the detection control signal in response to an operation activation signal. The detector is
Outputting the detection signal at a second level while the voltage levels of the first power supply voltage and the second power supply voltage are maintained at the first level;
The first power supply voltage and the second power supply voltage are voltages generated from a battery,
The power supply voltage removal according to claim 1, wherein if the battery is removed, the voltage levels of the first power supply voltage and the second power supply voltage become the second level with different time differences. Sensing circuit. The detector is
While the first power supply voltage and the second power supply voltage are maintained at the first level, the voltage level of the first node is controlled to be higher than the voltage level of the second node. A voltage level controller that controls the voltage level of the first node to be lower than the voltage level of the second node when one voltage level of the second power supply voltage is the second level;
The power supply according to claim 2, further comprising: a comparator that operates in response to a boosted voltage and compares the voltage levels of the first node and the second node to generate the detection signal. Voltage rejection sensing circuit. The voltage level control unit
A first transistor having a gate receiving the second power supply voltage and having a first end coupled to the first node;
A first resistor having one end connected to the second end of the first transistor and the first voltage connected to the other end;
A second resistor coupled between the first node and the second node;
A second transistor having a gate receiving the second power voltage, a first terminal connected to the second node, and a second terminal connected to the comparator;
A third resistor having one end connected to the second node;
A third transistor having a first terminal connected to the other end of the third resistor, a first control signal applied to the gate, and a second transistor connected to a ground voltage;
The first control signal is:
4. The power supply voltage removal sensing circuit according to claim 3, wherein when the generation of the boosted voltage is completed, the boosted voltage is generated at a first level. The comparison unit includes:
A comparator operating in response to the boosted voltage, having a negative terminal connected to the first node, a positive terminal connected to a second terminal of the second transistor, and outputting the detection signal;
A capacitor connected between a positive terminal of the comparator and a ground voltage;
A fourth transistor connected in parallel with the capacitor between the positive terminal of the comparator and the ground voltage and receiving a reset pulse at the gate;
The reset pulse is
5. The power supply voltage removal sensing circuit according to claim 4, wherein the charge charged in the capacitor is discharged at an initial stage of operation of the power supply voltage removal sensing circuit. The voltage level control unit
A first resistor having one end connected to the first power supply voltage;
A plurality of first transistors connected in series between the other end of the first resistor and the first node, and receiving a plurality of corresponding second power supply voltages at their gates;
A second resistor coupled between the first node and the second node;
A plurality of second transistors connected in series between the second node and the comparator and receiving the corresponding second power supply voltages at the gate;
A third resistor having one end connected to the second node;
A third transistor having a first terminal connected to the other end of the third resistor, a first control signal applied to the gate, and a second transistor connected to a ground voltage;
The first control signal is:
4. The power supply voltage removal sensing circuit according to claim 3, wherein when the generation of the boosted voltage is completed, the boosted voltage is generated at a first level. The output unit is
A downshifting unit for lowering the voltage level of the detection signal;
A delay unit for delaying the output of the downshifting unit;
AND means for ANDing the output of the delay unit and the output of the downshifting unit;
A latch unit that inverts the output of the AND means and outputs the detection control signal when the operation activation signal is activated;
The downshifting unit is
The power supply voltage removal sensing circuit according to claim 1, further comprising n inverters connected in series, wherein the inverter operates in response to the first power supply voltage, and the n is an even number. . The output unit is
A downshifting unit for lowering the voltage level of the detection signal;
A delay unit for delaying the output of the downshifting unit;
An inverting OR means for inverting OR the output of the delay unit and the output of the downshifting unit;
AND means for ANDing the operation activation signal and the output of the inverted OR means;
An inverter that inverts the output of the logical product means and outputs it as the detection control signal,
The downshifting unit is
The power supply voltage removal sensing circuit according to claim 1, further comprising an inverter that inverts the detection signal, wherein the inverter operates in response to the first power supply voltage. A panel,
A drive driver for controlling the panel and displaying an image on the panel,
The drive driver is
A power supply voltage removal sensing unit for generating a detection control signal at a second level if a battery for supplying a power supply voltage to the driver and the panel is removed;
In response to the detection control signal, a voltage boosting unit that cuts off the boosted voltage applied to the panel;
A microprocessor that shuts off a control signal received by the drive driver in response to the detection control signal;
A display device for removing a panel afterimage at the time of battery removal, comprising: a source driver and a gate driver for controlling a source line and a gate line of the panel in response to the detection control signal. The gate driver is
In response to the second level detection control signal, activates every gate line of the panel;
The source driver is
In response to the detection control signal of the second level, the voltage level of the output terminal of every source line of the panel is set to the ground voltage level,
The panel is
The afterimage of the panel at the time of battery removal according to claim 9, wherein a voltage level of a reference voltage connected to a capacitor in the panel is set to a ground voltage level in response to the second level detection control signal. A display device that removes all at once. The power supply voltage removal sensing unit is
A detection unit for detecting that one of the first power supply voltage and the second power supply voltage generated from the battery is a second level and outputting a detection signal at the first level;
The battery removal according to claim 9, further comprising: an output unit that prevents a malfunction of the detection unit and inverts the detection signal and outputs the detection control signal in response to an operation activation signal. A display device that removes the afterimage of the panel at once. The detector is
Outputting the detection signal at a second level while the voltage levels of the first power supply voltage and the second power supply voltage are maintained at the first level;
The battery removal according to claim 11, wherein if the battery is removed, the voltage levels of the first power supply voltage and the second power supply voltage become the second level with different time differences. A display device that removes all panel afterimages at once. The output unit is
It operates when the operation activation signal is activated to the first level, and does not operate when the operation activation signal is deactivated to the second level.
The operation activation signal is:
12. The display device according to claim 11, wherein when the image is displayed on the panel, the display is activated to a first level, and the afterimage of the panel at the time of removing the battery is removed at once. The panel is
The display device according to claim 9, wherein the display device is an active matrix panel, and removes the afterimage of the panel at the time of battery removal. In the afterimage removal method that appears on the panel at the time of battery removal of the display device comprising a panel and a drive driver that controls the panel and displays an image on the panel,
Recognizing removal of the battery and generating a detection control signal at a second level;
Cutting off the boosted voltage applied to the panel in response to the detection control signal;
Blocking the control signal received by the drive driver in response to the detection control signal;
A method of removing afterimages appearing on the panel when the battery of the display device is removed, comprising: discharging all charges charged in the capacitor of the panel at a time in response to the detection control signal. Discharging all of the charges at once comprises
Activating all gate lines of the panel in response to the detection control signal;
In response to the detection control signal, setting a voltage level of an output terminal of every source line of the panel to a ground voltage level;
The battery of the display apparatus according to claim 15, further comprising: setting a voltage level of a reference voltage connected to the capacitor in the panel to a ground voltage level in response to the detection control signal. An afterimage removal method that appears on the panel during removal. Generating the detection control signal comprises:
Detecting that one of the first power supply voltage and the second power supply voltage generated from the battery is at the second level, and outputting a detection signal at the first level;
Inverting the detection signal in response to an operation activation signal and outputting as the detection control signal,
Outputting the detection signal comprises:
While the voltage levels of the first power supply voltage and the second power supply voltage are maintained at the first level, the detection signal is output at the second level, and the battery is removed, the first power supply voltage is output. The method of claim 15, wherein the voltage level of the second power supply voltage is the second level with a different time difference. The detection control signal is
Occurs when the operation activation signal is activated to the first level, and does not occur when the operation activation signal is deactivated to the second level,
The operation activation signal is:
The method of claim 17, wherein when the image is displayed on the panel, the display is activated to a first level. Detecting that one of the first power supply voltage and the second power supply voltage generated from the battery is at the second level, and outputting a detection signal at the first level;
And inverting the detection signal in response to an operation activation signal and outputting the inverted detection signal as a detection control signal. Outputting the detection signal comprises:
Outputting the detection signal at a second level while the voltage levels of the first power supply voltage and the second power supply voltage are maintained at the first level;
The power supply voltage removal according to claim 19, wherein if the battery is removed, the voltage levels of the first power supply voltage and the second power supply voltage become the second level with different time differences. Sensing method. In the power supply voltage removal sensing circuit for the afterimage removal of the display device,
A first power supply voltage generated from the first voltage source and a second power supply voltage generated from the second voltage source are received, and one voltage level of the first power supply voltage and the second power supply voltage is a predetermined voltage. Detecting that the level is reached and outputting a detection signal;
An output unit that receives the detection signal and outputs the detection control signal. The detector is
If the first power supply voltage and the second power supply voltage are higher than the predetermined voltage level, the voltage level of the first node is controlled to be higher than the voltage level of the second node, and the first power supply voltage and the second power supply voltage A voltage level controller for controlling the voltage level of the first node to be lower than the voltage level of the second node if one voltage level of the second power supply voltage is lower than the predetermined voltage level;
The power supply voltage removal sensing circuit according to claim 21, further comprising: a comparison unit that compares the voltage levels of the first node and the second node to generate the detection signal.   The comparison unit is driven by a third voltage source that generates a third power supply voltage having a voltage level higher than or equal to a higher one of the first and second power supply voltage levels. The power supply voltage removal sensing circuit according to claim 22.   The power supply voltage removal sensing circuit according to claim 22, wherein the comparison unit is driven by a voltage having a level different from the levels of the first and second power supply voltages.   The power supply voltage removal sensing circuit according to claim 22, wherein the comparison unit is driven by a voltage having the same level as one of the first and second power supply voltages. The output unit is
A downshifting unit for lowering the voltage level of the detection signal;
A delay unit for delaying the output of the downshifting unit;
The power supply voltage removal sensing circuit according to claim 22, further comprising: a logic circuit that performs a logical operation on the output of the delay unit and the output of the downshifting unit. The comparison unit includes:
A first input is electrically connected to the first node, and a second input is electrically connected to the second node through a first transistor;
A capacitor connected between the second input and a reference voltage;
23. The power supply voltage removal sensing circuit according to claim 22, wherein the reference voltage is a ground voltage. The detection unit includes a voltage level control unit and a comparison unit,
The voltage level control unit
A first resistor and a first transistor connected in series between a first voltage source and a first node, a second transistor connected between a second node and a third node, and the first node and the first node A second resistor connected between the two nodes;
The comparison unit includes a comparator that outputs the detection signal and includes a first input connected to the first node and a second input connected to the third node, and the comparator includes: The power supply voltage removal sensing circuit of claim 21, wherein the gate is connected to the second power supply voltage. The voltage level control unit
The third resistor and the third transistor are connected in series between the second node and a reference voltage, and the gate of the third transistor is connected to the first control signal. 28. A power supply voltage removal sensing circuit according to 28. The comparison unit includes:
A capacitor and a fourth transistor are connected in parallel between the second input of the comparator and the reference voltage. A gate of the fourth transistor is connected to a reset pulse, and the reference voltage is a ground voltage. 30. The power supply voltage removal sensing circuit according to claim 29, wherein: The second voltage source generates a plurality of different second power supply voltages, and the detection unit includes a voltage level control unit and a comparison unit,
The voltage level control unit
A first resistor and a plurality of first transistors connected in series between a first voltage source and a first node; a plurality of second transistors connected between a second node and a third node; A second resistor connected between the first node and the second node;
The comparator includes a comparator that outputs the detection signal and includes a first input coupled to the first node and a second input coupled to the third node;
The gates of the plurality of first transistors are respectively connected to the plurality of second power supply voltages, and the gates of the plurality of second transistors are respectively connected to the plurality of second power supply voltages. The power supply voltage removal sensing circuit according to claim 21, wherein: The voltage level control unit
The third resistor and the third transistor are connected in series between the second node and a reference voltage, and the gate of the third transistor is connected to the first control signal. 32. A power supply voltage removal sensing circuit according to 31. The comparison unit includes:
A capacitor and a fourth transistor are connected in parallel between the second input of the comparator and the reference voltage. A gate of the fourth transistor is connected to a reset pulse, and the reference voltage is a ground voltage. The power supply voltage removal sensing circuit according to claim 32, wherein: A panel having a display element connected to the source line and the gate line in a matrix structure;
A drive driver for controlling the panel and displaying an image on the panel,
The drive driver includes a power supply voltage removal sensing unit that generates a detection control signal for removing an afterimage of the panel, and the power supply voltage removal sensing unit includes:
A first power supply voltage generated from the first voltage source and a second power supply voltage generated from the second voltage source are received, and one voltage level of the first power supply voltage and the second power supply voltage is a predetermined voltage. Detecting that the level is reached and outputting a detection signal;
An output unit that receives the detection signal and outputs the detection control signal. Each of the display elements is
A transistor having a source electrode electrically connected to the source line and a gate electrode electrically connected to the gate line;
A capacitor electrically connected between a drain electrode of the transistor and a common voltage terminal,
The display device of claim 34, wherein the detection control signal accelerates discharge of the capacitive element. The drive driver is
A source driver for controlling the source line of the panel;
A gate driver for controlling the gate line of the panel;
A common voltage driver for controlling the common voltage terminal of the panel;
36. The display device of claim 35, wherein the source driver, the gate driver, and the common voltage driver discharge the capacitor in response to the detection control signal.   The source driver and the common voltage driver are responsive to the detection control signal to ground the source line and the common voltage terminal, and the gate driver is responsive to the detection control signal to display the respective displays. 37. The display device according to claim 36, wherein the transistor of the element is activated. The detector is
If the first power supply voltage and the second power supply voltage are higher than the predetermined voltage level, the voltage level of the first node is controlled to be higher than the voltage level of the second node, and the first power supply voltage and the second power supply voltage A voltage level controller for controlling the voltage level of the first node to be lower than the voltage level of the second node if one voltage level of the second power supply voltage is lower than the predetermined voltage level;
A comparator for comparing the voltage levels of the first node and the second node to generate the detection signal;
36. The display device of claim 35, wherein the comparison unit is driven by a boosted voltage used to drive the display panel. The output unit is
A downshifting unit for lowering the voltage level of the detection signal;
A delay unit for delaying the output of the downshifting unit;
36. The display device according to claim 35, further comprising: a logic circuit that performs a logical operation on the output of the delay unit and the output of the downshifting unit. The comparison unit includes:
A first input is electrically connected to the first node, and a second input is electrically connected to the second node through a first transistor;
The display apparatus of claim 38, further comprising a capacitor connected between the second input and a reference voltage. In the afterimage removal method of the panel display device,
An afterimage removal method comprising: detecting that a voltage level of at least one voltage source falls to a predetermined voltage level, and controlling to accelerate afterimage removal of the display device. In a method for removing an afterimage of a panel display device including a matrix structure display element connected to a source line, a gate line, and a common voltage terminal, each of the display elements includes a transistor and a capacitor.
Generating a detection control signal if the voltage level of at least one of the plurality of voltage sources falls to a predetermined voltage level; and
Controlling the source line, the gate line, and the common voltage terminal so that the capacitive elements of the respective display elements are discharged in response to the control signal. Afterimage removal method. The plurality of voltage sources include first and second voltage sources for generating first and second power supply voltages, and the step of generating the detection control signal includes:
If the first power supply voltage and the second power supply voltage are higher than the predetermined voltage level, the voltage level of the first node is controlled to be higher than the voltage level of the second node, and the first power supply voltage and the second power supply voltage Controlling the voltage level of the first node to be lower than the voltage level of the second node if one voltage level of the second power supply voltage is lower than the predetermined voltage level;
And comparing the voltage levels of the first node and the second node and generating the detection signal in response to the comparison result. The source line and the common voltage terminal are grounded in response to the detection control signal, and the transistors of the display elements are activated in response to the detection control signal. The afterimage removal method according to claim 43.

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