JP2005322274A - Microcomputer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To speed up digital signal processing in a microcomputer in which a DSP engine is mounted on a single LSI chip together with a CPU core. <P>SOLUTION: A built-in memory is divided into two types, that is, first memories 5 and 7, and second memories 4 and 6, and is made accessible in parallel by third buses XAB and XDB, and second buses YAB and YDB respectively. Operand access and address calculation processing necessary for data processing by the DSP engine is carried out by a CPU. The CPU core 2 can simultaneously transfer two data values from the built-in memory to the DSP engine 3. The third buses XAB and XDB, and the second buses YAB and YDB are separate from first buses IAB and IDB, and the CPU core 2 can execute instruction fetching, etc. through the first buses IAB and IDB in parallel with the access of the second memories 4 and 6, and the first memories 5 and 7. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a logic LSI formed as a semiconductor integrated circuit having a central processing unit and a digital signal processing unit, and relates to a technique effective when applied to a microcomputer requiring high-speed arithmetic processing.

  Japanese Patent Application No. 4-296778 or US Patent Application No. 145157 is an example of a microcomputer in which a multiplier and an arithmetic logic unit are mounted on the same chip. According to this, a logic LSI chip such as a microcomputer is provided with a central processing unit, a bus, a memory, and a multiplier. In particular, while reading data from the memory, a command of a multiplication instruction relating to the read data is multiplied from the central processing unit. A command signal line to be transferred to the device. As a result, while the central processing unit reads data from the memory, the command of the multiplication instruction relating to the read data is transferred from the central processing unit to the multiplier, so that the data can be directly transferred between the memory and the multiplier. become.

Japanese Patent Application No. 4-296778 US Patent Application No. 145157

  The inventors of the present invention studied to increase the speed of digital signal processing by mounting a digital signal processing unit together with a central processing unit on one LSI. At this time, the prior art realizes speeding up of multiplication processing in that data can be directly transferred from the memory to the multiplier. However, when pipeline processing of instruction execution by the central processing unit is assumed, The situation where the fetch cycle of the instruction to be executed by the processing unit and the memory access cycle for the multiplication process conflict is not considered. In addition, it is not considered that a plurality of operands for addition and multiplication are read from the memory in parallel to speed up the arithmetic processing. Furthermore, in that case, it was found that the usability of the microcomputer deteriorates if the relationship with the external access by the central processing unit is not taken into consideration. In addition, when a digital signal processing unit is mounted on a single LSI together with a central processing unit, devising the code assignment of CPU instructions and DSP instructions and the format of DSP instructions can increase the logic scale of instruction decode circuits as much as possible. It has been found necessary to suppress.

  An object of the present invention is to mount a digital signal processing unit together with a central processing unit in one LSI to speed up digital signal processing. Another object of the present invention is to suppress an increase in the physical scale as much as possible when a digital signal processing unit is mounted on a single LSI together with a central processing unit.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  That is, the microcomputer includes a central processing unit (2), first to third address buses (IAB, YAB, XAB) to which addresses are selectively transmitted from the central processing unit, and the first address bus. (IAB) and a second address bus (YAB) connected to the first memory (5, 7) by an address from the central processing unit, and the first address bus (IAB) and the third address bus Data is connected to the second memory (4, 6) connected to the address bus (XAB) and accessed by the address from the central processing unit, and to the first and second memories and the central processing unit. A first data bus (IDB) to be transmitted; A second data bus (YDB) connected to the first memory and transmitting data; a third data bus (XDB) connected to the second memory and transmitting data; and the first data bus An external interface circuit (12) connected to the address bus and the first data bus; a digital signal processing unit (3) connected to the first to third data buses and operated in synchronization with the central processing unit; A single chip includes a control signal line for transmitting a DSP control signal (20) for controlling the operation of the signal processing unit from the central processing unit to the digital signal processing unit.

  According to the above-described means, the built-in memory is divided into two planes, the first memory (5, 7) and the second memory (4, 6) in consideration of the product-sum operation by the digital signal processor (3). The central processing unit (2) allows the first memory and the second memory to be accessed in parallel by the third bus (XAB, XDB) and the second bus (YAB, YDB), respectively. As a result, two pieces of data from the built-in memory can be simultaneously transferred to the digital signal processing unit. Furthermore, since the third bus (XAB, XDB) and the second bus (YAB, YDB) are also individualized with the first bus (IAB, IDB) interfaced to the outside, the central processing unit is the first bus. External memory access is also enabled in parallel with the access to the second memory (4, 6) and the first memory (5, 7). In this way, since there are first to third three types of address buses (IAB, XAB, YAB) and data buses (IDB, XDB, YDB) respectively connected to the central processing unit (2), the 3 Different types of internal buses can be used to perform different memory access operations in the same clock cycle. Therefore, it is possible to easily cope with the case where the program and data exist in the external memory and to speed up the arithmetic processing.

  In order to improve the usability of the microcomputer, each of the first memory and the second memory may be composed of a RAM and a ROM.

  In order to increase the speed of address generation for repetitive operations such as product-sum operations in the central processing unit, the central processing unit may include a modulo address output unit (200). At this time, it is preferable that the address generated by the modulo address output unit can be selectively output to the second or third address bus.

  The digital signal processor includes first to third data buffer means (MDBI, MDBY, MDBX) individually interfaced with first to third data buses (IDB, YDB, XDB) and respective data. A plurality of register means (305 to 308) connectable to the buffer means via an internal bus, a multiplier (304) and an arithmetic logic unit (302) connected to the internal bus, and the DSP control signal And a decoder (34) for controlling the operation of the data buffer means, multiplier, arithmetic logic unit, and register means.

  When attention is focused on instruction decoding, the microcomputer transmits data between the central processing unit (2), the memory (4-7) controlled to be accessed by the central processing unit, and the memory and the central processing unit. And a digital signal processing unit (3) operated in synchronization with the central processing unit on a single chip to be a semiconductor integrated circuit. The instruction set that can be executed by the microcomputer is a digital signal processing unit that causes the central processing unit to bear a part of processing such as CPU instruction to be executed by the central processing unit (2) and address calculation for data fetching. (3) includes a DSP instruction to be executed. The central processing unit includes an instruction register (25) for fetching a 16-bit fixed length CPU instruction and a 16-bit or 32-bit length DSP instruction via the data bus, and an instruction fetched to the instruction register. The CPU instruction and the DSP instruction are identified based on some of the plurality of bits, and the DSP control signal (20) for controlling the operation of the digital signal processing unit and the operation control of the central processing unit are determined according to the identification result. And a decoder (24) for generating a CPU control signal.

  For example, the CPU instruction is assigned to a range in which the most significant 4 bits of the instruction code are “0000” to “1110”. The DSP instruction is assigned to a range in which the most significant 4 bits of the instruction code are “1111”. Further, an instruction in which the most significant 6 bits of the instruction code are assigned to a range of “111100” and “111101” is a 16-bit instruction code even in a DSP instruction. An instruction in which the most significant 6 bits of the instruction code are “111110” is a 32-bit instruction code. No instruction is assigned to the range in which the most significant 6 bits of the instruction code are “111111”, and the range is set as an unused area. In this way, by providing the above-described rules for code allocation for instructions of a maximum of 32 bits, if a part of each instruction code, for example, the most significant 6 bits is decoded, whether the instruction is a CPU instruction or 16 Whether the DSP instruction is a bit length DSP instruction or a 32-bit length DSP instruction can be determined by a small logic scale decoder, and it is not always necessary to decode all 32 bits at once.

  The decoder decodes the upper 16 bits of the instruction register to generate the CPU decode signal (243) and the DSP decode signal (244), and the first decode circuit has 32 bits. A code conversion circuit (242) for outputting a signal in which the lower 16 bits of the instruction register are encoded when a long DSP instruction is identified, and a code indicating that the output is invalid when identifying other instructions; In addition, the DSP decode signal and the output of the code conversion circuit are set as a DSP control signal (20).

  When focusing on the instruction format of the DSP instruction, the microcomputer includes a central processing unit (2), a digital signal processing unit (3) operated in synchronization with the central processing unit, the central processing unit and the digital signal. A processing unit is integrated into a semiconductor integrated circuit including an internally connected internal bus (IDB), and the central processing unit defines data transfer with the digital processing unit with respect to the central processing unit. An instruction of the first format having one code area (bit 9 to bit 0 of the 16-bit DSP instruction illustrated in FIG. 18), and a second code area having the same format as the first code area (FIG. 20, Example in Figure 21 And a third code area (FIG. 20) that defines arithmetic processing using the transfer data defined in the second code area for the digital signal processing unit. , And a second format instruction having a B field of the 32-bit DSP instruction illustrated in FIG. 21.

  Thereby, the execution control means can employ a decoding means having a common decoding logic for the first code area and the second code area when executing the instructions in the first and second formats. Contributes to reducing the logical scale of computers.

  The first format instruction and the second format instruction include a fourth code area (for example, bit 15 to bit 10 in a 16-bit DSP instruction, or a 32-bit DSP instruction to indicate whether the instruction is in the first format or the second format. Bits 32 to 26).

  The execution control means includes an instruction register (25) used in common for the first format instruction and the second format instruction, the first code area included in the instruction fetched in the instruction register, and a fourth Or a decoding means (240) for decoding the second code area and the fourth code area, and an execution means for performing address calculation according to the decoding result and performing the data transfer control. it can.

  The instruction register includes an upper area (UIR) shared for holding the first code area and the fourth code area or the second code area and the fourth code area, and holding the third code area. The decoding means uses a control signal (indicating that the instruction register holds an instruction of the second format based on the decoding result of the fourth code area). 248) and a means (242, 242A, 242B) for supplying code data of the third code area from the lower area to the digital signal processing unit based on the control signal.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, the built-in memory is divided into a first memory and a second memory in consideration of a product-sum operation by the digital signal processor, and can be accessed in parallel by the third bus and the second bus, respectively. Therefore, the central processing unit can simultaneously transfer two pieces of data from the built-in memory to the digital signal processing unit.

  In addition, since the third bus and the second bus are also individualized with the first bus interfaced to the outside, the central processing unit is externally connected in parallel with the access to the second memory and the first memory. Memory access is possible.

  As described above, since there are the first to third types of address bus and data bus respectively connected to the central processing unit, different memory access operations can be performed in the same clock cycle using the three types of internal buses. Since it can be executed, it is possible to easily cope with a case where a program or data exists in an external memory and to speed up the arithmetic processing.

  Further, the built-in memory is divided into a first memory and a second memory. Each of the two memories is provided with a ROM and a RAM. The RAM is a data memory, and the ROM is a program memory. And program memory can be separated, two data can be transferred in parallel to the digital signal processing unit, and instruction fetch, data transfer, and operation can be efficiently performed by parallel pipeline processing. .

  Therefore, when the digital signal processing unit is mounted on one LSI together with the central processing unit, the digital signal processing can be speeded up.

  By decoding a part of the instruction code for an instruction in which a CPU instruction and a DSP instruction are mixed, the instruction is a CPU instruction, a 16-bit DSP instruction, or a 32-bit DSP instruction. By assigning an instruction code so as to be identifiable, it is possible to determine the type of instruction with a small logic scale decoder, and it is not always necessary to decode all 32 bits at once. Therefore, when the digital signal processing unit is mounted together with the central processing unit in one LSI, the increase in the physical scale can be suppressed as much as possible.

  As the instruction format of the DSP instruction, a first code area (bit 9 to bit 0 of the 16-bit DSP instruction illustrated in FIG. 18) that defines data transfer with the digital signal processing unit to the central processing unit. ) And a second code area (A field of the 32-bit DSP instruction illustrated in FIGS. 20 and 21) having the same format as the first code area. A third code area (B field of the 32-bit DSP instruction illustrated in FIGS. 20 and 21) that defines the arithmetic processing using the transfer data defined in the code area 2 for the digital signal processing unit. The second format instructions are used to execute the first and second format instructions. That means may employ a decoding means having a common decode logic for the first coding region and the second coding region, also in this respect, it is possible to reduce the logical scale of the microcomputer.

  FIG. 1 shows an overall block diagram of a microcomputer 1 according to an embodiment of the present invention. The microcomputer shown in the figure is formed on a single semiconductor substrate such as single crystal silicon by a semiconductor integrated circuit manufacturing technique. The microcomputer 1 includes a CPU core 2 as a central processing unit, a DSP engine 3 as a digital signal processing unit, an X-ROM 4, a Y-ROM 5, an X-RAM 6, a Y-RAM 7, and an interrupt controller. (Interrupt Controller) 8, Bus State Controller 9, Built-in Peripheral Circuits 10 and 11, External Memory Interface 12, and Clock Pulse Generator (CPG) 13. The X-ROM 4 and Y-ROM 5 are read-only or electrically rewritable read-only memories for storing instructions or constant data, and the X-RAM 6 and Y-RAM 7 are temporary data storage or CPU This is a random access memory used as a work area for the core 2 and the DSP engine 3. The X-ROM 4 and the X-RAM 6 are collectively referred to as an internal instruction / data X memory (Internal Instruction / Data X Mem.), And the Y-ROM 5 and the Y-RAM 7 are referred to as an internal instruction / data Y memory (Internal Instruction / Data). Data Y Mem.)

  The microcomputer 1 of this embodiment has, as its bus configuration, an internal address bus IAB and an internal data bus IDB coupled to the external memory interface 12, an internal address bus XAB and an internal data bus XDB not coupled to the external memory interface 12, an external memory An internal address bus YAB and an internal data bus YDB which are not coupled to the interface 12 and a peripheral address bus PAB and a peripheral data bus PDB for the built-in peripheral circuits 10 and 11 are provided. Although the control bus is not shown, it is provided corresponding to a pair of address bus and data bus.

  A data bus IDB that can be connected to the outside of the chip through the external memory interface 12 is connected to the CPU core 2, and an interrupt signal 80 from the interrupt controller 8 is given. The CPU core 2 supplies a control signal 20 for controlling the DSP engine 3 to the DSP engine 3. Further, the CPU core 2 outputs address signals to an address bus IAB that can be connected to the outside of the chip through the external memory interface 12 and address buses XAB and YAB that are not connected to the external memory interface 12. The CPU core 2 is operated using the non-overlapping two-phase clock signals Clock 1 and Clock 2 output from the clock pulse generator (CPG) 13 as operation reference clock signals. Details of the CPU core 2 will be described later. The CPU core 2 in FIG. 1 includes a register file 21, an arithmetic logic unit (ALU) 22, an address adder (Add-ALU) 23, a decoder 24, an instruction register ( IR) 25 is representatively shown. The register file 21 is arbitrarily used as an address register or a data register, and includes a program counter and a control register. The decoder 24 decodes the instruction fetched into the instruction register 25 and generates an internal control signal (not shown in FIG. 1) and a control signal 20. The instruction register (IR) 25 includes a 16-bit upper area (UIR) and a lower area (LIR). Although details will be described later, the value of the lower region (LIR) can be selectively shifted to the upper region (UIR). Note that a sequence control circuit for controlling the instruction execution procedure when an exception such as an interrupt occurs or for controlling the saving and restoring of the internal state in response to the occurrence of an exception is not shown.

  The DSP engine 3 is connected to the data buses IDB, XDB, and YDB, and is operated using the clock signals Clock1 and Clock2 as operation reference clock signals. Details of the DSP engine 3 will be described later, but the DSP engine 3 of FIG. It is representatively shown. The data register file 31 is used for multiply-add operations and the like. The decoder 34 decodes the control signal 20 supplied from the CPU core 2 and generates an internal control signal (not shown in FIG. 1) of the DSP engine 3.

  X-ROM 4 and X-RAM 6 are connected to address buses IAB and XAB and data buses IDB and XDB. Y-ROM 5 and Y-RAM 7 are connected to address buses IAB, YAB and data buses IDB, YDB. The built-in memory is divided into X memory 4 and 6 and Y memory 5 and 7 in consideration of the product-sum operation by the DSP engine 3, and can be accessed in parallel by the internal buses XAB and XDB and YAB and YDB, respectively. ing. Furthermore, since the internal buses XAB, XDB and YAB, YDB are also individually separated from the externally interfaced buses IAB, IDB, external memory access is also performed in parallel with the access to the X memories 4, 6 and the Y memories 5, 7. Made possible. The X memories 4 and 6 and the Y memories 5 and 7 are used as a data temporary storage area, a constant data storage area, etc. for the product-sum operation by the DSP engine 3. Needless to say, the X-RAM and Y-RAM can also be used as a temporary data storage area or work area of the CPU core 2.

  The interrupt controller 8 receives an interrupt request signal (Interrupts) 81 from the built-in peripheral circuits 10, 11, etc., and arbitrates and accepts interrupt requests according to information for prioritizing various interrupt requests and masking interrupt requests. Then, an interrupt vector 82 corresponding to the accepted interrupt request is output to the address bus IAB, and an interrupt signal 80 is output to the CPU core 2.

  The bus state controller 9 is connected to the address buses IAB and PAB and the data buses IDB and PDB, and performs interface control between the built-in peripheral circuits 10 and 11 connected to the address bus PAB and the data bus PDB and the CPU core 2.

  The external memory interface 12 is connected to the address bus IAB and the data bus IDB, is connected to an address bus and a data bus (not shown) outside the chip of the microcomputer 1, and performs interface control with the outside.

FIG. 2 shows an example of the address map of the microcomputer 1. The microcomputer 1 of this embodiment manages an address space defined by 32 bits. The address bus IAB has a bit width of 32 bits. The address space includes an exception vector area, an X-ROM space (address space assigned to the X-ROM 4), an X-RAM space (address space assigned to the X-RAM 7), and a Y-ROM space ( Address space allocated to the Y-ROM 5), Y-RAM space (address space allocated to the Y-RAM 7), built-in peripheral circuit allocation space (address space to which the built-in peripheral circuits 10 and 11 are allocated), and the like. . In the example of FIG. 2, X-ROM 4 is assigned 24 KB, X-RAM 6 is assigned 4 KB, Y-ROM 5 is assigned 24 KB, and Y-RAM 7 is assigned 4 KB.
According to FIG. 2, an exception processing vector area is allocated to the 256B area in the space of H'00000000 to H'000003FF in hexadecimal notation. A normal space that can be used by the user is allocated to H'00000040 to H'01FFFFFF. The normal space is a memory area that can be connected to the outside of the microcomputer 1. An X-ROM space is allocated to H'0200000 to H'02005FFF. An X-RAM space is allocated to H'02006600 to H'02006FFF. H'0200700 to H'02007FFF is an X-RAM_Mirror space, and accessing this actually accesses the X-RAM space of H'0200600 to H'02006FFF. H'0208000 to H'0200FFFF is an X-RAM, RAM_Mirror space, and accessing this actually accesses the X-ROM space and the X-RAM space of H'0200000 to H'02007FFF. . A Y-ROM space is allocated to H'02010000 to H'02015FFF. A Y-RAM space is allocated to H'02016600 to H'02016FFF. H'0201000 to H'02017FFF is a Y-RAM_Mirror space, and when this is accessed, the Y-RAM space of H'020016 to H'02016FFF is actually accessed. H'0201000 to H'0201FFFF is a Y-ROM, RAM_Mirror space, and accessing this actually accesses the Y-ROM space and Y-RAM space of H'02010000 to H'02017FFF. . A normal space is allocated to H'02020000 to H'07FFFFFFF. A reserved area is allocated to H'080000 to H'1FFFFFFFF. This reserved area is inaccessible in the case of a user chip (real chip), and as an ASE space (emulation control space) in the case of an evaluation chip (evaluation chip used for emulation). Assigned. A normal space is allocated to H'20000000 to H'27FFFFFFF. A reserved area is allocated to H'2800000 to H'FFFFFDFF. H'FFFFFE00 to H'FFFFFFFF are assigned with built-in peripheral circuit allocation areas for assigning register address values of the built-in peripheral circuits.

  FIG. 3 is a block diagram of the CPU core 2 showing the modulo address output unit in detail. A portion surrounded by a broken line in FIG. 3 is a modulo address output unit 200. The modulo address output unit 200 outputs the value output from the modulo address register (for example, A0X) to the address bus (for example, XAB) through the buffer (for example, MABX), and simultaneously adds the value output from the modulo address register (A0X) ( This is a circuit block that performs an address update output operation that is added by, for example, ALU) and stored again in the modulo address register (A0X). . A circuit block described as a random logic circuit 201 is a circuit block including the decoder 24 of FIG. 1, the sequence control circuit, a control register, a status register, and the like.

  In FIG. 3, C1, C2, DR, A1, B1, A2, B2, and DW are buses representatively shown in the CPU core 2, respectively. The interface between the CPU core 2 and the data bus IDB is performed by the instruction register (IR) 25 and the data buffer 203. The instruction fetched to the instruction register (IR) 25 is supplied to the decoder 24 included in the random logic circuit 201. The interface between the CPU core 2 and the address bus IAB is performed by a program counter (PC) 204 and an address buffer (Address Buffer) 205. The interface between the CPU core 2 and the address bus XAB is performed by a memory address buffer (MABX) 206, and the interface between the CPU core 2 and the address bus YAB is performed by a memory address buffer (MABY) 207. The address information input path to the address buffer 205 can be selected from the buses C1, A1, and A2. The address information input path to the memory address buffers 206 and 207 can be selected from the buses C1, C2, A1, and A2. It can be selected from the inside. An arithmetic operator (AU) 208 is used to increment the value of the program counter 204. 209 is a general-purpose register (Reg.), 210 is an index register (Ix) used for address index modification, 211 is an index register (Iy) also used for index modification, and 212 is an adder (PAU) dedicated to address calculation. ) 213 is an arithmetic logic unit (ALU).

  The control bit MXY designates which address of the address bus XAB or the address bus YAB is to be subjected to the modulo operation. The address bus XAB is designated by the logical value “1”, and the address bus YAB is designated by the logical value “0”. The control bit DM indicates whether or not to perform a modulo operation, indicates that a modulo operation is performed by a logical value “1”, and indicates that a modulo operation is not performed by a logical value “0”. The modulo start address register (MS) 214 stores a modulo operation start address, and the modulo end address register (ME) 215 stores a modulo operation end address.

  A modulo address register (A0x, A1x) 216 is a current address register that stores the current modulo address, and 217 is a comparator that compares the value of the modulo end address register (ME) 215 with the value of the modulo address register (A0x, A1x) 216 (CMP) 218 is an AND gate that takes the logical product of the output of the comparator 217 and the three inputs of the control bits MXY and DM, and 219 selects the value of the bus C1 and the value of the modulo start address register (MS) 214. Selectors, which are used for modulo operations on the address bus XAB. The selector 219 selects the value of the register (MS) 214 by the logical value “1” output of the AND gate 218, and supplies the selected value to the modulo address register (A0x, A1x) 216. The modulo address register 216 is used by selecting either A0x or A1x.

  A modulo address register (A0y, A1y) 226 is a current address register that stores the current modulo address, and 227 is a comparator that compares the value of the modulo end address register (ME) 215 with the value of the modulo address register (A0y, A1y) 216. (CMP) 228 is an AND gate that takes the logical product of three outputs of the output of the comparator 227, the inverted bit of the control bit MXY, and the control bit DM, and 229 is the value of the bus C2 and the modulo start address register (MS) 214. These selectors are used for modulo operation on the address bus YAB. The selector 229 selects the value of the register (MS) 214 by the logical value “1” output of the AND gate 228 and supplies the selected value to the modulo address register (A0y, A1y) 226. The modulo address register 226 is used by selecting either A0y or A1y.

  Note that OP Code written in the random logic circuit 201 means an instruction code supplied from the instruction register 25, and CONST means a constant value.

  Here, as the modulo arithmetic operation in the CPU core 2, for example, an operation for generating address information to be supplied to the address bus XAB by modulo arithmetic using the modulo address register (A0x) 216 will be described.

  First, the modulo calculation start address is written in the modulo start address register (MS) 214, and the modulo calculation end address is written in the modulo end address register (ME) 215. In the modulo address register (A0x), an address value for starting the modulo operation is written. Next, since the modulo operation is performed on the address of the address bus XAB, the logical value “1” is written to the control bit MXY for determining which address of the XAB or YAB the modulo operation is to be performed (the address bus YAB). When a modulo operation is performed, a logical value “0” is written in the control bit MXY). Finally, a logical value “1” is written in a control bit DM for determining whether or not to perform a modulo operation.

  The modulo operation instruction is, for example, MOVS.W @Ax, Dx. In this instruction description, Ax is a modulo address register (A0x) 216 or a modulo address register (A1x) 216, and Dx corresponds to a register in the DSP engine 3. In FIG. 3, Dx is not shown. When the modulo operation instruction is executed, a value is read from the modulo address register (A0x) 216 and input to the memory address buffer (MABX) 206 and the arithmetic logic unit (ALU) 213. The value input to the memory address buffer (MABX) 206 is output to the address bus XAB as it is to specify the address of the XROM 4 or XRAM 6. On the other hand, the value of the modulo address register (A0x) 216 input to the arithmetic logic unit (ALU) 213 is added with the value of the index register (Ix) 210 or a constant (Const). When adding to the index register (Ix) 210, the instruction MOVS.W @ (Ax, Ix), Dx, etc. is executed. When adding a constant, the instruction MOVS.W @Ax, Dx, etc. When it is executed. The addition result is output from an arithmetic logic unit (ALU) 213. The value output from the arithmetic logic unit (ALU) 213 enters the selector 219. The other input of the selector 219 is a modulo calculation start address stored in the modulo start address register (MS) 214.

  Whether the output of the selector 219 becomes the output of the arithmetic logic unit (ALU) 213 or the value of the modulo start address register (MS) 214 is determined as follows. The value of the modulo address register (A0x) 216 and the value of the modulo end address register (ME) 215 are always compared by the comparator (CMP) 217, and if they match, the logical value “1” is output from the comparator (CMP) 217. If they do not match, a logical value “0” is output. The value output from the comparator (CMP) 217 is ANDed by the AND gate 218 together with the control bits DM and MXY (in this example, both the DM and MXY are logical values “1”, so the value of the comparator 217 remains unchanged. Output from the AND gate 218) and input to the selector 219. The selector 219 selects the value of the modulo start address register (MS) 214 when the value input from the AND gate 218 is a logical value “1”, and selects the arithmetic logic unit (ALU) when the logical value is “0”. ) Select the output value from 213.

  While the value input from the AND gate 218 is the logical value “0”, the output value from the arithmetic logic unit (ALU) 213 is continuously selected, so that the value output to the address bus XAB is sequentially updated. Go. When the value of the modulo end address register (ME) 215 and the value of the modulo address register (A0x) 216 match, the value input from the AND gate 218 to the selector 219 becomes the logical value “1”, and the modulo start address register ( MS) Select a value of 214. Thereby, the modulo address register (A0x) 216 is initialized by the value of the modulo start address register (MS) 214.

  In the above description of the modulo operation, the operation when the modulo address register (A0x) 216 is used has been described. Is also possible. If a logical value “0” is designated for the control bit MXY, a modulo operation can be performed on the address bus YAB. In this case, Ax in the modulo arithmetic instruction MOVS.W @Ax, Dx must be changed to a value Ay for designating the modulo address register (A0y) 226 or (A1y) 226. If 0 is specified for the control bit DM, execution of the modulo operation can be prohibited.

  FIG. 4 shows an example block diagram of the DSP engine 3. A circuit block described as a random logic circuit 301 is a circuit block including the decoder 34, the control circuit, the control register, the status register, and the like in FIG. In addition, the DSP engine 3 includes an arithmetic logic unit (ALU) 302, a shifter (SFT) 303, a multiplier (MAC) 304, a register (Reg.) 305, a register (A0, A1) 306, and a register (Y0, Y1). 307, a register (X0, X1) 308, a memory data buffer (MDBI) 309, a memory data buffer (MDBX) 310, and a memory data buffer (MDBY) 311. A memory data buffer (MDBY) 311 connects the data bus YDB and the bus D2. A memory data buffer (MDBX) 310 connects the data bus XDB and the bus D1. A memory data buffer (MDBI) 309 is connected to the data bus IDB and the buses C1, D1, A1, and B1. A multiplier (MAC) 304 inputs data from the buses A1 and B1, and outputs a multiplication result for the data to the buses C1 and D1. A shifter (SFT) 303 receives data from the bus A2 and outputs a shift operation result to the bus C2. An arithmetic logic unit (ALU) 302 inputs data from the buses A2 and B2, and outputs an operation result to the bus C2.

  FIG. 5 shows an example of an instruction format and an instruction code included in the instruction set of the microcomputer 1. The microcomputer 1 supports two types of instructions, a CPU instruction and a DSP instruction. All of the CPU instructions and a part of the DSP instructions are 16-bit instruction codes, and the remaining DSP instructions are 32-bit instruction codes. The CPU command is a command executed exclusively by the CPU core 2 without operating the DSP engine 3. The DSP instruction is an instruction executed by the DSP engine 3 by causing the CPU core 2 to perform a part of processing such as address calculation or operand access.

  The CPU instruction is assigned to a space in which the most significant 4 bits of the instruction code are “0000” to “1110”. In the DSP instruction, the most significant 4 bits of the instruction code are all assigned to “1111”. Further, an instruction in which 6 bits on the most significant side of the instruction code are assigned to “111100” and “111101” is a 16-bit instruction code even in a DSP instruction. An instruction in which the most significant 6 bits of the instruction code are “111110” is a 32-bit instruction code. No instruction is assigned to the space in which the most significant 6 bits of the instruction code are “111111”, which is an unused area (undefined instruction area). In the future, this area can be used to further extend the instruction code. As is clear from this instruction format, if the most significant 6 bits of each instruction code are decoded, the instruction is a CPU instruction, a 16-bit DSP instruction, or a 32-bit DSP instruction. It is possible to determine whether there is an undefined instruction or not with a small logic scale decoder. In the CPU instruction format of FIG. 5, nnnn is a destination operand designation area, ssss is a source operand designation area, dddd is a displacement designation area, and iiiiii is an immediate value designation area. In the case of an ADD instruction or the like, nnnn is also designated as a source operand designation area, and the operation result is stored in nnnn. The modulo operation instruction explained based on FIG. 3 corresponds to the instruction MOVS.W @ R2, A0 of FIG. 5. The instruction description in FIG. Is different. This is just a difference in form and is essentially the same.

  FIG. 6 shows a connection configuration example between the decoder 24 of the CPU core 2 and the decoder 34 of the DSP engine 3. Instruction fetch by the microcomputer 1 is performed in the instruction register (IR) 25 in units of 32 bits. The decoder 24 includes a first decoding circuit 240, a second decoding circuit 241, and a code conversion circuit 242. The first decoding circuit 240 decodes the value of the upper 16-bit area (UIR) of the instruction register (IR) 25 and determines whether the instruction is a CPU instruction, a 16-bit DSP instruction, or a 32-bit DSP instruction. In response, the CPU decode signal 243, the DSP decode signal 244, the code conversion control signal 245, and the shift control signal 246 are generated. The second decoding circuit 241 decodes the CPU decoding signal 243 and generates various internal control signals (CPU control signals) 247 for selecting an arithmetic unit and a register in the CPU core 2. When activated by the code conversion control signal 245, the code conversion circuit 242 compresses or outputs the number of bits of information held in the lower 16-bit area (LIR) of the instruction register (IR) 25, When deactivated by the code conversion control signal 245, information (non-operation code) indicating that the output is invalid is output. The code conversion circuit 242 can also be realized by a selector in the sense that when the signal 245 is inactive, it outputs a non-operation code instead of the value of the lower 16-bit area (LIR). The DSP decode signal 244 and the output of the code conversion circuit 242 are supplied to the decoder 34 of the DSP engine 3 as the DSP control signal 20. The first decoding circuit 240 decodes the most significant 6 bits stored in the upper 16-bit area (UIR) of the instruction register (IR) 25, so that the instruction code is a CPU instruction or 16 It can be determined whether the instruction is a bit DSP instruction or a 32-bit DSP instruction.

  When the decoded instruction is a 16-bit instruction, the code conversion control signal 245 is deactivated, and the code conversion circuit 242 outputs a non-operation code indicating that the output is invalid. When the decoded instruction is a 16-bit instruction, the shift control signal 246 is activated, and the instruction register (IR) 25 that receives it activates the lower 16-bit area (LIR) value to the upper 16 Shift to a bit area (LIR) and use the shifted instruction as all or part of the next instruction to be executed. For example, a case where a 16-bit CPU instruction is stored in the upper 16-bit area UIR of the instruction register IR and an upper 16-bit instruction code of the 32-bit DSP instruction is stored in the lower-side bit area LIR will be described. First, the 16-bit CPU instruction stored in the upper 16-bit area UIR is decoded by the first decoding circuit 240, and the CPU core 2 executes the instruction in accordance with the result, and is stored in the lower 16-bit area LIR. The upper 16-bit instruction code data of the 32-bit DSP instruction is transferred to the upper 16-bit area UIR. At this time, the random logic circuit 201 causes the arithmetic operation unit AU 208 to perform an address operation of an address to be stored in the program counter PC. The program counter PC stores an address according to the address calculation result calculated by the arithmetic operator AU208. According to the address stored in the program counter PC, the lower 16-bit instruction code data of the 32-bit DSP instruction is transferred from the instruction memory storing the 32-bit DSP instruction to the lower 16-bit area LIR of the instruction register IR. As a result, the 32-bit DSP instruction is stored in the instruction register IR. The 32-bit DSP instruction stored in the instruction register IR is supplied to the decoder 34 of the DSP engine 3 via the decoder 24. As another method, though not shown, a plurality of instruction prefetch buffers are provided in the CPU core 2. The plurality of instruction prefetch buffers prefetch instructions to be executed several cycles ahead of the currently executed instruction. When such a prefetch buffer is provided, when the upper 16-bit instruction code data of the 32-bit DSP instruction is transferred from the lower-side area LIR to the upper-side 16-bit area UIR as described above, the random logic circuit 201 selects an instruction prefetch buffer in which instruction code data of lower 16 bits of the 32-bit DSP instruction is prefetched. The lower 16-bit instruction code data of the 32-bit DSP instruction is read from the selected instruction prefetch buffer and stored in the lower 16-bit area LIR of the instruction register IR.

  When the decoded instruction is a 16-bit CPU instruction, the DSP decode signal 244 is a code meaning non-operation. When the decoded instruction is a 16-bit DSP instruction, the CPU control signal 247 is generated by the second decoding circuit 241 based on the CPU decode signal 243, and the control signal inside the DSP engine 3 is substantially the DSP. Decode signal 244 is decoded by decoder 34 and generated. When the decoded instruction is a 32-bit DSP instruction, the CPU control signal 247 is generated by the second decoding circuit 241 based on the CPU decode signal 243, and the control signal inside the DSP engine 3 is the DSP decode signal 244 and the code. The decoder 34 decodes and generates the output of the conversion circuit 242.

  The instruction set of the microcomputer 1 has an instruction code length of 16 bits and 32 bits, and the processing is different between the 16-bit instruction and the 32-bit instruction as described above. The operation will be described in detail.

  First, the case of a 16-bit instruction will be described. The first decoding circuit 240 decodes the upper 16 bits of the 32-bit instruction code fetched into the instruction register (IR) 25. In the first decoding circuit 240, when the most significant 6-bit code of the instruction code is other than “111110” and “11111”, it is understood that the instruction is a 16-bit length instruction. Along with the output of the signal 244, the shift control signal 246 for activating the instruction code data in the lower 16-bit area LIR of the instruction register (IR) 25 to the upper 16-bit area UIR is activated. In response to the activated shift control signal 246, the instruction register (IR) 25 shifts the instruction code stored in the lower 16-bit area LIR to the upper 16-bit area UIR. The shifted instruction code is then decoded by the first decoding circuit 240. The CPU decode signal 243 output from the decoder 24 is output to the second decode circuit 241, and the DSP decode signal 244 is supplied to the DSP engine 3. If the first decoding circuit 240 is found to be a 16-bit instruction, the code conversion control signal 245 is deactivated, and the code conversion circuit 242 confirms that the lower 16-bit instruction code is invalid. The code shown is generated as part of the DSP control signal 20. On the DSP engine 3 side, when the DSP decode signal 244 output from the first decode circuit 240 and the code signal output from the code conversion circuit 242 are input as the DSP control signal 20, the decoder 34 decodes the DSP control signal 20. To do. In the case of a 16-bit DSP instruction, the DSP control signal output from the code conversion circuit 242 is a signal indicating invalidity. Therefore, the decoder 34 pays attention to the DSP decode signal 244 and a multiplier in the DSP engine 3. Control signals such as (MAC) 304, arithmetic logic unit (ALU) 302, and shifter (SFT) 303 are output. The DSP engine 3 performs arithmetic processing according to these control signals.

  Next, the case of a 32-bit length instruction will be described. In the first decoding circuit 240 in the CPU core 2, a 32-bit instruction code is stored in the instruction register (IR) 25. Then, the upper 16 bits are decoded by the first decoding circuit 240 and decoded signals 243 and 244 are output. In the first decoding circuit 240, when the most significant 6-bit code of the instruction code is “111110”, it can be seen that the instruction is a 32-bit length instruction. Converts the instruction code of the lower 16 bits of the instruction register (IR) 25. The code-converted information is supplied as a DSP control signal 20 to the DSP engine 3 together with the DSP decode signal 244. The decoder 34 decodes the DSP control signal 20 to generate a control signal inside the DSP engine 3. The decoders 24 and 34 can be realized by a random logic circuit, for example.

  FIG. 17 shows another embodiment corresponding to FIG. In the embodiment of FIG. 6, the instruction data in the lower area LIR of the instruction register 25 is described as being shifted to the upper area UIR. The embodiment of FIG. 17 is provided with serial two-stage instruction prefetch buffers 250 and 251 constituting an instruction prefetch queue between the instruction register 25 and the internal data bus IDB. The data is selected by the selector 252 and given to the instruction register 25. Each of the instruction prefetch buffers 250 and 251 and the instruction register 25 holds data in units of 32 bits, and the holding operation is controlled by control signals φ1 to φ3 (synchronized with CLK1). Although not shown in particular, each of the instruction prefetch buffers 250 and 251 and the instruction register 25 has a master / slave configuration, and the master stage performs an input latch operation in synchronization with the rise of the corresponding control signal, and the slave The stage performs an input latch operation in synchronization with the fall of the corresponding control signal. As a result, the instruction data before and after the prefetch are stored in the instruction prefetch buffers 250 and 251 in two stages in series.

  The selector 252 selects 32-bit instruction data supplied to the port Pa or 32-bit instruction data supplied to the port Pb in accordance with the selection control signal φ4, and supplies it to the instruction register 25. The port Pa is supplied with 32-bit instruction data having the upper 16-bit area UPB1 of the instruction prefetch buffer 250 as the lower side and the lower 16-bit area LPB2 of the instruction prefetch buffer 251 as the upper side. The port Pb is supplied with the 32-bit instruction data stored in the instruction prefetch buffer 251 as it is.

  Thus, when the instruction prefetch buffer 251 holds a 32-bit DSP instruction, the selector 252 can set the 32-bit DSP instruction in the instruction register 25 by selecting the output of the port Pb. When the instruction prefetch buffer 251 holds a 16-bit DSP instruction or a 16-bit CPU instruction in the upper area UPB2, the selector 252 selects the output of the port Pb to select the 16-bit instruction in the instruction register 25. It can be set in the upper area UIR. When the instruction prefetch buffer 251 holds a 16-bit DSP instruction or a 16-bit CPU instruction in the lower area LPB2, the selector 252 selects the output of the port Pa to select the 16-bit instruction in the instruction register 25. Can be set in the upper region UIR of the. The instruction prefetch buffer 251 holds the upper 16-bit instruction code of the 32-bit DSP instruction in the lower area LPB2, and the instruction prefetch buffer 250 holds the lower 16-bit instruction code of the 32-bit DSP instruction in the upper area UPB1. When the selector 252 selects the output of the port Pa, the 32-bit DSP instruction can be set in the instruction register 25.

  In FIG. 17, reference numeral 253 denotes control logic for generating the latch control signals φ1 and φ2 of the instruction prefetch buffer, the latch control signal φ3 of the instruction register 25, and the selection control signal φ4. The control logic 253 generates the control signals φ1 to φ4 in accordance with the control signal 248 indicating whether the instruction is a 16-bit instruction or a 32-bit instruction and the state of the instruction code that remains unexecuted in each area of the instruction prefetch buffers 250 and 251. To do. This control logic 253 constitutes a part of control logic for instruction fetch. The control signal 248 is generated when the first decoding circuit 240 decodes the upper 6 bits of the instruction code data supplied from the upper area UIR of the instruction register 25, and details thereof will be described later. To do.

  The instruction code data is set in the instruction register 25 by the control logic 253 as follows. In the instruction fetch from the outside, there is room for newly storing 32-bit instruction code data in the instruction prefetch buffer 250 at the instruction fetch timing of the CPU core 2 (for example, an instruction fetch stage IF in a plurality of pipeline stages described later). Done in some cases. When an instruction fetch is performed at that timing, an instruction that has not yet been executed remains in the instruction prefetch buffer 251. In the first state where both the instruction codes stored in the areas UPB2 and LPB2 of the instruction prefetch buffer 251 are not yet executed, the 32-bit output of the instruction prefetch buffer 251 is sent to the selector 252 via the port Pb. Is selected and set in the instruction register 25. On the other hand, in the second state where only the instruction code stored in the lower area LPB2 of the instruction prefetch buffer 251 is not yet executed, the upper area UPB1 prefetched to the instruction prefetch buffer 250 and the lower area of the instruction prefetch buffer 251 are displayed. The instruction code data in the area LPB2 is set in the instruction register 25 via the port Pa.

  In the first state, when the decode circuit 240 decodes the instruction code data set in the upper area UIR of the instruction register 25, when it constitutes a 32-bit instruction, the instruction prefetch is performed at that time. The 32-bit instruction code data prefetched to the buffer 250 is transferred to the instruction prefetch buffer 251 as it is. On the other hand, when it is detected from the decoding result that the instruction is a 16-bit instruction, data shift from the instruction prefetch buffer 250 to the next-stage buffer 251 is not performed.

  In the second state, after the data is set to the instruction register 25 via the port Pa, the 32-bit instruction code data prefetched to the instruction prefetch buffer 250 is shifted and set to the instruction prefetch buffer 251 as it is. . After this shift set, if there is no instruction code data not yet executed in the instruction prefetch buffer 250, the instruction code data is prefetched into the instruction prefetch buffer 250 at the next instruction fetch timing.

  By such control, instruction code data not yet processed is set in the instruction register 25 after the instruction fetch timing. At this time, regardless of whether the instruction to be executed is a 16-bit CPU instruction, a 16-bit DSP instruction, or a 32-bit DSP instruction, the upper 16 bits are always supplied to the first decoding circuit 240. Become.

  The code conversion circuit 242 described with reference to FIG. 6 includes a selector 242A and code conversion logic 242B in FIG. Further, in the description of FIG. 6, the first decoding circuit 240 generates the control signals 245 and 246 whose levels are controlled depending on whether or not the instruction code decoded by the first decoding circuit 240 is a 16-bit instruction. In the example, a control signal 248 for identifying whether the decoded instruction code is a 16-bit instruction or a 32-bit instruction (in this embodiment, the 32-bit instruction is a DSP instruction) is output. When the control signal 248 means a 16-bit instruction, the selector 242A selects and supplies the no-operation code NOP to the code conversion logic 242B, and when the control signal 248 means a 32-bit DSP instruction, The instruction code in the lower area LIR of the instruction register 25 is supplied to the code conversion logic 242B. Although not particularly limited, the code conversion logic 242B corrects and outputs a part of the instruction code data in the lower area LIR of the instruction register 25, for example, code information for register selection, to a form suitable for the decoder 34 of the DSP engine 3.

  In the embodiment of FIG. 17, the first decoding circuit 240 decodes the 16-bit instruction code data held in the upper area UIR of the instruction register 25 and sends the CPU decode signal 243 obtained thereby to the second decoding circuit 243. The DSP decode signal 244 is supplied to the decoder 34. The CPU decode signal 243 is significant in both the CPU instruction and the DSP instruction and is supplied to the second decode circuit 241. The second decode circuit 241 decodes the CPU decode signal 243 to control information for address calculation and data calculation to be performed by the CPU core 2, and internal memories X-ROM 4, Y-ROM 5, X-RAM, Y Outputs address bus and data bus selection control information for accessing the RAM and external memory. As described above, the CPU core 2 performs address calculation and data path selection necessary for a DSP instruction.

  As described above, the DSP decode signal 244 is a decode signal that is significant when the instruction code supplied to the first decode circuit 240 is code data for a DSP instruction. The significant DSP decode signal 244 includes, for example, designation information such as a register in the DSP engine 3 that exchanges data with a memory that is accessed according to an address calculation performed in the CPU core 2. When the instruction code supplied to the first decoding circuit 240 is a CPU instruction, the DSP decode signal 244 is set to a code meaning invalid.

  Here, the code of the DSP instruction included in the instruction set of the microcomputer 1 will be described in more detail. FIGS. 18 and 19 show instruction codes of 16-bit DSP instructions, respectively, and FIGS. 20 and 21 show instruction codes of 32-bit DSP instructions. As described above, in the DSP instruction, the most significant 4 bits of the instruction code are assigned to “1111”, and the most significant 6 bits of the instruction code are “111100” and “111101” are 16-bit DSP instructions, An instruction whose uppermost 6 bits of the instruction code is “111110” is a 32-bit DSP instruction.

  The instruction format of the 16-bit DSP instruction shown in the first column (X Side of Data Transfer) in FIG. 18 is a data transfer instruction between the X memory (X-ROM 4, X-RAM 6) and the built-in register of the DSP engine 3. The instruction format shown in the second column (Y Side of Data Transfer) is a data transfer instruction between the Y memory (Y-ROM 5, Y-RAM 7) and the built-in register of the DSP engine 3. In the above instruction format, Ax and Ay designate a register included in the register array 209 (see FIG. 3) included in the CPU core 2, Ax = "0" designates the register R4, and Ax = "1" designates the register. R5 is designated, Ay = "0" designates the register R6, and Ay = "1" designates the register R7. Dx, Dy, Da specify registers included in the DSP engine, Dx = "0" is register X0, Dx = "1" is register X1, Dy = "0" is register Y0, Dy = "1" is register Y1, Da = "0" designates the register A0, and Da = "1" designates the register A1. Ix and Iy mean immediate values.

  The instruction format of the 16-bit DSP instruction shown in FIG. 19 is a data transfer instruction between a memory (not shown) connected to the outside of the microcomputer 1 and a built-in register of the DSP engine 3. As designates a register included in a register array 209 (see FIG. 3) built in the CPU core 2, and Ds designates a register X1, X0, Y1, Y0, A1, A0 built in the DSP engine or a register array 305 ( The register included in (see FIG. 4) is designated.

  The format of the 32-bit DSP instruction is a code “111110” area (bits 31 to 26) indicating that it is a 32-bit DSP instruction, an A field (bits 25 to 16), and a B field (bits 15 to 0). It is divided roughly into. FIG. 20 shows a mnemonic corresponding to the code of the field when focusing on the A field, and FIG. 21 shows a mnemonic corresponding to the code of the field when focusing on the B field.

  The code of the A field shown in FIG. 20 is the same as the code of bit 9 to bit 0 of the 16-bit DSP instruction shown in FIG. 18, and is shown in the first column (X Side of Data Transfer) of FIG. The A field code defines the data transfer between the X memory (X-ROM 4, X-RAM 6) and the built-in register of the DSP engine 3, and the A field code shown in the second column (Y Side of Data Transfer). Defines data transfer between the Y memory (Y-ROM5, Y-RAM7) and the built-in register of the DSP engine 3. The contents designated by the bits Ax, Ay, Dx, Dy, Da included in the A field are exactly the same as those in FIG.

  The code in the B field shown in FIG. 21 defines processing such as arithmetic operation, logical operation, shift operation, and load / store between registers performed in the DSP engine 3. For example, multiplication (PMULS), subtraction (PSUB), addition (PADD), rounding (PRND), shift (PSHL), logical product (PAND), exclusive logical sum (XOR), logical operation performed in the DSP engine 3 It defines operations such as sum (OR), increment (PINC), decrement (PDEC), clear (CLR), and loads (PLDS) and stores (PSTS) performed inside the DSP engine 3. The third column (3 Operand Operation with Condition) in FIG. 21 is a conditional code, and the condition (if cc) includes a logical value of a DC (data complete) bit (a bit indicating completion of data processing) or You can choose to ignore.

  An actual 32-bit DSP instruction is described by arbitrarily combining a B field code and an A field code. That is, the 32-bit DSP instruction defines a process of fetching an operand to be operated from inside or outside the microcomputer 1 and calculating it inside the DSP engine 3. As is apparent from the above description, the address calculation and data path selection for operand fetch are performed by the CPU 2. The code of the A field that defines the operand fetch in the 32-bit DSP instruction is the same as that of the 16-bit DSP instruction. The 16-bit DSP instruction is used for initial setting for a register in the DSP engine 3.

  As apparent from the configuration shown in FIG. 17 and the like, the code data of the A field of the 32-bit DSP instruction is set in the upper area UIR in the instruction register 25. A 16-bit DSP instruction having the same format as the A field is also set in the upper area UIR. Therefore, in any of them, the CPU core 2 may similarly select a data path necessary for necessary address calculation and data fetch (or operand fetch). In other words, the decoding circuits 240 and 241 required for the data fetch (or operand fetch) for executing the 32-bit DSP instruction and the data fetch (or operand fetch) for executing the 16-bit DSP instruction are common. This also contributes to the reduction of the logical scale of the microcomputer 1. The designation information of the internal register of the DSP engine 3 designated by the A field of the 32-bit DSP instruction and the designation information of the internal register of the DSP engine 3 designated by the 16-bit DSP instruction are given to the DSP engine 3 as the DSP decode signal 244. . Whether the DSP decode signal 244 is significant or not is determined by the first decoding circuit 240 by decoding the most significant 4 bits of the upper area UIR.

  Next, the contents of the arithmetic control in the microcomputer of the present embodiment will be described with reference to the instruction execution timing charts of FIGS. The microcomputer 1 of this embodiment performs a five-stage pipeline operation of IF, ID, EX, MA, and WB / DSP stages. IF is an instruction fetch stage, ID is an instruction decode stage, EX is an operation execution stage, MA is a memory access stage, WB / DSP is a stage for fetching data acquired from memory into a register of CPU core 2, or DSP engine 3 receives a DSP instruction The stage to execute. In each figure, Instruction / Data Access means memory access via the internal buses IAB and IDB, and the access target can be an external memory of the microcomputer 1 in addition to the built-in memories 4-7. X, Y Mem. Access means memory access via the internal buses XAB, XDB, YAB, YDB, and the access target is limited to the built-in memories 4-7. Isnt.Fetch is the instruction fetch timing to the instruction register (IR) 25, Fetch.Reg is the instruction register (IR) 25, Source Data Out is the source data output, Destination In is the destination data input timing, and Destination Register is the destination Each means a register. Pointer Reg. Means a pointer register, Address Calc. Means an address operation, Data Fetch means data fetch, and DSP Control signal Decord Timing means a decoding timing of the DSP control signal 20 by the decoder 34.

  FIG. 7 shows an execution time chart of the ALU operation instruction in the CPU core 2. Here, ADD Rm, Rn is taken as an example as an ALU operation instruction.

  In synchronization with the rising timing of the clock signal Clock2 immediately before the IF stage, an address in which an instruction (ADD Rm, Rn) to be executed is stored is output to the address bus IAB. In Instruction / Data Mem. Access, a memory access operation is performed in the IF stage. Specifically, the address specified by the address bus IAB is decoded in the period from the rising edge of the clock signal Clock1 to the rising edge of the clock signal Clock2, and the period from the rising edge of the clock signal Clock2 in the IF stage to the next rising edge of the clock signal Clock1. Instruction access is performed at. Therefore, an instruction is output to the data bus IDB from the rise of the clock signal Clock2 of the IF stage. The instruction output to the data bus IDB is taken into the instruction register (IR) 25 in synchronization with the rising timing of the clock signal Clock1 of the ID stage. In the ID stage, the data fetched into the instruction register (IR) 25 is decoded. In synchronization with the rising timing of the clock signal Clock 1 of the EX stage, the register storing the source data is accessed, and the value of the register is output to the internal buses A 1 and B 1 of the CPU core 2. In the instructions ADD Rm and Rn, the registers specified in Rm and Rn are the source registers. Rm and Rn can designate any register in the CPU core 2 (in FIG. 3, any register in the register 209, A0x, A1x, Ix, A0y, A1y, Iy, Rm, and Rn can be designated). The data output to the internal buses A1 and B1 of the CPU core 2 is subjected to an addition operation by an arithmetic logic unit (ALU) 213, and the result is output to the internal bus C1 of the CPU core 2. The calculation result output to the internal bus C1 of the CPU core 2 is a destination register in synchronization with the rising timing of the clock signal Clock2 of the EX stage (the destination register is designated as Rn by an ADD Rm, Rn instruction) Stored in a register). As described above, in the ALU operation instruction in the CPU core 2, the instruction execution operation is completed in the three pipeline stages of IF, ID, and EX.

  FIG. 8 shows a time chart of data reading operation from the memory to the CPU core 2. The operation will be described by taking MOV.L @Rm, Rn as an example of a data read operation instruction from the memory to the CPU core 2. Since the operations up to instruction fetch (IF) and instruction decode (ID) are the same as those in FIG. 7, detailed description thereof will be omitted.

  In synchronization with the rising timing of the clock signal Clock 1 of the EX stage, the register data serving as the address pointer is output to the internal bus A 1 of the CPU core 2. In this example, the register serving as the address pointer is the register specified by Rm. Registers that can be specified as Rm are arbitrary registers included in the CPU core 2 (in FIG. 3, any register included in Reg., A0x, A1x, Ix, A0y, A1y, and Iy can be specified as Rm). The data output to the internal bus A1 of the CPU core 2 is stored in the address buffer 205 and output to the address bus IAB in synchronization with the rising timing of the clock signal Clock2 of the EX stage. On the other hand, the data output to the internal bus A1 of the CPU core 2 is operated by an arithmetic logic unit (ALU) 213. In this case, the arithmetic logic unit (ALU) 213 performs 0 addition operation. The result is output to the internal bus C1 of the CPU core 2. The calculation result output to the internal bus C1 of the CPU core 2 is stored in a pointer register (in this case, a register designated by Rm) in synchronization with the rising timing of the clock signal Clock2 of the EX stage. In Instruction / Data Mem. Access, the address output to the address bus IAB is decoded in synchronization with the rising timing of the EX stage clock signal Clock 2 in the period from the rising edge of the clock signal Clock 1 of the MA stage to the rising edge of the clock signal Clock 2. The data access is performed in the period from the rise of the clock signal Clock2 of the MA stage to the rise of the next clock signal Clock1. Therefore, data is output to the data bus IDB from the rise of the clock signal Clock2 of the MA stage. The data output to the data bus IDB is taken into the CPU core 2 in synchronization with the rising timing of the clock signal Clock 1 of the WB / DSP stage, and the data is output to the internal bus DW of the CPU core 2. The data on the internal bus DW of the CPU core 2 is stored in the destination register in synchronization with the rising timing of the clock signal Clock2 of the WB / DSP stage, and the operation ends. In this example, the destination register is a register designated as Rn. Registers that can be designated as Rn are any registers included in the CPU core 2 (in FIG. 3, any register in Reg., A0x, A1x, Ix, A0y, A1y, and Iy can be designated as Rn). As described above, in the data read operation instruction from the memory to the CPU core 2, the instruction execution operation is completed in the five pipeline stages of IF, ID, EX, MA, and WB / DSP.

  FIG. 9 shows a time chart of a data write operation instruction from the CPU core 2 to the memory. The operation will be described by taking MOV.L Rm, @Rn as an example of a data write operation command from the CPU core 2 to the memory. Since the instruction fetch (IF) and instruction decode (ID) operations are the same as those in FIG. 8, a detailed description thereof will be omitted.

  Data in a register serving as an address pointer is output to the internal bus A1 of the CPU core 2 in synchronization with the rising timing of the clock signal Clock1 of the EX stage. In this example, the register serving as the address pointer is the register specified by Rn. Registers that can be designated as Rn are any registers included in the CPU core 2 (in FIG. 3, any register in Reg., A0x, A1x, Ix, A0y, A1y, and Iy can be designated as Rn). The data output to the internal bus A1 of the CPU core 2 is stored in the address buffer 205 and output to the address bus IAB in synchronization with the rising timing of the clock signal Clock2 of the EX stage. On the other hand, the data output to the internal bus A1 of the CPU core 2 is operated by an arithmetic logic unit (ALU) 213. In this case, the arithmetic logic unit (ALU) 213 performs 0 addition operation. The calculation result is output to the internal bus C1 of the CPU core 2. The calculation result output to the internal bus C1 of the CPU core 2 is stored in a pointer register (in this case, a register designated by Rn) in synchronization with the rising timing of the clock signal Clock2 of the EX stage. In the case of the instruction MOV.L Rm, @Rn, an address calculation is performed at the EX stage, and at the same time, preparation for outputting data to be written to the memory to the data bus IDB is performed. A value is output to the internal bus DR of the CPU core 2 from a register storing data to be written to the memory in synchronization with the rising timing of the clock signal Clock1 of the EX stage. In this example, the register storing data to be written to the memory is a register specified by Rm. Registers that can be designated as Rm are any registers included in the CPU core 2 (in FIG. 3, any register in Reg., A0x, A1x, Ix, A0y, A1y, and Iy can be designated as Rm). The value output to the internal bus DR of the CPU core 2 is output to the data bus IDB in synchronization with the rising timing of the clock signal Clock2 of the MA stage. In the Instruction / Data Mem. Access, the address output to the address bus IAB is decoded in synchronization with the rising timing of the EX stage clock signal Clock 2 in the period from the rising edge of the clock signal Clock 1 of the MA stage to the rising edge of the clock signal Clock 2. The data output to the data bus IDB is written in synchronization with the rising timing of the clock signal Clock2 of the MA stage, and the operation is terminated. In the data write operation command from the memory to the CPU core 2, the operation ends when the data is output to the data bus IDB as the CPU core 2, so that it operates in four pipeline stages of IF, ID, EX, and MA. Is completed.

  FIG. 10 shows a time chart when the DSP instruction is executed. As an example of the DSP instruction, the operation will be described using PADDC Sx, Sy, Dz NOPX NOPY as an example. This instruction adds the data stored in the register in the DSP engine 3 and transfers data between the DSP engine 3 and the X-ROM 4 and X-RAM 6 and the Y-ROM 5 and Y-RAM 7. There is no order.

  Since the instruction fetch operation is the same as in FIG. 7, a detailed description thereof is omitted. In the ID stage, the instruction code fetched by the CPU core 2 is decoded during the period from the clock signal Clock 1 to the clock signal Clock 2, and the result of decoding the instruction code at the timing of the clock signal Clock 2 of the ID stage is the DSP control signal 20 as a DSP. It is output to the engine 3. In the DSP engine 3, when the DSP control signal 20 is input from the CPU core 2, the DSP control signal 20 input in the period up to the MA stage is decoded. In synchronization with the rising timing of the clock signal Clock 1 of the WB / DSP stage, the register storing the source data is accessed, and the value of the register is output to the internal buses A 2 and B 2 of the DSP engine 3. In this example, the register storing the source data is a register specified by Sx and Sy. Registers that can be designated as Sx and Sy are arbitrary registers within the DSP engine 3 (in FIG. 4, any register in Reg. Can be designated as Sx and Sy). The data output to the internal buses A 2 and B 2 of the DSP engine 3 is operated by an arithmetic logic unit (ALU) 302, and the result is output to the internal bus C 2 of the DSP engine 3. The calculation result output to the internal bus C2 of the DSP engine 3 is stored in the destination register in synchronization with the rising timing of the clock signal Clock2 of the WB / DSP stage. In this example, the destination register is a register specified by Dz. A register that can be designated as Dz is an arbitrary register in the DSP engine 3 (an arbitrary register in Reg. In FIG. 4). With the DSP instruction as described above, the operation is completed in five pipeline stages of IF, ID, EX, MA, and WB / DSP.

  FIG. 11 shows a time chart of data read operation commands from the X and Y memories 4 to 7 to the DSP engine 3. As an example of a data read operation command from the X, Y memories 4 to 7 to the DSP engine 3, the operation will be described by taking MOVX.W @Ax, Dx MOVY.W @Ay, Dy as an example. This instruction is an instruction to transfer data stored at an address designated by Ax and Ay to a register designated by Dx and Dy. Since the instruction fetch and instruction decode operations are the same as those in FIG. 10, a detailed description thereof will be omitted.

  When a data read operation instruction from the X, Y memories 4 to 7 to the DSP engine 3 is executed, the CPU core 2 generates an address of the memory to be accessed. Therefore, in synchronization with the rising timing of the clock signal Clock 1 in the EX stage, the register storing the address to be accessed is accessed, and the value of the register is output to the internal buses A 1 to A 2 of the CPU core 2. In this example, the register storing the address to be accessed is a register designated by Ax and Ay. Registers that can be specified as Ax are registers A0x and A1x included in the CPU core 2, and registers that can be specified as Ay are registers A0y and A1y included in the CPU core 2. Data output to the internal buses A1 to A2 of the CPU core 2 is stored in the memory address buffer (MABX, MABY) and output to the address buses XAB, YAB in synchronization with the rising timing of the clock signal Clock2 of the EX stage. The On the other hand, the data output to the internal buses A1 to A2 of the CPU core 2 is subjected to address calculation by the ALU 213 and PAU 212. In this case, the ALU 213 and the PAU 212 perform 0 addition operation. The calculation result is output to the internal buses C1 and C2 of the CPU core 2. The calculation results output to the internal buses C1 and C2 of the CPU core 2 are stored in a pointer register (in this case, registers designated by Ax and Ay) in synchronization with the rising timing of the clock signal Clock2 of the EX stage. In the X and Y memories 4 to 7, the addresses output to the address buses XAB and YAB are decoded at the rising timing of the EX stage clock signal Clock2 in the period from the rising edge of the clock signal Clock1 of the MA stage to the rising edge of the clock signal Clock2. The data access is performed during the period from the rise of the clock signal Clock2 of the MA stage to the rise of the next clock signal Clock1. Therefore, data is output to the data buses XDB and YDB from the rise of the clock signal Clock2 of the MA stage. The data output to the data buses XDB and YDB is taken into the DSP engine 3 in synchronization with the rising timing of the clock signal Clock 1 of the WB / DSP stage, and the data is supplied to the internal buses D 1 and D 2 of the DSP engine 3. . Data on the internal buses D1 and D2 of the DSP engine 3 are stored in the destination register in synchronization with the rising timing of the clock signal Clock2 of the WB / DSP stage, and the operation ends. In this example, the destination register is a register designated as Dx and Dy. Registers that can be specified as Dx are registers X0 and X1 included in the DSP engine 3, and registers that can be specified as Dy are registers Y0 and Y1 included in the DSP engine 3. As described above, in the data read operation instruction from the memory to the DSP engine 3, the operation is completed in five pipeline stages of IF, ID, EX, MA, and WB / DSP. This is because such a parallel data reading operation allows the CPU core 2 to access the X and Y memories 4 to 7 via the mutually independent buses XAB and XDB and YAB and YDB.

  FIG. 12 shows a time chart of a data write operation from the DSP engine 3 to the X and Y memories 6 and 7. As an example of a data write operation instruction from the DSP engine 3 to the X, Y memories 6 and 7, the operation will be described by taking MOVX.W Da, @Ax MOVY.W Da, @Ay as an example. This instruction is an instruction to transfer the data stored in the register designated by Da to the address stored in the register designated by Ax and Ay.

  Since the instruction fetch and instruction decode operations are the same as those in FIG. 11, detailed description thereof will be omitted. When executing a data write operation instruction from the DSP engine 3 to the X and Y memories 6 and 7, the CPU core 2 generates a memory address to be accessed. Therefore, in synchronization with the rising timing of the clock signal Clock 1 in the EX stage, the register storing the address to be accessed is accessed, and the value of the register is output to the internal buses A 1 to A 2 of the CPU core 2. In this example, the register storing the address to be accessed is a register designated by Ax and Ay. Registers that can be specified as Ax are registers A0x and A1x included in the CPU core 2, and registers that can be specified as Ay are registers A0y and A1y included in the CPU core 2. The data output to the internal buses A1 and A2 of the CPU core 2 is stored in the memory address buffer (MABX, MABY) and output to the address buses XAB and YAB in synchronization with the rising timing of the clock signal Clock2 of the EX stage. The

  In synchronization with the rise timing of the clock signal Clock 1 of the MA stage, the internal register of the DSP engine 3 storing the data to be transferred is accessed, and the value of the register is stored in the internal buses D 1 and D 2 of the DSP engine 3. They are output and stored in memory data buffers (MDBX, MDBY). In this example, the internal register of the DSP engine 3 in which data to be transferred is stored is a register designated by Da. Registers that can be designated by Da are the registers A0 and A1 included in the DSP engine 3. The data stored in the memory data buffers (MDBX, MDBY) are output to the data buses XDB, YDB in synchronization with the rising timing of the clock signal Clock2 of the MA stage. In the X and Y memories 6 and 7, the addresses output to the address buses XAB and YAB are decoded at the rising timing of the EX stage clock signal Clock2 during the rising period of the clock signal Clock2 from the rising edge of the clock signal Clock1 of the MA stage. The data access is performed during the period from the rise of the clock signal Clock2 of the MA stage to the rise of the next clock signal Clock1. Therefore, the data output to the data buses XDB and YDB is written from the rising edge of the clock signal Clock2 of the MA stage. As described above, in the data write operation instruction from the DSP engine 3 to the X and Y memories 6 and 7, the operation is completed in four pipeline stages of IF, ID, EX, and MA. This is because such parallel data writing operation allows the CPU core 2 to access the X and Y memories 4 and 6 via the mutually independent buses XAB and XDB and TAB and YDB.

  FIG. 13 shows a time chart of the data reading operation from the memory to the DSP engine 3. As an example of a data read operation command from the memory to the DSP engine 3, the operation will be described by taking MOVS.L @As, Ds as an example. This instruction is an instruction to transfer data stored at an address designated by As to a register designated by Ds.

  The basic operation is the same as the data reading operation from the X, Y memories 4 to 7 to the DSP engine 3 shown in FIG. The difference between FIG. 11 and FIG. 13 is that the target memory is X and Y memories 4 to 7 in FIG. 11 and the X bus and Y bus are used, whereas in FIG. 13, the target memory is supported by the microcomputer 1. This means that the buses IAB and IDB are used because the memory is connected to the space. In synchronization with the rising timing of the EX stage clock signal Clock 1, the register having the address to be accessed is accessed, and the value of the register is output to the internal bus A 1 of the CPU core 2. In this example, the register storing the address to be accessed is the register specified by As. A register that can be designated by As is an arbitrary register in Reg. Included in the CPU core 2. The data output to the internal bus A1 of the CPU core 2 is stored in the address buffer 205 and output to the address bus IAB in synchronization with the rising timing of the clock signal Clock2 of the EX stage. On the other hand, the data output to the internal bus A1 of the CPU core 2 is subjected to an address operation by an arithmetic logic unit (ALU) 213. In this case, the arithmetic logic unit (ALU) 213 performs 0 addition operation. The calculation result is output to the internal bus C1 of the CPU core 2. The calculation result output to the internal bus C1 of the CPU core 2 is stored in a pointer register (in this case, a register designated by As) in synchronization with the rising timing of the clock signal Clock2 of the EX stage. In the memory to be accessed, the address output to the address bus IAB is decoded at the rising timing of the EX stage clock signal Clock2 during the rising period of the clock signal Clock2 from the rising edge of the clock signal Clock1 of the MA stage. Data access is performed during the period from the rise of the clock signal Clock2 of the stage to the rise of the next clock signal Clock1. Therefore, data is output to the data bus IDB from the rise of the clock signal Clock2 of the MA stage. The data output to the data bus IDB is taken into the DSP engine 3 in synchronization with the rising timing of the clock signal Clock1 of the WB / DSP stage, and the data is supplied to the internal bus D1 of the DSP engine 3. Data on the internal bus D1 of the DSP engine 3 is stored in the destination register in synchronization with the rising timing of the clock signal Clock2 of the WB / DSP stage, and the operation ends. In this example, the destination register is a register designated as Ds. A register that can be designated as Ds is an arbitrary register in the DSP engine 3. As described above, in the data read operation instruction from the memory to the DSP engine 3, the operation is completed in five pipeline stages of IF, ID, EX, MA, and WB / DSP.

  FIG. 14 shows a time chart of the data write operation from the DSP engine 3 to the memory. As an example of a data write operation command from the DSP engine 3 to the memory, the operation will be described by taking MOVS.L Ds, @As as an example. This instruction is an instruction to transfer the data stored in the register designated by Ds to the address designated by As.

  The basic operation is the same as the data write operation from the DSP engine 3 to the X and Y memories shown in FIG. The difference between FIG. 12 and FIG. 14 is that in FIG. 12, since the target memory is an X, Y memory, the buses XAB, XDB, and the buses YAB, YDB are used, whereas in FIG. 14, the target memory is a microcomputer. This means that the buses IAB and IDB are used because 1 is a memory connected to a space supported by 1.

  In synchronization with the rise timing of the EX stage clock signal Clock 1, the register holding the transfer destination address is accessed, and the value of the register is output to the internal bus A 1 of the CPU core 2. In this example, the register storing the address to be accessed is the register specified by As. The register that can be specified by As is an arbitrary register in the register Reg. Included in the CPU core 2. The data output to the internal bus A1 of the CPU core 2 is stored in the address buffer 205 and output to the address bus IAB in synchronization with the rising timing of the clock signal Clock2 of the EX stage. On the other hand, the data output to the internal bus A1 of the CPU core 2 is subjected to an address operation by an arithmetic logic unit (ALU) 213. In this case, the arithmetic logic unit (ALU) 213 performs 0 addition operation. The calculation result is output to the internal bus C1 of the CPU core 2. The calculation result output to the bus C1 of the CPU core 2 is stored in a pointer register (in this case, a register designated by As) in synchronization with the rising timing of the clock signal Clock2 of the EX stage.

  In synchronism with the rising timing of the clock signal Clock1 of the MA stage, the value of the register in the DSP engine 3 storing the data to be transferred is output to the internal bus D1 of the DSP engine 3, and the memory data buffer (MDBI) Stored in Data stored in the memory data buffer (MDBI) is output to the data bus IDB in synchronization with the rising timing of the clock signal Clock2 of the MA stage. In this example, a register in the DSP engine 3 storing data to be transferred is a register designated by Ds. A register that can be designated as Ds is an arbitrary register in the DSP engine 3. In the memory to be accessed, the address output to the address bus IAB is decoded at the rising timing of the EX stage clock signal Clock2 during the rising period of the clock signal Clock2 from the rising edge of the clock signal Clock1 of the MA stage, and the MA stage. Data access is performed during the period from the rising edge of the clock signal Clock2 to the rising edge of the next clock signal Clock1. Therefore, the data output from the DSP engine 3 is written into the memory at the rising timing of the clock signal Clock2 of the MA stage. As described above, in the data write operation instruction from the DSP engine 3 to the external memory, the operation is completed in four pipeline stages of IF, ID, EX, and MA.

  Next, as an example of the DSP operation instruction, PADD Sx, Sy, Du PMUL Se, Sf, Dg MOVX.W @Ax, Dx MOVY.W @Ay, Dy will be described as an example and the operation will be described with reference to FIG. . This instruction adds and multiplies data stored in a register in the DSP engine 3 and transfers data from the X-ROM 4, X-RAM 6, Y-ROM 5, and Y-RAM 7 to the DSP engine 3. The operation is a combination of the operations shown in FIGS. Since the instruction fetch and instruction decode operations are the same as those in FIG. 10, a detailed description thereof will be omitted.

  When a data read operation instruction from the X, Y memory to the DSP engine 3 is executed, the CPU core 2 generates an address of the memory to be accessed. Therefore, in synchronization with the rising timing of the clock signal Clock 1 in the EX stage, the register having the address to be accessed is accessed, and the value of the register is output to the internal buses A 1 and A 2 of the CPU core 2. In this example, the register storing the address to be accessed is a register designated by Ax and Ay. Registers that can be specified as Ax are registers A0x and A1x included in the CPU core 2, and registers that can be specified as Ay are registers A0y and A1y included in the CPU core 2. The data output to the internal buses A1 and A2 of the CPU core 2 is stored in the memory address buffer (MABX, MABY) and output to the address buses XAB and YAB in synchronization with the rising timing of the clock signal Clock2 of the EX stage. The On the other hand, the data output to the CPU internal buses A1 and A2 is subjected to an address operation in the ALU 213 and PAU 212 (in this case, the ALU 213 and PAU 212 perform 0 addition operation), and the result is sent to the internal buses C1 and C2 of the CPU core 2. Is output. The calculation results output to the internal buses C1 and C2 of the CPU core 2 are stored in a pointer register (in this case, registers designated by Ax and Ay) in synchronization with the rising timing of the clock signal Clock2 of the EX stage. In the X and Y memories, the addresses output to the address buses XAB and YAB are decoded at the timing of the rise of the clock signal Clock2 of the EX stage during the period of rise of the clock signal Clock2 from the rise of the clock signal Clock1 of the MA stage. Data access is performed in the period from the rise of the clock signal Clock2 of the MA stage to the rise of the next clock signal Clock1. Therefore, data is output to the data buses XDB and YDB from the rise of the clock signal Clock2 of the MA stage. The data output to the data buses XDB and YDB is taken into the DSP engine 3 in synchronization with the rising timing of the clock signal Clock1 of the WB / DSP stage, and the data is output to the internal buses D1 and D2 of the DSP engine 3. . Data on the internal buses D1 and D2 of the DSP engine 3 are stored in the destination register (Destination Reg.) In synchronization with the rising timing of the clock signal Clock2 of the WB / DSP stage, and the operation ends. In this example, the destination register is a register designated as Dx and Dy. Registers that can be specified for Dx are X0 and X1 in the DSP engine 3, and registers that can be specified for Dy are Y0 and Y1 in the DSP engine 3.

  In parallel with the data transfer, a DSP calculation operation is also performed simultaneously. In synchronization with the rising timing of the clock signal Clock 1 of the WB / DSP stage, the register storing the source data is accessed, and the register value is output to the internal buses A 1, A 2, B 1, B 2 of the DSP engine 3. . In this example, the register storing the source data is a register designated by Sx and Sy in the case of an ADD (addition) operation, and a register designated by Se and Sf in the case of a MUL (multiplication) operation. Registers that can be designated as Sx, Sy, Se, and Sf are arbitrary registers in the DSP engine 3. The data output to the internal buses A1 and B1 of the DSP engine 3 is multiplied by the MAC 304, and the result is output to the DSP engine 3 internal bus C1. The data output to the internal buses A2 and B2 of the DSP engine 3 are added by the ALU 302, and the result is output to the DSP engine 3 internal bus C2. The calculation results output to the internal buses C1 and C2 of the DSP engine 3 are stored in the destination register in synchronization with the rising timing of the clock signal Clock2 of the WB / DSP stage. The destination register in this example is a register designated by Du for the ADD operation and Dg for the MUL operation. Registers that can be specified for Du and Dg are arbitrary registers in the DSP engine 3.

  As described above, an instruction for adding and multiplying data stored in a register in the DSP engine 3 and transferring data from the X-ROM 4, the X-RAM 6, the Y-ROM 5, and the Y-RAM 7 to the DSP engine 3. The operation is completed in five pipeline stages of IF, ID, EX, MA, and WB / DSP.

As a second example of a DSP operation instruction,
Inst1: PADD A0, M0, A0 PMUL A1, X0, A1 MOVX.W @ R4, X1 MOVY.W @ R6, Y0
Inst2: ADD R8, R9
Inst3: ADD R10, R11
Inst4: ADD R12, R13
As an example, the operation will be described with reference to FIG. These four instructions are examples in which different operations are realized in the same clock cycle by using the address buses IAB, XAB, and YAB simultaneously. Since the instruction operations from Inst1 to Inst4 are the same as those in FIGS. 7 and 15, detailed description thereof will be omitted.

  First, an instruction fetch of Inst1 is performed at the IF stage of Inst1. At the time of Inst1 ID stage, Inst2 is in the IF stage, so instruction fetch is performed.

  In the EX stage of Inst1, instruction calculation is performed for the ID stage in Inst2 and instruction fetch is performed for the IF stage in Inst3 while performing address calculation for accessing the X and Y memories.

  In the Inst1 MA stage, the address calculated in the EX stage is output to the address buses XAB and YAB (the timing at which the address is actually output is from the rising timing of the clock signal Clock2 of the EX stage). Data is taken in from XDB and YDB. At this time, since Inst2 is an EX stage, the ADD operation of R8 and R9 is performed and the operation is completed. Inst3 is an ID stage and instruction decoding is performed. Since Inst4 is an IF stage, the address where Inst4 is stored is output to the address bus IAB. The timing for actually outputting to the address bus IAB is from the rising timing of the clock signal Clock2 half a cycle before the IF stage of Inst4. This timing is the same as the timing of outputting addresses to the address buses XAB and YAB in Inst 1 (the second half of the EX stage and the first half of the MA stage). That is, the address buses XAB and YAB are used for data transfer, and the address bus IAB is used for instruction fetch. In the microcomputer 1, since there are internal address buses IAB, XAB, YAB and internal data buses IDB, XDB, YDB respectively connected to the CPU core 2, these three types of internal buses are used to be different in the same clock cycle. Memory access operations can be performed.

  Thereafter, Inst1 completes the operation by performing the DSP operation in the WB / DSP stage, Inst2 has already completed the operation, and Inst3 has completed the operation by performing the ADD operation of R10 and R11, and inst4 has completed the operation. Therefore, instruction decoding is performed.

  In the next cycle, only the EX stage of Inst4 is performed, and the ADD operation of R12 and R13 is performed to complete the operation.

  According to the present embodiment, the following effects are obtained. The built-in memory is divided into Y memory 5 and 7 and X memory 4 and 6 in consideration of the product-sum operation by the DSP engine 3, and the CPU core 2 uses the Y memory 5 and 7 and X memory 4 and 6 as an internal bus. XAB and XDB and internal buses YAB and YDB are respectively accessible in parallel. As a result, two pieces of data from the built-in memories 4 to 7 can be simultaneously transferred to the DSP engine 3. Further, since the internal buses XAB and XDB and the internal bus buses YAB and YDB are also individually separated from the internal buses IAB and IDB interfaced to the outside, the CPU core 2 accesses the X memories 4 and 6 and the Y memories 5 and 7. In parallel, external memory access is also possible. Thus, since there are three types of address buses IAB, XAB, YAB and data buses IDB, XDB, YDB respectively connected to the CPU core 2, these three types of internal buses are used to be different in the same clock cycle. Memory access operations can be performed. Therefore, it is possible to easily cope with the case where the program and data exist in the external memory and to speed up the arithmetic processing.

  By configuring each of the X memories 4 and 6 and the Y memories 5 and 7 from a RAM and a ROM, the usability of the microcomputer can be further improved.

  As described above, the built-in memory is divided into the X memory 4 and 6 and the Y memory 5 and 7, and each of the divided memories is provided with the ROM and the RAM. The RAM is the data memory and the ROM is the program memory. This makes it possible to separate the data memory and the program memory, transfer two pieces of data to the DSP engine 3 in parallel, and efficiently perform instruction fetch, data transfer, and computation by parallel pipeline processing. It can be carried out.

  Since the CPU core 2 includes the modulo address output unit 200, it is possible to speed up address generation for repetitive operations such as a product-sum operation in the CPU core 2.

  In the CPU instruction, the most significant 4 bits of the instruction code are assigned to a space from “0000” to “1110”. In the DSP instruction, the most significant 4 bits of the instruction code are all assigned to “1111”. Further, the instruction assigned to the space where the most significant 6 bits of the instruction code are “111100” and “111101” is a 16-bit instruction code even in a DSP instruction. An instruction in which the most significant 6 bits of the instruction code are “111110” is an instruction code having a 32-bit length. No instruction is assigned to the space in which the most significant 6 bits of the instruction code are “111111”, which is an unused area. In this way, by providing the above-described rules for code allocation for instructions of a maximum of 32 bits, if the most significant 6 bits of the instruction code are decoded, the instruction is a CPU instruction or a 16-bit DSP Whether it is an instruction or a 32-bit DSP instruction can be determined by a small logic scale decoder, and it is not always necessary to decode all 32 bits at once.

  As described with reference to FIG. 17, after the instruction fetch timing, instruction code data not yet processed is set in the instruction register 25. At this time, an instruction to be executed is a 16-bit CPU instruction, 16-bit CPU instruction. Whether the DSP instruction or the 32-bit DSP instruction, the upper 16 bits can be supplied to the first decoding circuit 240 without fail.

  The code of the A field of the 32-bit DSP instruction is set in the upper area UIR in the instruction register 25, and the 16-bit DSP instruction having the same format as the A field is also set in the upper area UIR. Accordingly, in any of them, the CPU core 2 can similarly perform a necessary address calculation and a data path selection necessary for data fetching. In other words, the decode circuits 240 and 241 can be shared for data fetch for executing a 32-bit DSP instruction and data fetch for executing a 16-bit DSP instruction. Can be reduced.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof. For example, identification of a CPU instruction, a 16-bit DSP instruction, and a 32-bit DSP instruction is not limited to using the most significant 6 bits of the instruction, and can be increased or decreased according to the number of instruction codes. Further, the function of shifting the lower 16 bits for the instruction register to the upper side can be replaced with another function. Further, the number of registers and the types of arithmetic units included in the CPU core and the DSP engine are not limited to the above embodiments, and can be changed as appropriate. Further, the number of memories can be increased without being limited to two. The number of address buses and data buses connected to the memory can be increased according to the number of memories. For example, a Z memory is newly provided in addition to the X and Y memories. Accordingly, an address bus ZAB is connected between the CPU and the Z memory, and a data bus ZDB is connected between the DSP engine and the Z memory. With such a configuration, not only the data from the X and Y memories is taken into the DSP engine during the product-sum operation, but also the data that has been calculated before the currently executing instruction is transferred to the Z memory circuit via the Z bus. It becomes possible to write simultaneously. Since the calculation data can be fetched and written into the memory with one instruction, the throughput of the entire microcomputer is further improved. The present invention is most suitable for use as a device-embedded control microcomputer applied to information compression / decompression processing and filtering processing in a mobile communication device, servo control, image processing in a printer, and the like.

1 is an overall block diagram of a microcomputer according to an embodiment of the present invention. It is an example address map of a microcomputer. It is a block diagram of a CPU core showing a modulo address output unit in detail. It is an example block diagram of a DSP engine. It is an example explanatory drawing regarding the instruction format and instruction code of a microcomputer. It is a block diagram which shows the connection structure of the decoder of a CPU core, and the decoder of a DSP engine. It is an execution time chart of an ALU operation instruction in the CPU core. It is an execution time chart of the instruction which reads data from a memory to a CPU core. 6 is an execution time chart of a command for writing data from a CPU core to a memory. It is an example time chart when a DSP command is executed. It is an execution time chart of an instruction for reading data from an X, Y memory to a DSP engine. 6 is an execution time chart of an instruction for writing data from a DSP engine to X and Y memories. It is an execution time chart of the instruction which reads data from a memory to a DSP engine. It is an execution time chart of the instruction which writes data from a DSP engine to memory. It is an example execution time chart of a DSP operation instruction. It is an example time chart when a DSP operation instruction is executed continuously. It is a block diagram which shows another Example corresponding to FIG. 3 is an instruction format diagram showing codes of a 16-bit DSP instruction that defines data transfer between a built-in memory of the microcomputer and a built-in register of the DSP engine 3. FIG. 4 is an instruction format diagram showing codes of a 16-bit DSP instruction that defines data transfer between an external memory of a microcomputer and a built-in register of the DSP engine 3. FIG. When attention is paid to the A field of a 32-bit DSP instruction, it is an instruction format diagram showing a code of the field and a mnemonic corresponding to the code. When attention is paid to the B field of a 32-bit DSP instruction, it is an instruction format diagram showing a code of the field and a mnemonic corresponding to the code.

Explanation of symbols

1 Microcomputer 2 CPU core (Central processing unit)
20 DSP control signal 24 Decoder 240 First decode circuit 241 Second decode circuit 242 Code conversion circuit 243 CPU decode signal 244 DSP decode signal 245 Code conversion control signal 247 CPU control signal 25 Instruction register 250, 251 Instruction prefetch buffer 200 Modulo Address output unit 206, 207 Memory address buffer 212 Address operator 213 Arithmetic logic operator 214 Modulo start address register 215 Modulo end address register 216, 226 Modulo address register 3 DSP engine (digital signal processing unit)
34 Decoder 302 Arithmetic Logic Operator 304 Multiplier 309, 310, 311 Memory Data Buffer 4 X-ROM (Second Memory)
5 Y-ROM (first memory)
6 X-RAM (second memory)
7 Y-RAM (first memory)
12 External memory interface

Claims (16)

A first processor having an address generator;
A second processor;
First to third address buses connected to the first processor;
First to third data buses connected to the second processor;
A first memory connected to the first and second address buses and the first and second data buses;
A second memory connected to the first and third address buses and the first and third data buses;
The first processor is connected to the first data bus;
The address generator can generate first to third address signals to be output to the first to third address buses;
The first processor is capable of reading the first data designated by the first address signal via the first data bus,
The first data includes an instruction,
When the first processor executes the instruction, the address generator can generate the second and third address signals to be output to the second and third address buses.
The second processor can read the second data of the first memory designated by the second address signal output by the first processor via the second data bus, and the third processor A microprocessor capable of reading out third data of the second memory designated by an address signal through the third data bus. In claim 1,
The address generator includes a first address generation unit and a second address generation unit,
The first address generation unit can generate the first address signal to be output to the first address bus.
The microprocessor according to claim 2, wherein the second address generation unit is capable of generating the second and third address signals for accessing the first and second memories. In claim 2,
The second processor can acquire the second data and the third data at the same time using the second address signal and the third address signal output from the first processor. A microprocessor to do. In claim 3,
The microprocessor, wherein the second processor is capable of executing arithmetic processing using the second data and the third data signal acquired via the second data bus and the third data bus. . In claim 2,
The second processor can read data from at least one of the first memory and the second memory using the second address signal and the third address signal, and performs an operation using the read data. A microprocessor capable of executing processing. In claim 3,
The second processor has an execution unit,
The microprocessor, wherein the execution unit is capable of executing an operation using the second data and the third data. A CPU having an address generator;
A DSP whose operation can be controlled by the CPU;
First to third address buses connected to the CPU;
First to third data buses connected to the DSP;
A first memory connected to the first and second address buses and the first and second data buses;
A second memory connected to the first and third address buses and the first and third data buses;
The address generator can generate a first address output to the first address bus, a second address output to the second address bus, and a third address output to the third address bus. so,
The CPU can read the first data designated by the first address signal via the first data bus,
The DSP can read the second data from the first memory specified by the second address, and can read the third data from the second memory specified by the third address,
The microprocessor, wherein the DSP is capable of performing arithmetic processing using the second data and the third data. In claim 7,
The CPU is
An address register;
An address output unit for generating the address from the start address to the end address by outputting the value in the address register to the second or third address bus and repeatedly updating the value in the address register And a microcomputer. In claim 7,
The microcomputer includes an address output circuit for supplying the second and third addresses to the second and third address buses. In claim 9,
The address output circuit includes a first address buffer connected to the second address bus, a second address buffer connected to the third address bus, and address information to be supplied to the first and second address buffers. And a computing means for computing. In claim 7,
The CPU generates a control signal for controlling the DSP by decoding an instruction included in the first data,
The microcomputer, wherein the address generator generates the second address or the third address in response to the control signal. A central processing unit;
A digital signal processing unit operating in synchronization with the central processing unit;
First to third address buses connected to the central processing unit;
A first data bus connected to the central processing unit and the digital signal processing unit;
Second and third data buses connected to the digital signal processing unit;
A first memory connected to the first and second address buses and the first and second data buses;
A second memory connected to the first and third address buses and the first and third data buses;
The central processing unit obtains first data specified by a first address signal via an interface circuit connected to the first address bus and the first data bus;
The central processing unit includes address supply means capable of supplying second and third address signals for accessing the first and second memories in parallel to the second and third address buses, respectively. ,
The digital signal processing unit includes first and second data for receiving the data output from the first and second memories according to the second and third address signals via the second and third data buses, respectively. A microcomputer comprising second data buffer means. In claim 12,
The central processing unit includes an instruction register that stores an instruction, and an instruction decoding circuit that decodes the instruction stored in the instruction register and supplies a control signal based on the decoding result;
The address supply means supplies the second and third address signals to the corresponding second and third address buses in response to the control signal,
The digital signal processing unit includes first and second data buffer means for taking in the second and third data output from the first and second memories via the corresponding second and third data buses. A microcomputer comprising: a multiplier capable of calculating the second and third data supplied from the first and second data buffer means; and an arithmetic logic operation means. In claim 13,
The digital signal processing unit includes a decoding circuit capable of supplying an internal control signal for controlling the multiplier and arithmetic logic means in response to a control signal output from the instruction decoding circuit. A microcomputer characterized by. In claim 14,
The microcomputer according to claim 1, wherein the central processing unit includes a general-purpose register in which the second and third address signals are stored. CPU,
A DSP that operates according to the CPU and includes a multiplier;
First to third address buses to which addresses are selectively supplied from the CPU;
A first data bus connected to the CPU and the DSP;
Second and third data buses connected to the DSP;
A first memory connected to the first and second address buses and the first and second data buses and accessed by an address supplied from the CPU;
A second memory connected to the first and third address buses and the first and third data buses and accessed by an address supplied from the CPU;
The CPU outputs an address signal to the first address bus, fetches an instruction from the first data bus, and supplies a first control signal for controlling a DSP operation to the DSP based on the fetched instruction. Is possible,
The CPU generates an address signal for outputting data held in at least one of the first memory and the second memory to the second data bus or the third data bus based on the fetched instruction, and generates the generated address A signal can be output to at least one of the second address bus and the third address bus;
The microcomputer according to claim 1, wherein the DSP is capable of executing arithmetic processing using data acquired from at least one of the second data bus or the third data bus based on the first control signal.

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