JP2005317948A - Reference voltage generating circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a reference voltage generating circuit that employs a new resistor, indicating a stabler resistor value with respect to changes in the temperature of the environment, thereby outputting the reference voltage Vref of stabler values to temperature changes. <P>SOLUTION: In the reference voltage generating circuit, including a resistive dividing circuit containing, a plurality of resistors connected in series, wherein the reference voltage generating circuit is particularly a reference voltage generating circuit of type that countervails the mutual positive and negative temperature coefficients, by combining circuits having the positive and negative temperature coefficients to the changes in temperature of the environment; and particularly, it is as the resistance dividing circuit, comprising a plurality of the resistors connected between gates of first MOSFETs connected to first power supply circuits, between the drains and the grounds of the first MOSFETs and between a source and a power supply voltage Vcc, in a reference voltage generating circuit that employs a source follower circuit which regulates the gradients of negative temperature coefficients in the voltages outputted by the first power supply source, a plurality of the resistors comprise thin metallic films. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a technique for stabilizing the output of a reference voltage generation circuit used for a battery-powered mobile phone or the like.

The threshold value of a field effect transistor (hereinafter referred to as FET) varies depending on the environmental temperature. Therefore, a combination of a plurality of field effect transistors having different conductivity type gates and a circuit that outputs a first voltage (hereinafter referred to as Vpn) having a negative temperature coefficient with respect to a change in environmental temperature has the same conductivity. A circuit that outputs a second voltage having a positive temperature coefficient (hereinafter referred to as Vnn) by combining a plurality of field effect transistors having gates with different impurity concentrations, which are doped, is provided. A reference voltage generation circuit that outputs a stable reference voltage Vref regardless of a change in environmental temperature by adjusting the temperature coefficient of the voltage and adding the adjusted first voltage and second voltage is known. . A reference voltage generation circuit applying such a principle of work function difference between gates is disclosed in, for example, Patent Document 1 below. Hereinafter, the process of flattening the gradient of the temperature coefficient is referred to as temperature characteristic compensation.
JP 2001-284464 A

  FIG. 15A is a diagram showing the configuration of the reference voltage generation circuit 110 using the principle of the work function difference between the gates. This circuit is composed of p-channel FETs 101 to 105 and resistors 106 and 107. The FETs 101, 102, 104, and 105 have the same substrate and channel-doped impurity concentrations, are formed in the n-well of the p-type substrate, and the substrate potential of each transistor is set to the same value as the source potential.

  The FET 101 has an n-type gate doped with high-concentration impurities (hereinafter simply referred to as “high-concentration n-type gate”), and the FET 102 has a p-type gate doped with high-concentration impurities (hereinafter simply referred to as “high concentration”). p-type gate). The ratio S = W / L between the channel width W and the channel length L of the FET 101 and the FET 102 is set to the same value.

  The FET 104 has a high-concentration p-type gate, and the FET 105 has a p-type gate doped with a low-concentration impurity (hereinafter simply referred to as a low-concentration p-type gate). The ratio S = W / L between the channel width W and the channel length L of the FET 104 and FET 105 is set to the same value.

  A potential is applied to the gate of the FET 101 from a FET 103 having a high-concentration p-type gate and a source follower circuit including a resistance dividing circuit including two resistors 106 and 107 connected in series. The gate of the FET 102 and the gate of the FET 103 are connected to each other. The FET 103 is connected between the source and the gate. The gate of the FET 101 is connected to the connection point between the source of the FET 103 and the resistor 106 (point P10 representing the potential V10 in the figure). The drain of the FET 103 is connected to the gate of the FET 105.

  The FET 102 is connected between the source and the gate, functions as a constant current source, and allows the same current to flow through the FETs 101 connected in series. Thereby, the source-gate potential of the FET 101 obtained by subtracting the potential V10 from the power supply voltage Vcc becomes Vpn (= Vcc-V10). V11 is represented by {(resistance value of the resistor 107) / (resistance value of the resistor 106)} × Vpn.

  The FET 104 is connected between the source and the gate, functions as a constant current source, and allows the same current to flow through the FET 105 connected in series. Thus, when the source-gate potential of the FET 105 is expressed as Vnn, the source potential V12 of the FET 105 is V11 + Vnn = {(resistance value of the resistor 107) / (resistance value of the resistor 106)} × Vpn + Vnn (= Vref). It is represented by

  The FET 101 and the FET 102 connected in series constitute a first power supply circuit having a negative temperature coefficient with respect to a change in environmental temperature. On the other hand, the FET 104 and FET 105 connected in series constitute a second power supply circuit having a positive temperature coefficient with respect to a change in environmental temperature. By adjusting the resistance values of the resistors 106 and 107 constituting the resistance dividing circuit in the source follower circuit by, for example, trimming technology, the slope of the negative temperature coefficient is adjusted to cancel the positive and negative temperature coefficients. That is, a circuit that compensates for temperature characteristics and outputs a stable reference voltage Vref against changes in environmental temperature is configured.

  In addition to the values of the resistance 106 and the resistance 107, the gradient of the temperature coefficient of each circuit includes the high concentration n-type gate included in the FET 101, the high concentration p-type gate included in the FETs 102, 103, and 104, and the FET 105. It can be adjusted by changing the impurity concentration of the low-concentration p-type gate provided.

  FIG. 15B is a diagram showing a configuration of a reference voltage generation circuit 120 different from the reference voltage generation circuit 110 described above. The reference voltage generation circuit 120 includes p-channel FETs 121 to 123, FET 126 and FET 127, and resistors 124 and 125. The FETs 121, 122, 126, and 127 have the same substrate and channel dope impurity concentrations, are formed in the n-well of the p-type substrate, and the substrate potential of each transistor is set to the same value as the source potential.

  The FET 121 has a high concentration n-type gate, and the FET 122 has a high concentration p-type gate. The ratio S = W / L between the channel width W and the channel length L of the FET 121 and the FET 122 is set to the same value.

  The FET 126 has a high concentration p-type gate, and the FET 127 has a low concentration p-type gate. The ratio S = W / L between the channel width W and the channel length L of the FET 126 and FET 127 is set to the same value.

  A potential is applied to the gate of the FET 121 from a source follower circuit including a FET 123 having a high-concentration p-type gate and a resistance dividing circuit including two resistors 124 and 125 connected in series. The gate of the FET 122 and the gate of the FET 123 are connected to each other. The FET 123 is connected between the source and the gate. The gate of the FET 121 is connected to the connection point between the source of the FET 123 and the resistor 125 (point P13 representing the potential V13 in the figure). A contact P15 between the resistor 124 and the resistor 125 and the gate of the FET 126 are connected.

  The FET 122 is connected between the source and the gate, functions as a constant current source, and allows the same current to flow through the FETs 121 connected in series. Thereby, the source-gate potential of the FET 121 obtained by subtracting the potential V13 from the power supply voltage Vcc becomes Vpn (= Vcc−V13). V14 is represented by Vcc − {(resistance value of the resistor 124) × {(resistance value of the resistor 124) + (resistance value of the resistor 125)} × Vpn.

  The FET 126 is connected between the source and gate, functions as a constant current source, and allows the same current to flow through the FET 127 connected in series. Thus, when the source-gate potential of the FET 127 is expressed as Vnn, the source potential V15 of the FET 127 is Vcc−V14 + Vnn = {(resistance value of the resistor 124) / (resistance value of the resistor 124 + value of the resistor 125). } × Vpn + Vnn (= Vref).

  The FET 121 and the FET 122 connected in series constitute a first power supply circuit having a negative temperature coefficient with respect to a change in environmental temperature. On the other hand, the FET 126 and the FET 127 connected in series constitute a second power supply circuit having a positive temperature coefficient with respect to a change in environmental temperature. The slope of the negative temperature coefficient is adjusted by adjusting the resistance values of the resistor 124 and the resistor 125 constituting the resistor dividing circuit in the source follower circuit, for example, by trimming technology, that is, the temperature characteristic is compensated. A circuit that outputs a stable reference voltage Vref against changes in environmental temperature is configured. In addition to the values of the resistors 124 and 125, the gradient of the temperature coefficient of each circuit is the impurity concentration of the high-concentration p-type gate included in the FET 122 and the low-concentration n-type gate included in the FET 127. Can be adjusted by changing.

  When the reference voltage generation circuit 110 (hereinafter simply referred to as the circuit 110) and the reference voltage generation circuit 120 (hereinafter simply referred to as the circuit 120) are compared, the FET 101 and the FET 102 of the circuit 110, and the FET 121 and the FET 122 of the circuit 120 are In terms of characteristics, the first-stage circuit, the FET 103 and the resistors 106 and 107 of the circuit 110, and the second-stage circuit formed of the FET 123 and the resistors 124 and 125 of the circuit 120 are both in terms of characteristics. There is no difference in the circuit. The potential difference between both ends of the resistor 106 of the circuit 110 and the voltage difference between both ends of the resistor 124 and the resistor 125 of the circuit 120 are Vpn, and the drain-source voltage Vds1 of the FET 101 of the circuit 110 and the FET 121 of the circuit 120 is Vpn + Vgs (the source-gate voltage of the FET 103 of the circuit 110 and the FET 123 of the circuit 120).

  At this time, the drain-source voltage Vds2 of the FET 102 of the circuit 110 and the FET 122 of the circuit 120 is obtained by Vds2 = Vcc−Vds1. From the above equations, it can be seen that only the drain-source voltage Vds2 of the FET 102 of the circuit 110 and the FET 122 of the circuit 120 is affected by the Vcc fluctuation.

  17A and 17B are diagrams showing the Vg-Id characteristics of the FET 101 and the FET 102 of the reference voltage circuit 110 when Vcc fluctuates. When the power supply voltage Vcc increases, the Vg-Id characteristic of the FET 102 changes, and Vpn increases by ΔVpn. Although not shown, the Vg-Id characteristics of the FET 121 and the FET 122 of the reference voltage generation circuit 120 are the same, and when the power supply voltage Vcc increases, Vpn increases by ΔVpn.

  On the other hand, the third stage circuit composed of the FET 104 and the FET 105 of the reference voltage generation circuit 110 and the third stage circuit composed of the FET 126 and the FET 127 of the reference voltage generation circuit 120 have the constant currents of the FET 104 and the FET 126, respectively. Vnn is generated between the source and gate voltage of the FET 104 and FET 126 and the source and gate voltage of the FET 105 and FET 127, whereas the source and gate voltage of the FET 104 is Vgs = 0, whereas the FET 126 Is specified by Vgs = (resistance value of resistor 124) / {(resistance value of resistor 124) + (resistance value of resistor 125)} × Vpn.

  Therefore, Vpn fluctuates in any of the reference voltage generation circuits 110 and 120, but the fluctuation of Vpn affects the constant current source of the third-stage circuit as shown in FIG. Only the voltage generation circuit 120 is provided. If Vgs of the constant current source fluctuates, the operating point fluctuates, causing fluctuations in Vnn. That is, when the power supply voltage Vcc varies, the reference voltage generation circuit 110 varies only by Vpn, but the reference voltage generation circuit 120 varies both Vpn and Vnn. As described above, the more stable circuit is the reference voltage generation circuit 110 shown in FIG.

  FIGS. 16A and 16B show changes in Vref (hereinafter referred to as input stability) with respect to fluctuations in the power supply voltage Vcc of the reference voltage generation circuits 110 and 120, and fluctuations in Vref with respect to temperature fluctuations (hereinafter referred to as temperature characteristics). Show). The ideal value of the temperature characteristic is the same for the reference voltage generation circuits 110 and 120. The input stability indicates the stability of the value of the output reference voltage Vref with respect to fluctuations in the value of the power supply voltage Vcc. The more stable the reference voltage Vref, the closer to the ideal value. And It is assumed that the temperature characteristic with respect to the environmental temperature shows a value closer to the ideal value as the inclination of the temperature coefficient is flatter. In the figure, the input stability and temperature characteristics of the circuits 110 and 120 when polycrystalline silicon is used for the resistor are represented by ◆, and the ideal value is represented by ▲.

  In the ideal case where the resistance is indicated by a symbol ▲, the input stability is more stable in the reference voltage generation circuit 110 than in the reference voltage generation circuit 120, and the temperature characteristics are as follows for the reference voltage generation circuit 110 and the reference voltage generation circuit 120. It is equivalent. However, in the case of a resistor using polycrystalline silicon, as indicated by the asterisk, the result of the experiment in which the reference voltage generation circuit 110 is significantly inferior to the ideal value from the reference voltage generation circuit 120 in both the input stability and the temperature characteristics. was gotten.

  The reason is considered as follows. In the case of a resistor using polycrystalline silicon, the carrier density inside the polycrystalline silicon is caused by a potential difference between a conductor such as a metal wiring in contact with one surface of the polycrystalline silicon and a substrate insulator or well in contact with the other surface. Affected, which changes the resistance value.

  For example, when both the resistance using polycrystalline silicon and the potential of the conductor connected to the resistance are set to 0 v, there is no potential difference between them, so the resistance value of the resistance using polycrystalline silicon is the original value. Indicates.

  Next, when the potential of the polycrystalline silicon is increased from 0 v to 1 v while the potential of the conductor is kept at 0 v, the potential difference (ΔV) to the conductor becomes −1 V and becomes negative based on the resistance using the polycrystalline silicon. When the resistance using polycrystalline silicon is n-type, a depletion layer is generated in the resistance, and the resistance value of the resistance using the polycrystalline silicon is increased.

  On the other hand, under a bias condition in which ΔV is positive, an accumulation layer is generated in the resistor, so that the resistance value of the resistor using the polycrystalline silicon is small.

  18A shows the resistances 106 and 107 of the reference voltage generation circuit 110 and the ΔV of the n well, and FIG. 18B shows the resistances 124 and 125 of the reference voltage generation circuit 120 and the ΔV of the n well. ΔV with respect to the n-well, which is a conductor in contact with the resistors 106, 124, and 125, is not affected by the fluctuation of Vcc, but the resistance 107 of the resistor 107 varies with the fluctuation of the power supply voltage Vcc. That is, when the power supply voltage Vcc varies, the resistance value of the resistor 107 also varies, and the potential V11 represented by (resistance value of the resistor 107) / (resistance value of the resistor 106) × Vpn varies. Thus, the value of the reference voltage Vref also varies. In the case of a resistor using polycrystalline silicon, the reference voltage generation circuit 110 is far inferior to the ideal value from the reference voltage generation circuit 120 as shown in FIG.

  On the other hand, the depletion layer and the accumulation layer generated inside these resistors have temperature dependency. This temperature dependence increases as ΔV increases. Among the resistors 106, 107, 124, and 125, ΔV of the resistor 107 is the largest, so that the reference voltage generation circuit 110 is more ideal than the reference voltage generation circuit 120 as shown in FIG. The result is greatly inferior to the value.

  It is an object of the present invention to provide a highly efficient reference voltage generation circuit that exhibits input stability and temperature characteristics close to ideal values.

  A first reference voltage generation circuit according to the present invention is a reference voltage generation circuit including a resistance dividing circuit composed of a plurality of resistors connected in series, wherein the plurality of resistors are formed of a metal thin film. To do.

A second reference voltage generation circuit according to the present invention includes a plurality of field effect transistors having gates of different conductivity types in the first reference voltage generation circuit according to the present invention, and has a negative temperature with respect to a change in environmental temperature. A first power supply circuit that outputs a voltage having a coefficient; a first field effect transistor having a gate connected to the first power supply circuit; a drain and a ground of the first field effect transistor; and a source and a power supply voltage. A source follower circuit that includes a resistance divider circuit composed of the plurality of resistors connected in series with Vcc, and that adjusts the slope of the negative temperature characteristic of the voltage output from the first power supply circuit; and the source Consisting of a plurality of field-effect transistors connected to a follower circuit and having gates of the same conductivity type and different impurity concentrations, a positive temperature coefficient with respect to environmental temperature changes A power supply circuit for generating a voltage having a second power supply circuit for outputting a voltage obtained by adding the output of the source follower circuit, to compensate for the inclination of the temperature coefficient,
Have

  According to a third reference voltage generating circuit of the present invention, in the first or second reference voltage generating circuit of the present invention, the metal thin film is made of CrSi.

  According to a fourth reference voltage generating circuit of the present invention, in the third reference voltage generating circuit of the present invention, the resistor formed of the metal thin film is provided on the wiring pattern and the wiring pattern. An insulating film having a connection hole is provided at a connection portion of the pattern, and the metal thin film is ohmic-connected to the connection portion of the wiring pattern through the connection hole.

  According to a fifth reference voltage generating circuit of the present invention, in the fourth reference voltage generating circuit of the present invention, the metal thin film contacts the natural oxide film on the inner surface of the connection hole with which the metal thin film contacts, and the bottom of the connection hole. The natural oxide film on the surface of the wiring pattern is removed.

  According to a sixth reference voltage generating circuit of the present invention, in the fourth or fifth reference voltage generating circuit of the present invention, a refractory metal film is interposed between the metal thin film and the connection portion of the wiring pattern. It is characterized by that.

  According to a seventh reference voltage generation circuit of the present invention, in the fourth or fifth reference voltage generation circuit of the present invention, the wiring pattern includes a metal material pattern and a refractory metal formed on the metal material pattern. It is characterized by being comprised with the film | membrane.

  An eighth reference voltage generation circuit according to the present invention is the fourth or fifth reference voltage generation circuit according to the present invention, wherein the wiring pattern includes a polysilicon pattern and a refractory metal formed on the polysilicon pattern. It is characterized by being comprised with the film | membrane.

  A ninth reference voltage generation circuit according to the present invention is the reference voltage generation circuit according to any one of the first to eighth aspects of the present invention, wherein the first power supply circuit includes a high-concentration n-type gate field effect transistor, A high-concentration p-type gate field effect transistor is connected in series.

  A tenth reference voltage generation circuit according to the present invention is the reference voltage generation circuit according to any one of the first to eighth aspects of the present invention, wherein the second power supply circuit includes a field effect transistor having a high concentration p-type gate, A low-concentration p-type gate field effect transistor is connected in series.

  An eleventh reference voltage generation circuit according to the present invention is the reference voltage generation circuit according to any one of the first to eighth aspects of the present invention, wherein the second power supply circuit includes a high-concentration n-type gate field effect transistor, A low-concentration n-type gate field effect transistor is connected in series.

  Since the first reference voltage generating circuit of the present invention uses a metal thin film as a resistor, a depletion layer and a power storage layer are less likely to be generated compared to a resistor using polycrystalline silicon, and the reference voltage is stable against changes in environmental temperature. The stability of the output reference voltage can be improved with respect to the degree of change in the circuit drive voltage.

  The second reference voltage generation circuit of the present invention combines a circuit having positive and negative temperature coefficients with respect to a change in environmental temperature to cancel each other's positive and negative temperature coefficient slopes, that is, compensates for temperature characteristics. In particular, a reference voltage generating circuit of the above type, in particular, a field effect transistor having a gate connected to the first power supply circuit, a drain and a ground of the field effect transistor, and a source and a power supply voltage Vcc Including a resistance divider circuit composed of two resistors connected in series, and using a source follower circuit that adjusts the slope of the negative temperature coefficient of the voltage output from the first power supply circuit, By using the resistance formed by the metal thin film of the reference voltage generating circuit having the above configuration, a depletion layer and a power storage layer are less likely to be generated compared to a resistance using polycrystalline silicon. Stability and the reference voltage that, relative to the potential change of the circuit drive voltage, the stability of the reference voltage output can be greatly improved.

  The third reference voltage generation circuit of the present invention uses polycrystalline silicon by adopting a resistance using CrSi, which is a metal thin film, as the resistance in the first or second reference voltage generation circuit of the present invention. Compared to resistors, depletion layers and power storage layers are less likely to occur, and the stability of the reference voltage against changes in environmental temperature and the stability of the output reference voltage against changes in the circuit drive voltage potential can be greatly improved. it can.

  According to a fourth reference voltage generation circuit of the present invention, in the third reference voltage generation circuit of the present invention, the resistor is provided on the wiring pattern and the wiring pattern, and a connection hole is provided in a connection portion of the wiring pattern. By being composed of an insulating film and CrSi that is ohmic-connected to the connection portion of the wiring pattern through a connection hole, a depletion layer and a power storage layer are less likely to be generated compared to a resistor using polycrystalline silicon. The stability of the output reference voltage can be increased with respect to the stability of the reference voltage with respect to the change and the potential change of the circuit drive voltage.

  According to a fifth reference voltage generating circuit of the present invention, in the fourth reference voltage generating circuit of the present invention, the resistance further includes an inner surface of a connection hole in contact with CrSi and a wiring pattern surface in which CrSi contacts through the connection hole. Since the natural oxide film is removed, the fluctuation of the resistance value due to the growth of the oxide film over time can be suppressed. As a result, the stability of the reference voltage to be output with respect to the change in the environmental voltage and the potential change in the circuit drive voltage can be improved over time, compared to the resistance using polycrystalline silicon. Can be increased.

  The sixth reference voltage generation circuit of the present invention is the fourth and fifth reference voltage generation circuits of the present invention, wherein a refractory metal film is interposed between the metal thin film and the connection portion of the wiring pattern, It is possible to use a resistance having a predetermined resistance value that does not fluctuate due to heat treatment performed during the manufacturing process and heat generated during actual use. As a result, the stability of the reference voltage against the change in the environmental temperature and the change in the potential of the circuit drive voltage over time, compared to the resistance using polycrystalline silicon, Can be increased.

  A seventh reference voltage generation circuit of the present invention is the reference voltage generation circuit according to any one of the fourth to sixth of the present invention, wherein the wiring pattern is a metal material pattern and a refractory metal formed on the upper surface of the metal material pattern. Since the film is composed of a film, it is possible to use a resistance having a predetermined resistance value in which the resistance value does not fluctuate due to heat treatment performed during the manufacturing process and heat generated during actual use. Compared to resistors that use polycrystalline silicon, the stability of the reference voltage against changes in the environmental temperature and the stability of the reference voltage that is output against changes in the circuit drive voltage are increased over time. Can do.

  The eighth reference voltage generation circuit according to the present invention is the fourth to seventh reference voltage generation circuit according to the present invention, wherein the wiring pattern is a polysilicon pattern and a high melting point formed on the upper surface of the polysilicon pattern. Since it is composed of a metal film, it is possible to use a resistance having a predetermined resistance value in which the resistance value does not fluctuate due to heat treatment performed during the manufacturing process and heat generated during actual use. As a result, the stability of the reference voltage to be output with respect to the change in the environmental voltage and the potential change in the circuit drive voltage can be improved over time, compared to the resistance using polycrystalline silicon. Can be increased.

  A ninth reference voltage generation circuit according to the present invention is the reference voltage generation circuit according to any one of the first to eighth aspects of the present invention. The second power supply circuit includes a high-concentration p-type gate field effect transistor, a low concentration p A series-connected field-effect transistor with a gate type, which uses a metal thin film as a resistor. Compared to a resistor using polycrystalline silicon, a depletion layer and a storage layer are less likely to occur, and a standard for changes in environmental temperature. The stability of the output reference voltage can be significantly improved with respect to the voltage stability and the potential change of the circuit drive voltage.

  A tenth reference voltage generation circuit according to the present invention is the reference voltage generation circuit according to any one of the first to eighth aspects according to the present invention. The second power supply circuit includes a high-concentration p-type gate field effect transistor and a low-concentration p. Since a metal thin film is used for the resistor, a depletion layer and a storage layer are less likely to occur than a resistor using polycrystalline silicon, and the reference voltage against changes in environmental temperature is reduced. The stability of the output reference voltage can be significantly improved with respect to the stability and the potential change of the circuit drive voltage.

  An eleventh reference voltage generation circuit according to the present invention is the reference voltage generation circuit according to any one of the first to eighth aspects according to the present invention. The second power supply circuit includes a field effect transistor having a high concentration n-type gate, a low concentration n Since a metal thin film is used for the resistor, a depletion layer and a storage layer are less likely to occur than a resistor using polycrystalline silicon, and the reference voltage against changes in environmental temperature is reduced. The stability of the output reference voltage can be significantly improved with respect to the stability and the potential change of the circuit drive voltage.

(1) Embodiment 1
FIG. 1 is a diagram showing a configuration of a reference voltage generation circuit 100 according to the first embodiment. The reference voltage generation circuit 100 uses a new resistor instead of the resistors 106 and 107 using polycrystalline silicon used in the conventional reference voltage generation circuit 110 described with reference to FIG. Resistors 108 and 109 showing stable resistance values with respect to changes in temperature are used. The components other than the resistors 108 and 109 are the same as those of the conventional reference voltage generation circuit 110, and are denoted by the same reference numerals.

  The reference voltage generation circuit 100 includes p-channel field effect transistors (hereinafter simply referred to as FETs) 101 to 105 and resistors 108 and 109. The FETs 101, 102, 104, and 105 have the same substrate and channel-doped impurity concentrations, are formed in the n-well of the p-type substrate, and the substrate potential of each transistor is set to the same value as the source potential.

  The FET 101 has an n-type gate doped with high-concentration impurities (hereinafter simply referred to as “high-concentration n-type gate”), and the FET 102 has a p-type gate doped with high-concentration impurities (hereinafter simply referred to as “high concentration”). p-type gate). The ratio S = W / L between the channel width W and the channel length L of the FET 101 and the FET 102 is set to the same value.

  The FET 104 has a high-concentration p-type gate, and the FET 105 has a p-type gate doped with a low-concentration impurity (hereinafter simply referred to as a low-concentration p-type gate). The ratio S = W / L between the channel width W and the channel length L of the FET 104 and FET 105 is set to the same value.

  A potential is applied to the gate of the FET 101 from a FET 103 having a high-concentration p-type gate and a source follower circuit including a resistance dividing circuit including two resistors 108 and 109 connected in series. The gate of the FET 102 and the gate of the FET 103 are connected to each other. The FET 103 is connected between the source and the gate. The gate of the FET 101 is connected to a connection point between the source of the FET 103 and the resistor 108 (a point P1 representing the potential V1 in the figure). The drain of the FET 103 is connected to the gate of the FET 105.

  The FET 102 is connected between the source and the gate, functions as a constant current source, and allows the same current to flow through the FETs 101 connected in series. As a result, the source-gate potential of the FET 101 obtained by subtracting the potential V1 from the power supply voltage Vcc is Vpn (= Vcc-V1). V2 is represented by {(resistance value of the resistor 109) / (resistance value of the resistor 108)} × Vpn.

  The FET 104 is connected between the source and the gate, functions as a constant current source, and allows the same current to flow through the FET 105 connected in series. Thus, when the source-gate potential of the FET 105 is expressed as Vnn, the source potential V3 of the FET 105 is V2 + Vnn = {(resistance value of the resistor 109) / (resistance value of the resistor 108)} × Vpn + Vnn (= Vref). It is represented by

  The FET 101 and the FET 102 connected in series constitute a first power supply circuit having a negative temperature coefficient with respect to a change in environmental temperature. On the other hand, the FET 104 and FET 105 connected in series constitute a second power supply circuit having a positive temperature coefficient with respect to a change in environmental temperature. By adjusting the resistance values of the resistors 108 and 109 constituting the resistance divider circuit in the source follower circuit by, for example, trimming technology, the slope of the negative temperature coefficient is adjusted to cancel the positive and negative temperature coefficients. That is, a circuit that compensates for temperature characteristics and outputs a stable reference voltage Vref against changes in environmental temperature is configured.

  In addition to the values of the resistance 108 and the resistance 109, the gradient of the temperature coefficient of each circuit includes the high concentration n-type gate included in the FET 101, the high concentration p-type gate included in the FETs 102, 103, and 104, and the FET 105. It can be adjusted by changing the impurity concentration of the low-concentration p-type gate provided.

(2) Description of resistors 108 and 109 The resistors 108 and 109 used in the reference voltage generation circuit 100 are each provided with a wiring pattern and a wiring pattern on the wiring pattern. It has a semiconductor structure composed of an insulating film having a connection hole in the connection portion and a metal thin film that is ohmic-connected to the connection portion of the wiring pattern through the connection hole. The resistors 108 and 109 having the above-described configuration not only show a stable resistance value against a change in environmental temperature but also the same environment as compared with a resistor made of polycrystalline silicon by using a metal thin film as a resistor. Its value stabilizes under temperature conditions. This is because even if the difference between the bias voltage applied to the conductor adjacent to the resistor and the bias voltage applied to the resistor itself is large, a depletion layer or an accumulation layer is generated compared to a resistor made of polycrystalline silicon. This is considered to be one of the causes because it is difficult and the resistance value fluctuates little.

  The configuration, manufacturing method, and resistance characteristics of the resistors 108 and 109 are all the same. Hereinafter, the resistor 108 will be described. FIGS. 2A to 2F and FIGS. 3A to 3E are diagrams for explaining the manufacturing procedure of the resistor 108. FIG. FIG. 3E shows the configuration of the resistor 108 that is finally manufactured. In FIG. 3E, display of circuit elements (transistors and capacitors) other than those related to the description is omitted.

  First, referring to FIG. 3E, the configuration of the resistor 108 which is the final product will be briefly described, and then FIGS. 2A to 2F and FIGS. 3A to 3E are sequentially referred to. Now, a specific method for manufacturing the resistor 108 will be described. Further, after the description of the manufacturing method, the characteristics of the resistor 108, another manufacturing method, and advantages of using the manufacturing method will be described.

  An element isolation oxide film 2 is formed on a part of the silicon substrate 1. A first interlayer insulating film (underlying insulating film) 3 made of a BPSG film or a PSG (phospho-silicate glass) film is formed on the silicon substrate 1 including the formation region of the element isolation oxide film 2. On the first interlayer insulating film 3, a wiring pattern 6 including a metal material pattern 4 and a refractory metal film 5 formed on the surface of the metal material pattern 4 is formed. The metal material pattern 4 is formed of, for example, an AlSiCu film. The refractory metal film 5 is formed of, for example, a TiN film and functions as a barrier film that also serves as an antireflection film.

  An opening 7 is provided in the wiring pattern 6 on the element isolation oxide film 2. A plasma CVD oxide film 8, an SOG (spin on glass) film 9, and a plasma CVD oxide film 10 are formed in this order on the wiring pattern 6 including the opening 7. Hereinafter, these three films are referred to as a second interlayer insulating film 11. In the second interlayer insulating film 11, connection holes 12 and 13 are provided at locations that are both ends of the metal thin film resistor, that is, at the outer peripheral portion immediately above the opening 7.

  On the second interlayer insulating film (insulating film) 11, a CrSi thin film resistor (metal thin film resistor) extends from the region between the connection holes 12 and 13 to the inner walls of the connection holes 12 and 13 and the wiring pattern 6. ) 15 is formed. Both ends of the CrSi thin film resistor 15 are ohmically connected to the wiring pattern 6 in the connection holes 12 and 13.

  A silicon oxide film 16 and a silicon nitride film 17 are sequentially formed as a passivation film 18 on the second interlayer insulating film 11 including the formation region of the CrSi thin film resistor 15.

  Hereinafter, the manufacturing method (steps S1 to S11) of the resistor 108 will be described in order with reference to FIGS. 2A to 2F and FIGS. 3A to 3E.

(Step S1)
First, reference is made to FIG. For example, on the wafer-like silicon substrate 1 on which the formation of the element isolation oxide film 2 and transistor elements (not shown) is completed using an atmospheric pressure CVD apparatus, the film thickness is 8000 mm made of a BPSG film or a PSG film. A first interlayer insulating film 3 is formed. Thereafter, a heat treatment such as reflow is performed to smooth the surface of the first interlayer insulating film 3.

(Step S2)
Next, refer to FIG. For example, using a DC magnetron sputtering apparatus, a wiring metal film 20 having a thickness of about 5000 mm made of an AlSiCu film is formed on the first interlayer insulating film 3, and subsequently having a thickness of about 800 mm as an antireflection film. A refractory metal (TiN) film 21 is formed.

  As shown in FIG. 2C, the wiring metal film 20 and the refractory metal film 21 are processed into the metal material pattern 4 and the refractory metal film 5 constituting the wiring pattern 6 by subsequent processing. The refractory metal film 21 also functions as a barrier film for stabilizing the value of contact resistance with the metal thin film resistor. For this reason, the refractory metal film 21 is preferably formed continuously in the same vacuum after the formation of the wiring metal film 20.

(Step S3)
Reference is made to FIG. A well-known photolithography process and an etching process are performed to pattern (partially remove) the refractory metal film 21 and the wiring metal film 20 to form the opening 7, and the metal wiring pattern 4 and the refractory metal film. 5 is formed. Since the refractory metal film 21 functions as an antireflection film during the patterning, the resist pattern used for defining the formation area of the wiring pattern 6 can be minimized and thinned.

  At this stage, the metal thin film resistor (CrSi thin film 14 to be described later) is not yet formed, and the base film of the wiring pattern 6 is formed of the first interlayer insulating film 3. Therefore, the patterning of the refractory metal film 21 and the wiring metal film 20 can be sufficiently over-etched by the dry etching technique, and the circuit can be miniaturized as compared with the case of using the wet etching technique. .

(Step S4)
Reference is made to FIG. For example, a plasma CVD oxide film 8 having a thickness of 6000 mm is formed on the first interlayer insulating film 3 including the formation region of the wiring pattern 6 by a known plasma CVD method.

(Step S5)
Reference is made to FIG. A coating process and an etch-back process for SOG, which are well-known techniques, are performed to form an SOG film 9 on the plasma CVD oxide film 8 and planarize it, and then diffusion of components from the SOG film 9 is prevented. A plasma CVD oxide film 10 having a thickness of about 2000 mm is formed. Hereinafter, the plasma CVD oxide film 8, the SOG film 9, and the plasma CVD oxide film 10 are referred to as a second interlayer insulating film 11.

(Step S6)
Reference is made to FIG. A resist pattern 22 is formed on the second interlayer insulating film 11 at locations corresponding to both ends of the metal thin film resistor, that is, on the outer peripheral portion immediately above the opening 7 provided in the wiring pattern 6 by a well-known photolithography technique. Form. Thereafter, two holes 23 and 24 used for providing the two connection holes (12, 13) in the resist pattern 22 are opened.

(Step S7)
Next, refer to FIG. For example, using a well-known parallel plate type plasma etching apparatus, RF power: 700 W (watt), Ar: 500 sccm (standard cc / min), CHF ₃ : 500 sccm, CF ₄ : 500 sccm, pressure: 3.5 Torr (torr) ), The connection holes 12 and 13 are formed using the resist pattern 22 provided with the connection holes 23 and 24 as a mask. The refractory metal film 5 having a thickness of about 600 mm that functions as an antireflection film / barrier layer is left at the bottom of the connection holes 12 and 13. After the connection holes 12 and 13 are formed, the resist pattern 22 is removed.

  After the connection holes 12 and 13 are formed, a by-product removal process caused by an etching process and adhering to the side wall of the connection hole 21 may be performed. Furthermore, in order to improve the step coverage of the metal thin film resistance inside the connection holes 12 and 13, a taper etching process, an etching process combining a wet etching technique and a dry etching technique or the like is adopted, and the connection hole The shape of 12, 13 can also be improved.

  In (Step S7) described above, the etching rate of the refractory metal film 5 can be reduced more than the etching rate of the second interlayer insulating film 11 by optimizing the execution conditions of the plasma etching process. Thereby, the refractory metal film 5 having a sufficient thickness can be left at the bottom even after the connection holes 12 and 13 are formed, while suppressing an increase in the film thickness when the refractory metal film 5 is formed. .

  In addition, the above-described (Step S7) has an advantage that when the connection holes 12 and 13 are formed before the formation of the metal thin film resistor, there are no restrictions due to the thinness of the metal thin film resistor. Thereby, a dry etching technique suitable for circuit miniaturization can be applied to the formation of the connection holes 12 and 13 rather than wet etching.

(Step S8)
Reference is made to FIG. For example, using an Ar sputtering chamber of a multi-chamber sputtering apparatus, a connection hole is formed in a vacuum under conditions of DC bias: 1250 V, Ar: 20 sccm, pressure: 8.5 mTorr (millitorr), and processing time: 20 seconds. An Ar sputter etching process is performed on the surface of the second interlayer insulating film 11 including the insides of 12 and 13. The execution conditions of the Ar sputter etching process are the same as those for removing the thermal oxide film having a thickness of about 50 mm in a 1000 ° C. wet atmosphere. After the treatment, the thickness of the refractory metal film 5 remaining at the bottom of the connection holes 12 and 13 is about 500 mm.

  After the completion of the Ar sputter etching process, a CrSi thin film (metal thin film) 14 used as a resistor is formed while maintaining a vacuum. More specifically, after a silicon wafer is transferred from an Ar sputter etching chamber to a sputter chamber equipped with a CrSi target, a Si / Cr = 80/20 wt% (weight percent) CrSi target is used, and DC power: 0 The treatment is performed under the conditions of 7 kw (kilowatt), Ar: 85 sccm, and treatment time: 9 seconds. With this process, a CrSi thin film 14 having a thickness of about 50 mm is formed on the surface of the second interlayer insulating film 11 including the insides of the connection holes 12 and 13.

  Before the CrSi thin film 14 is formed, by performing an Ar sputter etching process on the second interlayer insulating film 11 including the inside of the connection holes 12 and 13, the inside of the connection holes 12 and 13 can only be purified. In addition, a very small amount of the natural oxide film formed on the surface of the refractory metal film 9 at the bottom of the connection holes 12 and 13 can be removed. Thereby, good ohmic connection between the wiring pattern 6 and the CrSi thin film 14 can be performed.

  Furthermore, by performing the Ar sputter etching process, it is possible to improve the dependency of the CrSi thin film resistor (15) formed by processing the CrSi thin film 14 in a later process on the base film.

(Step S9)
Reference is made to FIG. A resist pattern 16 for defining a formation region of the metal thin film resistor (15) is formed on the CrSi thin film 14 by a well-known photolithography technique. For example, the CrSi thin film resistor 15 is formed by patterning the CrSi thin film 14 using the resist pattern 16 as a mask by an RIE (reactive ion etching) apparatus.

(Step S10)
Reference is made to FIG. After the formation of the CrSi thin film resistor 15, the resist pattern 16 is removed. The CrSi thin film resistor 15 is electrically connected to the wiring pattern 6 inside the connection holes 12 and 13. For this reason, when an ohmic connection is formed on the upper surface of the resistor 108 to be finally manufactured, there is an advantage that it is not necessary to perform a removal process of the metal oxide film on the surface of the CrSi thin film resistor 15.

(Step S11)
Reference is made to FIG. For example, the silicon oxide film 16 and the silicon nitride film 17 are sequentially formed as the passivation film 18 on the second interlayer insulating film 11 including the formation region of the CrSi thin film resistor 15 by plasma CVD.

  The resistor 108 is manufactured by executing the above processes (Step S1) to (Step S11).

  In the manufacturing method of the resistor 108 described above, after the wiring pattern 6 and the connection holes 12 and 13 are formed, the CrSi thin film resistor 15 is formed, and the CrSi thin film resistor 15 and the wiring pattern 6 are ohmically connected inside the connection holes 12 and 13. I do. Employing the manufacturing method has an advantage that it is not necessary to perform patterning using a wet etching technique after patterning the CrSi thin film resistor 15.

  Further, since the contact surface of the CrSi thin film resistor 15 with the wiring pattern 6 is not exposed to the atmosphere, the surface oxide film removal process for the CrSi thin film resistor 15 and the formation of a barrier film for preventing erroneous removal by etching are not performed. In both cases, a stable ohmic connection between the CrSi thin film resistor 15 and the wiring pattern 6 can be obtained. Thereby, it is possible to realize miniaturization of the CrSi thin film resistor 15 and stabilization of the resistance value without particularly increasing the number of steps regardless of the film thickness of the CrSi thin film resistor 15.

  Further, since the refractory metal film 5 functioning as a barrier film is interposed between the CrSi thin film resistor 15 and the metal material pattern 4, variation in the contact resistance value between the CrSi thin film resistor 15 and the wiring pattern 6 can be reduced. Thus, the resistance value can be stabilized and the yield of the resistor 108 as a product can be improved.

  Furthermore, since the refractory metal film 5 also functions as a barrier film and an antireflection film, the number of manufacturing steps and manufacturing costs are reduced and a metal thin film resistor is obtained compared to a conventional manufacturing method in which a barrier film is separately formed. The contact resistance between the CrSi thin film resistor 15 and the wiring pattern 6 can be stabilized.

(3) Characteristics of the resistor 108 A resistor made of polycrystalline silicon has a depletion layer or accumulation layer in the resistor due to the difference between the bias voltage applied to the adjacent conductor and the bias voltage applied to the resistor itself. It is known that the resistance value fluctuates. On the other hand, it is understood that the resistor 108 manufactured by the method of (Step S1) to (Step S11) hardly generates a depletion layer or an accumulation layer under the same conditions and has a small amount of variation in resistance value. It was.

Hereinafter, the characteristics of the resistor 108 manufactured by the above-described methods (Step S1) to (Step S11) will be described with reference to FIGS. FIG. 4 is a graph showing the relationship between the sheet resistance (Ω / μm ² ) of the metal thin film resistor (CrSi thin film resistor 15) included in the resistor 108 and the film thickness (Å). FIG. 5 shows a value (σ / AVE) obtained by dividing the standard deviation (σ) of the sheet resistance of the metal thin film resistor (CrSi thin film resistor 15) at 63 locations in the wafer surface by the average value (AVE). It is a graph which shows the relationship with a CrSi film thickness.

  In order to prepare the graphs shown in FIG. 4 and FIG. 5, a multi-chamber sputtering apparatus was used, and under conditions of DC power: 0.7 kW, Ar: 85 sccm, and pressure: 8.5 mTorr, Si / Cr = 50/50 wt% By adjusting the deposition time for two types of targets (hereinafter referred to as the first target) and 80/20% (hereinafter referred to as the second target), a CrSi thin film having a thickness of 25 to 500 mm A plurality of samples of the resistor 108 having the resistor 15 (four for the first target and five for the second target) were manufactured. For the first target, a sample having a film thickness of 500 mm was not created. 4 and 5, the graph of the first target is indicated by a dotted line, and the graph of the second target is indicated by a solid line.

  Further, for each sample, an Ar sputter etching process (described in step S8) performed before forming the CrSi thin film is performed on each sample using a multi-chamber sputtering apparatus, with a DC bias of 1250 V and Ar: 20 sccm. The test was performed for 160 seconds under the condition of pressure: 8.5 mTorr. The Ar sputter etching process is a process corresponding to removing a thermal oxide film formed in a wet atmosphere at 1000 ° C. by a thickness of about 400 mm.

  In each sample, only the AlSiCu film (metal material pattern 4) having a thickness of 5000 mm is used as the lower wiring pattern 6 connected to the CrSi thin film resistor 15 which is a metal thin film resistor. A structure in which the TiN film of the refractory metal film 5 is not formed is adopted at the bottom.

The sheet resistance (Ω / μm ² ) was measured at 1 V across one resistor 108 out of 20 belt-like patterns having a width of 0.5 μm (micrometer) and a length of 50 μm arranged at intervals of 0.5 μm. This was performed by a two-terminal method in which a current value was measured by applying a voltage of. The plane dimensions of the connection holes 12 and 13 connecting the wiring pattern 6 which is a metal wiring and the CrSi thin film resistor 15 were 0.6 μm × 0.6 μm.

  As shown in FIG. 4, the composition of the first target (Si / Cr = 50/50 wt% (graph indicated by the dotted line)) and the second target (Si / Cr = 80/20% (graph indicated by the solid line)). Regardless, it can be seen that the linearity of the film thickness and the sheet resistance is maintained from a thickness of 200 mm or more to a very thin film thickness of 25 mm. As described above, according to the manufacturing method described above, it is possible to manufacture a thin metal thin film resistor having a minute size that cannot be formed by the conventional technique using the wet etching technique.

  Further, as shown in FIG. 5, when the variation in sheet resistance at 63 locations in the wafer surface is seen, the first target (Si / Cr = 50/50 wt% (shown by a solid line)) and the second target (Si It can be seen that both of / Cr = 80/20% (indicated by a dotted line) are hardly affected by the film thickness and show a stable resistance value. From this, it can be understood that according to the manufacturing method described above, an extremely fine and thin metal thin film resistor (CrSi thin film resistor 15) pattern can be stably formed.

FIG. 6A shows the sheet resistance (Ω / μm ² ) of the CrSi thin film resistor 15 and the base film of the CrSi thin film resistor 15 when the Ar sputter etching process is performed before forming the CrSi thin film resistor 15 as the metal thin film resistor. FIG. 6B is a graph showing the relationship with the Ar sputter etching process after forming the CrSi thin film resistor 15 as the metal thin film resistor. It is a graph which shows. In each graph, the vertical axis represents the sheet resistance (Ω / μm ² ) of the CrSi thin film resistor 15, and the horizontal axis represents the time (hr) that has elapsed since the base film was formed.

When producing the graphs shown in FIGS. 6A and 6B, two silicon wafers of a plasma SiN film formed to a thickness of 2000 mm by a plasma CVD method and a plasma NSG (non-doped silicate glass) film are used. A sample of the resistor 108 in which the CrSi thin film resistor 15 was formed was prepared, and the sheet resistance (Ω / μm ² ) of the CrSi thin film resistor 15 included in the resistor 140 of these two samples was measured by a four-terminal method.

The plasma SiN film of the base film uses a parallel plate type plasma CVD apparatus, and the temperature is 360 ° C., the pressure is 5.5 Torr, the RF power is 200 W, SiH _{4 is} 70 sccm, N _{2 is} 3500 sccm, and NH _{3 is} 40 sccm. Formed with. The plasma NSG film was formed using a parallel plate plasma CVD apparatus under the conditions of temperature: 400 ° C., pressure: 3.0 Torr, RF power: 250 W, SiH ₄ : 16 sccm, N ₂ O: 1000 sccm.

  The CrSi thin film resistor 15 uses a multi-chamber sputtering apparatus, and for a target of Si / Cr = 80/20 wt%, DC power: 0.7 kW, Ar: 85 sccm, pressure: 8.5 mTorr, and deposition time: A film having a thickness of 100 mm was formed under the condition of 13 seconds.

  Samples to be subjected to Ar sputter etching were subjected to Ar sputter etching for 80 seconds under the conditions of DC bias: 1250 V, Ar: 20 sccm, and pressure: 8.5 mTorr using a multi-chamber sputtering apparatus. This is a process corresponding to etching and removing a thermal oxide film formed at 1000 ° C. in a wet atmosphere by 200 mm.

  As shown in FIG. 6B, when the Ar sputter etching process is not performed before the CrSi thin film resistor 15 is formed, the sheet resistance is greatly different due to the difference in the base film (on the SiN film and on the NSG film). I understand. Further, it can be seen that the time elapsed from the formation of the base film to the formation of the CrSi thin film resistor 15 is greatly affected. On the other hand, as shown in FIG. 6A, when the Ar sputter etching process is performed, both the type of the underlying film and the elapsed time hardly affect the sheet resistance characteristics of the CrSi thin film resistor 15. I understand.

  (Step S2) As described in the subsequent stage, after the Ar sputter etching process is performed, the wiring metal film 20 and the refractory metal film 21 are continuously formed in vacuum, whereby the previous Ar sputter etching process is performed. It can be seen that the variation in resistance value caused by the elapsed time from the start and the difference in the undercoat film which varies from product to product can be greatly improved.

  Further, it has been found that the effect of the Ar sputter etching process affects not only the influence of the base but also the stability of the resistance value of the CrSi thin film resistor 15 itself.

  FIG. 7 shows a period of time in which the CrSi thin film resistor 15 of the resistor 108 is formed and then left in the atmosphere at a temperature of 25 ° C. and a humidity of 45%, and the sheet resistance change rate (ΔR / It is a figure which shows the relationship of (R0), a vertical axis | shaft shows (DELTA) R / R0 (%) and a horizontal axis shows leaving time (hour).

  The base film and CrSi thin film resistor of the resistor 108 sample used in the graph of FIG. 7 were formed under the same conditions as the resistor 108 sample used in the graph of FIG. As a sample of the resistor 108, an Ar sputter etching process is not performed at all (a graph 71 indicated by a dotted line shows the characteristics of the sample), and a thermal oxide film having a thickness of 100 mm formed by performing the Ar sputter etching process for 40 seconds. (A graph 72 shown by a solid line shows the characteristics of the sample), and a thermal oxide film having a thickness of 200 mm that can be obtained by executing the Ar sputter etching process for 80 seconds (a graph 73 shown by an alternate long and short dash line) Three types of samples showing the characteristics of the sample) were prepared. Hereinafter, a sample that has not been subjected to the Ar sputter etching process is referred to as an “Ar etch-free” sample, and a sample with a film thickness of 100 mm that has been subjected to the Ar sputter etching process for 40 seconds is referred to as an “Ar etch: 100 mm” sample. A sample having a thickness of 200 mm that has been etched for 80 seconds is referred to as an “Ar etch: 200 mm” sample.

  In the sample without “Ar etching”, it can be seen that the resistance value increases as time passes after the formation, and the resistance value fluctuates by 3% or more when left for 300 hours or more.

  On the other hand, in the samples of “Ar etch: 100 Å” and “Ar etch: 200 Å”, the rate of change in resistance value is greatly reduced, and the sheet resistance immediately after formation is ± 1% even after being left for 300 hours or more. There was no deviation from the error range.

  Further, when comparing the sample of “Ar etch: 100 と” and the sample of “Ar etch: 200 Å”, it was found that the effect of the Ar sputter etching amount is small, and the effect is small with a small etching amount.

  As described above, the characteristics of the resistance 108 with respect to the influence of the base film on the sheet resistance and the influence of the atmospheric standing time have been described with reference to FIGS. 4 to 7. Si / Cr = 50/50 wt%) and the CrSi thin film resistance of the second target (Si / Cr = 80/20 wt%) are not limited. The same effect as above was confirmed in all of the CrSi thin film and the CrSiN film formed with a target of Si / Cr = 50/50 to 90/10 wt%. Also, the Ar sputter etching method is not limited to the DC bias / sputter etching method used this time.

  FIG. 8 shows the metal thin film resistance and metal wiring resulting from the heat treatment for the sample in which the refractory metal film 5 is left at the bottom of each hole and the sample completely removed when the connection holes 12 and 13 are formed. It is a figure which shows the result of having investigated the fluctuation | variation with contact resistance. A vertical axis | shaft shows the value normalized with the contact resistance value before heat processing. The horizontal axis indicates the number of heat treatments.

  In FIG. 8, the execution time of the dry etching process at the time of forming the connection holes 12 and 13 is adjusted to completely remove the sample of the resistor 108 in which about 500 mm of the refractory metal film at the bottom of the connection holes 12 and 13 is left. The sample of the resistor 108 was used. A TiN film was used as the refractory metal film 5. The CrSi thin film resistor 15 has a thickness of 50 mm under the conditions of Si / Cr = 80/20 wt%, DC power: 0.7 kW, Ar: 85 sccm, pressure: 8.5 mTorr, and deposition time: 6 seconds. Formed a thing.

  The Ar sputter etching process performed before forming the CrSi thin film resistor 15 was performed under the conditions of DC bias: 1250 V, Ar: 20 sccm, pressure: 8.5 mTorr, and processing time: 160 seconds. This treatment corresponds to etching and removing 400 nm of the thermal oxide film formed at 1000 ° C. in a wet atmosphere. The planar dimensions of the connection holes 12 and 13 were 0.6 μm × 0.6 μm. A four-terminal method was used as the contact resistance measurement method.

  The sample of the resistor 108 was subjected to a heat treatment for 30 minutes in a nitrogen atmosphere at 350 ° C. to examine how the characteristics of the contact resistance change. A sample of the resistor 108 having a TiN film used as the refractory metal film 5 at the bottom of the connection holes 12 and 13 (in the figure, a solid line graph 81 indicating “with TiN”) is subjected to heat treatment under the above conditions twice. However, it showed almost the same contact resistance characteristics as before the heat treatment. In contrast, the sample from which the TiN film has been completely removed (dotted line graph 82 indicating “No TiN” in the figure) is subjected to the heat treatment under the above conditions twice, so that the contact resistance value is the contact before the heat treatment. It fluctuated 20% or more compared to the resistance value. This means that the TiN film used as the refractory metal 5 has a function as a barrier film that prevents resistance variation due to the interaction between the CrSi thin film resistor 15 and the metal material pattern 4 constituting the wiring pattern 6. doing.

  The presence of a TiN film used as the refractory metal film 5 between the CrSi thin film resistor 15 and the metal material pattern 4 makes it possible to greatly change the contact resistance due to heat treatment performed in the manufacturing process such as sintering and CVD. In addition to being able to reduce the contact resistance, it is possible to prevent fluctuations in contact resistance due to heat treatment such as solder processing performed in an assembly operation as a subsequent process. As a result, the contact resistance as set can be obtained stably, and fluctuations in the contact resistance before and after assembly can be prevented, so that the accuracy of the product can be improved and the yield of the product can be improved.

  In the method of manufacturing the resistor 108 described with reference to FIGS. 2 and 3, the wiring metal film 20 and the refractory metal film 21 are continuously formed in a vacuum in the step (Step S2). The present invention is not limited to this.

  For example, when the wiring metal film 20 is formed, and once exposed to the atmosphere, the refractory metal film 21 is formed, the wiring oxide film 20 is affected by the natural oxide film formed on the surface of the wiring metal film 20. It becomes difficult to ensure electrical conduction between the metal film 20 and the refractory metal film 21. As described above, the wiring pattern 6 includes the metal material pattern 4 and the refractory metal film 5 formed by patterning the wiring metal film 20 and the refractory metal film 21. By completely removing the refractory metal film 5 at the bottom of the connection holes 12 and 13 at the stage of forming the connection holes 12 and 13 in the second interlayer insulating film 11 formed on the wiring pattern 6, the wiring pattern 6 And a good ohmic connection can be formed between the CrSi thin film resistor 15.

  In (Step S2) described above, the thickness of the refractory metal film 21 functioning as an antireflection film / barrier film is set to 800 mm. However, the embodiment of the present invention is not limited to this. . In general, the thickness of the refractory metal film as the antireflection film is formed to be 500 mm or less. In the method of manufacturing the resistor 108 described with reference to FIGS. 2 and 3, overetching when forming the connection holes 12 and 13 (see (Step S7)) and Ar sputter etching processing when forming a metal thin film ((Step In S8), since the film thickness of the refractory metal film 5 is slightly reduced, the refractory metal film 5 remains as a barrier film that works stably at the bottoms of the connection holes 12 and 13. The thickness of the refractory metal film 21 is preferably 500 mm or more.

  However, as described above, by optimizing the etching process conditions for forming the connection holes 12 and 13 and the Ar sputter etching process conditions, the refractory metal film 5 can be formed even if the film thickness of the refractory metal film 5 is 500 mm or less. It is possible to exhibit the function as a barrier film while minimizing the decrease in the film thickness.

  In (Step S8) described above, Ar sputter etching is performed immediately before the formation of the CrSi thin film 14, but the refractory metal film 5 using a TiN film as a barrier film remains at the bottoms of the connection holes 12 and 13. In this case, since the refractory metal film 5 does not form a natural oxide film that is as strong as the AlSiCu film even when exposed to the atmosphere, the CrSi thin film 14 and the wiring can be formed without performing Ar sputter etching immediately before the formation of the CrSi thin film 14. A good ohmic connection of pattern 6 can be formed. However, as described with reference to FIG. 7, since the resistance value of the CrSi thin film resistor 15 can be more stabilized by performing the Ar sputter etching process immediately before the formation of the CrSi thin film 14, the Ar sputter etching process is executed. Is preferred.

  In the resistor 108, the second interlayer insulating film 11 is flattened by using the formation of the SOG film 9 and the etch-back technique, but the insulating film (or insulating layer) serving as the base of the CrSi thin film resistor 14 is used. ) Is not limited to this. Examples of the insulating film that is the base of the CrSi thin film resistor 14 include an insulating film that has been flattened using a CMP (chemical mechanical polish) technique, which is a known technique, and a plasma CVD oxide film that has not been flattened. Other insulating films may be used.

  However, since many analog resistance elements are used not only in the TCR but also in a configuration in which pairability and specific accuracy are important, in particular, a metal thin film resistor (CrSi thin film) constituting the resistor 108 is used. When the resistor 15) is used as an analog resistance element, it is preferable that the second interlayer insulating film 11 serving as the base of the metal thin film resistor is subjected to a planarization process.

  In the resistor 108, the passivation film 18 is formed on the CrSi thin film resistor 15, but the present invention is not limited to this. The film on the CrSi thin film resistor 15 may be an insulating film other than the passivation film 18 such as an interlayer insulating film for forming a second-layer metal wiring.

(4) Description of Method for Manufacturing Resistor According to Modification FIGS. 9A to 9D are diagrams for describing a method for manufacturing the resistor 160 according to the modification of the resistor 108 described above. FIG. 9D shows a completed drawing of the resistor 160. In the actual resistor 160, transistor elements, capacitor elements, and the like are formed on the same substrate, but illustration of these elements is omitted. The same components as those used in the method of manufacturing the resistor 108 shown in FIGS. 2 and 3 are denoted by the same reference numerals, and redundant description is omitted here.

  First, the configuration of the resistor 160 will be described with reference to FIG. On the silicon substrate 1, an element isolation oxide film 2, a wiring pattern 6, and a second interlayer insulating film 11 are sequentially formed. The wiring pattern 6 is obtained by laminating a first interlayer insulating film 3, a metal material pattern 4, and a refractory metal film 5 in order from the lower layer. The second interlayer insulating film 11 is formed by laminating a plasma CVD oxide film 8, an SOG film 9, and a plasma CVD oxide film 10 in order from the lower layer. Two portions of the second interlayer insulating film 11 correspond to both ends of the metal thin film resistor, that is, two outer peripheral portions immediately above the opening 7 (see FIG. 2C) provided in the wiring pattern 6. Connection holes 12 and 13 are provided.

  A CrSi thin film resistor 15 is formed on the second interlayer insulating film 11 from the region between the connection hole 12 and the connection hole 13 to the inner wall of the connection hole 21 and the wiring pattern 6. A CrSiN film (metal nitride film) 31 is formed on the upper surface of the CrSi thin film resistor 15. A CrSiO film is not formed between the CrSi thin film resistor 15 and the CrSiN film 31. Although not shown, an interlayer insulating film or a passivation film (corresponding to the passivation film 18 of the resistor 108 shown in FIG. 3E) is formed on the second interlayer insulating film 11 including the region where the CrSi thin film resistor 15 is formed. Has been.

  Hereinafter, a method for manufacturing the resistor 160 will be described with reference to FIGS. 9A to 9D in order.

(Step S20)
First, reference is made to FIG. A wafer shape in which the formation of the element isolation oxide film 3 has been completed by the same process as (Step S1) to (Step S7) already described with reference to FIGS. 2 (a) to (f) and FIG. 3 (a). On the silicon substrate 1, a first interlayer insulating film 3, a wiring pattern 6 made of a metal wiring pattern 4 and a refractory metal film 5, and a plasma CVD oxide film 8, an SOG film 9, and a plasma CVD oxide film 10 made of a plasma CVD oxide film 10. After forming the two interlayer insulating film 11, connection holes 12 and 13 are formed in the second interlayer insulating film 11.

(Step S21)
Reference is made to FIG. In the above-described (Step S8), the process having the same contents as described with reference to FIG. For example, after performing Ar sputter etching on the surface of the second interlayer insulating film 11 including the inside of the connection holes 12 and 13 in a vacuum in an Ar sputter etching chamber of a multi-chamber sputtering apparatus, the vacuum state is changed. Then, a CrSi thin film 14 for metal thin film resistance is formed.

After the CrSi thin film 14 is formed, a CrSiN film 30 is continuously formed on the CrSi thin film 14 without breaking the vacuum. Here, the Si / Cr = 80/20 wt% CrSi target used in the formation of the CrSi thin film 14 is used, DC power: 0.7 kW (kilowatt), Ar + N ₂ (mixed gas of argon and nitrogen): 85 sccm, pressure A CrSiN film 30 having a thickness of about 50 mm was formed on the CrSi thin film 14 under the conditions of: 8.5 mTorr and processing time: 6 seconds.

(Step S21)
Reference is made to FIG. In the above-described (Step S9), the formation region of the metal thin film resistor is defined on the CrSiN film 30 by using a well-known photolithography technique by the same process as described with reference to FIG. A resist pattern 16 is formed. Using a RIE (reactive ion etching) apparatus, the CrSiN film 30 and the CrSi thin film 14 are patterned (partially removed) using the resist pattern 16 as a mask to form a laminated pattern composed of the CrSiN film 31 and the CrSi thin film resistor 15. To do.

(Step S22)
Reference is made to FIG. After the formation of the laminated pattern composed of the CrSiN film 31 and the CrSi thin film resistor 15, the resist pattern 16 is removed. Similar to the above embodiment, since the CrSi thin film resistor 15 is electrically connected to the wiring pattern 6, it is not necessary to perform a metal oxide film removal process on the surface of the CrSi thin film resistor 15 using a hydrofluoric acid aqueous solution. . Furthermore, since the upper surface of the CrSi thin film resistor 15 is covered with the CrSiN film 31, there is an advantage that the upper surface of the CrSi thin film resistor 15 is not oxidized even when exposed to an atmosphere containing oxygen, such as air.

  Although illustration is omitted, an interlayer insulating film or a passivation film (see the passivation film 18 shown in FIG. 3E) is formed on the second interlayer insulating film 11 including the regions where the CrSi thin film resistor 15 and the CrSiN film 31 are formed. To do.

  In general, a metal thin film such as CrSi has high reactivity with oxygen, and the resistance value fluctuates when the metal thin film is exposed to the atmosphere for a long time. In the resistor 160, by forming the CrSiN film 31 on the upper surface of the CrSi thin film resistor 15, the upper surface of the CrSi thin film resistor 15 is exposed to the atmosphere, and the resistance value of the CrSi thin film resistor 15 varies with time. Can be prevented. At the stage where the CrSi thin film 14 for forming the CrSi thin film resistor 15 is formed, ohmic connection between the CrSi thin film 14 and the wiring pattern 6 is completed, so that a new thin film is formed on the CrSi thin film 14. However, there is no influence on the characteristics.

FIG. 10 is a diagram showing the relationship between the N ₂ partial pressure of the gas for forming the CrSiN film and the resistivity of the CrSiN film. The vertical axis represents resistivity ρ (mΩ · cm (milliohm · centimeter)), and the horizontal axis represents N ₂ partial pressure (%). Here, under conditions of target: Si / Cr = 50/50 wt%, DC power: 0.7 kW, Ar + N ₂ : 85 sccm, pressure: 8.5 mTorr, treatment time: 6 seconds, N ₂ minutes of Ar + N ₂ gas The pressure was adjusted to form a CrSiN film.

The CrSiN film formed by reactive sputtering with an N ₂ partial pressure of 18% or more is 10 times higher than when a gas not containing N ₂ is used at all (N ₂ partial pressure is 0%). Resistivity is shown. Therefore, if the CrSiN film is formed by setting the N ₂ partial pressure to 18% or more, even if the CrSiN film is directly formed on the CrSi thin film resistor, the resistance value of the entire CrSi thin film resistor is the same as that of the CrSi thin film. Therefore, the CrSiN film hardly affects the resistance value. Here, the upper limit of the N ₂ partial pressure is about 90%. If the N ₂ partial pressure is set to be larger than 90%, it is not preferable because the sputtering rate is significantly reduced and the production efficiency is lowered.

  In the resistor 160, the CrSiN film 31 is formed on the CrSi thin film resistor 15. A CVD insulating film such as a silicon nitride film may be formed on the CrSi thin film resistor 15. However, a CVD chamber is not connected to a general multi-chamber sputtering apparatus, and in order to continuously form a CVD-based insulating film on the CrSi thin film resistor 15 in a vacuum, a corresponding new equipment is purchased. It is necessary and has a great influence on the manufacturing cost.

  If the CrSiN film 30 is formed on the CrSi thin film 14 for forming the CrSi thin film resistor 15 such as the resistor 160, a vacuum can be formed using an existing multi-chamber sputtering apparatus without purchasing a new apparatus. In this state, the CrSiN film 30 serving as an oxidation resistant cover film for the CrSi thin film resistor 15 can be formed.

  In the resistor 160, a TiN film is used as the refractory metal film 5. However, the refractory metal film constituting the wiring pattern 6 is not limited to this, and other materials such as TiW and WSi can be used. Alternatively, a refractory metal film may be used.

  In addition, the resistor 160 includes a single wiring pattern 6 as a metal wiring. However, the present invention is not limited to this, and it is conceivable to configure a multilayer metal wiring structure having a multilayer wiring pattern.

  In the resistor 160, the wiring pattern 6 having the refractory metal film 5 formed on the upper surface of the metal material pattern 4 is used. However, the present invention is not limited to this, and the wiring pattern 6 has a high melting point on the upper surface. Only the metal material pattern 4 may be used without forming the metal film 5. In this case, for example, when an Al-based alloy is used as the metal material pattern 4, a strong natural oxide film is formed on the surface of the metal material pattern, so that a metal thin film for metal thin film resistance is formed after the connection hole is formed. Before the formation, it is preferable to perform a step of removing the natural oxide film on the surface of the metal material pattern at the bottom of the connection hole. The natural oxide film removing step may be performed in combination with an Ar sputter etching process for the purpose of suppressing a change with time of the resistance value of the CrSi thin film resistor 15.

  The resistor 160 uses the metal material pattern 7 and the refractory metal film 9 as the wiring pattern 11 for taking the potential of the CrSi thin film resistor 23, but a polysilicon pattern is used instead of the metal material pattern 7. It may be used.

(5) Description of Resistance Manufacturing Method According to Another Modification FIG. 11 is a diagram for explaining a manufacturing method of the resistance 170 according to another modification. FIG. 11D is a completed view of the resistor 170. In the resistor 170 shown in FIG. 11D, transistor elements and capacitor elements are actually formed on the same substrate, but these elements are omitted. Components formed by the same method as the method of manufacturing the resistor 108 described with reference to FIGS. 2 and 3 are denoted by the same reference numerals, and redundant description is omitted here.

  First, an example of the resistor 170 will be described with reference to FIG. An element isolation oxide film 2 is formed on a silicon substrate 1. A wiring pattern 49 is formed on an oxide film (not shown) formed on the silicon substrate 1 and on the element isolation oxide film 2. The wiring pattern 49 is obtained by forming a polysilicon pattern 45 and a refractory metal film 47 in order from the lower layer. The refractory metal film 47 is made of, for example, WSi or TiSi.

  A first interlayer insulating film 3 is formed on the silicon substrate 1 including the formation region of the wiring pattern 49 and the element isolation oxide film 2. Connection holes 12 and 13 are formed in the first interlayer insulating film 5 corresponding to both ends of the metal thin film resistor and the wiring pattern 49.

  On the first interlayer insulating film 5, a CrSi thin film resistor 23 is formed from the region between the connection holes 21, 21 to the inner wall of the connection hole 21 and the wiring pattern 49. Although illustration is omitted, an interlayer insulating film, a metal wiring, and a passivation film are formed on the first interlayer insulating film 5 including the region where the CrSi thin film resistor 23 is formed.

Hereinafter, a method for manufacturing the resistor 170 will be described with reference to FIGS. 11A to 11D in order.
(Step S30)
Reference is made to FIG. An element isolation oxide film 2 is formed on the silicon substrate 1, and an oxide film (not shown) such as a gate oxide film of a transistor is formed on the surface of the silicon substrate 1 other than the element isolation oxide film 2. Then, a polysilicon film (polysilicon pattern) is formed. For example, the polysilicon pattern 45 with reduced resistance is formed simultaneously with the formation of the gate electrode of the transistor. A refractory metal film is formed on the entire surface of the silicon substrate 1 including the polysilicon pattern 45, and the polysilicon pattern 45 is salicided to form a refractory metal film 47 such as TiSi or WSi on the polysilicon pattern 45. And a wiring pattern 49 is formed.

(Step S31)
Reference is made to FIG. Similar to (step S1) described with reference to FIG. 2A, the first interlayer insulating film 5 is formed on the entire surface of the silicon substrate 1 including the wiring pattern 49.

(Step S32)
Reference is made to FIG. A resist pattern (not shown) for forming connection holes in the first interlayer insulating film 3 corresponding to both ends of the metal thin film resistor and the wiring pattern 49 is formed by photolithography. Using the resist pattern as a mask, the first interlayer insulating film 3 is selectively removed to form connection holes 12 and 13 in the first interlayer insulating film 3. The refractory metal film 47 remains on the bottoms of the connection holes 12 and 13. Thereafter, the resist pattern is removed.

(Step S33)
Reference is made to FIG. By the same process as (Step S8) and (Step S9) described with reference to FIGS. 3B and 3C, the inside of the connection holes 12 and 13 is formed in vacuum using, for example, a multi-chamber sputtering apparatus. Ar sputter etching is performed on the surface of the second interlayer insulating film 11 including the metal thin film, and subsequently, after completion of the Ar sputter etching, a metal thin film for forming a metal thin film resistor is formed without breaking the vacuum. Is patterned to form a CrSi thin film resistor 23.

  Thereafter, although not shown, an interlayer insulating film, a metal wiring, and a passivation film are formed on the first interlayer insulating film 3 including the region where the CrSi thin film resistor 15 is formed.

  Also in this embodiment, as in the case of the resistor 108 described with reference to FIGS. 2 and 3, it is not necessary to pattern the CrSi thin film resistor 15 after the CrSi thin film resistor 15, and further, the CrSi thin film resistor 15 is not required to be patterned. Since the contact surface with the wiring pattern 49 is not exposed to the atmosphere, a good ohmic connection between the CrSi thin film resistor 15 and the wiring pattern 49 can be stably obtained, regardless of the film thickness of the CrSi thin film resistor 15. The CrSi thin film resistor 15 can be miniaturized and the resistance value can be stabilized without increasing the number of steps.

  Further, since the refractory metal film 47 functioning as a barrier film is interposed between the CrSi thin film resistor 15 and the polysilicon pattern 45, variation in contact resistance between the CrSi thin film resistor 15 and the wiring pattern 49 can be reduced. Thus, the accuracy of the resistance value and the yield can be improved.

  Further, the refractory metal film 47 contributes to lowering the resistance of the polysilicon pattern 45, and the refractory metal film 47 can be formed without increasing the number of manufacturing steps as compared with the prior art. The contact resistance between the metal thin film resistor and the wiring pattern can be stabilized while preventing an increase in cost.

  In the embodiment of the above manufacturing method, Ar sputter etching is performed before the metal thin film for the CrSi thin film resistor 15 is formed. Therefore, the elapsed time from the previous process, the difference in the base film that differs for each product, etc. The variation in resistance value caused by the above can be reduced.

  In the resistor 170 shown in FIG. 11, a CrSiN film may be formed on the CrSi thin film resistor 15 in the same manner as the resistor 160 shown in FIG.

In addition, in the samples manufactured under the conditions shown in FIGS. 4, 5, 6 (a), (b), 7, 8, and 10, the resistors 108, 109, 160, and 170 are made of metal. Although an example using CrSi as the material for the thin film resistor is shown, the present invention is not limited to this, and examples of the material for the metal thin film resistor include NiCr, TaN, CrSi ₂ , CrSiN, CrSi, CrSi0, etc. Other materials may be used.

(6) Another Embodiment of Reference Voltage Generating Circuit FIG. 12 is a diagram showing a configuration of the reference voltage generating circuit 200 according to the second embodiment. FIG. 13 is a diagram illustrating a configuration of the reference voltage generation circuit 300 according to the third embodiment. The reference voltage generation circuit 300 is a circuit using a new resistor for the reference voltage generation circuit 120 shown in FIG.

  In the reference voltage generating circuit 200 shown in FIG. 12, this circuit includes p-channel field effect transistors (hereinafter simply referred to as FETs) 201 to 205 and resistors 210 and 220. The FETs 201, 202, 204, and 205 have the same substrate and channel-doped impurity concentrations, are formed in the n-well of the p-type substrate, and the substrate potential of each transistor is set to the same value as the source potential.

  The FET 201 has a high concentration p-type gate, and the FET 102 has a high concentration n-type gate. The ratio S = W / L between the channel width W and the channel length L of the FET 201 and the FET 202 is set to the same value.

  The FET 204 has a low concentration n-type gate, and the FET 205 has a high concentration n-type gate. The ratio S = W / L between the channel width W and the channel length L of the FET 204 and FET 205 is set to the same value.

  A potential is applied to the gate of the FET 201 from a FET 203 having a high-concentration n-type gate and a source follower circuit including a resistance dividing circuit including two resistors 210 and 220 connected in series. The gate of the FET 202 and the gate of the FET 203 are connected to each other. The FET 203 is connected between the source and the gate. The gate of the FET 201 is connected to a connection point between the source of the FET 203 and the resistor 210 (point P4 representing the potential V4 in the figure). The drain of the FET 203 is connected to the gate of the FET 205.

  The FET 202 is connected between the source and the gate, functions as a constant current source, and allows the same current to flow through the FETs 201 connected in series. Thus, the source-gate potential of the FET 201 obtained by subtracting the potential V4 from the power supply voltage Vcc becomes Vpn (= Vcc−V4). V5 is represented by {(resistance value of the resistor 220) / (resistance value of the resistor 210)} × Vpn.

  The FET 204 is connected between the source and the gate, functions as a constant current source, and allows the same current to flow through the FET 205 connected in series. Thus, when the source-gate potential of the FET 205 is expressed as Vnn, the source potential V6 of the FET 205 is V5 + Vnn = {(resistance value of the resistor 220) / (resistance value of the resistor 210)} × Vpn + Vnn (= Vref). It is represented by

  The FET 201 and the FET 202 connected in series constitute a first power supply circuit having a negative temperature coefficient with respect to a change in environmental temperature. On the other hand, the FET 204 and the FET 205 connected in series constitute a second power supply circuit having a positive temperature coefficient with respect to a change in environmental temperature. The slope of the negative temperature coefficient is adjusted by adjusting the resistance values of the resistor 220 and the resistor 210 constituting the resistance dividing circuit in the source follower circuit, for example, by trimming technology, and the positive and negative temperature coefficients are canceled out. That is, a circuit that compensates for temperature characteristics and outputs a stable reference voltage Vref against changes in environmental temperature is configured.

  In addition to the values of the resistors 210 and 220, the gradient of the temperature coefficient of each circuit is low in the high-concentration p-type gate provided in the FET 201, the high-concentration n-type gate provided in the FETs 202, 203, and 205, and the FET 204. The concentration can be adjusted by changing the impurity concentration of the n-type gate.

  FIG. 13 is a diagram showing a configuration of the reference voltage generation circuit 300. As shown in FIG. The reference voltage generation circuit 300 includes p-type channel FETs 301 to 303, FET 306 and FET 307, and resistors 304 and 305. The FETs 01 to 303, FET 306, and FET 307 have the same substrate and channel-doped impurity concentration, are formed in the n-well of the p-type substrate, and the substrate potential of each transistor is set to the same value as the source potential.

  The FET 301 has a high concentration n-type gate, and the FET 302 has a high concentration p-type gate. The ratio S = W / L between the channel width W and the channel length L of the FET 301 and the FET 302 is set to the same value.

  The FET 306 has a high concentration p-type gate, and the FET 307 has a low concentration p-type gate. The ratio S = W / L between the channel width W and the channel length L of the FET 306 and FET 307 is set to the same value.

  A potential is applied to the gate of the FET 301 from a source follower circuit including a FET 303 having a high-concentration p-type gate and a resistance dividing circuit including two resistors 304 and 305 connected in series. The gate of the FET 302 and the gate of the FET 303 are connected to each other. The FET 303 is connected between the source and the gate. The gate of the FET 301 is connected to the connection point between the source of the FET 303 and the resistor 305 (point P7 representing the potential V7 in the figure). A contact P9 between the resistors 304 and 305 and the gate of the FET 306 are connected.

  The FET 302 is connected between the source and the gate, functions as a constant current source, and allows the same current to flow through the FETs 301 connected in series. Thereby, the source-gate potential of the FET 301 obtained by subtracting the potential V7 from the power supply voltage Vcc becomes Vpn (= Vcc−V7). V8 is represented by Vcc − {(resistance value of resistor 304) × {(resistance value of resistor 305) + (resistance value of resistor 305)} × Vpn.

  The FET 306 is connected between the source and the gate, functions as a constant current source, and allows the same current to flow through the FET 307 connected in series. Accordingly, when the potential between the source and the gate of the FET 307 is expressed as Vnn, the source potential V9 of the FET 307 is Vcc−V9 + Vnn = {(resistance value of the resistor 304) / (resistance value of the resistor 304 + value of the resistor 305). } × Vpn + Vnn (= Vref).

  The FET 301 and the FET 302 connected in series constitute a first power supply circuit having a negative temperature coefficient with respect to a change in environmental temperature. On the other hand, the FET 306 and the FET 307 connected in series constitute a second power supply circuit having a positive temperature coefficient with respect to a change in environmental temperature. The slope of the negative temperature coefficient is adjusted by adjusting the resistance values of the resistors 304 and 305 constituting the resistor divider circuit in the source follower circuit, for example, by trimming technology, that is, the temperature characteristic is compensated. A circuit that outputs a stable reference voltage Vref against changes in environmental temperature is configured. In addition to the values of the resistors 304 and 305, the gradient of the temperature coefficient of each circuit is the impurity concentration of the high-concentration p-type gate included in the FET 302 and the low-concentration n-type gate included in the FET 307. Can be adjusted by changing.

(7) Characteristics of Reference Voltage Generation Circuit Using Novel Resistors FIGS. 14A and 14B are graphs showing the input stability and the environmental temperature of the reference voltage generation circuits 100 and 300 shown in FIGS. It is a figure which shows the temperature characteristic with respect to a change with the input stability and temperature characteristic of the reference voltage generation circuits 110 and 120 demonstrated by the ideal value and the prior art. The input stability indicates the stability of the value of the output reference voltage Vref with respect to fluctuations in the value of the power supply voltage Vcc. The more stable the reference voltage Vref, the closer to the ideal value. And The temperature characteristic shows a value closer to the ideal value as the gradient of the temperature coefficient is flatter. In the figure, the input stability and temperature characteristics of the circuits 110 and 120 when polycrystalline silicon is used as the resistor are represented by ◆, and the input stability and temperature of the circuits 100 and 300 using the new resistor using a CrSi metal thin film. Characteristic is represented by ■ and ideal value is represented by ▲.

  As shown in the figure, the reference voltage generation circuit 100 according to the first embodiment using the new resistors 108 and 109 is compared with the conventional reference voltage generation circuit 110 using the resistors 106 and 107 using polycrystalline silicon. The input stability is improved by 54% and the temperature characteristic is improved by 16%, which is a value substantially close to the ideal value.

  On the other hand, the reference voltage generation circuit 300 according to the third embodiment using the new resistors 304 and 305 is compared with the conventional reference voltage generation circuit 120 using the resistors 124 and 125 using polycrystalline silicon. Both the input stability and the temperature characteristics were not improved so much. As described in the section of the prior art, this is because the reference voltage generating circuit 300 is not so different from the ideal value in comparison with the case of using polycrystalline silicon because of the circuit configuration.

  As described above, as a result of examining the combination of the new resistor using the metal thin film and the conventional reference voltage generating circuit, the resistor (106, 107) using polycrystalline silicon in the conventional reference voltage generating circuit (110, 120). , 124, 125), by using a new resistor (108, 109, 304, 305) using a metal thin film, or a resistor 160, 170 according to a modified example, the input stability and temperature characteristics are improved. Although both are improved, the input stability is improved particularly when the new resistors 108 and 109 are applied to the conventional reference voltage generation circuit 110 (the reference voltage generation circuit 100 of the first embodiment corresponds to this). It was found that both the temperature characteristics and the temperature characteristics were drastically improved, and the values were close to ideal values.

It is a figure which shows the structure of the reference voltage generation circuit concerning embodiment. It is a figure for demonstrating the manufacturing method of the resistance used with a reference voltage generation circuit. It is a figure for demonstrating the manufacturing method of the resistance used with a reference voltage generation circuit. It is a figure which shows the characteristic of resistance using a metal thin film. It is a figure which shows the characteristic of resistance using a metal thin film. FIG. 6A and FIG. 6B are diagrams showing the resistance characteristics of the present invention. It is a figure which shows the characteristic of resistance using a metal thin film. It is a figure which shows the characteristic of resistance using a metal thin film. It is a figure for demonstrating the manufacturing method of the resistance concerning a modification. It is a figure for demonstrating the manufacturing method of the resistance concerning a modification. It is a figure for demonstrating the manufacturing method of the resistance concerning a modification. It is a figure which shows the circuit of the modification of a reference voltage generation circuit. It is a figure which shows the circuit of the modification of a reference voltage generation circuit. FIG. 14A is a diagram showing an improvement in the input stability of the reference voltage generation circuit of the present invention, and FIG. 14B is an improvement in characteristics of the reference voltage generation circuit of the present invention with respect to changes in environmental temperature. It is a figure which shows a degree. FIGS. 15A and 15B are circuit diagrams of a conventional reference voltage generating circuit. FIG. 16A shows the input stability of the conventional reference voltage generation circuit together with the ideal value, and FIG. 16B shows the characteristic with respect to the change of the environmental temperature together with the ideal value. FIGS. 17A and 17B are diagrams showing the Vg-Id characteristics of the FET in the reference voltage circuit when the power supply voltage fluctuates. FIG. 18A and FIG. 18B are diagrams showing the potential difference between the resistance of the reference voltage circuit and the n-well.

Explanation of symbols

5 refractory metal film, 6, 11, 49: wiring pattern, 11a: thermal oxide film, 12, 13: connection hole, 14, 15: CrSi thin film resistor, 45: polysilicon pattern, 106, 107, 108, 109, 124, 125, 140, 150, 160, 170, 304, 305: resistance, 101, 102, 103, 104, 105, 121, 122, 123, 126, 127, 301, 302, 303, 306, 307: field effect Transistor, 100, 110, 120, 200, 300: reference voltage generation circuit.

Claims (11)

In a reference voltage generating circuit including a resistance dividing circuit composed of a plurality of resistors connected in series,
A reference voltage generating circuit, wherein the plurality of resistors are formed of a metal thin film. A first power supply circuit configured by a plurality of field effect transistors having gates of different conductivity types and outputting a voltage having a negative temperature coefficient with respect to a change in environmental temperature;
The first field effect transistor having a gate connected to the first power supply circuit, the plurality of the field effect transistors connected in series between the drain and ground of the first field effect transistor and between the source and the power supply voltage Vcc. A source follower circuit that includes a resistance divider circuit composed of resistors and adjusts the slope of the negative temperature characteristic of the voltage output from the first power supply circuit;
A power supply circuit that is connected to the source follower circuit and includes a plurality of field effect transistors having gates of the same conductivity type and different impurity concentrations, and generates a voltage having a positive temperature coefficient with respect to a change in environmental temperature A second power supply circuit that adds the outputs of the source follower circuit and outputs a voltage compensated for the gradient of the temperature coefficient;
The reference voltage generating circuit according to claim 1, comprising:   The reference voltage generating circuit according to claim 1, wherein the metal thin film is made of CrSi.   The resistor composed of the metal thin film has a wiring pattern and an insulating film provided on the wiring pattern, and has a connection hole in a connection portion of the wiring pattern. 4. The reference voltage generating circuit according to claim 3, wherein the reference voltage generating circuit is ohmically connected to the connection portion through a connection hole.   5. The reference according to claim 4, wherein the natural oxide film on the inner surface of the connection hole in contact with the metal thin film and the natural oxide film on the surface of the wiring pattern in contact with the metal thin film at the bottom of the connection hole are removed. Voltage generation circuit.   6. The reference voltage generating circuit according to claim 4, wherein a refractory metal film is interposed between the metal thin film and a connection portion of the wiring pattern.   6. The reference voltage generation circuit according to claim 4, wherein the wiring pattern includes a metal material pattern and a refractory metal film formed on the metal material pattern.   6. The reference voltage generation circuit according to claim 4, wherein the wiring pattern includes a polysilicon pattern and a refractory metal film formed on the polysilicon pattern.   9. The first power supply circuit according to claim 1, wherein a high-concentration n-type gate field effect transistor and a high-concentration p-type gate field effect transistor are connected in series. The reference voltage generator circuit described in 1.   9. The second power supply circuit according to claim 1, wherein a field effect transistor having a high concentration p-type gate and a field effect transistor having a low concentration p-type gate are connected in series. The reference voltage generator circuit described in 1. 9. The second power supply circuit according to claim 1, wherein a high-concentration n-type gate field effect transistor and a low-concentration n-type gate field effect transistor are connected in series. The reference voltage generator circuit described in 1.

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