JP2005311052A - Semiconductor device - Google Patents

Abstract

A semiconductor device having high ESD tolerance is provided.
A source electrode is electrically connected to a p epitaxial layer through interspersed p contact regions, and a longitudinal resistance Repi1 of the p epitaxial layer is increased. By increasing the path resistance of the currents 55 and 57 that flow through the interspersed p contact regions 13, the p epitaxial layer 2, and the p substrate 1, the current 53 that flows in the MOSFET that is the protected element is suppressed, and the protective element By increasing the current 52 of VZD, the ESD tolerance of the MOSFET is increased.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device having a semiconductor protection element that protects semiconductor elements and circuits from overvoltage breakdown due to static electricity.

One of the characteristics required for power ICs is ESD (Electro Static Discharge) breakdown resistance. Particularly in the automobile field and the like, charged people and objects come into contact with each other, so this ESD breakdown resistance is very important.
In order to improve the ESD breakdown tolerance, a method of operating a parasitic thyristor formed in the switching element itself when an ESD voltage is applied has been reported (for example, Patent Document 1 and Patent Document 2). There is also a method of forming a semiconductor protection element such as a Zener diode in parallel with the switching element on the same semiconductor substrate. A method for improving the ESD breakdown tolerance by forming this semiconductor protective element will be described.
FIG. 10 is a plan view of an essential part of a conventional semiconductor device. A semiconductor chip 31 in which a MOSFET, which is a protected element, a vertical Zener diode (hereinafter referred to as VZD), which is a semiconductor protective element, and a circuit portion are integrated is fixed to the copper base 20. The source pad 21 which is a part of the source electrode 18 of the MOSFET and the external lead-out terminal 20b which is a part of the copper base 20 are connected by a wire 36, the drain / cathode electrode 17 and the external lead-out terminal 20a are connected by a wire 35, The gate pad 34 and the external lead-out terminal 20 c are connected by a wire 37. The copper base 20 and the external lead-out terminals 20a and 20c are fixed with mold resin. When configuring an ESD test circuit, the external lead terminals 20b and 20c are connected to GND (ground), and the external lead terminal 20a is connected to a main circuit inductor 39 constituting the ESD test circuit.

The inductances of the wire 36, the copper base 20, and the main circuit inductor 39 are Lmos, Lvzd, and Ld, respectively.
FIG. 11 is a cross-sectional view of a main part of a conventional semiconductor device. In this semiconductor device, VZD as a semiconductor protective element and MOSFET as a protected element are integrated on the same semiconductor substrate. By electrically connecting the VZD and the MOSFET in parallel, the ESD breakdown of the MOSFET is prevented and the ESD breakdown tolerance of the semiconductor device is improved.
In a MOSFET which is a protected element, a p epitaxial layer 2 (impurity concentration of 1 × 10 6) is formed on a p-type substrate 1 (impurity concentration of the order of 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ¹⁹ cm ⁻³ ) having a thickness of about 300 μm. about ¹⁵ cm ^-3, thickness to form a about 15 [mu] m), n-well region 3 (impurity concentration ^{1 × 10 15 cm -3 ~1 ×} 10 16 cm -3 about the surface layer of the p epitaxial layer 2, the thickness Are formed on the surface layer of the n-well region 3 (impurity concentration is 1 × 10 ¹⁵ cm ⁻³ to 1 × 10 ¹⁷ cm ⁻³ , thickness is about 1 μm to 2 μm). Form.

An n source region 5 (impurity concentration is on the order of 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ¹⁹ cm ⁻³ ) and an n offset region 6 (impurity concentration is 1 × 10 ¹⁷ cm ⁻³ ) are formed on the surface layer of the p well region 4. ˜1 × 10 ¹⁸ cm ⁻³ ) and an n drain region 7 (impurity concentration of 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ¹⁹ cm ⁻³ ) is formed on the surface layer of the n offset region 6. The source electrode 18 and the drain / cathode electrode 17 are formed on the n source region 5 and the n drain region 7. A LOCOS oxide film 8 is formed on the n offset region 6. A polysilicon gate electrode 15 is formed on the p well region 4 sandwiched between the n source region 5 and the n offset region 6 through a gate oxide film 14 having a thickness of several tens of nm. A high-concentration p-contact region 13 is formed on the surface layer of the p epitaxial layer 2, a p-contact region 11 is formed on the surface layer of the p-well region 4, and the n-source region 5, the p-contact region 13, and the p-contact region A source electrode 18 is extended on the substrate 11. An n contact region 12 is formed on the surface layer of the n well region 3, and a drain / cathode electrode 17 is extended on the n contact region 12. A back electrode 19 is formed on the back surface of the p substrate 1, and the back electrode 19 and the copper base 20 are fixed.

On the other hand, in VZD which is a semiconductor protection element, a deep n cathode region 9 is formed in the surface layer of the p epitaxial layer 2, a high concentration n contact region 10 is formed in the surface layer of the n cathode region 9, and the n contact region 10 A drain / cathode electrode 17 is extended thereon. VZD is formed by p substrate 1, p epitaxial layer 2 and n cathode region 9. The p contact region 13 is necessary for stabilizing the potential of the p epitaxial layer 2. Also, the p epitaxial layer 2 becomes the anode region of VZD.
During the ESD test, the source electrode 18 is connected to GND via a wire 36, the gate electrode 15 is connected to GND via a wire pad 34 (not shown), and the drain / cathode electrode 17 is connected to the wire 39 (not shown) with an ESD. The copper base 20 is connected to the GND while the main circuit inductor 35 constituting the test circuit 40 is connected.

The area of the p contact region 13 that serves to stabilize the potential of the p epitaxial layer 2 is large, and the vertical resistance Repi0 of the p epitaxial layer 2 immediately below the p contact region 13 is normally designed to be about 1Ω.
The breakdown voltage value of VZD is designed to be at least lower than the breakdown voltage value of the MOSFETs connected in parallel.
FIG. 12 is a diagram showing an equivalent circuit of the MOSFET and VZD of FIG. 11 and an ESD test circuit. The ESD test circuit is a circuit for an ESD test that simulates the Contact Discharge Mode.
The cathode of the VZD and the drain of the MOSFET are connected, and the source of the MOSFET is connected to the wire 36 (source wiring) of Repi0 and the inductance Lmos which are the longitudinal resistances of the p epitaxial layer. The anodes of Repi0 and VZD are connected, further connected to the copper base 20 of inductance Lvzd, the wire 36 is connected to GND via an external lead terminal 20b (not shown), and the copper base 20 is connected via an external lead terminal 20b (not shown). Connect to GND.

The gate of the MOSFET is connected to a gate resistor Rg, and Rg is connected to GND via a wire 37 having an inductance Lg. The cathode of VZD and the drain of MOSFET are connected to the main circuit inductor 39 of the inductance Ld of the ESD test circuit 40. The ESD test circuit 40 includes a main circuit inductor 39, a limiting resistor Resd, a switch SW, and a main circuit capacitor Cesd charged to an ESD voltage, and Cesd is connected to GND. By closing the switch SW, an ESD voltage is applied to the VZD and the MOSFET.
The state during the ESD test will be described with reference to FIGS. When a steep dV / dt overvoltage such as ESD is applied between the drain and the source of the MOSFET, the steep dV / dt causes a current 54 (this current is a displacement current (Idis = C × dV / dt C : N offset region 6 of MOSFET and pn junction capacitance of p well region 4) flows toward n source region 5. At this time, a current 54 flows through the gate capacitance (capacitance between the gate electrode 15 and the p-well region 4), and the potential of the gate electrode 15 is increased positively with respect to the source electrode 18, and A channel is formed in the p-well region 4. Therefore, the current 53 from the drain / cathode electrode 17 flows to the n source region 5 as the current 55 through the channel. This current 55 flows into the source electrode 18 and is divided into a current 56 and a current 57. Current 56 flows through wire 36 to GND. The current 57 flows into the p epitaxial layer 2 through the p contact region 13, and flows into the copper base 20 through the p substrate 1 and the back electrode 19.

When the current 53 increases, the potential of the drain / cathode electrode 17 rises. When the Zener voltage is exceeded in the n cathode region 9 of VZD, a Zener current (current 52) flows and the VZD operates. When the VZD operates, the current 51 from the ESD test circuit 40 is shunted into a current 53 flowing through the MOSFET and a current 52 flowing through the VZD, and a VZD Zener voltage is applied between the drain and source of the MOSFET to Since the increase is small, the increase in current 53 flowing in the MOSFET is suppressed, and the increase in current 51 flows in VZD.
Therefore, the MOSFET does not enter a snapback phenomenon or an avalanche phenomenon, and the MOSFET does not cause ESD breakdown.
Japanese Patent Laid-Open No. 2001-320047 FIG. Japanese Patent Laid-Open No. 2002-94063 FIG.

However, in FIG. 11, when Repi0 is as small as about 1Ω, the current 57 becomes large, so that the current 53 flowing through the MOSFET becomes large, and the MOSFET enters the snapback as shown in FIG. When the MOSFET snaps back, the current 53 flowing through the MOSFET increases rapidly, and the MOSFET causes ESD breakdown.
An object of the present invention is to solve the above-described problems and provide a semiconductor device having a high ESD tolerance.

To achieve the above object, a semiconductor substrate, a semiconductor layer formed on the semiconductor substrate, a lateral switching element formed on the semiconductor layer, and the semiconductor layer and the semiconductor substrate separated from the switching element. And a vertical semiconductor protective element that protects the switching element from overvoltage, a contact region in which the low potential electrode of the switching element and the semiconductor layer are formed on a surface layer of the semiconductor layer In this configuration, the resistance of the current path flowing from the low-potential electrode to the semiconductor substrate is increased by interposing the contact regions and interposing the contact regions.
A semiconductor substrate; a semiconductor layer formed on the semiconductor substrate; a lateral switching element formed on the semiconductor layer; and formed on the semiconductor layer and the semiconductor substrate apart from the switching element. In a semiconductor device having a vertical semiconductor protection element for protecting a switching element, the low potential electrode of the switching element and the semiconductor layer are electrically connected via a contact region formed on a surface layer of the semiconductor layer And a resistance of a current path flowing from the low potential electrode to the semiconductor substrate is increased by making a specific resistance of the semiconductor substrate under the switching element higher than a specific resistance of a portion of the semiconductor substrate forming the semiconductor protection element. And

A semiconductor substrate; a semiconductor layer formed on the semiconductor substrate; a lateral switching element formed on the semiconductor layer; and formed on the semiconductor layer and the semiconductor substrate apart from the switching element. In a semiconductor device having a vertical semiconductor protection element for protecting a switching element, the low potential electrode of the switching element and the semiconductor layer are electrically connected via a contact region formed on a surface layer of the semiconductor layer The semiconductor substrate and the back electrode of the semiconductor substrate are fixed via an insulating film, and the insulating film opens at the semiconductor protection element formation portion, and the semiconductor substrate and the back electrode are electrically connected through the opening. By making contact, the resistance of the current path flowing from the low potential electrode to the back electrode is increased.
Further, in these, the switching element includes a first conductivity type epitaxial layer formed on the surface layer of the first main surface of the first conductivity type semiconductor substrate, and a second conductivity type formed on the surface layer of the epitaxial layer. First well region, a first conductivity type second well region formed in the surface layer of the first well region, and a second conductivity type source region formed in the surface layer of the second well region A second conductivity type offset region formed in the surface layer of the first well region apart from the source region, a second conductivity type drain region formed in the surface layer of the offset region, and the source region And a gate electrode formed through a gate insulating film on the second well region sandwiched between the offset regions, and a semiconductor protection element is formed on the epitaxial layer in the first layer A vertical Zener diode formed apart from the well region and having a second conductivity type cathode region reaching the vicinity of the semiconductor substrate and the epitaxial layer, and the first well region is formed on the surface layer of the semiconductor layer. A first conductivity type contact region formed separately from the source region, a source electrode which is a low potential electrode formed on the contact region and the source region, and a drain formed in common on the drain region and the cathode / A semiconductor device having a cathode electrode, a back electrode formed on the back surface of the semiconductor substrate, and a conductor fixed to the back electrode.

In addition, the vertical resistance of the semiconductor layer in the region where the contact region is projected onto the semiconductor layer directly below may be 2Ω or more.
Further, it is preferable that the longitudinal resistance of the semiconductor layer in a region where the contact region is projected onto the semiconductor layer directly below is 10Ω or more.
Further, in the semiconductor device configured to sandwich the insulating film between the semiconductor substrate and the back electrode, the resistance of a current path flowing from the low potential electrode to the semiconductor substrate can be reduced by thinning the semiconductor substrate to 20 μm or less. Increase it.
The resistive conductive film may be polysilicon.
The ratio of the inductance value of the source wire connecting the conductor and the source electrode to the inductance value of the conductor between the portion where the back electrode is fixed and the portion where the source wire is fixed is 10 or more. There should be.

In this invention, by reducing the area of the p contact region and increasing the longitudinal resistance of the p epitaxial layer, the current flowing through the MOSFET during ESD is suppressed, ESD breakdown is prevented, and the ESD tolerance is improved. be able to.
Moreover, ESD tolerance can be improved by increasing the vertical resistance of the p-substrate under the MOSFET.
Further, by making the back electrode in contact with the p substrate only under the VZD and utilizing the lateral resistance of the p substrate, the current flowing through the MOSFET can be suppressed and the ESD tolerance can be improved.
In addition, by connecting the source electrode and the p-contact region via a resistive conductive film, the current flowing through the MOSFET can be suppressed and the ESD tolerance can be improved.

  In the embodiment of the present invention, in order to stabilize the potential of the p epitaxial layer, the source electrode and the p epitaxial layer are electrically connected through the p contact region. It is to prevent ESD breakdown of a MOSFET as a protected element by increasing the path resistance of a current flowing from the source region through the source electrode, the p epitaxial layer, and the p substrate. In the following description, the same reference numerals are assigned to the same parts as those of the conventional element.

1A and 1B are configuration diagrams of a semiconductor device according to a first embodiment of the present invention. FIG. 1A is a cross-sectional view of the main part, and FIG. 1B is a plan view of the main part corresponding to the source pad 21 in FIG. It is. Here, a cross-sectional view of a main part in which MOSFETs as protected elements are integrated on the same semiconductor substrate is shown.
In a MOSFET which is a protected element, a p epitaxial layer 2 (impurity concentration of 1 × 10 6) is formed on a p-type substrate 1 (impurity concentration of the order of 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ¹⁹ cm ⁻³ ) having a thickness of about 300 μm. about ¹⁵ cm ^-3, thickness to form a about 15 [mu] m), n-well region 3 (impurity concentration ^{1 × 10 15 cm -3 ~1 ×} 10 16 cm -3 about the surface layer of the p epitaxial layer 2, the thickness Are formed on the surface layer of the n-well region 3 (impurity concentration is 1 × 10 ¹⁵ cm ⁻³ to 1 × 10 ¹⁷ cm ⁻³ , thickness is about 1 μm to 2 μm). Form.

An n source region 5 (impurity concentration is on the order of 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ¹⁹ cm ⁻³ ) and an n offset region 6 (impurity concentration is 1 × 10 ¹⁷ cm ⁻³ ) are formed on the surface layer of the p well region 4. ˜1 × 10 ¹⁸ cm ⁻³ ) and an n drain region 7 (impurity concentration of 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ¹⁹ cm ⁻³ ) is formed on the surface layer of the n offset region 6. The source electrode 18 and the drain / cathode electrode 17 are formed on the n source region 5 and the n drain region 7. LOCOS oxide film 8 is formed on n offset region 6. A polysilicon gate electrode 15 is formed on the p well region 4 sandwiched between the n source region 5 and the n offset region 6 through a gate oxide film 14 having a thickness of several tens of nm. A high-concentration p-contact region 13 is formed on the surface layer of the p epitaxial layer 2, a p-contact region 11 is formed on the surface layer of the p-well region 4, and the n-source region 5, the p-contact region 13, and the p-contact region A source electrode 18 is extended on the substrate 11. An n contact region 12 is formed on the surface layer of the n well region 3, and a drain / cathode electrode 17 is extended on the n contact region 12. A back electrode 19 is formed on the back surface of the p substrate 1, and the back electrode 19 and the copper base 20 are fixed.

On the other hand, in VZD which is a semiconductor protection element, a deep n cathode region 9 is formed in the surface layer of the p epitaxial layer 2, a high concentration n contact region 10 is formed in the surface layer of the n cathode region 9, and the n contact region 10 A drain / cathode electrode 17 is extended thereon. VZD is formed by p substrate 1, p epitaxial layer 2 and n cathode region 9. The p contact region 13 is necessary for stabilizing the potential of the p epitaxial layer 2. Also, the p epitaxial layer 2 becomes the anode region of VZD.
During the ESD test, the source electrode 18 is connected to GND via a wire 36, the gate electrode 15 is connected to GND via a wire pad 37 (not shown), and the drain / cathode electrode 17 is connected to GND via a wire (not shown). The copper base 20 is connected to the GND while the main circuit inductor 39 constituting the circuit 40 is connected.

The thickness of the p epitaxial layer 2 is as thin as about 15 μm, and the current 57 flowing from the p contact region 13 flows to the p substrate 1 without spreading in the lateral direction. Therefore, when the area of the p contact region 2 is S1, the longitudinal resistance Repi1 of the p epitaxial layer 2 is determined by the specific resistance of the p epitaxial layer 2 × (p epitaxial layer thickness / S1). That is, by making the p contact regions 13 interspersed as shown in FIG. 5B, the area S1 is reduced to one-tenth of the conventional one, so that the Repi1 can be increased to about 10Ω.
By increasing the vertical resistance Repi1, it is possible to suppress the current 53 flowing through the MOSFET and prevent the MOSFET from snapping back.
FIG. 2 is a diagram showing an equivalent circuit and an ESD test circuit of the semiconductor device of FIG. The difference from FIG. 12 is that 1Ω of Repi0 is changed to 10Ω of Repi1.

FIG. 3 is a diagram showing waveforms obtained by circuit simulation using the equivalent circuit of FIG. This is a case where the specific resistance ρ of the p substrate 1 is 0.05 Ωcm, the device thickness is 500 μm, the device size is 1 mm ² (the device size here is the area of MOSFE and VZD), and the Repi 1 is 10 Ω. By increasing Repi1 to 10Ω, snapback of the MOSFET can be prevented.
FIG. 4 shows the relationship between the ESD breakdown voltage and Lmos / Lvzd with Rep1 as a parameter. The ESD Voltage on the vertical axis is the ESD breakdown voltage. When Repi1 is increased, the ESD breakdown voltage greatly depends on Lmos / Lvzd.
When Repi1 is made larger than 1Ω and Lmos / Lvzd is made larger, the ratio of the current 52 flowing through VZD increases, and the current 53 flowing through the MOSFET decreases, so that the ESD breakdown voltage increases. In order to set Lmos / Lvzd to 10 or more and set it to 5 kV or more which is an ESD breakdown voltage practically required in an integrated circuit, it is preferable to set Rep1 to 2 Ω or more. Further, when Lmos / Lvzd is 40 or more and Repi1 is 10Ω or more, the ESD breakdown voltage is 25 kV or more, which can be applied to an automobile that requires a large ESD tolerance.

  As shown in FIG. 10, when Lvzd is the inductance of the copper base 20 and Lmos is the inductance of the source wiring (wire 36), Lmos / Lvzd is about 20 to 100. When the source wiring is made of a conductor, Lmos / Lvzd is about 10.

FIG. 5 is a cross-sectional view of the main part of the semiconductor device according to the second embodiment of the present invention. Here, a cross-sectional view of a main part in which MOSFET and VZD are integrated on the same semiconductor substrate is shown.
The difference from FIG. 1 is that the contact resistance between the p substrate 1 and the back electrode 19 under the p contact region 13 and under the MOSFET is further increased, and the vertical resistance Rsub1 of the p substrate 1 is increased, so that the MOSFET snaps. This is the point that makes back more difficult to occur.
As a method for increasing the contact resistance, for example, damage implantation with heavy ions such as Ar is performed from the back surface of the p substrate 1. If this damage implantation is performed on the entire surface, the avalanche operating resistance of the VZD is also deteriorated. Further, by irradiating the back surface of the p substrate 1 under the p contact region 13 and the MOSFET with a YAG laser, the surface layer can be made amorphous to increase the contact resistance.

  Further, non-doped polysilicon is formed on the back surface of the p substrate 1, polysilicon at VZD locations is removed by photoetching, and a back electrode 19 is formed on the entire surface, so that the p substrate under the p contact region 13 and under the MOSFET. A similar effect can be obtained by increasing the resistance between 1 and the back electrode 19.

FIG. 6 is a cross-sectional view of the main part of the semiconductor device according to the third embodiment of the present invention. Here, a cross-sectional view of a main part in which MOSFET and VZD are integrated on the same semiconductor substrate is shown.
The difference from FIG. 1 is that the back electrode 19 is in electrical contact only under VZD. By doing so, the lateral resistance Rsub2 of the p-substrate 1 is added to Rep1, the resistance of the path through which the current 57 flows can be further increased, and the current 53 flowing through the MOSFET can be further suppressed. As a result, ESD destruction can be made more difficult to occur.
In this case, when Rsub2 is large, Repi0 is effective even at about 1Ω as in the prior art. Further, for example, if damage implantation with heavy ions such as Ar is performed on the p substrate 1, the resistance further increases and the current 57 is further suppressed.

FIG. 7 is a sectional view showing the principal part of a semiconductor device according to the fourth embodiment of the present invention. Here, a cross-sectional view of a main part in which MOSFET and VZD are integrated on the same semiconductor substrate is shown.
The difference from FIG. 6 is that the thickness of the p-substrate 1 is reduced. The smaller the thickness of the p-substrate 1 for increasing the lateral resistance, the better. However, since there is a sagging of the diffusion profile when the p epitaxial layer 2 is formed on the p substrate 1, if the thickness is too thin, the surface concentration of the p substrate 1 is lowered and an ohmic contact cannot be obtained. Therefore, the thickness of the p substrate 1 needs to be 10 μm or more. In addition, since the lateral resistance decreases when the p substrate 1 is thick, the thickness of the p substrate 1 is preferably 20 μm or less.
By reducing the thickness of the p substrate 1 in this way, the lateral resistance Rsub3 of the p substrate 1 is increased, the resistance of the path through which the current 57 flows can be increased, and the current 53 flowing through the MOSFET can be further suppressed. As a result, ESD destruction can be made more difficult to occur.

FIG. 8 is a cross-sectional view of the principal part of the semiconductor device according to the fifth embodiment of the present invention. Here, a cross-sectional view of a main part in which MOSFET and VZD are integrated on the same semiconductor substrate is shown.
The difference from FIG. 1 is that the p contact region 13 and the n source region 5 are connected by a resistive conductive film 25 such as polysilicon. A conductive film 27 such as Al is formed on the p contact region 13, and the conductive film 27 and the source electrode 18 are connected by a resistive conductive film 25. An insulating film 26 is formed on the resistive conductive film 25 and the conductive film 27, and a source electrode 18 is formed thereon.
Also in this case, since the resistance of the path of the current 57 is increased, snapback is less likely than in FIG. Even when the resistance of Repi1 is as small as about 1Ω, if the resistance of the resistive conductive film 25 is large, the current 57 is suppressed, which is effective in preventing ESD breakdown.

  Further, when the first to fourth embodiments and the fifth embodiment are combined, the effect is further increased.

FIG. 9 is a fragmentary cross-sectional view of the semiconductor device according to the sixth embodiment of the present invention. Here, a cross-sectional view of a main part in which MOSFET and VZD are integrated on the same semiconductor substrate is shown.
The difference from FIG. 1 is that only the n source region 5 is formed on the surface layer of the p well region 4. The same effect can be obtained when the present invention is applied to a MOSFET having such a structure.
Although the MOSFET of the above-described embodiment shows the case of the double resurf structure, the same effect can be obtained even in the case of a low breakdown voltage MOSFET of about 40 V that does not form the n-well region 3 (including the p-well region 4 in some cases). Is obtained.

BRIEF DESCRIPTION OF THE DRAWINGS It is a block diagram of the semiconductor device of 1st Example of this invention, (a) is principal part sectional drawing, (b) is a principal part top view equivalent to the source pad 21 of FIG. The figure which shows the equivalent circuit and ESD test circuit of the semiconductor device of FIG. The figure which shows the waveform which carried out the circuit simulation using the equivalent circuit of FIG. The figure which shows the relationship between the ESD breakdown voltage and the ratio of Lmos / Lvzd using Repi1 as a parameter Sectional drawing of the principal part of the semiconductor device of 2nd Example of this invention Sectional drawing of the principal part of the semiconductor device of 3rd Example of this invention. Sectional drawing of the principal part of the semiconductor device of 4th Example of this invention. Sectional drawing of the principal part of the semiconductor device of 5th Example of this invention Sectional drawing of the principal part of the semiconductor device of 6th Example of this invention Plan view of main part of conventional semiconductor device Sectional view of the main part of a conventional semiconductor device The figure which shows the equivalent circuit and ESD test circuit of MOSFET and VZD of FIG. The figure which shows the waveform which carried out the circuit simulation using the equivalent circuit of FIG.

Explanation of symbols

1 p substrate 2 p epitaxial layer 3 n well region 4 p well region 5 n source region 6 n offset region 7 n drain region 8 LOCOS oxide film 9 n cathode region 10 n contact region (n cathode region)
11 p contact region (p well region)
12 n contact region (n well region)
13 p contact region (p epitaxial layer)
14 Gate oxide film 15 Gate electrode 16 Insulating film 17 Drain / cathode electrode 18 Source electrode 19 Back electrode 20 Copper base 21 Source pad 22 Insulating film (formed between p substrate and back electrode)
23 Opening 25 Resistive conductive film 26 Insulating film (formed between source electrode, resistive conductive film and conductive film)
27 conductive film 31 semiconductor chip 32 MOSFET and VZD formation location 33 circuit portion 34 gate pad 35 wire (drain wiring)
36 wires (source wiring)
37 wires (gate wiring)
38 Mold resin 39 Main circuit inductor 40 ESD test circuit 51 to 58 Current Lmos Source wiring (wire 36) inductance Lvzd Copper base inductance Rg Gate electrode resistance Lg Gate wiring (wire 37) inductance Repi0 Conventional semiconductor device epitaxial Layer vertical resistance Repi1 Epitaxial layer vertical resistance Rsub1 of the semiconductor device of the present invention P substrate vertical resistance Rsub2, Rsub3 p substrate lateral resistance S0 Area S1 of the p contact region of the conventional semiconductor device Semiconductor of the present invention Area of device p-contact region Ld Inductance of main circuit inductor Resd Main circuit resistance Cesd Main circuit capacitor SW Switch GND Ground

Claims (9)

A semiconductor substrate; a semiconductor layer formed on the semiconductor substrate; a lateral switching element formed on the semiconductor layer; and the switching element formed on the semiconductor layer and the semiconductor substrate apart from the switching element. In a semiconductor device having a vertical semiconductor protection element that protects
The low-potential electrode of the switching element and the semiconductor layer are electrically connected via a contact region formed on the surface layer of the semiconductor layer, and the contact region is interspersed to form a semiconductor substrate. A semiconductor device characterized by increasing a resistance of a flowing current path. A semiconductor substrate; a semiconductor layer formed on the semiconductor substrate; a lateral switching element formed on the semiconductor layer; and the switching element formed on the semiconductor layer and the semiconductor substrate apart from the switching element. In a semiconductor device having a vertical semiconductor protection element that protects
The low potential electrode of the switching element and the semiconductor layer are electrically connected via a contact region formed on the surface layer of the semiconductor layer, and the specific resistance of the semiconductor substrate under the switching element is formed to form the semiconductor protection element. A semiconductor device characterized in that the resistance of a current path flowing from the low potential electrode to the semiconductor substrate is increased by making it higher than a specific resistance of a portion of the semiconductor substrate to be processed. A semiconductor substrate; a semiconductor layer formed on the semiconductor substrate; a lateral switching element formed on the semiconductor layer; and the switching element formed on the semiconductor layer and the semiconductor substrate apart from the switching element. In a semiconductor device having a vertical semiconductor protection element that protects
The low potential electrode of the switching element and the semiconductor layer are electrically connected via a contact region formed on the surface layer of the semiconductor layer, and the semiconductor substrate and the back electrode of the semiconductor substrate are interposed via an insulating film. The resistance of the current path that flows from the low-potential electrode to the back electrode is secured by opening the insulating film at the semiconductor protection element forming portion and electrically contacting the semiconductor substrate and the back electrode at the opening. A semiconductor device characterized in that the semiconductor device is increased. A semiconductor substrate; a semiconductor layer formed on the semiconductor substrate; a lateral switching element formed on the semiconductor layer; and the switching element formed on the semiconductor layer and the semiconductor substrate apart from the switching element. In a semiconductor device having a vertical semiconductor protection element that protects
A semiconductor characterized by increasing the resistance of a current path flowing from the low potential electrode to the semiconductor substrate by electrically connecting the low potential electrode of the switching element and the semiconductor layer through a resistive conductive film. apparatus. The switching element includes a first conductivity type epitaxial layer formed on a surface layer of a first main surface of a first conductivity type semiconductor substrate, and a second conductivity type second layer formed on the surface layer of the epitaxial layer. A first well region; a second well region of a first conductivity type formed in a surface layer of the first well region; a source region of a second conductivity type formed in a surface layer of the second well region; A second conductivity type offset region formed in the surface layer of the first well region apart from the source region, a second conductivity type drain region formed in the surface layer of the offset region, the source region and the offset A lateral MOSFET comprising a gate electrode formed on a second well region sandwiched between regions via a gate insulating film, wherein the semiconductor protection element is separated from the first well region in an epitaxial layer. A vertical Zener diode formed and formed of a cathode region of a second conductivity type reaching the vicinity of the semiconductor substrate and the epitaxial layer;
A contact region of a first conductivity type formed on the surface layer of the semiconductor layer apart from the first well region; a source electrode which is a low potential side electrode formed on the contact region and the source region;
A drain / cathode electrode formed in common on the drain region and the cathode;
A back electrode formed on the back surface of the semiconductor substrate, a conductor fixed to the back electrode,
The semiconductor device according to claim 1, wherein the semiconductor device includes: 2. The semiconductor device according to claim 1, wherein a longitudinal resistance of the semiconductor layer in a region obtained by projecting the contact region onto the semiconductor layer immediately below is 2Ω or more. 4. The semiconductor device according to claim 3, wherein resistance of a current path flowing from the low potential electrode to the semiconductor substrate is increased by thinning the semiconductor substrate to 20 μm or less. The semiconductor device according to claim 4, wherein the resistive conductive film is polysilicon. The ratio between the inductance value of the source wiring connecting the conductor and the source electrode and the inductance value of the conductor between the portion where the back electrode is fixed and the portion where the source wiring is fixed is 10 or more. The semiconductor device according to claim 5.

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