JP2005310921A - MOS type semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a MOS type semiconductor device for realizing a MOS type semiconductor device having an extremely fine channel length and a fully depleted channel region using a fin of a vertical type semiconductor thin film having an extremely fine width, and a manufacturing method thereof. To provide.
SOLUTION: Source regions 270 and 275, channel regions 260 and 265, and drain regions 280 and 285 are formed in parallel with the SOI substrate 21 in an opening portion of a first insulator layer 320 formed on the SOI substrate 21 using a selective epitaxial growth method. A region to be the fins 201 and 202 is formed by stacking as a semiconductor thin film, and the gate insulator film 240 and the gate electrode 255 are formed on the side surfaces of the channel regions 260 and 265 of the fins 201 and 202 in the channel width direction. A MOS type semiconductor device formed so as to be narrower than an extent that channel regions 260 and 265 are completely depleted by a voltage, and a method for manufacturing the same.
[Selection] FIG.

Description

  The present invention relates to a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structure, and more particularly, to a MOS semiconductor device having a completely depleted channel region and an extremely fine channel length, and a method for manufacturing the same.

  MOSFETs, which are MOS type semiconductor devices, have a simpler structure, easier element isolation, and easier manufacturing processes than bipolar type transistors. Therefore, integrated circuits with high integration density and high integration, especially digital integrated circuits. It is widely used as a basic constituent element. In particular, a CMOS (Complementary MOS) circuit, which is a multi-element MOS semiconductor device combining an n-channel MOSFET and a p-channel MOSFET, can achieve both low power consumption and high-speed operation. SoC (System on a Chip) or system LSI is widely used in various electronic devices, and its importance is considered to increase more and more in the future.

  As a guideline for realizing both high performance and high integration density of the MOSFET, a proportional reduction law that reduces the shape of the MOSFET in proportion is effective. In accordance with this guideline, the channel length of the MOSFET continues to be reduced from about 20 μm at the time invented by Kahn and Atalla in 1960, and MOSFETs of 100 nm or less are now in practical use. However, in the conventional planar structure MOSFET formed in the silicon substrate, as the channel length is reduced to several tens of nm or less, the subthreshold current flowing between the drain and the source at a gate voltage lower than the threshold voltage (threshold voltage) is generated. Even when the gate voltage is 0V, a minute leak current is generated between the drain and the source. This leakage current increases as the channel length is reduced, increasing power consumption during standby of an LSI in which hundreds of millions of miniaturized MOSFETs are integrated, and has become a major issue in recent years. As countermeasures, various proposals for improvement have been made in the conventional planar MOSFET structure, but the structure becomes complicated and the manufacturing process is complicated accordingly, and the planar structure built in silicon. The limitation of MOSFETs is said.

  In recent years, in order to improve the subthreshold current characteristics, a method of forming a MOSFET in a thin silicon single crystal thin film using an SOI (Silicon On Insulator) substrate having an extremely thin silicon single crystal thin film has been proposed. Yes. Various types of SOI substrates have been proposed, but as a general one, an insulating film such as a silicon oxide film is provided on the upper surface of a thick silicon single crystal substrate serving as an operation substrate, and a thin film is further formed on the upper surface. This is a substrate on which a silicon single crystal thin film is formed. Since the insulator film has a structure embedded between the silicon single crystal substrate and the silicon single crystal thin film, it is hereinafter referred to as a buried insulator film. A fully depleted MOSFET is proposed in which a channel region is formed in the silicon single crystal thin film thinned to 100 nm or less and the channel region is completely depleted by an applied gate voltage, and the subthreshold current characteristics are greatly improved. An improved MOSFET with a channel length of 100 nm or less was realized.

  However, in order to realize a further miniaturized MOSFET having a channel length of several tens of nm or less, it is necessary to reduce the silicon single crystal thin film to several tens of nm or less in order to completely deplete the channel region. However, it has been extremely difficult to realize using a conventional SOI substrate. In order to solve this problem, a channel is formed in a fin (hereinafter referred to simply as a fin) of a vertical single crystal silicon thin film obtained by processing a silicon single crystal thin film on an SOI substrate into a fin shape in a direction perpendicular to the substrate. A FinFET, which is a MOS semiconductor device having a structure in which a region is formed, has been proposed. This FinFET is disclosed in Patent Document 1 and Non-Patent Document 1. The FinFET disclosed in Patent Document 1 and Non-Patent Document 1 is a MOS type semiconductor device having a structure in which a source, a channel, and a drain are arranged in parallel or in a plane with respect to an SOI substrate. For the sake of distinction, the term “p-FinFET” will be used hereinafter for the purpose of planar.

A typical schematic diagram of this p-FinFET is shown in FIGS. FIG. 6 is a plan layout view, and FIGS. 7 and 8 are enlarged cross-sectional structural views in the aa ′ and bb ′ directions. A fin 100 having a _fin width W _fin of several tens of nanometers and a thickness H _fin of a silicon single crystal thin film formed on the upper surface of a buried insulator film 120 on a silicon substrate 110 constituting an SOI substrate is used as a vertical island. Processed into a shape. An interlayer insulator film 130 is formed on the upper surface of the fin 100. Forming a gate electrode 150 having a width of the gate electrode length L _g aspect several 10nm and several nm or less of the gate insulating film 140 on the fin 100. The channel region 160 of the MOSFET becomes a region of the fin 100 sandwiched between the MOS structures constituted by the gate insulator film 140 and the gate electrode 150 formed on both side surfaces of the fin 100 as shown in FIG. The source region 170 and the drain region 180 are formed inside the fin 100 extending on both sides of the gate electrode 150. The source region extraction electrode 172 is formed in the electrode extraction region 190 formed on the extension of the fin through the contact opening 171 of the source electrode. The drain region extraction electrode 182 and the gate extraction electrode 152 are also formed in the electrode extraction regions 191 and 192 formed on the extension of the fin via the contact openings 181 and 151 of the respective electrodes. By using the structure of the p-FinFET, it is like can be the channel region 160 fully depleted with a gate electrode length L _g of several 10nm to form stable, good performance MOSFET sub-threshold current characteristics This is a promising candidate for a MOSFET having an extremely fine gate electrode length that will be practically used in the future.

  The following four items are raised as problems of the conventional p-FinFET.

(1) In order to completely deplete the channel region 160 by the gate voltage, the p-FinFET needs to have a fin width W _fin formed in an extremely thin film of several tens of nanometers, and has an extremely fine line width and its variation. A small photolithography process is essential. Further, the gate electrode length L _g that defines the channel length L _C also requires a photolithography process with an extremely fine line width of about several tens of nanometers and a small variation like the _fin width W _fin . Even with the most advanced photolithography process, it is possible to form a fine pattern in the resolution limit area, so that the variation in line width between wafers and chips as well as between lots and wafers as well as within chips is large. Unavoidable. For this reason, the variation of the _fin width W _fin and the gate electrode length L _g acts synergistically to produce a large variation in the electrical characteristics of the p-FinFET, resulting in variations in the operating speed of the LSI, instability of the operation, etc. It was the cause of the bug.

  (2) As can be seen from the plane layout diagram of the p-FinFET shown in FIG. 6, the electrode lead-out regions 190 and 191 from the fin 100 region to the source and drain region lead-out electrodes 172 and 182 are connected to the respective contact openings 171 and 181 from the fin 100. Therefore, the distance D from the end face of the gate electrode 150 to the contact openings 171 and 181 inevitably increases. Since the distance D is formed of a semiconductor thin film having a high resistance, the parasitic series resistance of the source region 170 and the drain region 180 is increased, and the electrical characteristics of the p-FinFET are significantly deteriorated.

  (3) Although the area occupied by a single p-FinFET is extremely small as shown by the circular part indicated by the broken line in FIG. 6, the electrode lead-out regions 190, 191 and 192 of the source, drain and gate are substantially Since it is almost determined by the area occupied by the formation regions of the electrodes 172, 182 and 152, it has been difficult to achieve high density.

(4) Since the single p-FinFET channel is formed on both sides of the channel region 160 as shown in FIG. 7, the channel width W as MOSFET, if the height of the fin 100 and _{H fin, 2H fin} Given in. In order to arbitrarily change the channel width W, it is necessary to change H _fin , but it is extremely difficult to form a plurality of fins having different heights on the same substrate. Therefore, when the CMOS inverter circuit shown in FIG. 9 is configured using p-FinFET, as shown in the plan layout diagram of FIG. 10, a multi-channel structure in which n pieces of p-FinFETs having the same shape are connected in parallel. The p-FinFET configuration needs to be W = 2nH _fin . In the example shown in FIG. 10, the p-channel type p-FinFET has 10 fins and the n-channel type p-FinFET has 5 fins arranged in parallel so that the drain currents are almost equal. ing. However, in this configuration, W can only be controlled digitally as an integer of n. And, substantially the length of the fin required direction in which the gate electrode is disposed despite a nW _fin, the spacing between the fins in practice are added, the spacing W _fin Even if it is substantially equal to, a width of about 2 nW _fin is required, and the integration density in the channel width direction is about one half.

  In order to eliminate the need for an extremely fine photolithography process for forming the gate electrode length Lg in the above problem (1), there is a method in which the source, channel, and drain regions are formed in a direction perpendicular to the substrate surface. And Patent Documents 2 and 3. Hereinafter, the MOS semiconductor device having this structure is referred to as a v-FET because the source, channel, and drain regions are formed in a vertical direction.

As a means of defining the channel length L _C of the v-FET, and controlled by the etching depth of the groove to be formed in the single crystal silicon substrate in Patent Document 2, a thickness of a silicon single crystal thin film by an epitaxial growth method in Patent Document 3 I have control. In the manufacturing process of silicon semiconductors, it is generally known that the controllability, reproducibility, and uniformity among lots, wafers, and wafers with an epitaxially grown film thickness are superior to the etching depth. In addition, if an epitaxial growth method is used, it is easy to introduce a desired impurity at a desired concentration into a growing film. Therefore, the source, channel, and drain regions can be controlled with a single epitaxial growth process with good controllability. Compared to an etching method that can be formed and requires a complicated additional manufacturing process for introducing impurities into the semiconductor thin film, the manufacturing process can be greatly simplified. A perspective view of a typical shape of a v-FET using the epitaxial growth method is shown in FIG. The channel 161 of this v-FET is a region sandwiched between a source region 170 and a drain region 180 formed in a silicon single crystal island region 105 having a width of _Wisl , and includes a gate electrode 150 and a gate insulator film. 140 is formed on both side surfaces in contact with each other through 140. Therefore, the channel length L _C of the v-FET is determined by the channel length L _C that is the distance between the source region 170 and the drain region 180. the channel width W of the v-FET, if the gate electrode length and W _g, since the channel 161 is formed on both side surfaces of the island regions 105 of the silicon single crystal is given by 2W _g. Therefore, the drain current density is twice that of the conventional planar structure MOSFET, and has the advantage of p-FinFET. If the source, channel, and drain region forming method using the epitaxial growth method proposed for the v-FET is used, the fin width W _fin and the gate electrode length described in the above problem (1) of the p-FinFET are described. of two very fine photolithographic steps required for the formation of L _g, forming a gate electrode length L _g which defines the channel length L _C is not required. Further, since the source, channel and drain regions can be formed by one epitaxial growth, the manufacturing process can be greatly simplified. However, it has been difficult to apply a conventional v-FET as shown in FIG. 11 to a FinFET without any modification. In order to further reduce the size of the MOSFET, the channel region can be completely depleted easily even when a very fine channel region is formed by an epitaxial growth method using the v-FET structure, and the subthreshold current can be reduced. There has been a demand for a MOS type semiconductor device that does not deteriorate in characteristics and is easy to manufacture with high performance and a method for manufacturing the same. In addition, a great problem remains with respect to the method for extracting the source and drain electrodes. Furthermore, in the conventional v-FET, an example for specifically solving the problems (2) to (4) of the above-described p-FinFET has not been made, and it remains as a serious problem. Further, a selective epitaxial growth method which is one of the epitaxial growth methods is described in Non-Patent Document 3, and a desired MOS type semiconductor device can be obtained by combining different semiconductor materials or changing the composition ratio of the same kind of mixed crystal semiconductor. Is described in Non-Patent Document 2.

JP 2003-229575 A (3-4 pages, FIGS. 1 and 2) Japanese Patent Laid-Open No. 1-290263 (Fig. 1) JP-A-49-89492 (FIGS. 2 and 3) B. Yu et al., “FinFET scaling to 10 nm gate length,” IEEE International Electron Devices Meeting Technical Digest, lecture number 10.2 (2002). T. Ghani et al., “A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors,” IEEE International Electron Devices Meeting Technical Digest, lecture number 11.6 (2003). M. Yang et al., “High performance CMOS fabricated on hybrid substrate with different crystal orientations,” IEEE International Electron Devices Meeting Technical Digest, lecture number 18.7 (2003).

  A first object of the present invention is a vertical structure for solving the problems (1) to (4) of a p-FinFET while applying the advantages of the v-FET to a conventional p-FinFET. It is to provide FinFET (hereinafter referred to as v-FinFET) which is a MOS type semiconductor device. The second object of the present invention is to specifically provide a method for producing the above-mentioned v-FinFET. A third object of the present invention is to provide a multi-element MOS semiconductor device having a CMOS structure in which n-channel and p-channel v-FinFETs are integrated on the same substrate, and a method for manufacturing the same. It is in.

  In order to achieve the first object, a vertical semiconductor in which a source region, a drain region, and a channel region sandwiched between the source region and the drain region are formed of a laminated film parallel to the substrate A thin-film fin, and a gate electrode disposed on the entire or part of the side surface of the channel region exposed on the side surface of the fin via a gate insulator film, and applied to the gate electrode A MOS type semiconductor device in which the fin is formed so that the channel region is completely depleted by the gate voltage is used.

By laminating the channel region in parallel to the substrate, it is possible to form the channel length L _C with a very short channel length by using an epitaxial growth method or the like excellent in film thickness controllability. . As a result, the MOS type semiconductor device can be miniaturized and the MOS type semiconductor device having excellent characteristics capable of high speed operation can be obtained. In addition, the two fine photolithography steps required for the conventional p-FinFET are only required once. As a result, the MOS semiconductor device can be easily manufactured and the manufacturing variation can be reduced. Therefore, the variation in the operation speed and the unstable operation of the conventional MOS semiconductor device can be greatly improved. And, by forming the fin so that the channel region is completely depleted by the gate voltage applied to the gate electrode, the subthreshold current characteristics are good and the standby is possible even with an extremely fine channel length. A MOS semiconductor device having low power and excellent characteristics is obtained. In other words, the MOS type semiconductor device of the present invention has a relatively short channel length, a small and excellent p-FinFET of the conventional p-FinFET, and the channel region is stacked parallel to the substrate. Focusing on the structure, forming the channel region extremely thin using an epitaxial growth method etc., further miniaturizing the channel length while further depleting the channel region, further miniaturization of the MOS type semiconductor device, While achieving both high performance, it has greatly improved the difficulty of processing, which was the biggest problem.

  The planar shape of the fin is not particularly limited and may be a polygon or a circle. The channel region may be formed so that the channel region is completely depleted by the gate voltage applied to the gate electrode.

  At this time, the gate electrode is disposed on at least one pair of opposing two surfaces of the side surface of the channel region exposed on the side surface of the fin via the gate insulator film, and the gate electrode is interposed via the gate insulator film. The distance between at least one pair of the two opposing surfaces of the channel region facing each other is the interval at which the channel region is completely depleted by the gate voltage applied to the gate electrode. The MOS semiconductor device formed below can be obtained.

  Dispersion of electric field strength in the channel region is reduced by arranging the gate electrode on at least one pair of opposing two sides of the side surface of the channel region exposed on the side surface of the fin via the gate insulator film. Thus, a MOS semiconductor device in which the channel region is easily depleted easily is obtained.

The fact that the channel region is easily depleted means that the channel region can be completely depleted with a lower gate voltage. In addition, assuming that the gate voltages are the same, the channel region can be completely depleted even with a wider fin width W _fin . Thereby, the yield in a manufacturing process improves. In other words, even when the width W _fin of the fin, which requires fine processing in the manufacturing process, varies and is formed to be somewhat large, the MOS semiconductor device can absorb the variation and completely deplete the channel region. It is. Further, the gate electrode is disposed via the gate insulator film, and at least one set of the distances between the two opposing surfaces of the channel region is applied to the gate electrode. Since the channel region is formed below the interval at which the channel region is completely depleted by voltage, the subthreshold current characteristics are good, the standby power is small, and the characteristics are excellent, even with extremely miniaturized channel lengths. It becomes a MOS type semiconductor device.

The planar shape of the fin is not particularly limited and may be a polygon or a circle. At least one of the two opposing surfaces of the channel region where the gate electrode is disposed is completely depleted by the gate voltage applied to the gate electrode. What is necessary is just to be formed below the space | interval made. When the fin shape is a parallelogram and the gate electrode is disposed on all four side surfaces of the channel region, the distance between the two opposing surfaces of the channel region where the gate electrode is disposed is There are two intervals, and it is only necessary that the interval between at least one pair of two opposing surfaces be less than the interval at which the channel region is completely depleted by the gate voltage applied to the gate electrode. That is, it is only necessary that the shorter one of the two intervals is formed to be equal to or less than the interval at which the channel region is completely depleted by the gate voltage applied to the gate electrode. When the planar shape of the fin is circular, the distance between two opposing surfaces of the channel region where the gate electrode is disposed is the diameter of the circular fin. In this case, “disposed through at least one pair of opposing two surfaces of the side surface of the channel region via the gate insulator film” means that the gate insulator is formed on all side surfaces of the channel region exposed on the side surface of the circular fin. When the gate electrode is disposed through the film, or the gate electrode is disposed through the gate insulator film at two opposite sides (two surfaces) of the side surface of the channel region exposed on the side surface of the circular fin. Including the case. In the MOS type semiconductor device of the present invention, the shortest distance among the distances between two opposing surfaces of the channel region where the gate electrode is disposed is the fin width W _fin .

  The fin has a quadrilateral planar shape, and the gate electrode is disposed on at least two opposite sides in the longitudinal direction of the channel region on the side surface of the channel region exposed on the side surface of the fin via the gate insulator film. It is preferable that the MOS type semiconductor device is formed so that the distance between the two opposing surfaces in the longitudinal direction of the region is equal to or less than the interval at which the channel region is completely depleted by the gate voltage applied to the gate electrode.

In the v-FinFET of the present invention, since the source, channel and drain regions are stacked in the vertical direction of the fin, the distance in the short direction of the quadrilateral fin is the width of the fin of the conventional p-FinFET. narrows formed W _fin comparable, if disposed longitudinally opposite dihedral gate electrode through a gate insulating film on the channel region, a longitudinal whole area of the channel region, is applied to the gate electrode The gate voltage is kept in a fully depleted state. Therefore, the distance in the longitudinal direction of the fin has a high degree of freedom in design, and the channel width W can be continuously varied only by changing the distance, and a MOS semiconductor device that meets the required specifications can be easily designed. As will be described later, a CMOS inverter circuit formed by combining a plurality of MOS semiconductor devices can be remarkably reduced in size.

In the v-FinFET, in order to completely deplete the channel region, it is necessary to process the _fin width W _{fin very} finely like the conventional p-FinFET. It is conceivable that the electrical characteristics of the v-FinFET vary due to variations in the _fin width W _fin , causing a problem in the LSI. Therefore, it is also preferable that the gate electrode be a MOS semiconductor device that is disposed in contact with the entire side surface of the channel region exposed on the side surface of the fin via the gate insulator film. As a result, the channel region is more easily depleted, and the yield in the manufacturing process is further improved. Therefore, even if the channel length is extremely miniaturized, the MOS semiconductor device has excellent subthreshold current characteristics, low standby power, excellent characteristics, and very easy to manufacture.

  In the conventional p-FinFET and v-FET, it is impossible to dispose a gate electrode over the entire side surface of the channel region exposed on the side surface of the fin. However, since the source, channel and drain regions of the v-FinFET of the present invention are stacked in the vertical direction of the fin, the gate electrode is exposed to the side surface of the fin through the gate insulator film. It is easy to arrange in a state in contact with the entire surface. As a result, the electric field distribution in the channel becomes more uniform, and the channel region is more easily depleted.

The fin has a circular planar shape, and the gate electrode is a MOS type semiconductor device disposed in contact with the entire side surface of the channel region exposed on the side surface of the fin via the gate insulator film. Is also preferable. By making the planar shape of the fin circular, the electric field in the channel can be made more uniform, and the channel region can be further fully depleted. Compared with a quadrilateral _fin having the same fin width W _fin , the channel region can be completely depleted with a lower gate voltage when the circular fin is used. In addition, assuming that the gate voltages are the same, the channel region can be completely depleted by using a circular _fin even with a wider fin width W _fin .

  A conductor pattern for conducting a region located on the substrate side of the source region or drain region and a lead electrode of the source region or drain region provided in the MOS type semiconductor device is formed on the substrate side of the source region or drain region. It is also preferable to use a MOS semiconductor device in which the substrate region side surface of the located region is electrically connected to the extraction electrode of the source region or drain region via the outside of the gate electrode.

  Accordingly, the conduction between the source region or the drain region and the extraction electrode can be ensured regardless of the arrangement of the gate electrodes. In particular, even when the gate electrode is disposed in contact with the entire side surface of the channel region exposed on the side surface of the fin, the MOS type in which conduction between the source region or the drain region and the extraction electrode is ensured. It becomes a semiconductor device.

  In this case, the conductor pattern is in contact with substantially the entire surface of the source region or drain region located on the substrate side on the substrate side, and the conductor pattern is in a direction parallel to the substrate and the source region or drain region. 7. The MOS semiconductor device according to claim 6, wherein the drain region is drawn out in a direction perpendicular to the longitudinal direction of the substrate-side surface of the region located on the substrate side.

  By extracting the conductor pattern in a direction parallel to the substrate and in a direction perpendicular to the longitudinal direction of the substrate-side surface of the source region or drain region located on the substrate side, the entire conductor pattern is extracted. It can be formed thick and the wiring resistance value is greatly reduced. As a result, a MOS semiconductor device having a small parasitic series resistance and excellent electrical characteristics is obtained. When the planar shape of the fin is circular, the surface on the substrate side of the region located on the substrate side of the source region or the drain region is also circular, and the concept of the longitudinal direction does not exist. In this case, as long as the direction is parallel to the substrate, no great difference is caused in the parasitic series resistance regardless of which direction the conductor pattern is drawn.

  The fin is preferably a MOS type semiconductor device formed on the upper surface side of an insulator film formed on the substrate. Although it is possible to configure the v-FinFET of the present invention using a silicon single crystal substrate, the fins are formed on the upper surface side of the insulator film formed on the substrate, so that the source, drain, and gate are formed. It is possible to obtain electrical characteristics of a higher-performance MOS semiconductor device having a small parasitic capacitance. Specifically, fin, source, drain, and gate regions, electrodes thereof, and interconnections are formed on the upper surface side of the buried insulator film using an SOI substrate.

  It is also preferable to use a MOS semiconductor device having a region where impurities are selectively introduced at least on the side surface of the channel region of the fin. By selectively introducing a predetermined impurity into the side surface of the channel region by an oblique ion implantation method or the like, the so-called short channel effect that deteriorates the subthreshold current characteristics can be further improved. That is, the standby power can be reduced by increasing the threshold voltage to reduce the leakage current.

  Fin is a MOS type semiconductor composed of a group IV semiconductor single crystal thin film, a group III-V semiconductor single crystal thin film, a group II-VI semiconductor single crystal thin film, a polycrystalline thin film of these semiconductors, or an amorphous thin film of those semiconductors An apparatus is also preferred. By using fin materials that meet the required specifications, MOS semiconductor devices with various electrical characteristics can be obtained. Examples of the group VI semiconductor include Ge, SiGe, C, and SiC, examples of the III-V group semiconductor include GaAs, GaP, and GaN, and examples of the group II-IV semiconductor include ZnSe and the like.

  The fin is preferably a MOS semiconductor device which is a laminated film in which semiconductor thin films of different semiconductor materials or semiconductor thin films in which the composition ratio of the same kind of mixed crystal semiconductor material is changed are combined. Thereby, a MOS semiconductor device having desired electrical characteristics can be obtained. For example, as described in Non-Patent Document 2, in order to form a strained silicon region having a high carrier mobility, Si, Ge, or SiGe is combined, or the same kind of mixture is used so as to change the composition ratio of SiGe. A laminated film of semiconductor thin films in which the composition ratio of the crystal semiconductor is changed can also be used.

  A multi-element MOS semiconductor device comprising a combination of a plurality of MOS semiconductor devices, wherein the multi-element MOS semiconductor device includes MOS semiconductor devices having different channel region thicknesses among the plurality of MOS semiconductor devices. A semiconductor device is also preferable. As a result, a multi-element MOS semiconductor device having desired electrical characteristics according to various required characteristics is obtained.

  In order to achieve the second object, the MOS semiconductor device manufacturing method of the present invention has a size approximately equal to the planar shape of a fin, which is a desired vertical semiconductor thin film, on an insulator layer formed on a substrate. A step of forming an opening, a source or drain region in the opening, a channel region on the region, and a drain or source region on the channel region stacked in parallel to the substrate. A step of forming a fin, a step of exposing a side surface of the channel region on the side surface of the fin from the insulator layer, and a gate insulator film on the whole or a part of the exposed side surface of the channel region. And a step of providing a gate electrode.

  At this time, in the step of forming the opening, the planar shape of the fin, which is a desired vertical semiconductor thin film, is formed through the gate insulator film on the entire or part of the side surface of the channel region exposed on the side surface of the fin. Thus, a MOS semiconductor device manufacturing method having a planar shape in which the channel region is completely depleted by the gate voltage applied to the gate electrode disposed in this manner.

  Further, the planar shape of the fin forming the v-FinFET which is the MOS semiconductor device according to the present invention and the size of the opening of the insulator film do not necessarily coincide with each other, and the opening is larger than the planar shape of the fin. Then, after depositing a desired single crystal semiconductor thin film, it may be processed into a desired fin shape by using a photolithography technique. Therefore, a step of forming an opening larger than the planar shape of the fin, which is a desired vertical semiconductor thin film, in the insulator layer formed on the substrate, a source or drain region in the opening, and the region Forming a vertical semiconductor thin film by stacking a drain region or a source region on the channel region, processing the semiconductor thin film into a planar shape of the fin, and exposing to a side surface of the fin And a step of disposing a gate electrode on the entire side surface or a part of the side surface of the channel region through a gate insulator film.

  At this time, in the process of processing the semiconductor thin film into the planar shape of the fin, the planar shape of the fin, which is a desired vertical semiconductor thin film, is gated on the entire or part of the side surface of the channel region exposed on the side surface of the fin. A multi-element MOS semiconductor device manufacturing method having a planar shape in which a channel region is completely depleted by a gate voltage applied to a gate electrode disposed via an insulator film can be provided. .

  In a step of forming a fin or a vertical semiconductor thin film, a selective epitaxial growth method is used to grow a fin or a vertical semiconductor thin film only in an opening formed in an insulator layer. A manufacturing method is preferred. In the process of forming fins that are vertical semiconductor thin films or the process of forming vertical semiconductor thin films, by using a selective epitaxial growth method, lots of vertical semiconductor thin films, wafers, wafers, chips, and Excellent controllability, reproducibility, and uniformity within the chip. As a result, the manufacturing method of a MOS semiconductor device with little characteristic variation and good yield is obtained. In addition, if an epitaxial growth method is used, it is easy to introduce a desired impurity at a desired concentration into a growing film. Therefore, the source, channel, and drain regions can be controlled with a single epitaxial growth process with good controllability. Compared to an etching method that can be formed and requires a complicated additional manufacturing process for introducing impurities into the semiconductor thin film, the manufacturing process can be greatly simplified.

  In this case, the film thickness of the fin or the vertical semiconductor thin film is grown so as to be approximately equal to the thickness of the insulator layer in which the opening is formed. This eliminates the need for polishing for planarizing the surface of the v-FinFET using a CMP method or the like, which will be described later, and simplifies the manufacturing process.

  It is also preferable to use a method for manufacturing a MOS type semiconductor device having a step of forming a region selectively doped with an impurity using an oblique ion implantation method on at least the side surface of the channel region of the fin. Thereby, it is possible to control more precise electrical characteristics of the MOS type semiconductor device, for example, the threshold voltage.

  In the semiconductor device manufacturing apparatus of the present invention, a fin forming process, a gate electrode forming process, and a contact opening are provided in order to facilitate ultra fine pattern formation in a photolithography process and facilitate processing in a multilayer wiring process. It is also preferable to apply a CMP (Chemical-Mechanical Polishing) method as much as possible as means for flattening the cross-sectional shape of the work piece of the v-FinFET as much as possible in each process such as a hole filling process.

  In order to achieve the third object, the semiconductor device of the present invention is a multi-element MOS semiconductor device formed by combining a plurality of the MOS semiconductor devices, and an n-channel MOS semiconductor device and A multi-element MOS semiconductor device is formed by forming a CMOS circuit by forming a p-channel MOS semiconductor device on the same substrate.

  In this case, the first fin constituting the n-channel type MOS semiconductor device and the second fin constituting the p-channel type MOS semiconductor device are constituted by a laminated film of the same type of semiconductor thin film. A multi-element MOS semiconductor device can be obtained.

  The first fin constituting the n-channel type MOS semiconductor device and the second fin constituting the p-channel type MOS semiconductor device are composed of stacked semiconductor thin films made of different semiconductor materials or compositions. It is preferable to use a multi-element MOS semiconductor device. For example, an n-channel v-FinFET is formed using a semiconductor material having a high electron mobility in accordance with the required use of a multi-element MOS semiconductor device, and p is formed using a semiconductor material having a high hole mobility. A channel-type v-FinFET may be configured. In addition, it is desirable to use a common constituent material for the gate insulator film and the gate electrode of the v-FinFET of both channels in order to simplify the manufacturing process. In order to realize the above, a gate insulator film or a gate electrode having different materials, compositions, and film thicknesses may be used for n-channel and p-channel v-FinFETs. As a result, a CMOS circuit having significantly superior electrical characteristics can be realized as compared with the case where both channel v-FinFETs are formed of single crystal silicon.

A multi-element MOS type in which the gate insulator film constituting the n-channel type MOS semiconductor device and the gate insulator film constituting the p-channel type MOS semiconductor device are different in film thickness, composition or material. A semiconductor device is also preferable. By changing the film thickness, composition, or material of the gate insulator film, the electrical characteristics of the n-channel and p-channel v-FinFETs can be controlled independently, and a multi-element MOS semiconductor that meets the required characteristics It becomes a device. As the gate insulator film, in addition to the silicon oxide film, a silicon nitride oxide film, a silicon nitride film, a high dielectric film such as Ta ₂ O ₅ , HfO ₂ , a multilayer film of a silicon oxide film or the like and a high dielectric film May be used.

An electrode material having a different film thickness, composition, or material, or a semiconductor composition, material, and a gate electrode constituting an n-channel MOS semiconductor device and a gate electrode constituting a p-channel MOS semiconductor device, A multi-element MOS semiconductor device using semiconductor electrode materials having different conductivity types or different impurity concentrations is also preferable. By changing the film thickness, composition, or material of the gate electrode, the electrical characteristics of the n-channel and p-channel v-FinFET structure MOS semiconductor devices can be controlled independently, and the multi-element type meets the required characteristics. This is a MOS type semiconductor device. The gate electrode is not limited to a polycrystalline silicon film normally used in a conventional planar MOS semiconductor device, but is a polycrystalline semiconductor film such as a polycrystalline Ge film or a polycrystalline SiGe film, TiSi ₂ Film, various silicide films such as CoSi ₂ film, semiconductor-metal alloy film, metal film such as Al, Mo, W, etc., single layer film of such alloy film, and various gate electrode materials described above A multilayer film may be used in combination.

  In order to achieve the third object, a method for manufacturing a semiconductor device according to the present invention provides a desired vertical structure for forming an n-channel MOS semiconductor device on a first insulator layer formed on a substrate. Forming a first opening having a size substantially equal to the planar shape of the first fin, which is a semiconductor thin film of the type, a source or drain region in the first opening, and a channel region on the region And forming a first fin by laminating a drain or source region on the channel region in parallel to the substrate, and forming a second insulator layer on at least the first fin. A p-channel type MOS semiconductor in a step and the first insulator layer, the second insulator layer, or an insulator layer in which the first insulator layer and the second insulator layer overlap A first vertical semiconductor thin film for constructing the device. Forming a second opening having a size substantially equal to the planar shape of the fin, a source or drain region in the second opening, a channel region on the region, a drain or on the channel region Forming a second fin by laminating a source region in parallel with the substrate; and side surfaces of the channel regions of both the first fin and the side surfaces of the second fin A body layer, the second insulator layer or the step of exposing the first insulator layer and the insulator layer where the second insulator layer overlaps, and the entire side surfaces of both exposed channel regions or And a step of disposing a gate electrode on a part of the surface through a gate insulator film.

  In the case where the second insulator layer is formed on the first fin and on the first insulator layer, the second opening includes the first insulator layer and the second insulator layer. Overlapping insulator layers are formed. When the second insulator layer is selectively formed only on the first fin, the second opening is formed in the first insulator layer. When the second insulator layer is deposited thick enough to hide the first fin after the first insulator layer is removed, the second opening is formed in the second insulator layer. It will be.

  After the step of forming the first fin, which is a vertical semiconductor thin film, the second insulator layer is formed on the first fin and the second insulator layer is also formed on the first insulator layer. A second vertical thin semiconductor film for forming a p-channel MOS semiconductor device is formed on the insulator layer formed by overlapping the first insulator layer and the second insulator layer. What is necessary is just to form the 2nd opening part substantially equal to the planar shape of this fin. In addition, after the step of forming the first fin, which is a vertical semiconductor thin film, the first insulator layer is removed, and then the second insulator layer is formed thick. A second opening substantially equal to the planar shape of the second fin, which is a desired vertical semiconductor thin film for constituting a p-channel MOS semiconductor device, may be formed.

  At this time, in the step of forming the opening, the planar shape of the fin, which is a desired vertical semiconductor thin film, is formed through the gate insulator film on the entire or part of the side surface of the channel region exposed on the side surface of the fin. Thus, a multi-element MOS semiconductor device manufacturing method having a planar shape in which the channel region is completely depleted by the gate voltage applied to the gate electrode disposed in this manner.

  In order to achieve the third object, the first insulator layer formed on the substrate is a first vertical semiconductor thin film that is a desired vertical semiconductor thin film for forming an n-channel MOS semiconductor device. Forming a first opening larger than the planar shape of the fin, a source or drain region in the first opening, a channel region on the region, and a drain or source region on the channel region. Forming a vertical semiconductor thin film for forming an n-channel MOS semiconductor device by stacking layers in parallel with the substrate, and forming a second insulator layer on at least the first fin A p-channel MOS type on the first insulator layer, the second insulator layer, or the insulator layer in which the first insulator layer and the second insulator layer overlap with each other. Desired vertical semiconductor for constituting a semiconductor device Forming a second opening larger than the planar shape of the second fin, which is a film, a source or drain region in the second opening, a channel region on the region, and a channel region on the channel region A step of forming a vertical semiconductor thin film for forming a p-channel MOS semiconductor device by laminating drain or source regions parallel to the substrate, and forming the n-channel MOS semiconductor device Simultaneously processing a semiconductor thin film for forming the semiconductor thin film for forming the p-channel MOS semiconductor device into a planar shape of the first fin or a planar shape of the second fin; And a step of disposing a gate electrode through a gate insulator film on the whole or a part of the side surfaces of both channel regions exposed on the side surfaces of the first fin and the second fin. And as the manufacturing method of the type MOS semiconductor device.

  If this manufacturing process is used, the photolithography process required to form an extremely fine pattern necessary for forming the first fin and the second fin is changed from two times to one time, and the photolithography process is simplified. In addition, it is possible to realize more precise control and better reproducibility of the fin shape constituting the MOS type semiconductor device having the v-FinFET structure of both channels.

  At this time, in the process of processing the semiconductor thin film into the planar shape of the fin, the planar shape of the fin, which is a desired vertical semiconductor thin film, is gated on the entire or part of the side surface of the channel region exposed on the side surface of the fin. A multi-element MOS semiconductor device manufacturing method having a planar shape in which a channel region is completely depleted by a gate voltage applied to a gate electrode disposed via an insulator film can be provided. .

  A multi-element MOS in which a fin or a vertical semiconductor thin film is grown only in an opening formed in an insulator layer using a selective epitaxial growth method in a step of forming a fin or a step of forming a vertical semiconductor thin film It is preferable to use a method for manufacturing a semiconductor device.

  In this case, a method for manufacturing a multi-element MOS semiconductor device, in which the thickness of the fin or the thickness of the vertical semiconductor thin film is grown so as to be substantially equal to the thickness of the insulator layer in which the opening is formed, can do.

  A method of manufacturing a multi-element MOS semiconductor device including a step of forming a region selectively doped with an impurity using an oblique ion implantation method on at least a side surface of a channel region of a fin which is a vertical semiconductor thin film It is also preferable.

  It is also preferable to use a method of manufacturing a multi-element MOS semiconductor device including a step of forming the first fin and the second fin with different semiconductor materials or compositions.

  In order to further reduce the size of the MOSFET, the channel region can be completely depleted easily even when a very fine channel region is formed by an epitaxial growth method or the like by applying the structure of the v-FET. A MOS type semiconductor device that does not deteriorate current characteristics and is easy to manufacture and a method for manufacturing the same have been realized.

  1 to 3 show an n-channel v-FinFET which is a MOS semiconductor device according to the present invention. FIG. 1 is a sectional structural view thereof, and FIG. 2 is an enlarged sectional structural view of a portion P in FIG. FIG. 3 shows a plan layout diagram of FIG. In FIG. 3, the fin 200 has substantially the same planar shape as the outer peripheral portion of the side wall 341 of the fifth insulator layer, and is located below the side wall 341 of the fifth insulator layer.

A buried insulator film 220 composed of a silicon oxide film or the like formed on the upper surface of the substrate 210 such as a silicon single crystal substrate, and a high height limited to be surrounded by the first insulator film 310 on the upper surface. An SOI substrate 21 on which an n ⁺ semiconductor thin film 230 such as a silicon single crystal semiconductor doped with an n-type impurity is formed, and a silicon single crystal thin film having a desired shape and configuration on the n ⁺ semiconductor thin film 230 And a fin 200 which is a vertical semiconductor thin film. The fin 200 is configured as an n ⁺ layer, an n layer, a p layer, an n layer, and an n ⁺ layer that are continuous in order from the lower surface in parallel to the base 210, and is a channel region formed by the p layer. A gate insulator film 240 such as a silicon oxide film is disposed in contact with the entire exposed side surface of the 260, and a gate electrode 250 such as a polycrystalline silicon film is disposed in contact with the gate insulator film.

  In the present embodiment, the gate electrode 250 is disposed in contact with all the side surfaces of the channel region 260 exposed on the side surfaces of the fin 200 via the gate insulator film 240, but the present invention is not limited thereto. . The channel region 260 may be disposed in contact with a part of the side surface. Considering that the channel region 260 is completely depleted, it is preferable to dispose the channel region 260 on at least one pair of two opposite sides of the side surface of the channel region 260. More preferably, as in this embodiment, the gate electrode 250 is disposed in contact with all of the side surfaces of the channel region 260. This is because the channel region 260 is more easily depleted.

It should be noted that various combinations of the constituent materials, compositions, and film thicknesses of the n ⁺ layer, n layer, p layer, n layer, and n ⁺ layer shown above may be considered in order to obtain the desired electrical characteristics of the v-FinFET. Needless to say. Furthermore, an impurity introduction region 261 into which a desired impurity is introduced is formed on the side surface of the channel region 260 by using an oblique ion implantation method or the like to control more precise electrical characteristics of the v-FinFET, for example, a threshold voltage. It is also possible to do this. In the case where the channel region is p-type as in this embodiment mode, B, In, or the like can be used as an impurity to be implanted into the impurity introduction region 261. When the channel region is a low concentration p-type, the short channel effect tends to be prominent. Therefore, it is preferable to use In that has a large mass and a small diffusion coefficient due to heat as an impurity. Further, the timing of implanting the impurities is preferably before the gate insulator film 240 is formed.

A source region 270 composed of an n layer and an n ⁺ layer on the lower surface side of the fin 200 passes through the outside of the gate electrode 250 via an n ⁺ semiconductor thin film 230 in contact with the entire surface of the source region 270 on the SOI substrate 21 side. Thus, it is connected to the extraction electrode 272 in the source region formed of a metal film such as W embedded in the contact opening 271 of the source electrode. That is, a conductor pattern that connects the source region 270 and the extraction electrode 272 in the source region is formed by the n ⁺ semiconductor thin film 230 and a metal film such as W embedded in the contact opening 271 of the source electrode. The n ⁺ semiconductor thin film 230 constituting the conductor pattern is drawn in the direction parallel to the SOI substrate 21 and perpendicular to the longitudinal direction of the surface of the source region 270 on the substrate side. As shown in FIG. 3, the n ⁺ semiconductor thin film 230 as the conductor pattern can be formed thick, and the wiring resistance value is greatly reduced.

The drain region extraction electrode 282 is buried in the contact opening 281 of the drain electrode opened on the upper surface of the n ⁺ layer of the drain region 280 formed of the n layer and the n ⁺ layer formed on the upper surface side of the fin 200. It is made of a metal film such as W. The gate extraction electrode 252 is formed of a metal film such as W embedded in the contact opening 251 of the gate electrode.

One of the great features of the present invention, it is possible arbitrarily set longitudinal channel width W _n of like conventional v-FET fin 200 is not required, the source, drain and electrodes drawer neck portion of the gate straight It is possible to pull out easily. Accordingly, since the electrode lead-out region 190 having a long interval D having a neck portion required in the conventional p-FinFET as shown in FIGS. 6 and 10 is not necessary, high integration density, particularly the source region 170, The series resistance of the drain region 180 can be significantly improved.

A first insulator layer 320 such as a silicon oxide film formed so as to surround the side surface on the lower surface side of the fin 200 is an interlayer insulator layer between the n ⁺ semiconductor thin film 230 and the gate electrode 250. Further, the fourth insulator layer 330 such as a silicon oxide film is an interlayer insulator layer between the gate electrode 250 and the extraction electrode 272 in the source region and the extraction electrode 282 in the drain region. In order to limit the contact opening 281 of the drain electrode to the inner region of the drain region 280, the side wall 341 of the fifth insulator layer such as a silicon oxide film may be formed so as to surround the periphery of the contact opening. Is possible.

In the n-channel type v-FinFET according to the present invention, the channel length L _Cn is equal to that of the p layer of the channel region 260 sandwiched between the n layer constituting the source region 270 of the fin 200 and the n layer constituting the drain region 280. Determined by thickness. If an epitaxial growth method is used to form the fin 200, the film thickness of each of the n ⁺ layer, n layer, p layer, n layer, and n ⁺ layer can be formed with extremely precise controllability and reproducibility. It is easy to realize a very fine channel length L _Cn . Therefore, since there is no need to use a conventional p-FinFET cutting edge very fine photolithography process is required in the step of forming the gate electrode length L _g of the gate electrode 250, thereby facilitating the manufacture. The gate electrode 250 is disposed on the entire side surface of the channel region 260 exposed on the side surface of the fin 200 via the gate insulator film 240, and the width W _fin of the _fin 200 is applied to the gate electrode 250. It is necessary to form the channel region 260 so narrow that the channel region 260 is completely depleted by the gate voltage applied. The width W _{fin of the} fin 200 is preferably 100 nm or less. If it is larger than 100 nm, it is difficult to completely deplete the channel region 260. The width W _{fin of the} fin 200 is more preferably 50 nm or less. The lower limit value of the width W _fin of the fin 200 is determined by the machining accuracy. With the current processing accuracy, the lower limit of the width W _fin of the fin 200 is about 10 nm. The height H _fin of the _fin 200 has an impurity distribution and a desired shape so that the source region 270 and the drain region 280 satisfy the desired electrical characteristics of the v-FinFET while ensuring the desired channel length L _Cn. Set as follows.

As shown in FIG. 3, in the present invention, since the channel of the MOS type semiconductor device is formed on both sides of the fin 200 as in the conventional p-FinFET, the longitudinal width of the fin 200 is set to W _n. For example, the channel width W is given by 2W _n .

Although the SOI substrate 21 having the buried insulator film 220 formed on the upper surface of the base 210 and the n ⁺ semiconductor thin film 230 formed on the upper surface is used as the substrate of the embodiment of FIGS. A structure in which fins are formed on a semiconductor substrate that is often used for the above is also possible. Further, a plurality of v-FinFETs having two or more types of p-layer film thicknesses (thicknesses of channel regions 260) serving as channel regions of the fins 200 that determine the channel length L _Cn of the v-FinFETs are formed on the same substrate. Accordingly, it is possible to integrate v-FinFETs having different channel lengths having desired electrical characteristics. In the embodiment shown in FIGS. 1 to 3, the gate electrode 250 is disposed so as to surround the entire periphery of the fin 200 formed in a rectangular shape with the gate insulator film 240 interposed therebetween. longitudinal fins 200 (i.e., W _n direction) or both side surfaces of the further addition fin width direction (i.e., W _fin direction) of may be formed on three sides including the one side of the. 1 to 3 exemplify the fin 200 having a rectangular planar shape, the planar shape of the fin may be any shape or layout such as a polygon or a circle. The shape in which the gate insulator film and the gate electrode are disposed can be arbitrarily set according to the planar shape.

FIG. 4 shows a plan layout diagram of a first other example of the v-FinFET when the plan shape of the fin 200 is a hexagon. In FIG. 4, the fin 200 has substantially the same planar shape as the hexagonal outer peripheral portion of the side wall 341 of the fifth insulator layer, and is located below the side wall 341 of the fifth insulator layer. In this case the channel width W is given by approximately 2W _n.

FIG. 5 shows a plan layout diagram of a second example of the v-FinFET when the plan shape of the fin 200 is circular. Also in FIG. 5, the fin 200 has substantially the same planar shape as the circular outer peripheral portion of the side wall 341 of the fifth insulator layer, and is located below the side wall 341 of the fifth insulator layer. In this case, the channel width W is expressed by the circumferential length of the fin 200 and is πW _fin (πW _n ).

Already a silicon single crystal substrate as a normally base 210 as illustrated, a silicon oxide film as the buried insulating film 220, n ⁺ it is conceivable to use a silicon single crystal thin film as a semiconductor thin film 230 and the fins 200, n ⁺ semiconductor thin film As a material of the 230 and the fin 200, a group IV semiconductor thin film other than silicon (for example, a thin film such as Ge, SiGe, C, and SiC), a group III-V semiconductor thin film (for example, GaAs, GaP, GaN, AlP, and the like) Etc.) and II-VI group semiconductor thin films (for example, thin films of ZnSe, ZnS, CdS, CdTe, etc.) can also be used. In addition, as one of the features of the present invention, since the epitaxial growth method is used as a method for forming the fin 200, it is possible to deposit a laminated film in which the above-described various semiconductor thin films are combined as the fin 200. -A FinFET can be realized.

FIG. 12 shows a cross-sectional structure of a CMOS inverter which is a multi-element MOS semiconductor device using a v-FinFET according to the present invention, and FIG. 13 shows a plan layout view thereof. In FIG. 13, the fins 201 and 202 have substantially the same planar shape as the quadrilateral outer peripheral portions of the side walls 341 and 342 of the fifth insulator layer, and are located below the side walls 341 and 342 of the fifth insulator layer. Moreover, the same number is given to those having the same function as the n-channel type v-FinFET shown in FIGS. In the case of a CMOS inverter circuit, the source, channel, and drain regions 270, 260, and 280 of the n-channel type v-FinFET are arranged on the upper surface of the n ⁺ semiconductor thin film 230 in parallel to the base 210 and n ⁺ layers from the lower surface. , N layer, p layer, n layer, and n ⁺ layer are formed as the first fin 201 deposited as a continuous laminated film in this order. Similarly, the source, channel, and drain regions 275, 265, and 285 of the p-channel type v-FinFET are formed on the upper surface of the p ⁺ semiconductor thin film 235 in parallel to the base 210 from the lower surface by the p ⁺ layer, the p layer, and the n layer. The second fin 202 is formed as a continuous laminated film in the order of the layer, the p layer, and the p ⁺ layer.

  A gate insulator film 240 and a gate electrode 255 having a desired shape are disposed around the first fin 201 and the second fin 202. As in the case of the n-channel v-FinFET shown in FIG. 1, impurities are introduced into the side surface of the channel region of the n-layer constituting the p-channel v-FinFET, particularly for controlling the threshold voltage. The region 266 can also be formed using an oblique ion implantation method or the like. As the impurity implanted into the impurity introduction region 266, As, P, or the like can be used when the channel region is n-type as in this embodiment. Further, the timing of implanting the impurities is preferably before the gate insulator film 240 is formed.

The n ⁺ and p ⁺ semiconductor thin films 230 and 235 are formed on the upper surface of the buried insulator film 220, and their periphery is formed so as to be surrounded by the first insulator film 310. In order to constitute a CMOS inverter, the gate electrodes 255 of the v-FinFETs of both channels are formed in common, and the inverter input signal _VIN is applied via the gate lead electrode 257. The output signal _VOUT is taken out by commonly connecting the extraction electrodes 282 and 287 in the drain regions of the n-channel and p-channel v-FinFETs. A power source V _SS (usually connected to GND) is applied to the extraction electrode 272 in the source region of the n-channel type v-FinFET, and a power source V _DD is applied to the extraction electrode 277 in the source region of the p-channel type v-FinFET. Applied. The first insulator layer 320 is an interlayer insulator layer between the gate and the source, and the fourth insulator layer 330 is an interlayer insulator layer between the gate and the drain.

The channel length L _Cn of the n-channel type v-FinFET of the present invention is the thickness of the p layer of the first fin 201 (that is, the thickness of the channel region 260), and the channel length L _Cp of the p-channel type v-FinFET is It is determined by the film thickness of the n layer of the fins 202 of 2 (that is, the film thickness of the channel region 265), and each is set so as to satisfy the desired v-FinFET characteristics.

According to the plan layout diagram of the CMOS inverter using the v-FinFET according to the present invention shown in FIG. 13, it is extremely simple compared to the plan layout of the CMOS inverter using the conventional p-FinFET shown in FIG. It can be seen that a high-density layout is realized. The channel widths of the n-channel and p-channel v-FinFETs of the present invention are given by 2W _n and 2W _p equal to twice the longitudinal direction of the first fin 201 and the second fin 202. In order to equalize the drain current values flowing in the n-channel and p-channel v-FinFETs and to make the rising and falling switching times substantially the same, as in the conventional planar structure CMOS inverter, 2 W _n and the ratio of 2W _p, may be set to be inversely proportional to the mobility of electrons and holes. Therefore, the conventional p-FinFET is not a digital adjustment determined by the ratio of the number of fins connected in parallel. If the v-FinFET of the present invention is used, the channel length can be precisely set only by setting the length of the channel. It has a great feature that the width ratio can be adjusted. Since the layout of the v-FinFET of the present invention can be formed by one isolated large island-shaped _fin having an extremely fine pattern width W _fin , mutual fins required in the conventional parallel-connected p-FinFET are used. There is no need for a gap region for separating the gaps. For this reason, there is an advantage that the pattern layout is greatly simplified and the integration density is almost doubled in the channel width direction. Therefore, in the present invention, the process of forming an extremely fine repetitive pattern as shown in FIGS. 5 to 33 of Patent Document 1 is not required, and the fin pattern forming process can be greatly simplified. Also have.

Also, the v-FinFET of the present invention, since the channel length _{L C} settable in thickness control of the semiconductor thin film by epitaxial growth method, the conventional gate electrode length required by p-FinFET _{L g} (see FIG. 6) A photolithography process for forming an extremely fine pattern for processing is not required. Furthermore, since the film thickness of the semiconductor thin film by the epitaxial growth method can be controlled with extremely high precision compared to the line width control of pattern formation by the photolithography method, the channel length L _C between lots, wafers, wafers, and chips In addition, the reproducibility, controllability and uniformity within the chip are greatly improved.

  It should be noted that a semiconductor material having high electron mobility is applied to the first fin 201 of the semiconductor thin film constituting the n-channel type v-FinFET, and a high positive polarity is applied to the second fin 202 of the semiconductor thin film constituting the p-channel type v-FinFET. If a semiconductor material having hole mobility is used, a CMOS inverter circuit having significantly superior electrical characteristics can be realized as compared with the case where both channel v-FinFETs are formed of single crystal silicon. Further, in order to independently control the electrical characteristics of the n-channel and p-channel v-FinFETs, the gate insulator film 240 and the gate electrode 255 may be formed with different film materials, compositions and film thicknesses. In addition, it is also possible to form these plural types of v-FinFETs on the same substrate.

In the embodiment of the CMOS inverter, the planar shape of the fin is a quadrilateral, but is not limited to this, and a hexagonal or circular fin may be used. An example of using circular fins is shown in FIG. In FIG. 14, the fins 201 and 202 have substantially the same planar shape as the circular outer peripheral portions of the side walls 341 and 342 of the fifth insulator layer, and are located below the side walls 341 and 342 of the fifth insulator layer. In this embodiment, a plurality of circular second fins 202 having the same shape are arranged so that the drain current values flowing in the n-channel and p-channel v-FinFETs are equal to each other, and the rising and falling switching times are substantially reduced. Although it is equivalent, it is not limited to this. The first fin 201 of the semiconductor thin film that constitutes the n-channel type v-FinFET and the second fin 202 of the semiconductor thin film that constitutes the p-channel type v-FinFET are composed of one by one, and their diameters are changed. The switching time for rising and falling may be made substantially equal. In this embodiment, since the planar shape of the channel region is circular, a CMOS inverter that is advantageous due to complete depletion of the channel region is obtained. For example, the channel region can be completely depleted with a lower gate voltage when the circular fins 201 and 202 are used as compared with the case of a quadrilateral _fin having the same fin width W _fin . On the premise that the gate voltages are the same, the channel region can be completely depleted by using the circular fins 201 and 202 even with a wider fin width W _fin . For this reason, even if the width W _fin of the fin, which is a microfabrication process, varies in the manufacturing process, the variation can be absorbed and the channel region can be completely depleted, and the CMOS inverter has a high manufacturing yield and is easy to manufacture. It becomes.

A method for manufacturing a CMOS inverter composed of v-FinFETs according to the present invention will be described with reference to cross-sectional structure diagrams shown in FIGS. 15a to 19f. As the substrate, an SOI substrate 21 is used in which a buried insulator film 220 such as a silicon oxide film and a semiconductor thin film 225 such as a silicon single crystal thin film are laminated on a base 210 such as a silicon single crystal base ( FIG. 15a). The semiconductor thin film 225 in this case is an n-type or p-type or a high specific resistance semiconductor thin film that does not substantially contain impurities. An island-like region of the semiconductor thin film 225 surrounded by a first insulator film 310 such as a silicon oxide film is formed using a means such as a selective oxidation method. Next, a high-concentration n-type impurity that becomes a part of the source region of the n-channel type v-FinFET is used for the semiconductor thin film in these island-shaped regions by using means such as a combination of photolithography and ion implantation. and ^{n +} semiconductor thin film 230 comprising, to form a ^{p +} semiconductor film 235 containing a high concentration p-type impurity serving as a part of the source region of the p-channel type v-FinFET (Figure 15b). A first insulator layer 320 such as a silicon oxide film or a silicon nitride film having a film thickness substantially equal to the height of the first fin 201 constituting the n-channel v-FinFET is deposited on the entire surface, and the first An opening having a size substantially equal to the planar shape of the first fin 201 is formed in the insulator layer 320. Using a selective epitaxial growth method as described in Non-Patent Document 3, an n ⁺ layer, an n layer, a p layer, and an n layer that should serve as the first fin 201 of the n-channel v-FinFET only in the opening. Then, the n ⁺ layer is successively grown from the bottom in parallel with the substrate to selectively grow the laminated film. In this selective epitaxial growth step, no semiconductor thin film is deposited on the upper surface of the first insulator layer 320 (FIG. 15c).

If necessary, the surface is planarized using a CMP (Chemical-Mechanical Polishing) method. A second insulator layer 321 such as a silicon oxide film or a silicon nitride film is deposited on the entire surface, and then a p-channel type layer is formed on the laminated film of the first insulator layer 320 and the second insulator layer 321. An opening having substantially the same planar shape as that of the second fin 202 of the v-FinFET is formed (FIG. 15d). Using the selective epitaxial growth method, a laminated film composed of a p ⁺ layer, a p layer, an n layer, a p layer, and a p ⁺ layer is sequentially deposited from the bottom in parallel with the substrate using the selective epitaxial growth method (FIG. 15e). Next, in order to make the heights of the first fins 201 and the second fins 202 substantially equal, planarization is performed using a CMP method (FIG. 15f). In this embodiment, an opening is formed in the laminated film of the first insulator layer 320 and the second insulator layer 321 (FIG. 15d), but the first insulator layer 320 is completely removed. Thereafter, the second insulator layer may be deposited thick enough to hide the first fin 201 to form an opening on the second insulator layer (the first insulator layer in FIG. 15d). 320 and the second insulator layer 321 occupies only the second insulator layer). In addition, after the second insulator layer 321 is selectively deposited only on the upper side of the first fin 201, an opening may be formed on the first insulator layer 320, or the second insulation layer may be formed. Before the body layer 321 is selectively deposited only on the upper side of the first fin 201, an opening may be formed on the first insulator layer 320.

  In the present embodiment, the shape of the opening formed in the insulator layers 320 and 321 is such that the gate electrode 155 disposed on the entire side surfaces of the channel regions 260 and 265 exposed on the side surfaces of the fins 201 and 202 via the gate insulator film. The planar shape of the fins 201 and 202 is such that the channel regions 260 and 265 are completely depleted by the gate voltage applied to the, but the present invention is not limited to this. If the planar shape of the fins 201 and 202 is such that each channel region is completely depleted, the gate electrode 155 need not be disposed on the entire side surface of the channel region via a gate insulator film. Good. However, it is easier to completely deplete the channel region if the gate electrode is provided on the entire side surface of the channel region.

In the present embodiment, the width W _fin (see FIG. 13) of the fins 201 and 202 is preferably 100 nm or less. If it is larger than 100 nm, it is difficult to completely deplete the channel region. The width W _{fin of the} fins 201 and 202 is more preferably 50 nm or less. The lower limit value of the width W _fin of the fins 201 and 202 is determined by the machining accuracy. With the current processing accuracy, the lower limit value of the width W _fin of the fins 201 and 202 is about 10 nm.

Below, the 1st another example which implement | achieved the manufacturing process from FIG. 15b to FIG. 15f using another manufacturing method is demonstrated using FIG. From the state of FIG. 15b formed in the above-described process, the first insulator layer 320 is deposited on the entire surface, and an opening sufficiently larger than the planar shape of the first fin 201 constituting the n-channel v-FinFET is formed. Then, using the selective epitaxial growth method, the n ⁺ layer, the n layer, the p layer, the n layer, and the n ⁺ layer are successively grown from the bottom in parallel to the substrate, and the first semiconductor thin film is laminated. A film 205 is selectively formed. If necessary, the surface thereof is planarized using a CMP method. After the second insulator layer 321 is deposited on the upper surface, the second fin 202 constituting the p-channel v-FinFET is formed on the laminated film of the second insulator layer 321 and the first insulator layer 320. An opening sufficiently larger than the planar shape is formed. A p ⁺ layer, a p layer, an n layer, a p layer, and a p ⁺ layer are successively grown in parallel to the substrate from the bottom using a selective epitaxial growth method in the opening to form a second semiconductor thin film laminated film 206. Selectively formed (FIG. 16a). After planarizing using CMP method to such an extent that the surface of the laminated film 205 of the first semiconductor thin film is exposed, the laminated films 205 and 206 of the first and second semiconductor thin films are selectively used by photolithography. Etching is performed to form first and second fins 201 and 202 (FIG. 16b). Next, a third insulator layer 322 is deposited in the gap between each fin generated in the above etching process and the first insulator layer 320, and is planarized by CMP to embed the third insulator layer 322. In this case, a shape similar to FIG. 15f is completed (FIG. 16c). In this case, the material of the third insulator layer 322 is preferably the same as the material of the first insulator layer 320, but is not limited thereto. If the materials of the third insulator layer 322 and the first insulator layer 320 are the same, the thermal expansion coefficients of the third insulator layer 322 and the first insulator layer 320 are the same, improving the reliability of the CMOS inverter, particularly the heat cycle resistance. If this manufacturing process is used, the photolithography process required to form an extremely fine pattern necessary for forming the first fin 201 and the second fin 202 is changed from two times to one time. In addition to simplification, it is possible to realize more precise control and better reproducibility of the fin shape constituting the v-FinFET of both channels.

  In the present embodiment, the planar shape of the first fin 201 and the second fin 202 is applied to the gate electrode disposed on the entire side surface of the channel region exposed on each side surface through the gate insulator film. The shape of each channel region is substantially the same as the planar shape in which each channel region is completely depleted by the gate voltage, but the present invention is not limited to this. If the planar shape of the fins 201 and 202 is such that each channel region is completely depleted, the gate electrode may not be disposed on the entire side surface of the channel region via the gate insulator film. . However, it is easier to completely deplete the channel region if the gate electrode is provided on the entire side surface of the channel region.

In the present embodiment, the width W _fin (see FIG. 13) of the fins 201 and 202 is preferably 100 nm or less. If it is larger than 100 nm, it is difficult to completely deplete the channel region. The width W _{fin of the} fins 201 and 202 is more preferably 50 nm or less. The lower limit value of the width W _fin of the fins 201 and 202 is determined by the machining accuracy. With the current processing accuracy, the lower limit value of the width W _fin of the fins 201 and 202 is about 10 nm.

  Furthermore, if the manufacturing process described here is used, the fin can be formed by the following method. First, from the state of FIG. 15b, the first insulator layer 320 is deposited on the entire surface, and the first insulator layer 320 is sufficiently larger than the planar shape of the first fin 201 constituting the n-channel type v-FinFET. A first opening is formed. A laminated film of the first semiconductor thin film is formed in the first opening using a normal epitaxial growth method. Thereafter, the first semiconductor thin film deposited on the first insulator layer 320 is planarized by a CMP method or the like. Similarly, a second opening sufficiently larger than the planar shape of the second fin 202 constituting the p-channel v-FinFET is formed in the first insulator film 320, and the second opening is formed using a normal epitaxial growth method. A laminated film of the second semiconductor thin film is formed in the opening. Thereafter, the second semiconductor film deposited on the first insulator film 320 is planarized by a CMP method or the like. The laminated film of the first and second semiconductor thin films is selectively etched using photolithography technology to form the first and second fins 201 and 202, and the state shown in FIG. 16b is obtained. Next, a third insulator layer 322 is deposited in the gap between each fin generated in the above etching process and the first insulator layer 320, and is planarized by CMP to embed the third insulator layer 322. In this case, the same shape as in FIG. 16c is completed.

  In the description so far, it has been described that the height of the semiconductor thin film formed by the epitaxial growth method is substantially equal to the height of the opening of the insulator layer, but when combined with the planarization method by the CMP method, The film thickness may be thicker or thinner than the height of the opening. In order to simplify the manufacturing process by reducing the planarization process by the CMP method, the height of the semiconductor thin film formed by the epitaxial growth method and the height of the opening of the insulator layer are set as in this embodiment. It is preferable to make them approximately equal.

In addition, the semiconductor thin film of each layer constituting the laminated film of the n ⁺ layer, n layer, p layer, n layer and n ⁺ layer and the laminated film of the p ⁺ layer, p layer, n layer, p layer and p ⁺ layer The material, composition, film thickness, and combinations thereof can be set in the epitaxial growth process so that desired electrical characteristics of the n-channel and p-channel v-FinFETs can be obtained.

In the present invention, the channel lengths L _Cn and L _{Cp of} n-channel and p-channel v-FinFETs are determined by the film thicknesses of the n-layer and p-layer formed on the first fin 201 and the second fin 202. Is done. The epitaxial growth method, but may be precise control of the film thickness control and the impurity concentration, between so can be precisely controlled channel length L _C is the most important parameter for determining the electrical properties of the MOSFET, the channel length L _C Lot In addition, a v-FinFET having excellent reproducibility between wafers, controllability and uniformity within a wafer, between chips, and within a chip can be obtained. This is because the controllability of the channel length L _C , that is, the electrical characteristics of the v-FinFET, compared to the process of forming a very fine gate electrode length L _g using the state-of-the-art photolithography technology in the conventional p-FinFET. This means that the controllability of the mechanical characteristics is extremely excellent.

  15f or 16c is completed, the first insulator layer 320 or the first insulator layer 320 and the third insulator layer 322 are uniformly etched back to insulate the side surfaces of the channel regions 260 and 265. Exposed from body layer 320 or 322. The etched back first insulator layer 320 or the first insulator layer 320 and the third insulator layer 322 become an interlayer insulator layer of the source region and the gate region of the v-FinFET. If necessary, impurity introduction regions 261 and 266 are formed on the side surfaces of the channel regions 260 and 265 using means such as an oblique ion implantation method in order to control the electrical characteristics of the v-FinFET, particularly the threshold voltage. Next, a gate insulator film 240 such as a silicon oxide film or a silicon nitride film is formed in contact with a part or the whole of the exposed side surfaces of the fins 201 and 202 (FIG. 17a). In the present embodiment, the gate insulator film 240 is formed on the entire exposed side surfaces of the fins 201 and 202. Further, a gate electrode film is formed in contact with the gate insulator film 240, and is flattened by CMP so that the surfaces of the gate electrode film and the fin are substantially equal. Thereafter, the gate electrode film is uniformly etched back until a part of the side surface of the upper portion of the fin is exposed. Next, using the photolithography technique, the gate electrode film is etched into a desired shape to form the gate electrode 255 (FIG. 17b). A fourth insulator layer 330 such as a silicon oxide film is deposited on the entire surface so as to fill the gap, and is flattened so as to have a height substantially equal to the upper portion of the fin using a CMP method (FIG. 17c).

In the present embodiment, the gate electrode 255 is formed on the entire surface of the channel regions 260 and 265 exposed on the side surfaces of the fins 201 and 202 via the gate insulator film 240, but the present invention is not limited to this.
You may arrange | position in the state which touches a part of each side surface of channel region 260,265. Considering that the channel regions 260 and 265 are completely depleted, it is preferable to dispose the channel regions 260 and 265 on at least one pair of opposing two surfaces of each side surface of the channel regions 260 and 265. More preferably, the gate electrode 250 is disposed in contact with all of the side surfaces of the channel regions 260 and 265 as in the present embodiment. This is because the channel regions 260 and 265 are more easily depleted. The fact that the channel regions 260 and 265 are easily depleted easily allows the channel regions 260 and 265 to be completely depleted with a lower gate voltage. Further, assuming that the gate voltages are the same, the channel regions 260 and 265 can be completely depleted even with a wider fin width W _fin . For this reason, even if the _fin width W _fin, which is a microfabrication process, varies in the manufacturing process, the variation can be absorbed and the channel regions 260 and 265 can be completely depleted, and the manufacturing yield is high and the manufacturing is easy. -It becomes a manufacturing method of FinFET.

From this state, the upper portions of the fins 201 and 202 are uniformly etched back (FIG. 17d), and then a fifth insulator layer 340 such as a silicon oxide film is deposited on the entire surface (FIG. 17e). Further, the fifth insulator Layer 340 is anisotropically etched to form fifth insulator layer sidewalls 341 and 342 on the sides of the recesses formed on top of fins 201 and 202. This step forms contact openings for forming drain electrodes 282 and 287 in the drain region (FIG. 17f). Next, contact openings for forming source, drain and gate lead electrodes of n-channel and p-channel v-FinFETs are formed in the fourth insulator layer 330. Further, a silicide film 350 is formed on the upper surfaces of the n ⁺ semiconductor film 230, the p ⁺ semiconductor thin film 235, the gate electrode 255, the first fin 201, and the second fin 202 exposed by the opening formation in order to reduce the contact resistance. It is also possible to introduce a forming step. Next, after depositing a metal film for electrode formation on the entire surface, the surface thereof is flattened by CMP to fill the contact opening with the metal film, and the source region extraction electrodes 272 and 277 and the drain region extraction electrode 282 are formed. 287 and the gate lead electrode 257 are formed (FIG. 17g). After this, since it becomes a multilayer wiring process in the manufacturing process of a normal planar structure CMOS inverter, description is abbreviate | omitted.

  In the above manufacturing method, the example in which the side walls 341 and 342 of the fifth insulator layer are formed so as to surround the upper openings of the fins 201 and 202 is shown, but as shown in the second alternative example of FIG. Since the drain region extraction electrodes 282 and 287 and the gate electrode 255 are insulated from each other by the fourth insulator layer 330, the side walls 341 and 342 are not necessarily formed, and this side wall forming step is omitted. Is also possible.

  A second alternative example of the manufacturing method of the present invention from FIG. 17a to FIG. 17g is described in FIG. 19a to FIG. 19c. In the step after realizing the shape of FIG. 17a, after forming the gate electrode film on the entire surface, the gate electrode film is anisotropically etched to form the gate electrode 256 on the side wall around the fin (FIG. 19a). At this time, over-etching is performed so that the upper portion of the gate electrode 256 is lower than the upper portion of the fin by a desired depth. A fourth insulator layer 330 is deposited on the entire surface, and the surface is flattened by CMP to obtain the shape shown in FIG. 19b. In the previous steps, the same shape as in FIG. 17c was realized. In the subsequent steps, similar to the above-described steps, the upper portions of the fins are uniformly etched back to form recesses (FIG. 19c), and the fifth insulator layer 340 is deposited on the entire surface (FIG. 19d). Side walls 341 and 342 of the fifth insulator layer are formed around the recess by reactive etching (FIG. 19e). Openings for forming source, drain, and gate lead electrodes are formed, and a silicide film 350 is formed on the bottoms as necessary. Next, a metal film for electrode formation is deposited on the entire surface and flattened by the CMP method, and the contact opening is filled with the metal film, so that the extraction electrodes 272 and 277 in the source region, the extraction electrodes 282 and 287 in the drain region, and the gate are filled. An extraction electrode 257 is formed to have the same shape as that in FIG. 17g (FIG. 19f). After this, a multilayer wiring process in the manufacturing process of a normal planar structure CMOS inverter is performed. In the case of this embodiment, since the gate electrode 256 can be formed on the entire periphery of the fin without using a photolithography process for forming electrodes, the process can be greatly simplified. However, in the case of this embodiment, it becomes difficult to form an interconnection using a conductive film for forming a gate electrode, and there is a limit to the pattern layout for increasing the density. However, also in this embodiment, if a photolithography process for forming a gate electrode is introduced, the gate electrode can be formed in a desired region in a desired shape, so that mutual wiring is possible, and the degree of freedom and density of layout design are increased. Can also be improved.

  In order to further reduce the size of the MOSFET, the channel region can be completely depleted easily even when a very fine channel region is formed by an epitaxial growth method or the like by applying the structure of the v-FET. A MOS type semiconductor device that does not deteriorate current characteristics and is easy to manufacture and a method for manufacturing the same have been realized.

In conventional p-FinFET, determine the channel length L _C is the most important parameter affecting the electrical characteristics of the MOSFET is a vertical gate electrode length is formed perpendicular to the fins of the semiconductor thin film L _g is there. Therefore, in order to form a gate electrode length of several tens of nanometers, a state-of-the-art ultra-fine photolithography technique is required. Therefore, the gate electrode length between lots, wafers, wafers, chips, and chips is highly accurate. It is extremely difficult to achieve controllability and low variation characteristics. However, in the v-FinFET of the present invention, the channel length L _C is determined by the thickness of the film formed by the epitaxial growth method with excellent film thickness controllability, so that excellent controllability is achieved even with a channel length of about several tens of nm. It can be formed with uniformity and reproducibility.

  In the conventional p-FinFET, the source, channel, and drain regions are arranged in parallel to the substrate in the same manner as the conventional planar structure MOSFET, so that a desired impurity is introduced into each region in a desired distribution. Therefore, it is necessary to repeat a plurality of photolithography processes and ion implantation processes, which increases the number of manufacturing processes and makes them complicated. However, in the v-FinFET of the present invention, the source, channel, and drain regions constituting the fins of the vertical semiconductor thin film can be formed by laminating in one epitaxial growth process, so that the manufacturing process is compared with the conventional example. It can be greatly simplified.

  In the conventional p-FinFET, in order to gradually widen the line width from a fin region or gate electrode of several tens of nanometers and lead to the source, drain and gate lead electrodes, an electrode lead region requiring a long distance is required. For this reason, although the shape of a single p-FinFET is extremely small, the integration density is significantly reduced due to the large area for electrode formation. Furthermore, in the conventional p-FinFET, since the distance between the electrode lead-out regions is long, the parasitic series resistance of the source and drain in which the regions are formed in the semiconductor thin film is remarkably increased, and the electrical characteristics of the MOSFET are increased. Will deteriorate significantly. However, in the v-FinFET of the present invention, since it can be drawn straight from the source, drain, and gate regions formed widely in the longitudinal channel width direction of the fin to the electrode formation region, it is necessary for electrode drawing. The distance can be extremely shortened, and in particular, the parasitic series resistance of the source and drain formed of a semiconductor thin film can be remarkably improved. As a result, a MOSFET having excellent electrical characteristics can be realized. In particular, the present invention has a great advantage that the drain or source lead electrode can be directly taken out from the top of the fin.

The width W _fin of the fin of the conventional p-FinFET is standardized so as to maintain a shape narrow enough to be completely depleted by the gate voltage applied to the gate electrodes formed on both sides of the fin, When a large channel width of 2H _fin or more is required, it is necessary to design n fins having the same shape in parallel so that the channel width W = 2nH _fin . Therefore, the integration density in the channel width direction is reduced to about one half, and the channel width can only be changed digitally. However, in the v-FinFET of the present invention, the source, the channel, and the drain are stacked in the vertical direction of the fin. Therefore, if the fin width W _fin is made as narrow as the conventional p-FinFET, The entire region in the longitudinal direction is kept in a fully depleted state by the gate voltage applied to the gate electrodes formed on both side surfaces of the fin. Accordingly, the channel width can be set to an arbitrary width using a photolithographic technique as in the case of a conventional planar structure MOSFET, and the channel width can be continuously varied.

  Furthermore, according to the present invention, since the epitaxial growth method is used for forming the fin, the laminated film of the semiconductor thin films constituting the fin is not limited to the same type of semiconductor material, and the composition of the same type of semiconductor material. Combinations of different thin films and combinations of different types of semiconductor materials can be freely set. This means that a high-performance n-channel type and p-channel type v-FinFET can be selectively formed on the same substrate by selecting a semiconductor material having high carrier mobility, and has excellent electrical characteristics. A CMOS inverter circuit can be realized. Although the embodiments of the present invention have been described by taking the CMOS inverter circuit as an example, it goes without saying that other CMOS logic circuits and CMOS analog circuits can be configured.

1 is a cross-sectional structure diagram of an n-channel v-FinFET according to the present invention. FIG. 2 is an enlarged cross-sectional structure diagram of a P part in FIG. 1. FIG. 2 is a plan layout diagram of the v-FinFET of FIG. 1. FIG. 6 is a plan layout view of a first other example of an n-channel type v-FinFET according to the present invention. FIG. 10 is a plan layout view of a second other example of the n-channel v-FinFET according to the present invention. It is a plane layout view of a conventional p-FinFET. FIG. 7 is an enlarged cross-sectional structure diagram in the a-a ′ direction of FIG. 6. FIG. 8 is an enlarged cross-sectional structure diagram in the b-b ′ direction of FIG. 7. It is a circuit diagram of a CMOS inverter. It is a plane layout view of a CMOS inverter using a conventional p-FinFET. It is a perspective view which shows the structure of the conventional v-FET. 1 is a cross-sectional structure diagram of a CMOS inverter using a v-FinFET according to the present invention. FIG. 13 is a plan layout view of the CMOS inverter of FIG. 12. FIG. 6 is a plan layout diagram of another example of a CMOS inverter using the v-FinFET of FIG. 5. It is a cross-sectional structure diagram for demonstrating the manufacturing method of the CMOS inverter using v-FinFET by this invention. It is a cross-sectional structure diagram for demonstrating the manufacturing method of the CMOS inverter using v-FinFET by this invention. It is a cross-sectional structure diagram for demonstrating the manufacturing method of the CMOS inverter using v-FinFET by this invention. It is a cross-sectional structure diagram for demonstrating the manufacturing method of the CMOS inverter using v-FinFET by this invention. It is a cross-sectional structure diagram for demonstrating the manufacturing method of the CMOS inverter using v-FinFET by this invention. It is a cross-sectional structure diagram for demonstrating the manufacturing method of the CMOS inverter using v-FinFET by this invention. FIG. 6 is a cross-sectional structure diagram for explaining a first alternative example of a method for manufacturing a CMOS inverter using a v-FinFET according to the present invention. FIG. 6 is a cross-sectional structure diagram for explaining a first alternative example of a method for manufacturing a CMOS inverter using a v-FinFET according to the present invention. FIG. 6 is a cross-sectional structure diagram for explaining a first alternative example of a method for manufacturing a CMOS inverter using a v-FinFET according to the present invention. It is a cross-sectional structure diagram for demonstrating the manufacturing method of the CMOS inverter using v-FinFET by this invention. It is a cross-sectional structure diagram for demonstrating the manufacturing method of the CMOS inverter using v-FinFET by this invention. It is a cross-sectional structure diagram for demonstrating the manufacturing method of the CMOS inverter using v-FinFET by this invention. It is a cross-sectional structure diagram for demonstrating the manufacturing method of the CMOS inverter using v-FinFET by this invention. It is a cross-sectional structure diagram for demonstrating the manufacturing method of the CMOS inverter using v-FinFET by this invention. It is a cross-sectional structure diagram for demonstrating the manufacturing method of the CMOS inverter using v-FinFET by this invention. It is a cross-sectional structure diagram for demonstrating the manufacturing method of the CMOS inverter using v-FinFET by this invention. It is sectional structure drawing for demonstrating the 2nd another example of the manufacturing method of the CMOS inverter using v-FinFET by this invention. It is a cross-section figure for demonstrating the 3rd another example of the manufacturing method of the CMOS inverter using v-FinFET by this invention. It is a cross-section figure for demonstrating the 3rd another example of the manufacturing method of the CMOS inverter using v-FinFET by this invention. It is a cross-section figure for demonstrating the 3rd another example of the manufacturing method of the CMOS inverter using v-FinFET by this invention. FIG. 7 is a cross-sectional structure diagram for explaining a third alternative example of a method for manufacturing a CMOS inverter using a v-FinFET according to the present invention. It is a cross-section figure for demonstrating the 3rd another example of the manufacturing method of the CMOS inverter using v-FinFET by this invention. It is a cross-section figure for demonstrating the 3rd another example of the manufacturing method of the CMOS inverter using v-FinFET by this invention.

Explanation of symbols

100,200,201,202 fins
105 Island-like region of silicon single crystal
110 Silicon substrate
120 buried insulator film
130 Interlayer dielectric film
140,240 Gate insulator film
150,250,255,256 Gate electrode
151,251 Gate electrode contact opening
152,252,257 Gate extraction electrode
161 channels
160,260,265 channel area
170,270,275 Source area
171,271 Contact opening of source electrode
172,272,277 Source region extraction electrode
180,280,285 drain region
181,281 Drain electrode contact opening
182,282,287 Drain region extraction electrode
190,191,192 Electrode extraction area
205,206 Multilayer film of semiconductor thin film
21 SOI substrate
210 substrate
220 Embedded insulator film
225 Semiconductor thin film
230 n ⁺ semiconductor thin film
235 p ⁺ semiconductor thin film
261,266 Impurity introduction region
310 First insulator film
320 First insulator layer
321 Second insulator layer
322 Third insulator layer
330 Fourth insulator layer
340 Fifth insulator layer
341,342 Side wall of fifth insulator layer
350 Silicide film

Claims (27)

A fin that is a vertical semiconductor thin film in which a source region, a drain region, and a channel region sandwiched between the source region and the drain region are formed of a laminated film parallel to the substrate;
A gate electrode disposed on the entire or part of the side surface of the channel region exposed on the side surface of the fin via a gate insulator film;
A MOS type semiconductor device in which the fin is formed so that a channel region is completely depleted by a gate voltage applied to the gate electrode. The gate electrode is disposed on at least one pair of opposing two surfaces of the side surface of the channel region exposed on the side surface of the fin via the gate insulator film,
The distance between at least one of the two opposing surfaces of the channel region in which the gate electrode is disposed via the gate insulator film is determined by the gate voltage applied to the gate electrode. The MOS type semiconductor device according to claim 1, wherein the channel region is formed below an interval at which the channel region is completely depleted. The fin has a quadrilateral planar shape,
The gate electrode is disposed on at least two opposite sides in the longitudinal direction of the channel region on the side surface of the channel region exposed on the side surface of the fin via the gate insulator film,
3. The MOS according to claim 1, wherein an interval between two opposing surfaces in the longitudinal direction of the channel region is formed to be equal to or less than an interval at which the channel region is completely depleted by a gate voltage applied to the gate electrode. Type semiconductor device. 4. The MOS semiconductor device according to claim 1, wherein the gate electrode is disposed in contact with the entire side surface of the channel region exposed on the side surface of the fin via the gate insulator film. The fin has a circular planar shape,
3. The MOS semiconductor device according to claim 1, wherein the gate electrode is disposed in contact with the entire side surface of the channel region exposed on the side surface of the fin via the gate insulator film. A conductor pattern for conducting a region located on the substrate side of the source region or drain region and a lead electrode of the source region or drain region provided in the MOS type semiconductor device is formed on the substrate side of the source region or drain region. The MOS semiconductor device according to claim 1, wherein the MOS type semiconductor device is electrically connected to an extraction electrode in a source region or a drain region from the surface of the region located on the substrate side through the outside of the gate electrode. The conductor pattern is in contact with substantially the entire substrate side of the source region or drain region located on the substrate side, and the conductor pattern is in a direction parallel to the substrate and in the source region or drain region. The MOS type semiconductor device according to claim 6, wherein the MOS type semiconductor device is drawn out in a direction perpendicular to a longitudinal direction of a surface on the substrate side of a region located on the substrate side. The MOS type semiconductor device according to claim 1, wherein the fin is formed on an upper surface side of an insulator film formed on the substrate. The MOS type semiconductor device according to claim 1, further comprising a region selectively doped with impurities on at least a side surface of the channel region of the fin. 2. The fin is composed of a group IV semiconductor single crystal thin film, a group III-V semiconductor single crystal thin film, a group II-VI semiconductor single crystal thin film, a polycrystalline thin film of these semiconductors, or an amorphous thin film of those semiconductors. 10. The MOS type semiconductor device according to 9. The MOS type semiconductor device according to claim 1, wherein the fin is a laminated film in which semiconductor thin films of different semiconductor materials or semiconductor thin films in which the composition ratio of the same kind of mixed crystal semiconductor material is changed are combined. A multi-element MOS semiconductor device comprising a combination of a plurality of MOS semiconductor devices according to claim 1,
A multi-element MOS semiconductor device having a MOS semiconductor device having different channel region thicknesses among a plurality of MOS semiconductor devices. A multi-element MOS semiconductor device comprising a combination of a plurality of MOS semiconductor devices according to claim 1, wherein an n-channel MOS semiconductor device and a p-channel MOS semiconductor device are provided. A multi-element MOS semiconductor device formed on the same substrate to constitute a CMOS circuit. The first fin constituting the n-channel type MOS semiconductor device and the second fin constituting the p-channel type MOS semiconductor device are formed of a laminated film of the same type of semiconductor thin film. 14. A multi-element MOS semiconductor device according to item 13. The first fin constituting the n-channel type MOS semiconductor device and the second fin constituting the p-channel type MOS semiconductor device are composed of stacked semiconductor thin films made of different semiconductor materials or compositions. The multi-element MOS semiconductor device according to claim 13. The gate insulator film constituting the n-channel type MOS semiconductor device and the gate insulator film constituting the p-channel type MOS semiconductor device are different in film thickness, composition or material. The multi-element MOS semiconductor device described. In a gate electrode constituting an n-channel type MOS semiconductor device and a gate electrode constituting a p-channel type MOS semiconductor device,
17. The multi-element MOS semiconductor device according to claim 13, wherein electrode materials having different film thicknesses, compositions or materials, or semiconductor electrode materials having different semiconductor compositions, materials, conductivity types or impurity concentrations are used. Forming an opening having a size substantially equal to the planar shape of the fin, which is a desired vertical semiconductor thin film, in an insulator layer formed on the substrate;
Forming a fin in the opening by stacking a source or drain region, a channel region on the region, and a drain or source region on the channel region in parallel to the substrate;
Exposing the side surface of the channel region of the side surface of the fin from the insulator layer;
And a step of disposing a gate electrode over the whole or a part of the exposed side surface of the channel region via a gate insulator film. Forming an opening larger than the planar shape of the fin, which is a desired vertical semiconductor thin film, in the insulator layer formed on the substrate;
Forming a vertical semiconductor thin film by laminating a source or drain region in the opening, a channel region on the region, and a drain or source region on the channel region;
Processing the semiconductor thin film into a planar shape of the fin;
And a step of disposing a gate electrode on a whole or a part of a side surface of the channel region exposed on the side surface of the fin via a gate insulator film. The first insulator layer formed on the substrate has a first size that is approximately equal to the planar shape of the first fin, which is a desired vertical semiconductor thin film for forming an n-channel MOS semiconductor device. Forming an opening of
In the first opening, a source or drain region, a channel region on the region, and a drain or source region on the channel region are stacked in parallel to the substrate to form the first fin. Process,
Forming a second insulator layer on at least the first fin;
A p-channel MOS semiconductor device is formed on the first insulator layer, the second insulator layer, or the insulator layer in which the first insulator layer and the second insulator layer overlap each other. Forming a second opening having a size substantially equal to the planar shape of the second fin, which is a desired vertical semiconductor thin film,
A step of forming the second fin by laminating a source or drain region in the second opening, a channel region on the region, and a drain or source region on the channel region in parallel to the substrate. When,
The side surface of the channel region of both the first fin and the side surface of the second fin is connected to the first insulator layer, the second insulator layer, or the first insulator layer and the second insulation. Exposing the insulator layer overlapping the body layer;
And a step of disposing a gate electrode over the whole or a part of the side surfaces of both exposed channel regions via a gate insulator film. A first opening larger than the planar shape of the first fin, which is a desired vertical semiconductor thin film for forming an n-channel MOS semiconductor device, is formed in the first insulator layer formed on the substrate. Forming a step;
A source or drain region in the first opening, a channel region on the region, and a drain or source region on the channel region are stacked in parallel to the substrate to form an n-channel MOS semiconductor device. Forming a vertical semiconductor thin film to constitute;
Forming a second insulator layer on at least the first fin;
A p-channel MOS semiconductor device is formed on the first insulator layer, the second insulator layer, or the insulator layer in which the first insulator layer and the second insulator layer overlap each other. Forming a second opening larger than the planar shape of the second fin, which is a desired vertical semiconductor thin film,
A p-channel MOS semiconductor device is formed by stacking a source or drain region in the second opening, a channel region on the region, and a drain or source region on the channel region in parallel to the substrate. Forming a vertical semiconductor thin film to constitute;
A semiconductor thin film for forming the n-channel type MOS semiconductor device and a semiconductor thin film for forming the p-channel type MOS semiconductor device are simultaneously formed in the planar shape of the first fin or the second A step of processing into a planar shape of the fins,
And a step of disposing a gate electrode on a whole surface or a part of a side surface of both channel regions exposed on the side surfaces of the first fin and the second fin through a gate insulator film. Of manufacturing a MOS semiconductor device. In the step of forming the opening, the planar shape of the fin, which is a desired vertical semiconductor thin film, is disposed on the entire or part of the side surface of the channel region exposed on the side surface of the fin via the gate insulator film. 21. The method of manufacturing a MOS semiconductor device according to claim 18 or 20, or a multi-element MOS type, wherein the channel region is completely depleted by a gate voltage applied to the gate electrode formed. A method for manufacturing a semiconductor device. In the step of processing the semiconductor thin film into the planar shape of the fin, the planar shape of the fin, which is a desired vertical semiconductor thin film, is formed on the entire or part of the side surface of the channel region exposed on the side surface of the fin. The method for manufacturing a MOS type semiconductor device according to claim 19 or 21, wherein the channel region is completely depleted by a gate voltage applied to a gate electrode disposed via the gate electrode. A method for manufacturing an element-type MOS semiconductor device. 24. The fin or vertical semiconductor thin film is formed only in the opening formed in the insulator layer using a selective epitaxial growth method in the step of forming a fin or the step of forming a vertical semiconductor thin film. Or a method for manufacturing a multi-element type MOS semiconductor device. 25. The method for manufacturing a MOS type semiconductor device according to claim 24, wherein the film thickness of the fin or the thickness of the vertical semiconductor thin film is grown so as to be substantially equal to the thickness of the insulator layer in which the opening is formed. A method for manufacturing an element-type MOS semiconductor device. 26. The method of manufacturing a MOS type semiconductor device or a multi-element type according to claim 18, further comprising a step of forming a region into which impurities are selectively introduced by using an oblique ion implantation method on at least a side surface of the channel region of the fin. Manufacturing method of MOS type semiconductor device. 24. The manufacturing of a multi-element MOS semiconductor device according to claim 20, 21 or 23, comprising a step of forming the first fin and the second fin with different semiconductor materials or compositions. Method.

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