JP2005303089A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a wiring pattern whose wiring width and wiring interval are small almost to resolution limits of an exposure device by eliminating influence of proximity effect and micro-loading effect and suppressing resist fall. <P>SOLUTION: A semiconductor device which has a wiring pattern, including a main wire 111 and dummy wires 211 to 216 formed in an insulating film on a semiconductor substrate has the main wire 111 having a specified wire length L1 and the plurality of dummy wires arranged along the wire width W1 of the main wire 111, respective dummy wire arrays being formed by arranging the plurality of dummy wires 211 to 216 which have a wire width W2 of 0.5 to 2 time as large as the wire width W1 of the main wire 311 and have a wire length L2 of ≤50 μm along the wire length L1 of the main wire 111. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device in which a wiring pattern including a main wiring and a dummy wiring is formed in an insulating film on a semiconductor substrate, and in particular, a wiring pattern layout in which a wiring width and a wiring interval are as small as the resolution limit of an exposure apparatus. The present invention relates to a semiconductor device having the same.

As a method of measuring the resistance of the wiring in the semiconductor device, the voltage V between the voltage measuring terminals when the current I is supplied between the current supplying terminals connected to the wiring is measured, and the voltage V is divided by the current I. There is a method for obtaining the resistance of the wiring.
However, after the lithography process and the etching process, the wiring length L of the wiring is maintained as designed, but the wiring width W is shifted due to the proximity effect and the microloading effect. For this reason, there is a problem that the measured resistance does not correspond to the resistance of the wiring having the design wiring width W in the wiring dense portion in the same semiconductor device. Therefore, a proposal has been made to form dummy wirings on both sides of the wiring (see, for example, Patent Document 1). Japanese Patent Application Laid-Open No. 2004-133830 proposes a method of preparing a calibration curve between the wiring resistance and the shift amount of the wiring width in advance and obtaining the wiring width in the integrated circuit from the wiring resistance.

  In addition, a technique has been proposed in which a plurality of dummy patterns having a width approximately the same as the actual pattern are arranged in the wiring width direction in an empty area where the actual pattern is not formed to reduce the difference in pattern density (for example, , See Patent Document 2).

JP-A-8-55892 (page 3, FIG. 1) Japanese Patent Laid-Open No. 9-311432 (page 3-4, FIG. 1-2)

However, as a result of intensive studies by the present inventor, in the method of Patent Document 1 described above, when a wiring to be measured having a wiring width of 0.14 μm or less is formed, the following problems occur and the measured It has been found that it is difficult to make the resistance of the wiring correspond to the wiring resistance of the wiring dense part in the actual integrated circuit.
When forming a wiring having a wiring width of 0.14 μm or less, generally, Cu having a lower resistance than an Al alloy is used as a wiring material, and the wiring is formed by a damascene method. In the damascene method, a groove is formed in an insulating film on a semiconductor substrate by lithography and etching processes, and Cu is embedded in the groove by a PVD (Physical Vapor Deposition) method or a plating method. This excess Cu is removed by CMP (Chemical Mechanical Polishing). If necessary, the wiring inside the trench may be covered with an insulating film.
When forming a wiring pattern using this damascene method, the wiring width of the dummy wiring is smaller than twice the wiring width of the wiring to be measured, and there is only one dummy wiring on each side of the wiring to be measured. In some cases, the resist does not resolve due to the proximity effect in the lithography process. This problem is particularly remarkable when the wiring width of the wiring to be measured is equal to or smaller than the value corresponding to the resolution limit for the isolated wiring of the exposure apparatus. For example, when an ArF excimer laser exposure apparatus having a current numerical aperture NA = 0.75 is used, the wiring width of the wiring to be measured is 0.12 μm or less, which is a value corresponding to the resolution limit for an isolated wiring. It was remarkable. If the resist of the dummy wiring disappears without being resolved, the measured wiring becomes equivalent to the isolated wiring even if the resist of the measured wiring remains, and a microloading effect occurs in the etching process. As a result, the cross-sectional shape of the wiring dense part in the integrated circuit and the cross-sectional shape of the wiring to be measured are significantly different. As a result, it is difficult to make the resistance of the wiring dense part in the integrated circuit correspond to the resistance of the wiring to be measured.

  Therefore, the present inventor examined combining the method of Patent Document 2. In other words, a method was attempted in which a plurality of dummy wirings having a wiring length equivalent to the wiring length of the wiring to be measured are arranged in the wiring width direction so as to approach the pattern density of the wiring dense portion. However, when the wiring length of the wiring to be measured is 100 μm or more and the exposure amount is excessive, there is a problem in that the frequency with which the resist pattern corresponding to the remaining portion of the positive resist collapses or peels off increases. This problem is particularly noticeable when the distance between the measured wiring and the dummy wiring is not more than a value corresponding to the resolution limit for the isolated wiring of the exposure apparatus. For example, when an ArF excimer laser exposure apparatus having a current numerical aperture NA = 0.75 is used, the interval between the wiring to be measured and the dummy wiring is 0.12 μm which is a value corresponding to the resolution limit for the isolated wiring. This was particularly noticeable below.

  As described above, in the manufacture of semiconductor devices that will be increasingly required to be miniaturized in the future, wiring having the same wiring width as the resolution limit for the isolated wiring of the exposure device is affected by the proximity effect and microloading effect. It is very difficult to achieve the same electrical characteristics (in this case, resistance value) by eliminating and suppressing resist collapse and peeling, realizing a wiring with the same shape and dimensions as the densely packed portion of the integrated circuit. It was.

  The present invention has been made to solve the above-described conventional problems, eliminates the influence of the proximity effect and the microloading effect, suppresses the resist collapse, and the wiring width and the wiring interval are as small as the resolution limit of the exposure apparatus. An object is to obtain a wiring pattern.

A semiconductor device according to the present invention is a semiconductor device in which a wiring pattern including a main wiring and a dummy wiring is formed in an insulating film on a semiconductor substrate,
A main wiring having a predetermined wiring length;
A plurality of dummy wiring rows arranged in the wiring width direction of the main wiring,
A dummy wiring having a wiring width of 0.5 to 2 times the wiring width of the main wiring and having a wiring length longer than the wiring width of the main wiring and shorter than the wiring length of the main wiring; Each dummy wiring row is configured by arranging a plurality of wirings in the wiring length direction.

A semiconductor device according to the present invention is a semiconductor device in which a wiring pattern including a main wiring and a dummy wiring is formed in an insulating film on a semiconductor substrate,
A main wiring having a predetermined wiring length;
A plurality of dummy wiring rows arranged in the wiring width direction of the main wiring,
By arranging a plurality of dummy wirings having a wiring width of 0.5 to 2 times the wiring width of the main wiring and having a wiring length of 50 μm or less in the wiring length direction of the main wiring, It is characterized by comprising.

A semiconductor device according to the present invention is a semiconductor device in which a wiring pattern including a main wiring and a dummy wiring is formed in an insulating film on a semiconductor substrate,
A main wiring having a wiring length of 100 μm or more;
A plurality of dummy wiring rows arranged in the wiring width direction of the main wiring,
By arranging a plurality of dummy wirings having a wiring width of 0.5 to 2 times the wiring width of the main wiring and having a wiring length of 50 μm or less in the wiring length direction of the main wiring, It is characterized by comprising.

In the semiconductor device according to the present invention, a lead-out wiring that connects the dummy wirings of a plurality of dummy wiring rows including the dummy wiring row closest to the main wiring;
It is preferable to further include a terminal connected to any one of the dummy wirings connected by the lead wiring.

  In the semiconductor device according to the present invention, it is preferable that the main wiring has a shape bent in a horizontal direction of the semiconductor substrate at a plurality of locations.

In the semiconductor device according to the present invention, the main wiring includes a first main wiring arranged in a lower layer, a second main wiring arranged in an upper layer than the first main wiring, the first and first wirings. Vias for connecting the two main wirings,
It is preferable that a plurality of the dummy wiring rows are arranged in the wiring width direction of the first and second main wirings.

In the semiconductor device according to the present invention, the main wiring has a plurality of the first and second main wirings and the vias, respectively.
The vias are preferably arranged at different intervals.

  In the semiconductor device according to the present invention, it is preferable that the dummy wirings are respectively disposed on opposite sides of the first and second main wirings with respect to the via.

  According to the present invention, it is possible to eliminate the influence of the proximity effect and the microloading effect, suppress resist collapse, and obtain a wiring pattern whose wiring width and wiring interval are as small as the resolution limit of the exposure apparatus.

  Embodiments of the present invention will be described below with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and the description thereof may be simplified or omitted.

Embodiment 1 FIG.
FIG. 1 is a plan view for explaining a semiconductor device according to the first embodiment of the present invention.
A wiring pattern shown in FIG. 1 is formed on the insulating film on the semiconductor substrate. The wiring patterns are insulated by an insulating film. As shown in FIG. 1, a main wiring 111 having a predetermined wiring length L is formed. The wiring 111 is a wiring to be measured in which electrical characteristics such as resistance are measured. Both ends of the wiring 111 are connected to pads 121 and 122 as current supply terminals and pads 131 and 132 as voltage measurement terminals. A row of a plurality of dummy wirings 211 to 216 is formed on both sides of the main wiring 111. Each dummy wiring row is equivalent to the wiring width W1 of the main wiring 111. More specifically, a plurality of dummy wirings 211 to 216 having a wiring width W2 that is 0.5 to 2 times the wiring width W1 are arranged in the wiring length direction. Is configured. The dummy wirings 211 to 216 constituting each dummy wiring row have a wiring length L2 that is longer than the wiring width W1 of the main wiring 111 and shorter than the wiring length L1. When the wiring length L1 of the main wiring 111 is 100 μm or more, the wiring length L2 of the dummy wirings 211 to 216 is set to 50 μm or less (described later).

  In other words, the plurality of dummy wiring rows arranged in the wiring width direction of the main wiring 111 has a wiring length L2 that is longer than the wiring width W1 of the main wiring 111 and shorter than the wiring length L1, and the wiring width of the main wiring 111 It is divided into dummy patterns 211 to 216 each having a wiring width W2 equivalent to W1 (specifically, 0.5 times to 2 times the wiring width W1).

  In the first embodiment, the wiring length L1 of the main wiring 111 is 100 μm, the wiring width W1 of the main wiring 111 is 0.10 μm, and the wiring width W2 of the dummy wirings 211 to 216 is 0.10 μm. Further, the distance S1 between the main wiring 111 and the dummy wiring 211 and the distance S2 between the dummy wirings were each 0.10 μm.

Next, a method for manufacturing the semiconductor device will be described.
FIG. 2 is a process sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
First, as shown in FIG. 2A, another insulating film 101 is formed on the semiconductor substrate 100 covered with the insulating film 100a. Then, a positive resist film 102 is formed on the insulating film 101.
Next, as shown in FIG. 2B, the exposure light 103 is irradiated to the resist film 102 through a mask 10 in which openings corresponding to the wiring pattern shown in FIG. 1 are formed. For the pattern exposure, for example, an ArF excimer laser exposure apparatus having a numerical aperture NA = 0.75 is used. As the mask 10, for example, a halftone phase shift mask in which a translucent film 10b is formed on a transparent substrate 10a can be used. The opening is formed in the translucent film 10b. Thereafter, PEB (post-exposure baking) and development processing are performed to form a resist pattern 104 as shown in FIG.
Further, as shown in FIG. 2C, the insulating film 101 is anisotropically etched using the resist pattern 104 as a mask. Thereby, a groove corresponding to the wiring pattern is formed in the insulating film 101.
Next, after a thin barrier metal (adhesion layer) is formed on the entire surface of the substrate 100 including the inside of the groove, a Cu film is deposited by a PVD method and an electrolytic plating method. Then, an unnecessary Cu film deposited outside the inside of the groove is removed by a CMP method. Thereby, a wiring pattern as shown in FIG. 2D, that is, the main wiring 111 and the dummy wirings 211 to 216 are formed. The cross-sectional structure shown in FIG. 2D corresponds to the AA ′ cross section in FIG.

As described above, in the first embodiment, a plurality of dummy wiring rows are provided in the wiring width direction of the main wiring 111. By arranging a plurality of dummy wirings 211 to 216 having a wiring width W2 equivalent to the wiring width W1 of the main wiring 111 and having a wiring length L2 shorter than the wiring length L1 of the main wiring 111 in the wiring length direction. The dummy wiring row was configured. Therefore, the main wiring 111 having a narrow wiring width equal to or smaller than the resolution limit for the isolated wiring of the exposure apparatus can be formed. More specifically, even if the resolution limit for the isolated wiring of the exposure apparatus is 0.12 μm, the influence of the proximity effect and the microloading effect is eliminated, and the wiring width W1 is reduced without the influence of resist non-resolution or resist collapse. It becomes possible to form the trench wiring 111 having a thickness of 0.10 μm.
Furthermore, by setting the wiring length L2 of the dummy wirings 211 to 216 to 50 μm or less, it is possible to form the groove wiring 111 having a wiring length L1 of 100 μm or more. That is, even if the wiring length L1 of the main wiring 111 is as long as 100 μm or more, a large margin for resist collapse can be obtained. This is because, when a positive resist is used, the resist remaining in the corresponding portion between the dummy wirings in the wiring length direction becomes a support in the wiring width direction.
In addition, since a cross-sectional shape equivalent to the wiring dense portion of the integrated circuit is obtained, when the wiring 111 is a wiring to be measured, the wiring 111 having wiring characteristics (here, resistance value) equivalent to that of the wiring dense portion is obtained. can get.

  On the other hand, as a comparative example with respect to the first embodiment, a line-and-space pattern of 100 μm length and 0.10 μm / 0.10 μm was formed on both sides of the main wiring 111 as a dummy wiring. That is, the main wiring and the dummy wiring were formed with L1 = L2 = 100 μm, W1 = W2 = 0.10 μm, and S1 = S2 = 0.10 μm. In this comparative example, the resist pattern collapsed near the center in the wiring length direction (near 50 μm) in both the main wiring and the dummy wiring.

  In the first embodiment, two pads are provided as the current supply terminals 121 and 122 and the voltage measurement terminals 131 and 132, respectively. However, the current supply terminals 121 and 122 and the voltage measurement terminals 131 and 132 are provided. May also be used to reduce the number of pads (the same applies to the second, third, fourth, and fifth embodiments described later).

  Further, although three dummy wiring lines are provided on both sides of the main wiring 111, in order to make the pattern density uniform if there are no restrictions such as masking for lithography and data processing for electron beam direct drawing exposure. In addition, it is preferable that there are many dummy wiring lines. Here, if at least two dummy wiring rows are provided on both sides of the main wiring 111, the effect of the first embodiment can be obtained (the same applies to the second, third, fourth, and fifth embodiments described later).

  Further, in the first embodiment, the main wiring 111 is not limited to a wiring to be measured for measuring resistance, but may be a wiring for measuring electrical characteristics such as capacitance between wirings and leakage current. The wiring may be a part of a normal element function (the same applies to the second, third, fourth, and fifth embodiments described later).

  In the first embodiment, an example in which three dummy wiring rows are arranged on both sides of the main wiring 111 when the same type of wiring does not exist on both sides of the main wiring 111 has been described. If the same type of wiring exists, the dummy wiring row only needs to be arranged on the opposite side. For example, when the same kind of wiring exists on the dummy wirings 214 to 216 side, only the columns of the dummy wirings 211 to 213 may be formed (the same applies to the second, third, fourth, and fifth embodiments described later).

  Alternatively, like a conventional gate wiring or Al alloy wiring, a wiring material film for forming a wiring layer may be formed on the entire surface of the substrate, and the wiring material film may be processed to pattern the wiring. Furthermore, the present invention can be applied to a pattern for measuring the resistance of a diffusion layer surrounded by an isolation insulating film (the same applies to Embodiment 2-7 described later).

Embodiment 2. FIG.
FIG. 3 is a plan view for explaining the semiconductor device according to the second embodiment of the present invention.
As shown in FIG. 3, the wiring 111 has a wiring width W2 that is 0.5 to 2 times the wiring width W1 of the main wiring 111 on both sides of the main wiring 111, as in the first embodiment. A row of a plurality of dummy wirings 211 to 213 and 214 to 216 having a wiring length L2 longer than the width W1 and shorter than the wiring length L1 is formed. A plurality of rows of dummy wirings 211 to 213 including the dummy wiring 211 closest to the main wiring 111 are connected via a lead wiring 217, and the dummy wiring 213 is connected to a voltage supply terminal 221 via a lead wiring 218. Yes. Similarly, a plurality of columns of dummy wirings 214 to 216 including the dummy wiring 214 closest to the main wiring 111 are connected via the lead wiring 219, and the dummy wiring 216 is connected to the voltage supply terminal 222 via the lead wiring 220. It is connected. By supplying a voltage to the voltage supply terminals 221 and 222, a voltage is supplied to the dummy wirings 211 and 214 that are closest to the main wiring 111.
In the second embodiment, as in the first embodiment, the wiring length L1 of the main wiring 111 is 100 μm, the wiring width W1 of the main wiring 111 is 0.10 μm, and the wiring width W2 of the dummy wirings 211 to 216 is 0. 10 μm. Further, the distance S1 between the main wiring 111 and the dummy wirings 211 and 214 and the distance S2 between the dummy wirings were each 0.10 μm.

  As described above, in the second embodiment, a plurality of dummy wiring rows are provided in the wiring width direction of the main wiring 111 as in the first embodiment. By arranging a plurality of dummy wirings 211 to 216 having a wiring width W2 equivalent to the wiring width W1 of the main wiring 111 and having a wiring length L2 shorter than the wiring length L1 of the main wiring 111, the dummy wiring is arranged. A wiring line was constructed. Further, the dummy wirings 211 to 213 and 214 to 216 are connected via the lead wirings 217 and 219, and the dummy wirings 213 and 216 are connected to the voltage supply terminals 221 and 222 via the lead wirings 218 and 220. As a result, a voltage can be supplied to the dummy wirings 211 and 214 closest to the main wiring 111. Therefore, in addition to the effects obtained in the first embodiment, the current flowing from the dummy wirings 211 and 214 to the main wiring 111 through the insulating film can be measured. Therefore, new knowledge about the characteristics of the insulating film existing between the main wiring 111 and the dummy wirings 211 and 214, pattern formation defects, and the like can be obtained.

  In the second embodiment, the dummy wirings 213 and 216 and the terminals 221 and 222 are connected via the lead-out wirings 218 and 220. However, the dummy wirings 211 and 214 and the terminals 221 and 222 which are close to the main wiring 111 are connected. Or the dummy wirings 212 and 215 connected to the dummy wirings 211 and 214 and the terminals 221 and 222 may be connected.

Embodiment 3 FIG.
FIG. 4 is a plan view for explaining the semiconductor device according to the third embodiment of the present invention.
As shown in FIG. 4, the main wiring 112 has a meandering shape bent at right angles at a plurality of positions in the horizontal direction of the substrate. More specifically, the main wiring 112 extends in the left-right direction in the drawing, for example, a wiring 112 a having a length of 200 μm and a wiring 112 b extending in the vertical direction in the drawing, for example, 2 μm in length. The total wiring length (total wiring length) of the main wiring 112 is, for example, 20198 μm. Both ends of the wiring 112 are connected to pads 123 and 124 as current supply terminals and pads 133 and 134 as voltage measurement terminals. Similar to the first embodiment, both sides of the main wiring 112 have a wiring width W2 equivalent to the wiring width W1 of the main wiring 112, and are longer than the wiring width W1 of the main wiring 111 and shorter than the wiring length L1. A row of a plurality of dummy wirings 231 to 236 having a length L2 is provided. The columns of the dummy wirings 231 to 236 are arranged to meander in parallel with the main wiring 112.
In the third embodiment, as in the first embodiment, the wiring width W1 of the main wiring 112 is 0.10 μm, and the wiring width W2 of the dummy wirings 231 to 236 is 0.10 μm. Further, the distance S1 between the main wiring 112 and the dummy wirings 231 and 234 and the distance S2 between the dummy wirings were each 0.10 μm.

As described above, in the third embodiment, the main wiring 112 is not a straight line, but the wirings 112a and 112b are alternately connected to form a meandering shape. As in the first embodiment, a plurality of dummy wiring rows are provided in the wiring width direction of the main wiring 112. By arranging a plurality of dummy wirings 231 to 236 having a wiring width W2 equal to the wiring width W1 of the main wiring 112 and having a wiring length L2 of 50 μm or less in the wiring length direction of the main wiring 112, the dummy wiring row is formed. Configured. Therefore, in addition to the effects obtained in the first embodiment, electrical characteristic measurement that requires the wiring length of the main wiring 112 to be 400 μm or more, such as wiring electromigration evaluation (hereinafter referred to as “EM evaluation”). It can be performed.
Further, by bending the main wiring 112, a compact wiring pattern can be formed. In other words, if the main wiring having the same total wiring length is formed in a straight line pattern that is not bent, the main wiring alone occupies a length exceeding 20 mm, for example. However, according to the third embodiment, only one side of the main wiring is 200 μm. Can only occupy a square. Therefore, the space on the semiconductor substrate can be effectively utilized.
It should be noted that the interval between the adjacent wirings 112a and 112a can be reduced to an interval at which two dummy wiring rows can be arranged at intervals S1 and S2. In this case, the wirings 112a and 112a sandwiching the two dummy wiring rows share the two dummy wiring rows, thereby obtaining the effect of the third embodiment.

Embodiment 4 FIG.
FIG. 5 is a plan view for explaining the semiconductor device according to the fourth embodiment of the present invention.
The main wirings 113 and 114 are formed in two wiring layers through vias 311, respectively. That is, FIG. 5 shows a two-layer Cu wiring module formed as a wiring pattern on a semiconductor substrate (not shown). A first main wiring 113 is formed in the first wiring layer. In the second wiring layer above the first wiring layer, a second main wiring 114, current supply terminals 125 and 126, and voltage measurement terminals 135 and 136 are formed. A via 311 connecting the first and second main wirings 113 and 114 is formed in the via layer between the first wiring layer and the second wiring layer. The terminals 125, 126, 135, and 136 may not be formed in the second wiring layer, but may be formed as Al pads further above the second wiring layer.
In the first wiring layer, on both sides of the main wiring 113, as in the first embodiment, the wiring width W2 is 0.5 to 2 times the wiring width W1 of the main wiring 113, and the wiring length L2 is 50 μm or less. A plurality of rows of dummy wirings 241 to 243 and 244 to 246 are formed. Similarly, in the second wiring layer, columns of a plurality of dummy wirings 251 to 253 and 254 to 256 are formed on both sides of the main wiring 114. In the first and second wiring layers, the dummy wirings 241 to 246 and 251 to 256 are formed not only on both sides of the main wirings 113 and 114 but also on both sides at positions corresponding to the upper wiring or the lower wiring main wirings 114 and 113. ing. Thereby, in the vicinity of the via 311 of the main wirings 113 and 114, the influence of the proximity effect and the microloading effect from the wiring length direction can be eliminated.
In the fourth embodiment, the wiring lengths of the main wirings 113 and 114 are each slightly over 100 μm, and the distance L3 between the via 311 centers is 100 μm. In the fourth embodiment, the wiring width W1 of the main wirings 113 and 114 is 0.10 μm, and the wiring width W2 of the dummy wirings 241 to 246 and 251 to 256 is 0.10 μm. Further, an interval S1 between the main wirings 113 and 114 and the dummy wirings 241, 244, 251, and 254 and an interval S2 between the dummy wirings were set to 0.10 μm, respectively.

Next, although not shown, a method for manufacturing the semiconductor device will be briefly described.
A first wiring layer including the main wiring 113 and the dummy wirings 241 to 246 is formed on the semiconductor substrate by using the damascene method described with reference to FIG. Next, a via layer including the via 311 is formed using a damascene method. Further, a second wiring layer including the main wiring 114 and the dummy wirings 251 to 256 is formed using a damascene method. A method for forming such a multilayer wiring layer is generally called a single damascene method. By using this method, as described above, a two-layer Cu wiring module in which the main wirings 113 and 114 are arranged across two wiring layers via the via 311 is formed. The pads (terminals) may be formed in the second wiring layer together with the main wiring 114 or the like, or may be formed as an upper layer module having a pad made of an Al alloy above the second wiring layer.

  As described above, in the fourth embodiment, the main wirings 113 and 114 are formed not over the same layer but over a plurality of wiring layers via the via 311. Further, the wirings 113 and 114 are arranged so that the distance L3 between the centers of the vias 311 is 50 μm or more. Then, columns of dummy wirings 241 to 246 and 251 to 256 are arranged on both sides of the main wirings 113 and 114. Therefore, by measuring the resistance of the wirings 113 and 114 including the via 311 in series, it is possible to measure the resistance of the pattern in which the distance between the via centers is 50 μm or more. Therefore, in addition to the effects obtained in the first embodiment, it is possible to obtain the patterns 113 and 114 including the vias 311 having the same characteristics as those of the wiring dense portion, and the EM evaluation of the patterns 113 and 114 including the vias 311 is also performed. Newly implemented. In particular, when a EM evaluation of a pattern including a via is performed under a normal test condition on a sample in which a barrier metal is buried with a thickness of 5 nm or more at the bottom of the via 311, the wiring length between via centers is less than 50 μm. However, it is generally known that the lifetime of the EM evaluation becomes longer than the original value due to the backflow effect when it is short, and the backflow effect is suppressed by using the wiring pattern according to the fourth embodiment. An EM test can be performed.

  In the fourth embodiment, the case where the multilayer wiring layer is formed using the single damascene method has been described. However, the via 311 portion of the via layer and the groove wiring portion of the second wiring layer (that is, the main wiring 114). Alternatively, the dummy wirings 251 to 256 and the terminals 125, 126, 135, and 136) may be formed by using a dual damascene method in which a metal material (Cu) is simultaneously embedded (the same applies to Embodiment 5-7 described later). .

Furthermore, although the case where the main wirings 113 and 114 are arranged over two wiring layers has been described in the fourth embodiment, the main wirings 113 and 114 may be arranged over three or more wiring layers through vias ( The same applies to Embodiment 5-7 described later).
Further, in the fourth embodiment, the example in which there are two locations where the main wirings 113 and 114 are connected and one via 311 is formed at each connection location has been described, but there are three locations where the layers are connected. Alternatively, two or more vias may be formed at each connection location (the same applies to Embodiment 5-7 described later).

Next, a modification of the fourth embodiment will be described.
FIG. 6 is a plan view for explaining a modification of the fourth embodiment of the present invention.
As shown in FIG. 6, the main wirings 113 and 114 in the vicinity of the via 311, that is, the regions 113 a and 114 a in the vicinity of the connection locations of the main wirings 113 and 114 are expanded. As described above, by expanding the connection portion vicinity regions 113a and 114a of the main wirings 113 and 114, misalignment of the via 311 with respect to the main wirings 113 and 114 can be eliminated, and the reliability of the wiring pattern is further improved. Can do.

Embodiment 5 FIG.
FIG. 7 is a schematic cross-sectional view showing the arrangement of the main wirings and vias in the semiconductor device according to the fifth embodiment of the present invention.
In the fifth embodiment, as in the fourth embodiment, a two-layer Cu wiring module in which the main wirings 113 and 114 are formed across two wiring layers through vias 311 will be described. As described in the fourth embodiment, terminals (pads) (not shown) are formed on the second wiring layer where the main wiring 114 is formed or on the second wiring layer.
The difference from the fourth embodiment is that, as shown in FIG. 7, the distances between the centers of the vias 311 are L11 = 2.4 μm, L12 = 4.8 μm, L13 = 9.6 μm, L14 = 20 μm, L15 = A plurality of vias 311 are arranged so that 49.6 μm and L16 = 100 μm. The main wirings 113 and 114 are alternately arranged corresponding to the plurality of vias 311. Other structures are the same as those of the fourth embodiment shown in FIG. Also in the fifth embodiment, as in the fourth embodiment, the wiring width (W2) is 0.5 to 2 times the wiring width (W1) of the main wirings 113 and 114 on both sides of the main wirings 113 and 114. And a plurality of dummy wiring columns having a wiring length (L2) of 50 μm or less. In the fifth embodiment, as in the fourth embodiment, the wiring width (W1) of the main wirings 113 and 114 is 0.10 μm, and the wiring width (W2) of the dummy wiring is 0.10 μm. Further, the interval (S1) between the main wires 113 and 114 and the dummy wires and the interval (S2) between the dummy wires were set to 0.10 μm, respectively.

  As described above, in the fifth embodiment, the plurality of main wirings 113 and 114 are formed not over the same layer but over a plurality of wiring layers via the plurality of vias 311. The center-to-center distances L11 to L16 of the plurality of vias 311 connecting the plurality of main wirings 113 and 114 are made different. A plurality of dummy wiring columns are arranged on both sides of the main wirings 113 and 114. Therefore, by conducting an EM evaluation test and analyzing the defective part due to the generation of voids, in addition to the effects obtained in the fourth embodiment, it is possible to obtain new knowledge regarding the frequency of void generation according to the via interval It became. In other words, it has become possible to newly obtain knowledge about the wiring length in which the backflow effect is suppressed. Since this knowledge is related to parameters specific to the sample structure and the sample preparation process, it can be quickly fed back to the improvement of the sample structure and the sample preparation process.

Embodiment 6 FIG.
FIG. 8 is a plan view for explaining the vicinity of the via of the semiconductor device according to the sixth embodiment of the present invention. FIG. 9 is a plan view showing a first wiring layer in the semiconductor device shown in FIG. 8, and FIG. 10 is a plan view showing a second wiring layer in the semiconductor device.
In the sixth embodiment, as in the fourth embodiment, a two-layer Cu wiring module in which the main wirings 115 and 116 are formed over two wiring layers through vias 311 will be described. The main wiring 115 is formed in the first wiring layer, and the main wiring 115 is formed in the second wiring layer. Terminals (pads) (not shown) are formed on the second wiring layer or an upper layer thereof.

As shown in FIGS. 8 to 10, the difference from the fourth embodiment is that, in the vicinity of the via 311 of the main wirings 115 and 116, on the opposite side of the main wiring 115 and 116 with respect to the via 311, during resistance measurement. This is that dummy wirings 411 and 412 that are not in series current paths are respectively arranged.
As in the fourth embodiment, the main wirings 115 and 116 have a wiring width W2 that is 0.5 to 2 times the wiring width W1 of the main wirings 115 and 116 and a wiring length L2 that is 50 μm or less. A plurality of columns of dummy wirings 261 to 270 and 271 to 280 are formed. In the sixth embodiment, as in the fourth embodiment, the wiring width W1 of the main wirings 115 and 116 is 0.10 μm, and the wiring width W2 of the dummy wirings 261 to 270 and 271 to 280 is 0.10 μm. Further, the distance S1 between the main wirings 115 and 116 and the dummy wirings 261, 266, 271, and 276 and the distance S2 between the dummy wirings were set to 0.10 μm, respectively.

  As described above, in the sixth embodiment, the main wirings 115 and 116 are formed not over the same layer but over a plurality of wiring layers via the via 311. A plurality of dummy wirings 261 to 270 having a wiring width W2 equivalent to the wiring width W1 of the main wirings 115 and 116 on both sides of the main wirings 115 and 116 in each wiring layer and having a wiring length L2 of 50 μm or less. , 271 to 280 are arranged. Further, dummy wirings 411 and 412 that do not form a series current path at the time of resistance measurement are provided on the opposite side of the via 311 from the wirings 115 and 116 where the main wirings 115 and 116 are connected to the via 311. Formed. Therefore, in addition to the effects obtained in the fourth embodiment, a wiring pattern with higher accuracy than that of the fourth embodiment and having the same three-dimensional shape and characteristics as the wiring of the dense wiring portion can be obtained. In particular, by using this wiring pattern and performing an EM test according to the lengths of the dummy wirings 411 and 412, it is possible to systematically estimate the life extension due to the effect of the reservoir.

Next, a modification of the sixth embodiment will be described.
FIG. 11 is a plan view for explaining the vicinity of a via of a semiconductor device according to a modification of the sixth embodiment of the present invention. 12 is a plan view showing a first wiring layer in the semiconductor device shown in FIG. 11, and FIG. 13 is a plan view showing a second wiring layer in the semiconductor device.
In the sixth embodiment, the dummy wirings 411 and 412 that are arranged on the opposite side of the vias 311 from the main wirings 115 and 116 and do not form a series current path when measuring resistance are formed. Further, the dummy wirings 411 and 412 formed on the extension lines of the main wirings 115 and 116 and the main wirings 115 and 116 are electrically short-circuited.
In contrast, in this modification, as shown in FIGS. 11 to 13, the via exists on the opposite side of the wirings 115 and 116 with respect to the via 311, and does not form a series current path when measuring resistance. The dummy wirings 413 and 414 and the main wirings 115 and 116 are electrically insulated.

  In this modification, as in the sixth embodiment, the shape of the dummy wirings 413 and 414 and the distance between the dummy wirings 413 and 414 and the main wirings 115 and 116 are actually present in the dense wiring portion of the integrated circuit. It can be set to be equivalent to the layout being done. Accordingly, not only after the lithography process but also after the etching process or CMP, the three-dimensional shape near the ends (near the vias) of the wirings 115 and 116 actually exists in the dense wiring part of the integrated circuit. It can be reproduced in the same manner as the three-dimensional shape at the wiring end. In other words, an optical proximity correction technique (Optical proximity correction: OPC) including the etching process, which is important when forming a fine pattern of W1 = 0.14 μm or less, can be realized in a simple form. Furthermore, by performing an EM test using the pattern shown in FIG. 11, a highly accurate via EM test can be performed.

In the sixth embodiment and the modification thereof, five dummy wiring lines are provided on both sides of the main wirings 115 and 116. However, there are restrictions on mask processing for lithography and data processing for electron beam direct drawing exposure. If not, it is preferable that the number of dummy wiring rows is large in order to make the pattern density uniform. Here, if at least two dummy wiring rows are provided on both sides of the main wirings 115 and 116, the effect of the sixth embodiment can be obtained (the same applies to the seventh embodiment described later).
In addition, the wiring pattern for measuring the resistance has been described. However, the wiring pattern exists between the wiring pattern for measuring the electrical characteristics such as the capacitance between the wirings and the leakage current, or between the elements, and the voltage or current is present. It can be used as a wiring pattern that functions to give and receive (the same applies to Embodiment 7 described later).
In the sixth embodiment and its modification, dummy wiring rows 261 to 270 and 271 to 280 are arranged on both sides of the main wirings 115 and 116 when the same kind of wiring does not exist on both sides of the main wirings 115 and 116. However, if the same type of wiring exists on one side of the main wirings 115 and 116, a dummy wiring row may be arranged only on the opposite side (the same applies to the seventh embodiment described later).
Further, as in the fifth embodiment, a plurality of vias may be provided and a plurality of main wirings 115 and 116 may be alternately arranged (the same applies to the seventh embodiment described later).

Embodiment 7 FIG.
FIG. 14 is a plan view for explaining the vicinity of the via of the semiconductor device according to the seventh embodiment of the present invention. 15 is a plan view showing a first wiring layer in the semiconductor device shown in FIG. 14, and FIG. 16 is a plan view showing a second wiring layer in the semiconductor device.
In the seventh embodiment, as in the fourth embodiment, a two-layer Cu wiring module in which the main wirings 115 and 116 are formed across two wiring layers via the via 311 will be described.

A difference from the fourth embodiment is that, as shown in FIGS. 14 to 16, dummy vias 312 for connecting dummy wirings 261 to 270 and dummy wirings 271 to 280 so as not to form a series current path at the time of resistance measurement. Is a plurality of points. That is, in the via layer between the first wiring layer and the second wiring layer, the via 311 that connects the first main wiring 115 and the second main wiring 116, the dummy wirings 261 to 270, and the dummy wiring 271. Dummy vias 312 that connect ˜280 are formed. Terminals (pads) (not shown) are formed on the second wiring layer or an upper layer thereof. By connecting the lower layer dummy wirings 261 to 270 and the upper layer dummy wirings 271 to 280 which are shifted from each other in the wiring length direction by the dummy vias 312, a via chain in which the dummy wirings are alternately connected in the wiring length direction is configured. The via pattern density may be selected within the range set by the design standard.
In the seventh embodiment, the wiring width W1 of the main wirings 115 and 116 is 0.10 μm, and the wiring width W2 of the dummy wirings 261 to 270 and 271 to 280 is 0.10 μm. Further, the distance S1 between the main wirings 115 and 116 and the dummy wirings 261, 266, 271, and 276 and the distance S2 between the dummy wirings were set to 0.10 μm, respectively.

  As described above, in the seventh embodiment, the main wirings 115 and 116 are formed not over the same layer but over a plurality of wiring layers via the via 311. A plurality of dummy wirings 261 to 270 having a wiring width W2 equivalent to the wiring width W1 of the main wirings 115 and 116 on both sides of the main wirings 115 and 116 in each wiring layer and having a wiring length L2 of 50 μm or less. , 271 to 280 are arranged. Furthermore, a plurality of dummy vias 312 connecting the lower layer dummy wirings 261 to 270 and the upper layer dummy wirings 271 to 280 are arranged so as not to form a series current path during resistance measurement. Thereby, in addition to the effects obtained in the fourth embodiment, not only the wiring layer but also the via layer can reproduce the environment equivalent to the via pattern dense part in the element, and the same three-dimensionality as the dense wiring part. Shapes and characteristics can be obtained. In other words, not only at the wiring portion in the resistance measurement pattern but also at the via portion, a three-dimensional shape equivalent to the layout actually existing in the dense wiring portion of the integrated circuit can be reproduced. became. Therefore, it is not necessary to investigate in detail the differences in the exposure shape, etching shape, and the etched shape due to CMP due to the density of vias, or the difference in peeling and cleaning effects due to the density of vias. In addition, it is possible to perform an EM test that simulates the three-dimensional shape and characteristics of the via dense portion in the element with higher accuracy.

Next, a modification of the seventh embodiment will be described.
FIG. 17 is a plan view for explaining the vicinity of the via of the semiconductor device according to the first modification of the seventh embodiment of the present invention. As shown in FIG. 17, in the first modification, the dummy wirings 261 to 270 of the first wiring layer and the dummy wirings 271 to 280 of the second wiring layer are arranged in parallel. Lower layer dummy wirings 261 to 270 and upper layer dummy wirings 271 to 280 are connected by dummy vias 312. That is, the upper and lower layers of dummy wiring are only unitized via the dummy via 312, and the dummy chain (via chain) as in the seventh embodiment is not configured. Also according to the first modification, an effect equivalent to the effect obtained in the seventh embodiment can be obtained.
Further, in the first modified example, the main wirings 115 and 116 near the via 311, that is, the regions 115 a and 115 a near the connection points of the main wirings 115 and 116 are expanded. Therefore, misalignment of the via 311 with respect to the main wirings 115 and 116 can be eliminated, and the reliability of the wiring pattern can be further improved.

  FIG. 18 is a plan view for explaining the vicinity of a via of a semiconductor device according to a second modification of the seventh embodiment of the present invention. As shown in FIG. 18, in the second modification, dummy wirings 413 and 414 that do not form a series current path at the time of resistance measurement are arranged on the opposite side of the via 311 from the main wirings 115 and 116. . A plurality of dummy vias 313 for connecting the lower layer dummy wiring 413 and the upper layer dummy wiring 414 are arranged. Also according to the second modification, an effect equivalent to the effect obtained in the seventh embodiment can be obtained.

It is a top view for demonstrating the semiconductor device by Embodiment 1 of this invention. It is process sectional drawing for demonstrating the manufacturing method of the semiconductor device by Embodiment 1 of this invention. It is a top view for demonstrating the semiconductor device by Embodiment 2 of this invention. It is a top view for demonstrating the semiconductor device by Embodiment 3 of this invention. It is a top view for demonstrating the semiconductor device by Embodiment 4 of this invention. It is a top view for demonstrating the modification of Embodiment 4 of this invention. In the semiconductor device by Embodiment 5 of this invention, it is a schematic sectional drawing which shows arrangement | positioning of this wiring and via | veer. It is a top view for demonstrating the via | veer vicinity of the semiconductor device by Embodiment 6 of this invention. FIG. 9 is a plan view showing a first wiring layer in the semiconductor device shown in FIG. 8. FIG. 9 is a plan view showing a second wiring layer in the semiconductor device shown in FIG. 8. It is a top view for demonstrating the via | veer vicinity of the semiconductor device by the modification of Embodiment 6 of this invention. FIG. 12 is a plan view showing a first wiring layer in the semiconductor device shown in FIG. 11. FIG. 12 is a plan view showing a second wiring layer in the semiconductor device shown in FIG. 11. It is a top view for demonstrating the via | veer vicinity of the semiconductor device by Embodiment 7 of this invention. FIG. 15 is a plan view showing a first wiring layer in the semiconductor device shown in FIG. 14. FIG. 15 is a plan view showing a second wiring layer in the semiconductor device shown in FIG. 14. It is a top view for demonstrating the via | veer vicinity of the semiconductor device by the 1st modification of Embodiment 7 of this invention. It is a top view for demonstrating the via | veer vicinity of the semiconductor device by the 2nd modification of Embodiment 7 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Mask 10a Transparent substrate 10b Translucent film 100 Semiconductor substrate 100a Insulating film 101 Insulating film 102 Resist film 103 Exposure light 104 Resist pattern 111,112,113,114,115,116 Main wiring 121,122,123,124,125, 126 Current supply terminals 131, 132, 133, 134, 135, 136 Voltage measurement terminals 211 to 216, 231 to 236 Dummy wirings 217 to 220 Drawer wirings 221 and 222 Voltage supply terminals 241 to 246, 251 to 256 Dummy wirings 261 to 270, 271 to 280 Dummy wiring 311 Via 312, 313 Dummy via 411, 412, 413, 414 Dummy wiring

Claims (8)

A semiconductor device in which a wiring pattern including a main wiring and a dummy wiring is formed in an insulating film on a semiconductor substrate,
A main wiring having a predetermined wiring length;
A plurality of dummy wiring rows arranged in the wiring width direction of the main wiring,
A dummy wiring having a wiring width of 0.5 to 2 times the wiring width of the main wiring and having a wiring length longer than the wiring width of the main wiring and shorter than the wiring length of the main wiring; A semiconductor device characterized in that each dummy wiring row is configured by arranging a plurality of wirings in the wiring length direction. A semiconductor device in which a wiring pattern including a main wiring and a dummy wiring is formed in an insulating film on a semiconductor substrate,
A main wiring having a predetermined wiring length;
A plurality of dummy wiring rows arranged in the wiring width direction of the main wiring,
By arranging a plurality of dummy wirings having a wiring width of 0.5 to 2 times the wiring width of the main wiring and having a wiring length of 50 μm or less in the wiring length direction of the main wiring, A semiconductor device comprising: A semiconductor device in which a wiring pattern including a main wiring and a dummy wiring is formed in an insulating film on a semiconductor substrate,
A main wiring having a wiring length of 100 μm or more;
A plurality of dummy wiring rows arranged in the wiring width direction of the main wiring,
By arranging a plurality of dummy wirings having a wiring width of 0.5 to 2 times the wiring width of the main wiring and having a wiring length of 50 μm or less in the wiring length direction of the main wiring, A semiconductor device comprising: The semiconductor device according to any one of claims 1 to 3,
A lead-out wiring that connects dummy wirings of a plurality of dummy wiring rows including the dummy wiring row that is closest to the main wiring;
A semiconductor device further comprising a terminal connected to any one of the dummy wirings connected by the lead wiring. The semiconductor device according to claim 1,
The main wiring has a shape bent in the horizontal direction of the semiconductor substrate at a plurality of locations. The semiconductor device according to any one of claims 1 to 5,
The main wiring includes a first main wiring arranged in a lower layer, a second main wiring arranged in an upper layer than the first main wiring, and a via connecting the first and second main wirings. And
A plurality of dummy wiring rows are arranged in the wiring width direction of the first and second main wirings, respectively. The semiconductor device according to claim 6.
The main wiring has a plurality of the first and second main wirings and the vias, respectively.
2. The semiconductor device according to claim 1, wherein the vias are arranged at different intervals. The semiconductor device according to claim 6 or 7,
2. A semiconductor device according to claim 1, wherein the dummy wirings are arranged on opposite sides of the first and second main wirings with respect to the via.

Images