JP2005286220A - Quality evaluation method of silicon wafer - Google Patents

Abstract

In addition to conventional flow pattern defects and Secco etch pit defects, the present invention provides an egg-shaped pit, a pit with a plurality of egg molds, and a plurality of egg molds in an interstitial silicon excess region. By counting the number of pits that contain lines from overlapping locations, it is possible to evaluate the quality of silicon wafers in a simple manner and in a short time, and to provide a quality evaluation method that can also evaluate and discriminate the boundaries. Is.
A silicon wafer is cut out from a silicon single crystal, and the cutting strain at the time of cutting is removed with a mixed solution of hydrofluoric acid and nitric acid, and then immersed in a mixed solution of hydrogen peroxide and ammonia. After immersing in hydrofluoric acid, immerse in a mixed solution of hydrofluoric acid and potassium dichromate, the egg-shaped pits appearing on the surface, the pits with multiple egg molds, and the parts where multiple egg molds overlap The silicon wafer quality evaluation method is characterized in that the quality of the silicon wafer in the interstitial silicon excess region is evaluated by counting the pits containing the lines from.
[Selection] Figure 1

Description

  The present invention relates to a quality evaluation method for silicon wafers.

  In general, when manufacturing a silicon wafer, it is usual to pull up a single crystal by the Czochralski method. In pulling a silicon single crystal, it is known that the type and concentration of point defects can be determined by the pulling speed V and the ratio of the temperature gradient G at the pulling crystal-melt boundary, V / G.

  FIG. 4 schematically shows the relationship between the V / G value and the distribution of point defects in the silicon single crystal ingot. As shown in the figure, the V / G value also decreases as the pulling speed of the single crystal ingot gradually decreases from the head side to the tail side after growing the neck. The point defect distribution inside also changes. As shown in FIG. 4, the value of the temperature gradient G at the pulling crystal-melt boundary is small, and when the pulling speed V is large, that is, when V / G is large, the void excess region 5 is formed. . As the value of V / G decreases, the voids aggregate and void defects are generated. Below the critical V / G value where the void excess region 5 disappears, a ring OSF (Ring Oxidation-induced Stacking Fault) region 6 is formed. Next, the defect-free region 7 is formed by the balance between the vacancies and the interstitial silicon concentration. When the V / G value further decreases, an interstitial silicon excess region 8 is formed, and an interstitial silicon agglomerated defect is generated.

Regarding the evaluation of aggregates of point defects occurring in these regions, the prior art includes cutting a wafer from a silicon semiconductor crystal rod immediately after growth and etching a strained layer on the surface with a mixed solution of hydrofluoric acid and nitric acid. After removal, pits and ripples are generated by a mixture of K ₂ Cr ₂ O ₇ , hydrofluoric acid and water, and the density of the pits and ripples is examined. The density of such pits and ripples and the collection of point defects It has been disclosed to evaluate a collection of point defects by utilizing the correlation of bodies (Patent Document 1). In another prior art, a flow pattern is a V-shaped etching unevenness caused by immersing a silicon wafer in a mixed solution of hydrofluoric acid and potassium dichromate and the presence of a crystal defect portion of the silicon wafer. And a method of counting the number of seco etch pits which are crystal defects not accompanied by the flow pattern, and evaluating the quality of the silicon wafer based on the total of these (Patent Document 2).
JP-A-4-285100 (Claims) JP-A-8-306753 (Claims)

  The silicon wafer quality inspection method disclosed in Patent Document 1 provides a method capable of evaluating a cluster of point defects quickly and inexpensively. According to this method, quality evaluation is performed in an interstitial silicon excess region. I can't do that. In addition, the quality evaluation method for silicon wafers in Patent Document 2 measures and evaluates not only flow pattern defects but also seco etch pits, thereby improving the reliability of silicon wafer defect evaluation methods that have been unstable in the past. This is a significant improvement, but this also did not evaluate the quality in the interstitial silicon excess region.

  Furthermore, in the copper decoration method of decorating copper in a soaking furnace maintained at 1000 ° C., which is another conventional technique, it takes time to decorate copper, and subsequent X-ray photography takes time, and this method However, it was possible to evaluate macroscopically but not quantitatively, and it was impossible to evaluate the quality in the interstitial silicon excess region.

  In addition to conventional flow pattern defects and Secco etch pit defects, the present invention provides an egg-shaped pit, a plurality of egg-shaped pits, and a plurality of egg-shaped overlapping portions in an interstitial silicon excess region. It is intended to provide a quality evaluation method that can evaluate the quality of silicon wafers in a simple method and in a short time by counting the pits that contain lines from the edge, and also evaluate and discriminate the boundaries. .

  In this invention, a silicon wafer is cut out from a silicon single crystal, the cutting strain at the time of cutting is removed with a mixed solution of hydrofluoric acid and nitric acid, and then immersed in a mixed solution of hydrogen peroxide and ammonia. After immersing in hydrofluoric acid, immerse in a mixed solution of hydrofluoric acid and potassium dichromate, the egg-shaped pits appearing on the surface, the pits where the egg molds overlapped, the location where the egg molds overlapped The silicon wafer quality evaluation method is characterized in that the quality of the silicon wafer in the interstitial silicon excess region is evaluated by counting the pits containing the lines from.

  According to the present invention, in addition to the conventional flow pattern defect and seco etch pit defect, there is a line from the egg-shaped pit, the pit with a plurality of egg molds overlapped, and further, the portion where the egg molds overlapped. Since quality evaluation can be performed in the interstitial silicon excess region of the silicon wafer based on the density of the pits, more information for evaluating the yield of the silicon wafer can be collected. Further, according to the present invention, the quality evaluation of such a silicon wafer can be performed quantitatively in a simple method and in a short time. Further, by adopting this evaluation method, it becomes possible to supply a wafer with a higher pressure resistance, and it is possible to further improve the yield.

  An embodiment of the present invention will be described below with reference to the drawings.

  By a conventional method, a silicon single crystal ingot having a diameter of 205 to 225 mm was grown by the CZ method. During the growth of the ingot, boron was doped into a quartz crucible having a diameter of 22 inches, and the electrical resistivity was adjusted to 10.5 Ωcm. The growth direction of the grown silicon single crystal is <100>. Further, when growing the silicon single crystal, the silicon single crystal was grown so that the V / G was adjusted and the growth rate was 0.5 to 0.55 mm / min in order to form an interstitial silicon excess region. .

  A silicon wafer having a thickness of 1 mm was cut out from the thus grown silicon single crystal and used as an evaluation sample. The strain at the time of cutting this silicon wafer with a mixed solution of hydrofluoric acid and nitric acid was removed. Then, wash it thoroughly with water, soak it in a mixture of hydrogen peroxide and ammonia water, and then immerse it in dilute hydrofluoric acid, then 9.70 mol / l hydrofluoric acid and 0.050 mol / l potassium dichromate And the sample was observed with an optical microscope.

  In this case, the state of the observed egg-shaped pit, the pit where a plurality of egg shapes overlap, and the pit where the line enters from the place where the egg shapes overlapped are schematically shown in FIG. Met. Further, FIG. 2 shows the density distribution of egg-shaped pits, pits in which a plurality of egg molds are overlapped, and pits having lines from the positions where the egg molds are overlapped. This figure shows where the pits are located from the center of the wafer. The region defined as the I-rich region in FIG. 2 is a high density among the interstitial silicon excess regions by the Cu decoration method in which copper is decorated in a soaking furnace maintained at 1000 ° C., which is a conventional technology. It is confirmed that the region where the interstitial silicon exists (I-rich region). From these results, if an egg-shaped pit, a pit with overlapping egg molds, or a pit with a line from a position where egg molds are overlapped appears in the present invention, it is determined that the region is an I-rich region. it can. Thus, in the present invention, the I-rich region can be more easily discriminated without performing the copper decoration method.

FIG. 3 shows areas determined by the quality evaluation method of the present invention. The number of egg-shaped pits, pits with overlapping egg molds, and the number of pits with a line from the overlapped part of the egg molds per wafer. Thus, it is clear that the interstitial silicon excess regions (1 to 3) of the wafers having an average of 3 pieces / cm ² or less all exhibit excellent pressure strength (C mode ratio). In FIG. 3, reference numeral 4 denotes an egg-shaped pit, an egg-shaped overlapping pit, and an interstitial silicon excess region of the wafer when the number of pits that are inserted from the overlapping portion of the egg-shaped is four or more. This shows the pressure strength (C mode ratio). Reference numeral 5 denotes the pressure strength (C mode ratio) of the void excess region.

Explanatory drawing which shows typically the state of the pit of the egg-shaped pit, the pit where two or more egg molds overlapped, and the pit where the line has entered from the part where the egg molds overlapped. A diagram showing the relationship between the distance from the wafer center and the pit density. The figure which showed the relationship between the various wafers evaluated by this invention, and oxide film pressure | voltage resistant strength. Explanatory drawing which shows typically the relationship between V / G and the point defect part in a silicon single crystal ingot.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Flow pattern defect, 2 ... Seco etch pit, 3, 4 ... Etching pit confirmed by evaluation of this invention, 5 ... Excess void area, 6 ... Ring OSF area, 7 ... Defect-free area, 8 ... Interstitial Silicon excess area.

Claims (1)

A silicon wafer is cut out from a silicon single crystal, and the cutting strain at the time of cutting is removed with a mixed solution of hydrofluoric acid and nitric acid, and then immersed in a mixed solution of hydrogen peroxide and ammonia and further immersed in dilute hydrofluoric acid. After that, it is immersed in a mixed solution of hydrofluoric acid and potassium dichromate, and an egg-shaped pit that appears on the surface, a pit that has multiple egg molds, and a line from where the egg molds overlap. A quality evaluation method for a silicon wafer, wherein the quality of the silicon wafer in the interstitial silicon excess region is evaluated by counting the number of pits contained.

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