JP2005277985A - Variable gain circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a variable gain circuit in which a level control range is wide. <P>SOLUTION: The circuit is provided with attenuator circuits 42 to 44 which are connected in tandem for an input signal, and differential amplifiers 51 to 54 to which respective output signals of the input signal and the attenuator circuits 42 to 44, are supplied. Resistors R55, R56 which are connected to output terminals of the differential amplifiers 51 to 54, and take out level controlled output signals, and a logarithmic compression circuit 60 which converts AGC voltage VCTL to a control current of a predetermined property, are comprised. The control currents 171 to 174 outputted from the logarithmic compression circuit 60 are supplied to the differential amplifiers 51 to 54 as control signals of operation switching and a gain, and at the same time, the control current equivalent to the control currents 171 to 174 are carried out feedback in the logarithmic compression circuit 60. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a variable gain circuit.

  In general, the receiver is provided with an AGC circuit, but FIG. 8 shows an example of the receiver and the AGC circuit. This receiver is of a so-called low IF system in which the intermediate frequency is made much lower than the reception frequency by bringing the local oscillation frequency close to the reception frequency, and at this time, the received signal is a pair of intermediate signals orthogonal to each other. In addition to frequency conversion to frequency signals, image characteristics are improved by phase processing.

  That is, a reception signal SRX having a target reception frequency is taken out from the electronic tuning antenna tuning circuit 11, and this reception signal SRX is supplied to the pair of mixer circuits 13A and 13B through the high-frequency amplifier 12.

  Further, the local oscillation circuit 31 is constituted by a PLL, and the phases are 90 ° with each other at a frequency close to the frequency of the reception signal SRX (for example, a frequency higher by 500 kHz than the reception frequency in the case of a digital audio broadcast receiver). Two different signals SLOA and SLOB are formed, and these signals SLOA and SLOB are supplied to the mixer circuits 13A and 13B as local oscillation signals.

  Thus, in the mixer circuits 13A and 13B, the received signal SRX is frequency-converted into a pair of intermediate frequency signals SIFA and SIFB by the local oscillation signals SLOA and SLOB. In this case, the intermediate frequency signals SIFA and SIFB include a signal component of the intended reception frequency (original signal component) and a signal component of the image frequency. The signal components of the reception frequency are called intermediate frequency signals SIFA and SIFB, and the signal components of the image frequency are called image components.

  Since the local oscillation signals SLOA and SLOB have a phase difference of 90 °, the intermediate frequency signals SIFA and SIFB are orthogonal with a phase difference of 90 °, and the image components are the intermediate frequency signals SIFA and SIFB. It is orthogonal with a phase difference of 90 ° in the opposite relationship.

  Further, a part of the control voltage supplied to the variable capacitance diode of the VCO (not shown) of the PLL is extracted from the PLL constituting the local oscillation circuit 31, and this control voltage is supplied to the tuning circuit 11 as a tuning voltage. Thus, tuning with respect to the received signal SRX is realized.

  Then, the intermediate frequency signals SIFA and SIFB (and image components) from the mixer circuits 13A and 13B are supplied to the amplitude phase correction circuit 14 to correct the relative amplitude error and phase error of the intermediate frequency signals SIFA and SIFB, The error-corrected intermediate frequency signals SIFA and SIFB are supplied to the phase shift circuits 16A and 16B through the bandpass filters 15A and 15B. For example, the intermediate frequency signals SIFA and SIFB are in phase and the image components are in reverse phase. The phase is shifted as follows. Then, the intermediate frequency signals SIFA and SIFB after the phase shift are supplied to and added to the arithmetic circuit 17, and the intermediate frequency signal SIF from which the image component is canceled is extracted from the arithmetic circuit 17.

  Subsequently, the intermediate frequency signal SIF is supplied to the digital processing circuit 20 through the intermediate frequency amplifier 18 and the band pass filter 19 and A / D converted, and predetermined digital processing corresponding to the format of the received signal SRX. And audio signals L and R are extracted.

  The amplifiers 12 and 18 are variable gain amplifiers, and a part of the intermediate frequency signal SIF is supplied from the bandpass filter 19 to the AGC voltage forming circuit 32 to form the AGC voltage VAGC. The AGC voltage VAGC is the amplifier. 18 is supplied as a gain control signal, and AGC is performed for the intermediate frequency stage. Further, the AGC voltage VAGC is supplied as a gain control signal to the high-frequency amplifier 12 through the adding circuit 34, and AGC is performed for the high-frequency stage.

  Further, the intermediate frequency signals SIFA and SIFB output from the mixer circuits 13A and 13B are supplied to the AGC voltage forming circuit 33 for excessive input, and the AGC voltage VOL is increased when the reception level becomes a specified value or more due to an interference wave or the like. The AGC voltage VOL is formed and supplied as a gain control signal to the high frequency amplifier 12 through the adding circuit 34, and a delay AGC is performed on the high frequency stage.

  The above receiving circuit is integrated into a one-chip IC (integrated circuit) except for the tuning circuit 11, the resonance circuit of the PLL 31, and the digital processing circuit 20. Further, the digital processing circuit 20 is also integrated on a single chip.

  Further, a microcomputer 35 is provided as a system control circuit, and an operation switch 36 such as a channel selection switch is connected to the microcomputer 35. When the switch 36 is operated, a predetermined control signal is supplied from the microcomputer 35 to the local oscillation circuit 31, the oscillation frequencies of the local oscillation signals SLOA and SLOB are changed, and the reception frequency is changed.

Further, for example, when the power is turned on, a correction control signal is supplied from the microcomputer 35 to the correction circuit 14, and the image components included in the intermediate frequency signals SIFA and SIFB are canceled as inverse homologous amplitudes in the arithmetic circuit 17 as described above. Thus, the amplitude / phase correction circuit 14 is controlled.
In the above receiver, AGC is performed by the amplifiers 12 and 18, but the high frequency amplifier 12 needs to perform AGC processing of the received signal SRX over a wide range from a very small reception level to an excessive reception level.

  For this reason, for example, a high-frequency amplifier 12 as shown in FIG. 9 is considered. That is, the reception signal SRX from the tuning circuit 11 is sequentially supplied to the attenuator circuits 12A to 12C, and the reception signal SRX output from the tuning circuit 11 and the attenuator circuits 12A to 12C is supplied to the variable gain amplifiers 12D to 12G, respectively. The The adder circuit 12H is connected to the amplifiers 12D to 12G, and the output is supplied to the mixer circuits 13A and 13B as the output of the high-frequency amplifier 12. As an example, the control range of the attenuation of the attenuators 12A to 12C and the gain of the amplifiers 12D to 12G is 12 dB.

  Then, based on the AGC voltage output from the adder circuit 34, the operation / non-operation of the amplifiers 12D to 12F is controlled, and the gain during operation is controlled as indicated by a solid line in FIG. That is, when the level of the received signal SRX is in the range (1) in FIG. 10 (when the received level is small), the received signal SRX is extracted from the amplifier 12D and supplied to the adder circuit 12H, and the gain of the amplifier 12D is controlled. Perform AGC. When the level of the received signal SRX is in the range (2), the received signal SRX is extracted from the amplifier 12E and supplied to the adder circuit 12H, and AGC is performed by controlling the gain of the amplifier 12E.

  When the level of the received signal SRX is in the range (3), the received signal SRX is extracted from the amplifier 12F and supplied to the adder circuit 12H, and the gain of the amplifier 12F is controlled to perform AGC. When the level of the received signal SRX is in the range (4), the received signal SRX is extracted from the amplifier 12G and supplied to the adding circuit 12H, and the gain of the amplifier 12G is controlled to perform AGC.

  Therefore, according to this AGC, the AGC of the received signal SRX can be performed over a wide range from a minute level to a large level. In particular, a reception signal SRX having a magnitude corresponding to the attenuation amount of the attenuator circuits 12A to 12C can be handled, and a large level reception signal SRX can be processed while maintaining low distortion. This is an excellent method for controlling the gain in the high frequency stage.

For example, there are the following prior art documents.
JP 2001-53564 A

  However, when the operations of the amplifiers 12D to 12G are switched as described above, it is actually difficult to perform the switching smoothly. As a result, the gain with respect to the reception level or the AGC voltage is indicated by a broken line in FIG. It becomes such a characteristic.

  Therefore, the amplifiers 12D to 12G are switched so as to operate in an overlapping manner so that the AGC characteristic approaches the characteristic of the solid line from the broken line in FIG. 10, but the slope of the AGC characteristic may still differ by about twice. This means that there is a difference of 6 dB in the loop gain of AGC, which indicates that the response time of AGC is twice different.

  The present invention is intended to solve the above problems.

In this invention,
A plurality of attenuator circuits cascaded to the input signal;
A plurality of variable gain amplifiers respectively supplied with the input signal and the output signals of the plurality of attenuator circuits;
An extraction circuit that is connected in common to the output ends of the plurality of variable gain amplifiers and outputs an output signal whose level is controlled;
A conversion circuit that converts the control voltage into a control current having a predetermined characteristic;
The control current output from the conversion circuit is supplied to the variable gain amplifier as an operation switching and gain control signal.
The variable gain circuit is configured such that a control current equivalent to the control current is negatively fed back by the conversion circuit.

  According to the present invention, level control of an input signal can be performed over a wide range from a minute level to a large level. Moreover, the level can be controlled from a small level to a large level while maintaining low distortion and low noise.

  Further, the switching of the variable gain amplifier and the attenuator circuit is smoothed by the negative feedback, and the gain change characteristic can be made constant. This also makes it possible to obtain a constant response characteristic regardless of the magnitude of the received signal in the case of AGC operation.

[1] Variable Gain Amplifier FIG. 1 shows an example in which the high frequency amplifier 12 is configured as a variable gain amplifier. In this example, the high frequency amplifier 12 includes three stages of attenuator circuits 42 to 44 connected in cascade, And differential amplifiers 51 to 54 for extracting output signals of the tuning circuit 11 and the attenuator circuits 42 to 44.

  That is, the secondary coil L11 of the tuning coil (not shown) of the tuning circuit 11 is equivalently represented by a series circuit of a resistor R11, a parallel circuit of an inductance L12 and a capacitor C12, and a resistor R12. The received signal SRX is extracted from R11 and R12 in a balanced manner.

  And the attenuator circuits 42-44 are comprised as shown, for example in FIG. That is, a parallel circuit of a capacitor C41 and a resistor R41 is connected between one input terminal T41 and an output terminal T43, and a resistor R43 and a capacitor C43 are connected between the output terminal T43 and a midpoint terminal T45. Are connected in parallel. A parallel circuit of a capacitor C42 and a resistor R42 is connected between the other input terminal T42 and the output terminal T44, and a resistor R44 and a capacitor C44 are connected between the output terminal T44 and the midpoint terminal T45. Are connected in parallel.

  Thus, the balance type attenuator circuits 42 to 44 are constituted by the elements R41 to R44 and C41 to C44, respectively.

  The attenuator circuits 42 to 44 constitute a balance type ladder attenuator circuit. Among the attenuator circuits 42 to 44, the output terminals T43 and T44 of the preceding attenuator circuit are the same as the attenuator circuit of the next stage. Connected to input terminals T41 and T42. The input terminals T41 and T42 of the attenuator circuit 42 are connected to the output side of the resistors R11 and R12, and the terminal T45 is connected to each other.

In this case, in each of the attenuator circuits 42 to 44,
C41 / R41 = C43 / R43
C42 ・ R42 ＝ C44 ・ R44
It is said.

  When the attenuation amounts of the attenuator circuits 42 to 44 are made equal, the values of the elements R41 to R44 and C41 to C44 of the attenuator circuits 42 to 44 are made equal to each other, and the resistors R43 and R44 of the attenuator circuit 44 are set. Of the attenuator circuit 42 and the values of the capacitors C43 and C44 of the attenuator circuit 44 are twice the values of the capacitors C43 and C44 of the attenuator circuit 42. The

Furthermore, if the attenuation amount per stage of each attenuator circuit 42 to 44 is 1 / n [times] (where n is an integer of 2 or more),
R43 / R41 = 2 / (n-1)
C41 / C43 = 2 / (n-1)
It is said. For example, the amount of attenuation per stage is 12 dB (= 1/4 times).

  The differential amplifier 51 is constructed by connecting the emitters of the transistors Q51 and Q52 to the collector of the constant current source transistor Q53, and the transistor Q53 and the transistor Q54 are used as a current mirror with the ground terminal T52 as a reference potential point. A circuit 51A is configured. The differential amplifiers 52 to 54 are configured by transistors (Q51, Q53) to (Q51, Q53) in the same manner as the differential amplifier 51, and the current mirror circuits 52A to 54A are transistors (Q53, Q54) to (Q53, Q54). ) In the same manner as the current mirror circuit 51A.

  The bases of the transistors Q51 and Q52 of the differential amplifier 51 are connected to the output sides of the resistors R11 and R12, and the bases of the transistors (Q51, Q52) to (Q51, Q52) of the differential amplifiers 52 to 54 are attenuator circuits 42. To 44 output terminals (T43, T44) to (T43, T44), respectively. Further, the bias voltage V45 is supplied to the midpoint terminals T45 to T45 of the attenuator circuits 42 to 44.

  Further, the collectors of the transistors Q51 and Q51 of the differential amplifiers 51 and 52 are connected to the emitter of the transistor Q55 having a common base to constitute a cascode amplifier 51B. The collectors of the transistors Q52 and Q52 of the differential amplifiers 51 and 52 are A cascode amplifier 52B is configured by being connected to the emitter of the transistor Q56 having a common base. Similarly, cascode amplifiers 53B and 54B are configured for the differential amplifiers 53 and 54, respectively.

  Further, in this case, the collectors of the transistors Q55 and Q55 of the cascode amplifiers 51B and 53B are connected to the common load resistor R55, and the collectors of the transistors Q56 and Q56 of the cascode amplifiers 52B and 54B are connected to the common load resistor R56. The received signal SRX obtained by these load resistors R55 and R56 is supplied to the mixer circuits 13A and 13B in the next stage. At this time, since the reception signal SRX is obtained in a balanced type, the mixer circuits 13A and 13B are configured in a balanced type.

  As will be described in detail later, if the AGC voltage obtained from the adder circuit 34 is the voltage VCTL, the AGC voltage VCTL is supplied to the logarithmic compression circuit 60 for voltage-current conversion, and the control currents I71 to I74 are logarithmically converted. The compressed control currents I71 to I74 are supplied to the transistors Q54 to Q54 on the input side of the current mirror circuits 51A to 54A. Reference numeral T51 indicates a power supply terminal. The entire circuit is integrated into a one-chip IC together with the receiving circuit of FIG.

  According to such a configuration, when the reception signal SRX is output from the tuning circuit 11, the attenuator circuits 42 to 44 output the reception signal SRX whose levels are sequentially reduced by 12 dB.

  At this time, of the control currents I71 to I74 output from the logarithmic compression circuit 60, for example, the control current I71 has a predetermined magnitude, and the other control currents I72 to I74 are 0. Then, the current I71 flows to the differential amplifier 51 through the current mirror circuit 51A, so that the differential amplifier 51 operates effectively, but the currents I72 to I74 do not flow to the other differential amplifiers 52 to 54. It becomes.

  Therefore, the reception signal SRX output from the tuning circuit 11 is extracted through the differential amplifier 51 and the cascode amplifiers 51B and 52B and supplied to the mixer circuits 13A and 13B. At this time, since the differential amplifiers 52 to 54 are inoperative, the reception signal SRX output from the attenuator circuits 42 to 44 is not supplied to the mixer circuits 42 to 44.

The gain A51 of the differential amplifier 51 is
A51 = a ・ I71 [times]
a: indicated by a constant. Therefore, when the magnitude of the control current I71 changes corresponding to the AGC voltage VCTL, the gain A51 of the differential amplifier 51 changes corresponding to the AGC voltage VCTL. As a result, the tuning circuit 11 passes through the differential amplifier 51. The level of the reception signal SRX supplied to the mixer circuits 13A and 13B is controlled.

  The gains A52 to A54 of the other differential amplifiers 52 to 54 are also controlled by the control currents I72 to I74 in the same manner as the gain A51, and the reception signal SRX output from the attenuator circuits 42 to 44 is the differential amplifiers 52 to 44. 54, the level of the received signals SRX to SRX supplied from the attenuator circuits 42 to 44 to the mixer circuits 13A and 13B through the differential amplifiers 52 to 54 changes when the AGC voltage VCTL changes. Be controlled.

  Therefore, the control currents I71 to I74 are set to have characteristics that change logarithmically with respect to the AGC voltage VCTL. For example, as shown in FIG. 3A (FIG. 3A is the same as FIG. 10), the AGC voltage VCTL is in the range (1). When the AGC voltage VCTL is within the range (2), the received signal SRX is taken out through the differential amplifier 51 and the gain A51 is controlled by the control current I71. If the gain A52 is controlled by the current I72,..., The gain AV of the amplifier 12 can be changed linearly over a wide range as shown in FIG.

[2] Logarithmic Compression Circuit FIG. 4 shows an example of the logarithmic compression circuit 60. The compression circuit 60 converts the AGC voltage VCTL into voltage and current and logarithmically compresses it into control currents I71 to I74 and Im. As will be apparent from the description below, Im = I71 in the range (1) in FIG. 3A, Im = I72 in the range (2), and Im = I73 in the range (3). In the range (4), Im = I74. That is, in the ranges (1) to (4), the control current Im is equivalent to the control currents I71 to I74.

  In FIG. 4, the AGC voltage VCTL is supplied to the non-inverting input terminal of the operational amplifier 61, the output terminal is connected to the base of the transistor Q61, and the resistor R61 is connected between the emitter and the ground terminal T52. . The signal voltage obtained at the resistor R61 is supplied to the inverting input terminal of the operational amplifier 61.

  The collector of transistor Q61 is connected to the collector of transistor Q62. This transistor Q62, together with the transistor Q63, constitutes a current mirror circuit 62 with the power supply terminal T51 as a reference potential point. The collector of the transistor Q63 is connected to the inverting input terminal of the operational amplifier 63 for voltage comparison, and is connected to the voltage source of the bias voltage V61 through the resistor R62.

  Further, the bases of the transistors Q64 and Q65 are connected to each other and to the collector of the transistor Q64, and the constant current source 64 is connected between the collector and the power supply terminal T51. The emitter of the transistor Q64 is connected to the voltage source of the bias voltage V61, the emitter of the transistor Q65 is connected to the inverting input terminal of the operational amplifier 63, and the collector of the transistor Q65 is connected to the power supply terminal T51.

  The output terminal of the operational amplifier 63 is connected to the base of the transistor Q66 having a common emitter, and the collector thereof is connected to the power supply terminal T51 through the resistor R63. Further, the collector of the transistor Q66 is supplied to the non-inverting input terminal of the operational amplifier 65, the output terminal is connected to the base of the transistor Q67, the resistor R64 is connected between the emitter and the ground terminal T52, and the transistor The emitter of Q67 is connected to the inverting input terminal of the operational amplifier 65.

  The voltage V60 obtained at the resistor R64 is supplied as a control voltage to the current generation circuit 67, and the collector of the transistor Qm of the current generation circuit 67 is connected to the emitter of the transistor Q65. Although details of the current generation circuit 67 will be described later, the control voltage V60 supplied thereto is converted into a control current, and this control current is negatively fed back to the operational amplifier 63 through the transistor Qm. The transistor Qm is equivalently shown as an output transistor in the current generation circuit 67, and its collector current becomes the control current Im. Further, control currents I71 to I74 are output from the current generation circuit 67.

  According to such a configuration, 100% negative feedback is applied to the operational amplifier 65 through the transistor Q67, and the operational amplifier 65 and the transistor Q67 operate as a voltage follower. As a result, the output of the operational amplifier 63 is negatively fed back to the transistor Qm through the transistor Q66 and further through the operational amplifier 65 and the transistor Q67.

Therefore,
VA: Potential of the inverting input terminal of the operational amplifier 63 VB: If the potential of the non-inverting input terminal of the operational amplifier 63 is set, negative feedback is applied to the operational amplifier 63.
VB = VA (11)
It becomes.

Also,
VR62: Terminal voltage of resistor R62 VBE64: Base-emitter voltage of transistor Q64 VBE65: Base-emitter voltage of transistor Q65
VA = V61 + VR62 (12)
V61 + VBE64 = VB + VBE65 (13)
It is.

Therefore, from the equations (11) to (13), VBE64−VBE65 = VR62 (14)
It becomes.

Also,
IC64: Collector current (emitter current) of transistor Q64
IC65: Collector current (emitter current) of transistor Q65
given that,
IC64 = α ・ exp （β ・ VBE64） (15)
IC65 = α ・ exp （β ・ VBE65） (16)
α: constant β = q / (K · T)
q: electron charge
K: Boltzmann constant
T: Absolute temperature. From the formulas (15) and (16), IC64 / IC65 = exp (β (VBE64−VBE65))
By substituting equation (14) for this, IC64 / IC65 = exp (β · VR62) (17)
Is obtained.

And taking the logarithm of this equation (17),
log (IC64) −log (IC65) = β · VR62
And transform this
log (IC65) = -β · VR62 + log (IC64) (18)
It becomes.

On the other hand, since 100% negative feedback is applied to the operational amplifier 61 through the transistor Q61, the terminal voltage of the resistor R61 becomes the voltage VCTL.
IR61: If the current of the resistor R61 is
IR61 = VCTL / R61
It becomes.

This current IR61 is also the collector current of the transistor Q61, and further flows through the current mirror circuit 62 to the resistor R62.
VR62 = IR61 / R62
= R62 / R61 · VCTL (19)
It becomes.

Therefore, substituting (19) into (18)
log (IC65) = -γ · VCTL + log (IC64) (20)
γ = β · R62 / R61
It becomes.

And
Im = IC65
Therefore, from equation (20)
log (Im) = -γ · VCTL + log (IC64) (21)
It becomes.

When VCTL = 0, from equation (21)
log (Im) = log (IC64) (22)
Thus, the current Im becomes equal to the collector current IC64 of the transistor Q64, that is, the output current of the constant current source 64.

  Therefore, as shown in FIG. 3B, the logarithmic value log (Im) of the collector current Im is linearly proportional to the AGC voltage VCTL with a negative coefficient -γ. That is, the AGC voltage VCTL is converted into the control current Im, and the control current Im is logarithmically compressed.

[2-1] Current generation circuit 67
FIG. 5 shows an example of the current generation circuit 67. The current generation circuit 67 generates control currents Im and I71 to I74 from the control voltage V60.

  In the example illustrated in FIG. 5, the current generation circuit 67 includes a voltage comparison circuit 71 and current mirror circuits 721 to 724 and 731 to 734. In this case, the voltage comparison circuit 71 compares the control voltage V60 with the reference voltage, thereby causing the currents I71 to flow through the differential amplifiers 51 to 54 at voltages corresponding to the boundaries of the ranges (1) to (4) in FIG. I74 is switched.

  That is, between the power supply terminal T51 and the ground terminal T52, the emitter and collector of the constant current source transistor Q84, the resistors R73 to R71, and the emitter and collector of the transistor Q83 are connected in series. A predetermined bias voltage is supplied to the base of Q84, and the base of transistor Q83 is connected to ground terminal T52. In this way, the reference voltage corresponding to the boundaries of the ranges (1) to (4) in FIG. 10 is taken out at the connection points of the resistors R71 to R73.

  Further, between the power supply terminal T51 and the ground terminal T52, the emitter and collector of the constant current source transistor Q86, the resistors R83 to R81, and the emitter and collector of the transistor Q85 are connected in series. A predetermined bias voltage is supplied to the base of Q86, and a control voltage V60 is supplied to the base of transistor Q85 from transistor Q67 shown in FIG.

  Then, the transistors Q81 and Q71 are differentially connected using the transistor Q70 as a constant current source to form a voltage comparison circuit 711, the base of the transistor Q81 is connected to the connection point of the resistors R82 and R81, and the base of the transistor Q71 is the resistance Connected to the connection point of the devices R72 and R71. In this case, the emitter resistor R70 is connected to the transistor Q70 and the base bias voltage V71 is supplied. In addition, the bias voltage V71 is connected in series between the base and emitter of a predetermined number of diode-connected transistors, and a DC current is supplied to the series circuit through a resistor so that both ends of the series circuit are connected. The band gap voltage obtained in

  Further, transistors Q82 and Q72 are differentially connected using the transistor Q81 as a constant current source to form a voltage comparison circuit 712. The base of the transistor Q82 is connected to the connection point of the resistors R83 and R82, and the base of the transistor Q72 is a resistor. Connected to the connection point of the devices R73 and R72. Further, the transistors Q74 and Q73 are differentiated by using the transistor Q82 as a constant current source to form a voltage comparison circuit 713. The base of the transistor Q74 is connected to the collector of the transistor Q86, and the base of the transistor Q73 is connected to the collector of the transistor Q84. Is done.

  The current mirror circuit 721 is composed of transistors Q75 to Q77 with the power supply terminal T51 as a reference potential point, and the collector of the transistor Q75 on the input side is connected to the collector of the transistor Q71. Similarly, current mirror circuits 722 to 724 are constituted by transistors (Q75 to Q77) to (Q75 to Q77), and the collectors of transistors Q75 to Q75 on the input side thereof are connected to the collectors of transistors Q72, Q73, and Q74.

  Further, the current mirror circuit 731 includes transistors Q78 and Q79 with the ground terminal T52 as a reference potential point, and the collector of the transistor Q78 on the input side is connected to the collector of the transistor Q76 on the first output side of the current mirror circuit 721. Is done. Similarly, the current mirror circuits 732 to 734 are composed of transistors (Q78, Q79) to (Q78, Q79), and the collectors of the transistors Q78 to Q78 on the input side are the transistors on the first output side of the current mirror circuits 722 to 724. Connected to collectors of Q76 to Q76.

  The collectors of the transistors Q77 to Q77 on the second output side of the current mirror circuits 721 to 724 are connected to the collectors of the transistors Q54 to Q54 on the input side of the current mirror circuits 51A to 54A shown in FIG. Therefore, the collector currents of the transistors Q77 to Q77 on the output side of the current mirror circuits 721 to 724 become the collector currents I71 to I74 of the transistors Q54 to Q54 on the input side of the current mirror circuits 51A to 54A in the amplifier 12.

  Further, the collectors of the transistors Q79 to Q79 on the output side of the current mirror circuits 731 to 734 are connected to each other and to the emitter of the transistor Q65 of the compression circuit 60 shown in FIG. The transistors Q79 to Q79 of the current mirror circuits 731 to 734 correspond to the transistor Qm in the current generation circuit 67 shown in FIG.

  In this case, the collector currents of the transistors Q75 to Q75 on the input side of the current mirror circuits 721 to 724 and the collector currents of the transistors (Q76, Q77) to (Q76, Q77) on the output side are set to a predetermined ratio. Thus, the collector currents of the transistors (Q76, Q77) to (Q76, Q77) of the current mirror circuits 721 to 724 are set to a ratio of 1/1: 1/4: 1/16: 1/64. This ratio is determined in accordance with the attenuation amount 12 dB (= 1/4) of the attenuator circuits 42 to 44.

  According to such a configuration, the control voltage V60 increases as the AGC voltage VCTL increases, and the collector current of the transistor Q85 decreases. Therefore, as the AGC voltage VCTL increases, the base voltages of the transistors Q81, Q82, and Q74 increase. Therefore, by setting the values of the resistors R71 to R73 and R81 to R83, the transistors are set as follows: Q71 to Q74, Q81, and Q82 can be turned on and off.

That is,
(A) When AGC voltage VCTL is within the range (1) in FIG. 3A Transistor Q81 is off and transistor Q71 is on (transistor Q81 is off, so transistors Q82 and Q72 to Q74 are also off)
(B) When the AGC voltage VCTL is within the range (2) in FIG. 3A Transistor Q81 is on, transistor Q71 is off Transistor Q82 is off, and transistor Q72 is on (transistor Q73 is off, so transistor Q73 Q74 is also off)
(C) When the AGC voltage VCTL is within the range (3) in FIG. 3A Transistor Q81 is on, transistor Q71 is off Transistor Q82 is on, transistor Q72 is off Transistor Q74 is off, and transistor Q73 is off on
(D) When the AGC voltage VCTL is within the range (4) in FIG. 3A Transistor Q81 is on, transistor Q71 is off Transistor Q82 is on, transistor Q72 is off Transistor Q74 is on and transistor Q73 is on Can be off.

  Then, in the case of (A), the collector current IC71 having a magnitude corresponding to the control voltage V60 flows through the transistor Q71. The collector current IC71 flows as a control current I71 to the amplifier 12 through the current mirror circuit 721, and flows as a control current Im (= I71) to the compression circuit 60 through the current mirror circuit 731.

  At this time, since the transistor Q81 is off, the transistors Q81 and Q72 to Q74 are off and their collector currents IC72 to IC74 = 0, so that in the amplifier 12, I72 to I74 = 0.

  Therefore, in FIG. 1, the reception signal SRX output from the tuning circuit 11 is supplied to the mixer circuits 13A and 13B through the differential amplifier 51. At this time, as shown in FIG. 3B, since the control current I71 (= Im) changes in a logarithmic function corresponding to the AGC voltage VCTL, the gain A of the differential amplifier 51 is a logarithm with respect to the AGC voltage VCTL. As a result, the characteristic of the range (1) in FIG. 3A is obtained.

  In the case of (B), a collector current IC72 having a magnitude corresponding to the control voltage V60 flows through the transistor Q72, and this collector current IC72 flows through the current mirror circuit 722 to the amplifier 12 as the control current I72. A control current Im (= I72) flows to the compression circuit 60 through the mirror circuit 732.

  At this time, since the transistors Q71, Q82 are off, the transistors Q71, Q73, Q74 are off and their collector currents IC71, IC73, IC74 = 0, so that in the amplifier 12, I71, I73, I74 = 0. .

  Accordingly, in FIG. 1, the reception signal SRX output from the attenuator circuit 42 is supplied to the mixer circuits 13A and 13B through the differential amplifier 52. At this time, as shown in FIG. 3B, the control current I72 (= Im) changes in a logarithmic function corresponding to the AGC voltage VCTL, so that the gain A of the differential amplifier 52 is a logarithm with respect to the AGC voltage VCTL. As a result, the characteristic of the range (2) in FIG. 3A is obtained.

  Further, in the case of (C) and (D), the same operation is performed, and the collector current IC73 or IC74 flows as the control current I73 or I74 in the amplifier 12, and therefore the range (3) or (4) in FIG. Characteristics are obtained.

  Therefore, the characteristics of the AGC voltage VCTL and gain (decibel value) shown in FIG. 3A can be obtained.

  At this time, the collector currents IC71 to IC74 converted from the control voltage V60 become the control current Im through the current mirror circuits 721 to 724 and the current mirror circuits 731 to 734, and are negative to the operational amplifier 63 as shown in FIG. Since the feedback is made, the joint of the characteristics at the boundaries of the ranges (1) to (4) in FIG. 3A can be changed linearly, and the change in gain (decibel value) can be made linear over a wide range as a whole. .

  In addition, since linear characteristics can be obtained over such a wide range, an AGC operation having a constant response characteristic over a wide input range from a weak received signal to a large received signal can be obtained.

[3] Logarithmic compression circuit (another example)
In the logarithmic compression circuit 60 shown in FIG. 4, bias currents Ib and Ib of the transistors constituting the operational amplifier 63 flow through the inverting input terminal and the non-inverting input terminal of the operational amplifier 63. When the AGC voltage VCTL (control voltage V60) increases, the collector current IC65 of the transistor Q65 decreases and the current IR61 also decreases. At this time, the current Ib flowing through the non-inverting input terminal of the operational amplifier 63 cannot be ignored. The logarithmic compression characteristic deviates from the linear characteristic as indicated by a broken line in FIG. Therefore, if gain control is performed, the range in which the decibel value of the gain can be controlled linearly becomes narrow.

  In order to solve such a problem, the collector current IC65 may be set so as to remain sufficiently larger than the base current Ib even when the collector current IC65 becomes small. In this case, current consumption as a logarithmic compression circuit increases.

  Further, in the logarithmic compression circuit shown in FIG. 4, since the absolute temperature T is included in the expression indicating the slope −γ of the compression characteristic, as is clear from the expression (20), as shown in FIG. The characteristics change depending on the temperature T.

  Therefore, in the logarithmic compression circuit 60 shown in FIG. 7, the bias currents Ib and Ib flowing through the operational amplifier 63 can be ignored and temperature compensation is performed.

  First, a compensation circuit for the bias currents Ib and Ib is configured as follows. In other words, in the operational amplifier 63, the differentially connected transistors P61 and P62 and the constant current source transistor P63 constitute a differential amplifier 631, and the transistors P65 and P66 constitute a current mirror circuit 632. A mirror circuit 632 is connected to the differential amplifier 631 as its load. Therefore, the operational amplifier 63 is configured in which the base of the transistor P61 is the non-inverting input terminal, the base of the transistor P62 is the inverting input terminal, and the collectors of the transistors P62 and P66 are the output terminals.

  Further, a transistor P81 is provided, and a bias voltage V81 is supplied to the base thereof, and a resistor R84 is connected between the emitter and the ground terminal T52 to constitute a constant current source 81. From the collector of the transistor P81 A constant current Is is taken out. In this case, the bias voltage V81 is a band gap voltage similar to the bias voltage V71.

  The current Is is supplied to the transistor P82. The transistor P82 constitutes a current mirror circuit 82 together with the transistors P64 and P63, and is biased by the transistor P83. Further, the transistor P64 constitutes the constant current source 64 in FIG. 4. Therefore, the collector current of the transistor P64 becomes the constant current IC64 in FIG. 4 and IC64 = Is. Further, the collector current of the transistor P63 also has the value Is.

  Further, the collector current of the transistor P83 is supplied to the transistor P84. The transistor P84, together with the transistors P85 and P86, constitutes a current mirror circuit 83. The collectors of the transistors P85 and P86 are connected to the bases of the transistors P61 and P62. Therefore, the collector currents of the transistors P85 and P86 are supplied to the bases of the transistors P61 and P62 as their bias currents Ib and Ib.

And at this time
hFE: If the current amplification factors of the transistors P82, P83, and P61 to P63 are used,
Collector current of transistor P83 = 3 · Is / hFE
It becomes. In the transistors P61 and P62,
Ib = Is / (2 · hFE)
It is.

Therefore, for example, if the junction area between the base and emitter of the transistors P85 and P86 is 1/6 of that of the transistor P84,
Collector current of transistors P85 and P86 = Is / (2 · hFE)
Therefore, the bias currents Ib and Ib flowing through the operational amplifier 63 (bases of the transistors P61 and P62) are canceled by the collector currents of the transistors P85 and P86, and linear compression characteristics are obtained as shown by the solid line in FIG. Can be obtained.

  Furthermore, a temperature compensation circuit for compression characteristics is configured as follows. That is, the collector of the output side transistor Q63 constituting the current mirror circuit 62 is connected to the collector of the input side transistor P91 of the current mirror circuit 91, and the output side transistor P92 is used as a constant current source. Thus, the differential amplifier 92 is configured.

  In the differential amplifier 92, a predetermined base bias voltage V92 is supplied to the base of the transistor P93, and the bias voltage V92 is divided by resistors R91 and R92, and the divided voltage is applied to the base of the transistor P94. Supplied. The bias voltage V92 is also a band gap voltage similar to the bias voltage V71.

  Therefore, when the current IR61 (= VCTL / R61) is taken out from the collector of the transistor Q63, the current IR61 flows through the differential amplifier 92 through the current mirror circuit 91. At this time, the current IR61 is supplied from the resistor R91. , The current is divided into the transistors P93 and P94 at a ratio corresponding to the voltage dividing ratio of R92.

  The current IR61 shunted to the transistor P94 is supplied to the resistor R62 through the current mirror circuit 93 constituted by the transistors P95 and P96 and further through the diode-connected transistor P97.

  Therefore, a current IR61 proportional to the AGC voltage VCTL flows through the resistor R62. The current IR61 flowing through the resistor R62 is a current shunted by the differential amplifier 92, and the magnitude thereof is the resistors R91 and R92. Since it is determined by the band gap voltage V92, the current IR61 flowing through the resistor R62 is a current having a positive temperature coefficient.

  Therefore, the voltage VR62 generated in the resistor R62 also has a positive temperature coefficient. Therefore, by setting the resistors R91 and R92 and the band gap voltage V92 in advance, the temperature change of the compression characteristic shown in FIG. It can be canceled out by the temperature characteristic of the current IR61, and the temperature change of the compression characteristic can be suppressed.

Furthermore, when controlling the gain AV of the high-frequency amplifier 12, the temperature change of the gain AV can also be suppressed. That is, the gain A51 of the differential amplifier 51 shown in FIG.
A51 = a ・ I71 [times]
a: It is indicated by a constant.
a = (1/2) β · RL
RL: load resistance, therefore
A51 = β ・ RL ・ I71 / 2 (31)
It is.

In the range (1) of FIG. 3A, the current mirror circuit 721
I71 = Im
Therefore, equation (31) is
A51 = β ・ RL ・ Im / 2 (32)
It becomes. Therefore, when the load resistance RL is formed in the IC, the load resistance RL varies with temperature, and the transistor has temperature characteristics, so that the gain A51 is affected by temperature.

However, in FIG. 7, the voltage V81 is a band gap voltage and V81 = VBE81 + N / β
VBE81: Base-emitter voltage of transistor P81
N: represented by a constant, and at this time, the constant N is set so that the temperature characteristic of the voltage V81 can be ignored.

Therefore, the constant current Is taken from the transistor P81 is
Is = (V81−VBE81) / R81
= (N / β) / R81 (33)
It becomes.

Further, as shown in FIG. 3B and the equation (22), the gain A51 of the differential amplifier 51 of FIG. 1 becomes the maximum value when VCTL = 0, and therefore, for simplicity, the case where VCTL = 0 is considered. , (22)
Im = IC64 (34)
It becomes. In FIG. 7, the collector current IC64 of the transistor Q64 is equal to the current Is. Therefore, equation (34) is derived from equation (33): Im = Is
= (N / β) / R81 (35)
It becomes.

Therefore, substituting this equation (35) into equation (32),
A51 = β ・ RL ・ Im / 2 (32)
= Β · RL · ((N / β) / R81) / 2
= (N / 2) ・ RL / R81
It becomes.

  That is, the gain A51 of the differential amplifier 51 is determined by a constant that does not depend on temperature and the resistance ratio RL / R81, and the resistance ratio RL / R81 is not affected by temperature. As described above, the conversion characteristics between the control voltage VCTL and the control current ICTL are not affected by the temperature. The same applies to the differential amplifiers 52 to 54.

  Therefore, according to the logarithmic compression circuit 60, the gain AV of the high-frequency amplifier 12 can be controlled so that its decibel value is linear, and the gain AV is not affected by temperature. Further, since the variation in the resistance ratio RL / R84 is small during the manufacture of the IC, the variation due to the IC can be suppressed.

[4] Summary According to the above AGC circuit, AGC of the received signal SRX can be performed over a wide range from a very small level to a large level, but the received signal SRX having a magnitude corresponding to the attenuation amount of the attenuator circuits 42 to 44. Therefore, the received signal SRX can be processed from a small level to a large level while maintaining low distortion and low noise.

  Further, the switching of the differential amplifiers 51 to 54 and the attenuator circuits 42 to 44 is smoothed by the negative feedback, and the gain change characteristic can be made constant. This also makes it possible to make the AGC operation have a constant response characteristic regardless of the magnitude of the reception signal SRX.

  Further, when controlling the gain AV of the high-frequency amplifier 12, the control current Im having a strong correlation with the gain AV is taken out and the current Im is controlled, so that extremely stable control is possible. Furthermore, since the loop gain of not only the AGC of the intermediate frequency amplification stage but also the high frequency AGC is stable, the AGC response characteristic can be set very accurately, and the digital broadcast receiver that is severe in the AGC response characteristic. However, excellent reception performance can be obtained.

  Furthermore, if the characteristic of the logarithmic compression circuit 60 is changed, an arbitrary gain change characteristic can be obtained corresponding to the characteristic, and the application range is wide. Further, since the difference in the gain change characteristic is corrected by the negative feedback, the gain variable circuit is formed by a circuit having completely different characteristics, such as control of the operating currents I71 to I74 of the attenuator circuits 42 to 44 and the differential amplifiers 51 to 54. Even when configured, a change characteristic of a predetermined gain can be obtained.

[List of abbreviations]
A / D: Analog to Digital
AGC: Automatic Gain Control
IC: Integrated Circuit
IF: Intermediate Frequency
PLL: Phase Locked Loop
VCO: Voltage Controlled Oscillator
Operational Amplifier: Operational Amplifier
Cascode: Cascade Connected Triode

It is a connection diagram showing one embodiment of the present invention. FIG. 2 is a connection diagram illustrating one form of a part of the circuit of FIG. 1. It is a characteristic view which shows the characteristic of the circuit of FIG. FIG. 2 is a connection diagram illustrating one form of a part of the circuit of FIG. 1. FIG. 2 is a connection diagram illustrating one form of a part of the circuit of FIG. 1. FIG. 5 is a characteristic diagram showing characteristics of the circuit of FIG. 4. It is a connection diagram which shows the other form of a part of circuit of FIG. It is a systematic diagram which shows an example of a receiver. It is a systematic diagram which shows a part of circuit of FIG. FIG. 10 is a characteristic diagram illustrating characteristics of the circuit of FIG. 9.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... Antenna tuning circuit, 12 ... High frequency amplifier, 13A and 13B ... Mixer circuit, 14 ... Amplitude phase correction circuit, 16A and 16B ... Phase shift circuit, 31 ... Local oscillation circuit, 32 and 33 ... AGC voltage formation circuit, 33A and 33B ... Peak value detection circuit, 35 ... Microcomputer, 36 ... Operation switch, 42-44 ... Attenuator circuit, 51-54 ... Differential amplifier, 60 ... Logarithmic compression circuit, 67 ... Current conversion circuit

Claims (6)

A plurality of attenuator circuits cascaded to the input signal;
A plurality of variable gain amplifiers respectively supplied with the input signal and the output signals of the plurality of attenuator circuits;
An extraction circuit that is connected in common to the output ends of the plurality of variable gain amplifiers and outputs an output signal whose level is controlled;
A conversion circuit that converts the control voltage into a control current having a predetermined characteristic;
The control current output from the conversion circuit is supplied to the variable gain amplifier as an operation switching and gain control signal.
A variable gain circuit in which a control current equivalent to the control current is negatively fed back by the conversion circuit. The variable gain circuit according to claim 1.
A variable gain circuit, wherein the conversion circuit is a logarithmic compression circuit that logarithmically compresses the control voltage to the control current. The variable gain circuit according to claim 1 or 2,
The variable gain amplifier is composed of a differential amplifier,
A variable gain circuit in which a constant current of a constant current source constituting the differential amplifier is used as the control current output from the conversion circuit. The variable gain circuit according to claim 3,
Each attenuation amount of the plurality of attenuator circuits is 1 / n [times] (n is an integer of 2 or more),
A variable gain circuit in which the magnitude of the control current supplied to each of the differential amplifiers is reduced by 1 / n as the current supplied to the subsequent differential amplifier. In the variable gain circuit according to claim 2, claim 3 or claim 4,
The control voltage is an AGC voltage,
A variable gain circuit configured such that an output signal extracted from the extraction circuit is a signal subjected to AGC. The variable gain circuit according to claim 1, 2 or 5,
A variable gain circuit that is integrated into a single chip IC.

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