JP2005277091A - Automatic arranging and wiring equipment, semiconductor device, arranging and wiring method and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce noise included in a control signal when it is inputted to a gated clock circuit, to prevent fluctuation of the clock signal of the gated clock circuit, and to stabilize an operation of the gated clock circuit. <P>SOLUTION: Automatic arranging and wiring equipment having an automatic arranging/wiring part 7-1 and 7-2 and a circuit inserting part 7-5 is used. In the automatic arranging/wiring part 7-1 and 7-2, the gated clock circuit where first wiring in which a clock signal flows is connected to a first input terminal and second wiring where a control signal controlling the clock signal flows is connected to a second input terminal is arranged. In the circuit inserting part 7-5, a noise reduction circuit as the circuit reducing noise of the control signal is arranged near the second input terminal on second wiring. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an automatic placement and routing apparatus, a semiconductor device, a placement and routing method for a semiconductor device, and a method for manufacturing a semiconductor device. The present invention relates to a method and a method for manufacturing a semiconductor device.

  2. Description of the Related Art An automatic placement and routing system that automatically places and routes function blocks and wirings in a large-scale integrated circuit (LSI) layout design is known. In the present specification, all the function blocks including (logic) function cells and (logic) function blocks are referred to as function blocks. An example of the automatic placement and routing apparatus is CAD (Computer Aided Design) using a computer. Placement and wiring using the automatic placement and routing apparatus is performed as follows, for example. First, data relating to a circuit diagram of an LSI to be designed, data of functional blocks prepared as a library, and data relating to a design rule are read. Next, functional blocks are arranged based on each read data. Subsequently, wiring between functional blocks is performed based on each read data. Thereafter, it is verified whether or not there is a problem with the placement and wiring, and rearrangement and rewiring are performed as necessary. Finally, data for the automatic placement and routing apparatus is generated as artwork data related to wiring of the entire chip corresponding to the pattern of each layer constituting the LSI.

  As a function block that is automatically arranged, there is a gated clock circuit. In this circuit, a first wiring through which a clock signal flows is connected to a first input terminal, and a second wiring through which a control signal for controlling the clock signal flows is connected to a second input terminal. The input clock signal is controlled by the control signal and output from the output terminal. The wiring through which the clock signal flows (example: first wiring, wiring connected to the output terminal) is protected by a shield, limited in wiring capacity, and the like. Therefore, the clock signal can be transmitted without being affected by noise or the like. On the other hand, the wiring through which the control signal flows (example: second wiring) is not particularly protected by a shield or limited in wiring capacity. Therefore, the control signal can be affected by noise or the like. A technique that is not affected by such noise is desired.

  As a related technique, Japanese Patent Laid-Open No. 2002-190528 discloses a technique of a gated clock design support apparatus. The present invention supports the design of a gated clock circuit. First timing constraint generation means, circuit design means, first timing analysis means, first timing determination means, wiring means, second timing constraint generation means, second timing analysis means, , Second timing determination means, and second circuit design means. The first timing constraint generation means generates a first timing constraint for the gated clock circuit portion by setting the first parameter α based on the first circuit information. The circuit design means refers to the first timing constraint and performs logic synthesis and placement processing of the first circuit. The first timing analysis means analyzes the timing of the circuit portion on which the first timing constraint is imposed in the circuit information. The first timing determination means refers to the result of the timing analysis under the first timing constraint to determine whether the timing is satisfied. The wiring means executes a clock wiring process of the circuit when the timing under the first timing constraint is satisfied. The second timing constraint generating means generates a second timing constraint of the gated clock circuit portion by setting the second parameter α based on the circuit information after the clock wiring process. The second timing analysis means performs timing analysis on the circuit portion on which the second timing constraint is imposed in the circuit information after the clock wiring processing. The second timing determination unit determines whether the timing is satisfied by referring to the result of the timing analysis under the second timing constraint. The second circuit design means performs logic synthesis and arrangement processing of the circuit when the timing is not satisfied with respect to the second timing constraint. Then, the second circuit information obtained by the second circuit design means is set as the first circuit information. The first timing constraint is generated using the second parameter α in the first circuit information. Thereafter, the process returns to the timing analysis process by the first timing analysis means. Further, the process proceeds from the processing of the first timing determination means until the second timing determination means determines that the timing is satisfied with reference to the result of the timing analysis under the second timing constraint. The process is repeated.

JP 2002-190528 A

  Accordingly, an object of the present invention is to provide an automatic placement and routing apparatus, a semiconductor device, a placement and routing method for a semiconductor device, and a semiconductor device capable of preventing fluctuations in the clock signal of a gated clock circuit caused by noise included in a control signal. It is to provide a manufacturing method. .

  Another object of the present invention is to provide an automatic placement and routing apparatus, semiconductor device, semiconductor device placement and routing method, and semiconductor device manufacturing capable of reducing noise included in a control signal when input to a gated clock circuit. It is to provide a method.

  Still another object of the present invention is to provide an automatic placement and routing apparatus, a semiconductor device placement and routing method, a semiconductor device manufacturing method, and a semiconductor device capable of stabilizing the operation of a gated clock circuit.

  Hereinafter, means for solving the problem will be described using the numbers and symbols used in the best mode for carrying out the invention. These numbers and symbols are added in parentheses in order to clarify the correspondence between the description of the claims and the best mode for carrying out the invention. However, these numbers and symbols should not be used for interpreting the technical scope of the invention described in the claims.

Therefore, in order to solve the above-described problem, the semiconductor device placement and routing method according to the present invention controls the first wiring (15) through which the clock signal (CLK) flows to the first input terminal to control the clock signal (CLK). A step (S02 to S04) of arranging a gated clock circuit (12) in which the second wiring (16) through which the signal (CNT) flows is connected to the second input terminal, and the second input on the second wiring (16). A step (S06) of inserting and arranging a noise reduction circuit (11) as a circuit for reducing noise of the control signal (CNT) in the vicinity of the terminal.
According to the present invention, noise included in the control signal (CNT) when input to the gated clock circuit (12) can be reduced by the noise reduction circuit (11) provided in the vicinity of the second input terminal. Then, it is possible to prevent fluctuations in the clock signal of the gated clock circuit (12) generated by noise included in the control signal (CNT).

In the semiconductor device placement and routing method, the noise reduction circuit (11) is placed within a range of 1 to 10 sites from the gated clock circuit (12) on the second wire (16).
According to the present invention, the control signal (CNT) output from the noise reduction circuit (11) can be input to the gated clock circuit (12) without being affected by noise.

In the semiconductor device placement and routing method, the noise reduction circuit (11) is one of a buffer circuit and an inverter circuit.
According to the present invention, the buffer circuit and the inverter circuit have a simple configuration, and noise of the control signal (CNT) can be reduced without a major design change.

  In order to solve the above problems, the automatic placement and routing apparatus of the present invention includes an automatic placement and routing unit (7-1 + 7-2) and a circuit insertion unit (7-5). In the automatic placement and routing unit (7-1 + 7-2), the first wiring (15) through which the clock signal (CLK) flows is connected to the first input terminal, and the second control signal (CNT) through which the clock signal (CLK) is controlled flows. A gated clock circuit (12) in which the wiring (16) is connected to the second input terminal is disposed. The circuit insertion part (7-5) arranges a noise reduction circuit (11) as a circuit for reducing noise of the control signal (CNT) in the vicinity of the second input terminal on the second wiring (16).

  In the automatic placement and routing apparatus, the noise reduction circuit (11) is placed within a range of 1 to 10 sites from the gated clock circuit (12) on the second wiring (16).

  In the automatic placement and routing apparatus, the noise reduction circuit (11) is one of a buffer circuit and an inverter circuit.

  In order to solve the above problems, a semiconductor device of the present invention includes a gated clock circuit (12) and a noise reduction circuit (11). The gated clock circuit (12) has a first wiring (15) through which a clock signal (CLK) flows as a first input terminal and a second wiring (16) through which a control signal (CNT) for controlling the clock signal (CLK) flows. The second input terminal is connected. The noise reduction circuit (11) is provided in the vicinity of the second input terminal on the second wiring (16). Control signal (CNT) noise is reduced.

  In the semiconductor device, the noise reduction circuit (11) is disposed within a range of 1 to 10 sites from the gated clock circuit (12) on the second wiring (16).

  In the semiconductor device, the noise reduction circuit (11) is one of a buffer circuit and an inverter circuit.

  In order to solve the above-described problem, a program according to the present invention includes a first wiring (15) through which a clock signal (CLK) flows and a first input terminal through which a control signal (CNT) that controls the clock signal (CLK) flows. A step (S02 to S04) of arranging a gated clock circuit (12) in which two wirings (16) are connected to the second input terminal, and a control signal in the vicinity of the second input terminal on the second wiring (16). A computer is caused to execute a placement and routing method for a semiconductor device including a step (S06) of placing a noise reduction circuit (11) as a circuit for reducing noise of (CNT).

  In the above program, the noise reduction circuit (11) is arranged within a range of 1 to 10 sites from the gated clock circuit (12) on the second wiring (16).

  In the above program, the noise reduction circuit (11) is one of a buffer circuit and an inverter circuit.

  In order to solve the above problems, a method of manufacturing a semiconductor device according to the present invention includes a step (S02 to S06) of performing automatic placement and routing of the semiconductor device according to the placement and routing method of a semiconductor device according to any one of the above. The automatic placement and routing is verified, a step (SS07 to S08) for completing the layout design of the semiconductor device, and a film formed on the semiconductor substrate using a mask created based on the layout design. And a lithography process (S23).

According to the present invention, noise included in a control signal when input to the gated clock circuit can be reduced, and fluctuations in the clock signal of the gated clock circuit can be prevented. Then, the operation of the gated clock circuit can be stabilized, and the stability of the semiconductor device can be further improved.
It becomes possible.

  Embodiments of an automatic placement and routing apparatus, a semiconductor device, a placement and routing method for a semiconductor device, and a method for manufacturing a semiconductor device according to the present invention will be described below with reference to the accompanying drawings.

First, the configuration of an embodiment of an automatic placement and routing apparatus to which a semiconductor device placement and routing method of the present invention is applied will be described with reference to the accompanying drawings.
FIG. 1 is a diagram showing a configuration of an embodiment of a placement and routing system to which a semiconductor device placement and routing method of the present invention is applied. The placement and routing system 10 includes an automatic placement and routing apparatus 1 and a design database 9.

  The design database 9 is a database on an information processing apparatus exemplified by a workstation. A circuit diagram data file 2, a cell / block library 3, and a design rule file 4 as data and a computer program related to the data are provided. The circuit diagram data file 2 includes connection data indicating connection relationships between terminals of each (logic function) cell / block constituting the LSI to be designed. The cell / block library 3 includes data related to (logic function) cells / blocks such as vias, NAND gates, and circuits that realize complex logic functions. The design rule file 4 includes design rules used at the time of placement and wiring and verification such as the wiring pitch of each wiring layer, the wiring width and the minimum wiring interval, and the dimensions of each element constituting the via cell.

  The automatic placement and routing apparatus 1 is an information processing apparatus exemplified by a workstation. A reading / preprocessing unit 6 as a computer program, an automatic placement and routing main unit 7 and a placement and routing result verification unit 8 are provided. The automatic placement and routing apparatus 1 and the design database 9 are communicably connected. For simplification of the system and space saving, both may be integrated.

  The read / preprocessing unit 6 reads connection data between terminals of each (logic function) cell / block constituting the design target LSI from the circuit diagram data file 2. In addition, artwork data relating to cells / blocks used for the LSI to be designed is read from the cell / block library 3. Further, design rules used at the time of placement and wiring and verification such as the wiring pitch of each wiring layer, the wiring width and the minimum wiring interval, and the dimensions of each element constituting the via cell are read from the design rule file 4.

  The automatic placement and routing main body unit 7 performs automatic placement and routing and outputs the execution result to the placement and routing result verification unit 8. An initial placement and routing unit 7-1, a tree structure creation unit 7-2, a clock net wiring unit 7-3, a signal wiring unit 7-4, and a buffer insertion unit 7-5 are included.

  The initial placement and routing unit 7-1 creates placement and routing data based on the read data, and performs placement and initial routing of the initial circuit in the placement and routing area of the semiconductor device. Initial circuit placement and initial wiring includes gated-clock circuits and associated wiring. In the gated clock circuit, a first wiring through which a clock signal flows is connected to a first input terminal, and a second wiring through which a control signal for controlling the clock signal is connected to a second input terminal, and the clock signal controlled by the control signal Is output from the output terminal.

  The tree structure creation unit 7-2 performs clock tree synthesis (clock-tree synthesis) on the initial circuit and the initial wiring. Then, a tree structure of the clock signal wiring through which the clock signal connected to the output terminal of the gated clock circuit flows is created.

  The clock net wiring unit 7-3 actually routes the first wiring through which the clock signal flows and the clock signal wiring having a tree structure, and provides a shield as a noise countermeasure for them. For example, power supply (VDD) wiring and ground (GND) wiring are provided in parallel in the adjacent wiring region.

  The signal wiring unit 7-4 actually wires wirings (example: second wiring) other than the first wiring through which the clock signal flows and the clock signal wiring in the tree structure.

  The buffer insertion unit 7-5 has a noise reduction as a circuit for reducing the noise of the control signal in the vicinity of the second input terminal on the second wiring not provided with the shield in the circuit configuration after the clock tree synthesis and the shield. Arrange the circuit. The noise reduction circuit is, for example, a buffer circuit or an inverter circuit.

  The placement and routing result verification unit 8 verifies the execution result of the placement and routing. At the time of verification, spare cells whose relationship with wiring violates the design rule described in the design rule data are removed. If no defect is found, the result of placement and routing is converted back to artwork data, and then output as a placement and routing result output file 5. When a defect is found, the automatic placement and routing main body unit 7 or the input / editing unit (not shown) corrects the defect and re-executes the placement and routing. And it verifies again.

  FIG. 2 is a diagram showing the effect of the semiconductor device to which the semiconductor device placement and routing method of the present invention is applied. The semiconductor device 20 is an example in which the upper gated clock circuit 12-1 and related parts are applied with the present invention. The lower gated clock circuit 12-2 and related parts are the configuration of the comparative example.

  First, the configuration of the comparative example will be described. The configuration of the comparative example includes a gated clock circuit 12-2, buffer circuits 13-4 to 13-6, a flip-flop group 18-2, a first wiring 15, a second wiring 16-2, and a second clock signal wiring 17-2. It comprises.

  The gated clock circuit 12-2 receives the clock signal CLK2 from the first wiring 15 (branch) at the first input terminal. Since the first wiring 15 is protected by the shield 22-2, the initial clock signal CLK1 is weakened on the way and becomes like the clock signal CLK2, but is not disturbed by noise. On the other hand, the control signal CNT2 is received from the second wiring 16-2 at the second input terminal. Since the second wiring 16-1 is not protected, the control signal CNT2 having an initially appropriate waveform is disturbed by noise on the way. The gated clock circuit 12-2 outputs the clock signal CLK2 as the clock signal CLK4 from the output terminal to the first clock wiring 17-2 based on the control of the control signal CNT2. The second clock signal wiring 17-2 connected to the flip-flop group 18-2 is protected by a shield 23-2 so as not to be affected by noise, and noise reduction like the buffer circuits 13-4 to 13-6 is performed at an appropriate interval. Since the circuit is included, the clock signal CLK4 is not affected by external noise when propagating to the flip-flop group 18-2.

Here, the influence of noise on the control signal CNT2 in the comparative example will be considered.
As described above, since the second wiring 16-1 (net) is considered to be less affected by noise than the clock signal, it is usually protected by shielding or wiring capacity limitation (wiring capacity limitation). There is no consideration. Therefore, even the control signal CNT2 having an appropriate waveform at the beginning is easily disturbed by noise on the way. The longer the wiring length, the greater the effect.
In that case, since the gated clock circuit 12-2 outputs the clock signal CLK4 based on the control signal CNT2 having a waveform disturbed by noise, the clock signal CLK4 is also affected by it. In such a case, a desired clock signal may not be obtained. For example, there arises a problem that the clock signal CLK4 is delayed from a desired timing. As a result, in the worst case, the logic may be inverted. In particular, the higher the clock frequency, the greater the possibility.

  Next, the configuration of the present invention will be described. The configuration of the present invention includes a gated clock circuit 12-1, buffer circuits 13-1 to 13-3, a flip-flop group 18-1, a first wiring 15, a second wiring 16-1, and a second clock signal wiring 17-1. The buffer circuit 11 is provided. The configuration of the present invention is different from the configuration of the comparative example in that the buffer circuit 11 is provided in the middle of the second wiring 16-1.

  That is, it is as follows. The gated clock circuit 12-1 receives the clock signal CLK2 from the first wiring 15 at the first input terminal. Since the first wiring 15 is protected by the shield 22-1, the clock signal CLK1 is not disturbed by noise even if the clock signal CLK1 is weakened in the middle and becomes like the clock signal CLK2. On the other hand, the control signal CNT1 'is received from the second wiring 16-1 at the second input terminal. Since the second wiring 16-1 is not protected, the control signal CNT1 having an initially appropriate waveform is disturbed by noise on the way. However, in the configuration of the present invention, since the control signal CNT1 is buffered by the buffer circuit 11, the influence of noise is reduced, and the potential of the control signal CNT1 'is a stable waveform signal. The gated clock circuit 12-1 outputs the clock signal CLK2 as the clock signal CLK3 from the output terminal to the first clock wiring 17-1 based on the control of the control signal CNT1 '. The first clock signal wiring 17-1 connected to the flip-flop group 18-1 is protected by a shield 23-1 so as not to be affected by noise, and noise reduction such as the buffer circuits 13-1 to 13-3 is performed at an appropriate interval. Since the circuit is included, the clock signal CLK3 is not affected by external noise when propagating to the flip-flop group 18-1.

  Since the clock signal CLK3 is output based on the control signal CNT1 'having a proper waveform that is not disturbed by noise, the clock signal CLK3 also becomes a signal having a proper waveform that is not affected by noise. Thereby, the problem that the clock signal CLK4 is delayed from the desired timing as in the comparative example can be avoided. Even when the clock frequency is increased, stable operation can be achieved without causing a problem such as logic inversion. The control signal CNT1 is delayed by the buffer circuit 11. However, if the control signal CNT1 is generated in consideration of the delay in advance, there is no problem in the operation of the gated clock circuit 12-1.

  Here, the buffer circuit 11 is preferably provided in the vicinity of the second input terminal. As a result, the control signal CNT whose noise has been reduced by the buffer circuit 11 can immediately enter the gated clock circuit 12 without being affected by the noise again. The buffer circuit 11 is preferably provided on the second wiring 16 at a position as close as possible to the second input terminal of the gated clock circuit 12. More specifically, the range for obtaining the above effect is a range from a site adjacent to the site where the gated clock circuit 12 is arranged to a site separated by ten. However, a site is a minimum unit for arranging functional cells / blocks when automatic placement and routing is performed. The size of the site is the minimum functional block of the technology. For example, when the inverter is 1, the size is 1/3.

  Here, the buffer circuit 11 may be another circuit, element, or a combination thereof as long as it can reduce noise and return the control signal to an appropriate state. For example, an inverter circuit. The flip-flop group 18-1 is an example, and may be another functional cell / block.

Next, an embodiment of the placement and routing method for a semiconductor device of the present invention (operation of the embodiment of the automatic placement and routing apparatus) will be described with reference to the accompanying drawings.
FIG. 7 is a flowchart showing an embodiment of a method for arranging and wiring a semiconductor device of the present invention. FIG. 3 to FIG. 6 are configuration diagrams showing changes in the state of the placement and routing corresponding to steps S03 to S06 in the flowchart of FIG.

(1) Step S01: Library Reading Processing Referring to FIG. 7, the reading / preprocessing unit 6 is registered in advance as library data in each of the circuit diagram data file 2, the cell / block library 3, and the design rule file 4. Data relating to the circuit diagram, the connection relationship between the terminals, the functional block to be arranged, the wiring pitch, the wiring width, the minimum wiring interval, the side length of the via, the dimensions of each element constituting the via cell, and the like are read. Then, the placement and routing rules are set.

(2) Step S02: Cell / Block Placement Processing The initial placement / wiring unit 7-1 creates an initial circuit in the placement / wiring area of the semiconductor device based on the read data (circuit diagram data, functional block data, design rule data). Do the placement of. The arrangement of the initial circuit includes the arrangement of the gated clock circuit.
(3) Step S03: Cell / Block Temporary Wiring Processing The initial placement and routing unit 7-1 performs initial wiring of the initial circuit based on the set placement and routing rules. The initial wiring is temporary wiring, not actual wiring. The initial wiring of the initial circuit includes wiring related to the gated clock circuit.

  Here, as shown in FIG. 3, the gated clock circuit 12-1 includes a first wiring 15 for the clock signal CLK at the first input terminal and a second wiring 16-1 for the control signal CNT1 at the second input terminal. The clock signal wiring 17-1 for the clock signal CLK3 is connected to the output terminal. A flip-flop group 18-1 is connected to the other end of the clock signal wiring 17-1. Similarly, the gated clock circuit 12-2 outputs the first wiring 15 (branch) for the clock signal CLK to the first input terminal and the second wiring 16-2 for the control signal CNT2 to the second input terminal. The clock signal wiring 17-2 for the clock signal CLK4 is connected to the terminal. A flip-flop group 18-2 is connected to the other end of the clock signal wiring 17-2. Each of these wirings is an initial wiring.

(4) Step S04: Tree Structure Creation Processing Referring to FIG. 7, the tree structure creation unit 7-2 performs clock tree synthesis (clock-tree synthesis) on the initial circuit and the initial wiring. Then, a tree structure of the clock signal wiring through which the clock signal connected to the output terminal of the gated clock circuit flows is created. The clock signal wiring is a temporary wiring, not an actual wiring. In addition, a buffer circuit is inserted.

  Here, as shown in FIG. 4, the clock signal between the gated clock circuit 12-1 and the flip-flop group 18-1 is based on a predetermined rule (example: predetermined interval, number of flip-flop groups). The wiring 17-1 (clock net) is divided and buffer circuits 13-1 to 13-3 are inserted. Similarly, the clock signal wiring 17-2 (clock net) is divided between the gated clock circuit 12-2 and the flip-flop group 18-2 based on a predetermined rule, and the buffer circuits 13-4 to 13-. 6 is inserted. In this way, a tree structure in the clock signal wirings 17-1 to 17-2 is created. Each of these wirings is a clock signal wiring.

(5) Step S05: Clock Net Wiring Processing The clock net wiring section 7-3 is the actual wiring for the first wiring 15 through which the clock signal CLK flows and the clock signal wirings 17-1 to 17-2 (clock net) having a tree structure. I do. The first wiring 15 and the clock signal wirings 17-1 to 17-2 are provided with a shield as a noise countermeasure (clock signal CLK protection). For example, power supply (VDD) wiring and ground (GND) wiring are provided in parallel in the adjacent wiring region.

  Here, as shown in FIG. 5, the first wiring 15 is provided with shields 22-1 and 22-2. The clock signal wiring 17-1 is provided with a shield 23-1, and the clock signal wiring 17-2 is provided with a shield 23-2.

(6) Step S06: Signal Wiring Processing The signal wiring unit 7-4 performs actual wiring on temporary wiring other than wiring related to the clock net. Here, actual wiring is performed for the second wirings 16-1 to 16-2.

(7) Step S07: Buffer Insertion Processing The buffer insertion section 7-5 is a noise reduction circuit as a circuit for reducing control signal noise in the vicinity of the second input terminals on the second wirings 16-1 to 16-2. Insert and place. The noise reduction circuit is, for example, a buffer circuit or an inverter circuit.

  Here, as shown in FIG. 6, the buffer circuit 11-1 is provided in the second wiring 16-1 near the second input terminal of the gated clock circuit 12-1. Similarly, the buffer circuit 11-2 is provided in the second wiring 16-2 near the second input terminal of the gated clock circuit 12-2.

(8) Step S08: Placement and routing verification processing The placement and routing result verification unit 8 is based on the design rules stored in the design rule file 4 and the placement and routing rules. Verify that there are no short-circuit defects. When a defect is found, the automatic placement and routing main body unit 7 or the input / editing unit (not shown) belonging thereto corrects the defect and re-executes the placement and routing. Thereafter, the verification is repeated until the defect disappears.

(9) Step S09: Placed and routed data output process When no defect is found in step S08, the placement and routing execution result (data for automatic placement and routing apparatus 10) is the artwork data corresponding to the pattern of each layer constituting the LSI. Reconvert to Then, after the reconversion, the data is output as a placement and routing result output file 5.

  With the above process, the placement and routing process is completed.

  In step S07, the noise reduction circuit (buffer circuit 11) is inserted and arranged in all the gated clock circuits 12. Thereby, the clock signal output from the gated clock circuit 12 is stabilized. However, the noise reduction circuit may be inserted and arranged only in the gated clock circuit 12 that requires high-speed operation. This is because such a gated clock circuit 12 is particularly susceptible to the noise of the control signal CNT. In that case, since the number of noise reduction circuits to be inserted can be reduced, an increase in power consumption can be suppressed. Examples of the high-speed operation include a case where the clock frequency of the clock signal CLK is 100 MHz or more.

  The process in that case is as shown in FIG. That is, the buffer insertion unit 7-5 first detects the gated clock circuit 12 satisfying a predetermined condition based on the data relating to the clock frequency of the read circuit diagram data (step S07-1). Here, as a predetermined condition, the gated clock circuit 12 connected to the first wiring 15 such that the frequency of the clock signal CLK is 100 MHz or more is detected. The buffer insertion unit 7-5 inserts and arranges a noise reduction circuit in the vicinity of the second input terminal on the second wiring 16 of the detected gated clock circuit 12 (step S07-2).

  In the above process (steps S01 to S09), it is possible to reduce noise included in the control signal input to the gated clock circuit by introducing a noise reduction circuit (eg, buffer circuit) in the second wiring. It becomes. As a result, it is possible to prevent fluctuations in the clock signal of the gated clock circuit caused by noise included in the control signal. Then, the operation of the gated clock circuit can be stabilized and the operation of the semiconductor device can be stabilized.

  As a method of reducing noise included in the control signal input to the gated clock circuit, a shield may be provided for the second wiring in the initial placement wiring. Alternatively, a wiring capacity limit may be provided for the second wiring. These methods may be combined with the above-described method of adding a noise reduction circuit. Thereby, the noise of the control signal can be further reduced.

  In the above process (steps S01 to S09), after all wiring is completed, the noise reduction circuit is inserted. However, it is also possible to insert at other timings. Such a process is illustrated in FIGS.

FIG. 10 is a flowchart showing another modification of the embodiment of the method of arranging and wiring a semiconductor device according to the present invention.
As processes, (1) step S31: library read process, (2) step S32: cell / block placement process, (3) step S33: inter-cell / block temporary wiring process, (4) step S34: tree structure creation process, (5) Step S35: Clock net wiring processing, (6) Step S36: Buffer insertion processing, (7) Step S37: Signal wiring processing, (8) Step S38: Placement wiring verification processing, (9) Step S39: Placement wiring Complete data output processing. Compared to the case of FIG. 7, the case of FIG. 10 is different in that the order of the buffer insertion process (S36) and the signal wiring process (S37) is switched. That is, after wiring the clock net, a noise reduction circuit is inserted and finally all wiring is performed.

FIG. 11 is a flowchart showing still another modification of the embodiment of the semiconductor device placement and routing method of the present invention.
As processes, (1) step S41: library reading process, (2) step S42: cell / block placement process, (3) step S43: cell / block temporary wiring process, (4) step S44: tree structure creation process, (5) Step S45: Buffer insertion processing, (6) Step S46: Clock net wiring processing, (7) Step S47: Signal wiring processing, (8) Step S48: Placement wiring verification processing, (9) Step S49: Placement wiring Complete data output processing. Compared to the case of FIG. 7, the case of FIG. 11 is different in that the buffer insertion process (S45) is performed before the actual wiring (S46, S47). That is, after inserting the noise reduction circuit, wiring of the clock net is performed, and finally all wiring is performed.

The semiconductor device manufacturing method of the present invention using the layout of the semiconductor device created by the above-described semiconductor device placement and routing method will be described. FIG. 9 is a flowchart showing an embodiment of a method for manufacturing a semiconductor device of the present invention.
(1) Step S21
The above-described steps S01 to S08 are performed to obtain the placement and routing result output file 5. That is, the layout design of the semiconductor device is completed by the placement and routing process of the semiconductor device.
(2) Step S22
Based on the layout design in step S21, a mask used in the semiconductor manufacturing process is designed. Then, a mask is produced based on the design. There is no particular limitation on the mask design and manufacturing method, but for example, a conventionally known method can be used.
(3) Step S23
Step S22: A semiconductor device is manufactured on the semiconductor substrate using the created mask. If the said mask is used for the manufacturing process of a semiconductor device, there will be no restriction | limiting in particular. For example, conventionally known methods such as film formation and lithography can be used.

  The semiconductor device of the present invention can be manufactured in steps S21 to S23. Also in this case, it is possible to reduce noise included in the control signal input to the gated clock circuit. Accordingly, the operation of the gated clock circuit can be stabilized and the operation of the semiconductor device can be stabilized.

FIG. 1 is a diagram showing a configuration of an embodiment of a placement and routing system to which a semiconductor device placement and routing method of the present invention is applied. FIG. 2 is a diagram showing the effect of the semiconductor device to which the semiconductor device placement and routing method of the present invention is applied. FIG. 3 is a configuration diagram showing a change in the state of the placement and routing corresponding to step S03 in the flowchart of FIG. FIG. 4 is a configuration diagram showing a state change of the placement and routing corresponding to step S04 in the flowchart of FIG. FIG. 5 is a configuration diagram showing a state change of the placement and routing corresponding to step S05 in the flowchart of FIG. FIG. 6 is a configuration diagram showing a state change of the placement and routing corresponding to step S06 in the flowchart of FIG. FIG. 7 is a flowchart showing an embodiment of a method for arranging and wiring a semiconductor device according to the present invention. FIG. 8 is a flowchart of step S06 in the embodiment of the semiconductor device placement and routing method of the present invention. FIG. 9 is a flowchart showing an embodiment of a method for manufacturing a semiconductor device of the present invention. FIG. 10 is a flowchart showing another modification of the embodiment of the method of arranging and wiring a semiconductor device according to the present invention. FIG. 11 is a flowchart showing still another modification of the embodiment of the semiconductor device placement and routing method of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Automatic placement and routing device 2 Circuit diagram data file 3 Cell / block library 4 Design rule file 5 Placement and routing result output file 6 Read / pre-processing unit 7 Automatic placement and routing main unit 7-1 Initial placement and routing unit 7-2 Tree structure creation Section 7-3 Clock net wiring section 7-5 Buffer insertion section 8 Placement and routing result verification section 9 Design database 10 Placement and routing system 12 (12-1, 12-2) Gated clock circuit 13 (13-1 to 13-6) Buffer circuit 15 First wiring 16 (16-1, 16-2) Second wiring 17 (17-1, 17-2) Clock signal wiring (first and second clock signal wiring)
18 (18-1, 18-2) flip-flop group

Claims (13)

Disposing a gated clock circuit in which a first wiring through which a clock signal flows is connected to a first input terminal and a second wiring through which a control signal for controlling the clock signal flows is connected to a second input terminal;
A placement and wiring method for a semiconductor device, comprising: inserting and placing a noise reduction circuit as a circuit for reducing noise of the control signal in the vicinity of the second input terminal on the second wiring. The method of arranging and wiring a semiconductor device according to claim 1,
The method of arranging and wiring a semiconductor device, wherein the noise reduction circuit is arranged within a range of 1 to 10 sites from the gated clock circuit on the second wiring. In the placement and routing method of the semiconductor device according to claim 1 or 2,
The noise reduction circuit is one of a buffer circuit and an inverter circuit. An automatic placement and routing unit for placing a gated clock circuit in which a first wiring through which a clock signal flows is connected to a first input terminal and a second wiring through which a control signal for controlling the clock signal is connected to a second input terminal;
An automatic placement and routing apparatus comprising: a circuit insertion unit that places a noise reduction circuit as a circuit for reducing noise of the control signal in the vicinity of the second input terminal on the second wiring. In the automatic placement and routing apparatus according to claim 4,
The automatic placement and routing apparatus, wherein the noise reduction circuit is arranged within a range of 1 to 10 sites from the gated clock circuit on the second wiring. In the automatic placement and routing apparatus according to claim 4 or 5,
The noise reduction circuit is one of a buffer circuit and an inverter circuit. A gated clock circuit in which a first wiring through which a clock signal flows is connected to a first input terminal, and a second wiring through which a control signal for controlling the clock signal flows is connected to a second input terminal;
A semiconductor device comprising: a noise reduction circuit that is provided in the vicinity of the second input terminal on the second wiring and serves as a circuit that reduces noise of the control signal. The semiconductor device according to claim 7,
The noise reduction circuit is disposed within a range of 1 to 10 sites from the gated clock circuit on the second wiring. The semiconductor device according to claim 7 or 8,
The noise reduction circuit is one of a buffer circuit and an inverter circuit. Disposing a gated clock circuit in which a first wiring through which a clock signal flows is connected to a first input terminal and a second wiring through which a control signal for controlling the clock signal flows is connected to a second input terminal;
Disposing a noise reduction circuit as a circuit for reducing the noise of the control signal in the vicinity of the second input terminal on the second wiring. program. The program according to claim 10, wherein
The program which arrange | positions the said noise reduction circuit in the range of 1 thru | or 10 sites from the said gated clock circuit on the said 2nd wiring. The program according to claim 10 or 11,
The noise reduction circuit is one of a buffer circuit and an inverter circuit. Performing the automatic placement and routing of the semiconductor device according to the placement and routing method of the semiconductor device according to any one of claims 1 to 3,
Verifying the automatic placement and routing, and completing a layout design of the semiconductor device;
Performing a lithography process on a film formed on the semiconductor substrate using a mask created based on the layout design.

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