JP2005277032A - Nonvolatile semiconductor memory device and method of charge injection for it - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent degradation in memory transistor characteristics while keeping a required height of a potential barrier according to the charge injection direction, and also to control the spreading of a distribution of injected charges. <P>SOLUTION: A gate laminate film 3 formed on a P-type semiconductor substrate 2 and containing a charge accumulation layer 5, and two N-type source-drain regions 8 and 9 formed on the semiconductor substrate 2 at both ends in one of orientations of the film 3 are provided. A potential barrier insulation film 4 interposed between the charge accumulation layer 5 and the semiconductor substrate 2 in the gate laminate film 3 has its local region 4B with different composition from that of other parts 4A. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a gate laminated film including a charge storage layer formed on a first conductive type semiconductor substrate, and two second conductive type sources formed on a semiconductor substrate on both ends in one direction of the gate laminated film. The present invention relates to a nonvolatile semiconductor memory device having a drain region and a charge injection method thereof.

A transistor (memory transistor) constituting a memory cell of a nonvolatile semiconductor memory device has a gate stacked film on a semiconductor substrate. The gate laminated film includes a gate insulating film composed of a plurality of layers and a gate electrode on the gate insulating film. As is well known, when a memory transistor is classified by a gate laminated film structure, an FG having a conductive floating gate (FG) surrounded by an insulator in a gate insulating film and in an electrically floating state. The gate insulating film is roughly divided into a type and a trap gate type such as a MONOS memory in which gate insulating films are formed by stacking films having different charge trap densities. In addition, as trap-gate type charge traps, those using the interface states of the insulating film and deep levels in the insulating film (for example, MONOS transistors and MNOS transistors), and those using fine particles such as polysilicon and metal It has been known.
A film or layer containing a large number of FG type floating gates and trap gate type charge traps is hereinafter referred to as a charge storage layer.

The insulating film interposed between the charge storage layer (floating gate) and the semiconductor substrate in the FG type is called a tunnel film because of its function during the charge injection operation. The tunnel film is usually a single-layer film, and is composed of, for example, a silicon oxide film.
On the other hand, the gate insulating film of the MONOS transistor is called a first potential barrier insulating film called a so-called bottom oxide film, a nitride film as a charge storage layer, and a so-called top oxide film in order from the semiconductor substrate side. Generally, it is composed of a second potential barrier insulating film. The first potential barrier insulating film interposed between the semiconductor substrate and the charge storage layer is usually made of a single-layer silicon oxide film. Furthermore, the first potential barrier insulating film is made of a plurality of films having different film qualities. It is known to comprise an insulating film (see, for example, Patent Document 1).

According to the technique described in Patent Document 1, a silicon oxide film is deposited on a silicon nitride film formed by thermally nitriding a semiconductor substrate or nitriding after thermal oxidation. A potential barrier insulating film is formed. This is because the potential barrier for electrons passing from the nitride film as the charge storage layer formed on the first potential barrier insulating film to the semiconductor substrate is kept high to prevent the data retention characteristics from deteriorating. Japanese Patent Application Laid-Open No. H10-228707 describes that the potential barrier of injected electrons is lowered to improve the injection efficiency.
Japanese Patent Laid-Open No. 06-296028

  However, if the entire semiconductor substrate is thermally nitrided or the oxide film is nitrided, nitrogen atoms are introduced near the interface with the semiconductor substrate and remain. In this case, since the interface state changes compared to the case where the semiconductor substrate is thermally oxidized to form a single-layer silicon oxide film, the current flowing through the channel during operation decreases, and the characteristics of the memory transistor deteriorate. There are challenges.

  In particular, in the case where charges are injected from a local portion of the substrate-side region immediately below the gate, it is only necessary to obtain a necessary potential barrier height at the portion where charges are injected.

  Furthermore, when the electric conductivity of the charge storage layer is extremely low, if the height of the potential barrier with respect to the charge injected into the charge storage layer is lowered on the entire channel surface, the distribution of the injected charge is expanded. In this regard, for example, since the conductivity of the charge storage layer is extremely low, the charge injected from the local portion of the substrate side region directly under the gate is stored in a part of the charge storage layer, and reversely applied to cancel the influence of the charge. Polar charge may be injected. At this time, if one of the distribution of the charge injected first and the distribution of the reverse polarity charge injected thereafter becomes extremely large, there is a high possibility that a part of the charge injected first cannot be offset. Moreover, when the state after the first data rewrite is set to the initial state, and the data is rewritten for the second time by injecting charges of opposite polarities, the data write state and the erase state in the first and second times. The electric charge distribution at is different. As this operation is repeated, one charge may gradually accumulate in the charge storage layer when viewed in a large span. This phenomenon results in insufficient writing or erasing, resulting in a decrease in endurance characteristics in which the threshold voltage difference (window width) between the written state and the erased state is gradually reduced. Also, if the charge with the opposite polarity to the retained charge gradually accumulates, the charge diffusion rate is low, but the charge recombines and neutralizes due to mutual diffusion when left for a long time. The same phenomenon as in the case where the retention characteristic is low and the retention characteristic from which the retained charge is released is low.

  Even if one of the charges does not accumulate gradually, if the distribution of injected charges is wide, there is a high possibility that the threshold value will be different for each rewrite. In this case, since the rewrite operation is not stable, it is necessary to increase the window width more than necessary in order to obtain a margin for the read operation, which causes a problem that the voltage reduction and the miniaturization are hindered.

The first problem to be solved by the present invention is to prevent the deterioration of the characteristics of the memory transistor while ensuring the necessary potential barrier height according to the charge injection direction, and to spread the distribution of the injected charge. Is to control.
The second problem to be solved by the present invention is to stabilize the rewrite operation, thereby making it possible to further reduce the operation margin, that is, the window width.

  A non-volatile semiconductor memory device according to a first aspect of the present invention is for solving the first problem, and includes a gate stacked film formed on a first conductivity type semiconductor substrate and including a charge storage layer. A non-volatile semiconductor memory device having two source / drain regions of the second conductivity type formed on a semiconductor substrate on both ends in one direction of the gate stacked film, wherein the gate stacked film includes a charge storage layer, Including a potential barrier insulating film interposed between the semiconductor substrate, and the potential barrier insulating film has a composition whose local portion located in a certain range in the direction of separation of the two source / drain regions is different from the composition of other portions. Have.

  In this nonvolatile semiconductor memory device, the potential barrier insulating film is a part (local part) of a certain range in the direction in which the two source / drain regions are separated (that is, the direction in which the channel current flows), and the composition is different from that of the other part. Is different. Since the potential barrier height with respect to a certain charge is different between the local portion of the potential barrier insulating film having a different composition and the other portion, the amount of charge passing per unit time is different under the same voltage condition. That is, for a certain charge, the amount of charge passing through the local portion is controlled according to the difference in the composition of the potential barrier insulating film. When this is performed on the charge injected into the charge storage layer from the semiconductor substrate side, the distribution of the stored charge in the charge storage layer is controlled.

  A non-volatile semiconductor memory device according to a second aspect of the present invention is for solving the second problem, and includes a non-volatile semiconductor memory having a gate stacked film including a charge storage layer formed on a semiconductor substrate. A heating electrode formed in the vicinity of the charge storage layer, and a voltage supply means for supplying a voltage between one end and the other end of the heating electrode and flowing a current to the heating electrode. Also have.

  A charge injection method for a nonvolatile semiconductor memory device according to the present invention is for solving the second problem, and is a gate stacked film including a charge storage layer formed on a first conductivity type semiconductor substrate, By injecting charges having opposite polarities into the charge storage layer to the memory transistor having two source / drain regions of the second conductivity type formed on the semiconductor substrate on both ends in one direction of the gate laminated film, respectively. A charge injection method for a nonvolatile semiconductor memory device for writing and erasing data, wherein a first charge is induced in one of a semiconductor substrate and a source / drain region, and the first charge is injected into a charge storage layer. A writing step for writing data; a second charge having a polarity opposite to the first charge is induced on the other of the semiconductor substrate and the source / drain region; An erasing step for erasing data by injecting into the storage layer, and a current flow through the conductive layer near the charge storage layer to heat the charge storage layer, thereby rearranging the charges stored in the charge storage layer. Performing a heating step.

  According to the nonvolatile semiconductor memory device and the charge injection method thereof according to the second aspect, the first charge and the second charge having different polarities are sequentially injected from the semiconductor substrate side or the source / drain region side to rewrite data. When a current is applied by applying a voltage to one end and the other end of the heating electrode in the vicinity of the charge storage layer (data writing and erasing step), the charge storage layer is heated by the Joule heat. Therefore, the injected charge is rearranged in the charge storage layer. That is, when the distribution of the first charge and the distribution of the second charge are deviated, the charge is canceled out in the overlapping portion, but the first charge and the second charge remaining apart in the non-overlapping portion are respectively It diffuses and gradually offsets with heating time. If this heating is performed at a certain temperature for a certain time or more, the other charge amount becomes zero, and a change in the charge amount does not occur any more and a thermal equilibrium state as a charge amount is obtained.

According to the nonvolatile semiconductor memory device of the present invention, the charge distribution in the charge storage layer can be controlled to some extent according to the position and size of a certain range portion (local part) whose composition is changed in the potential barrier insulating film. There is. In addition, the charge injection efficiency can be increased or decreased locally.
More specifically, for example, the charge distribution is narrowed with respect to a charge that would inevitably expand the distribution of the accumulated charge due to the difference in the position where the charge is generated, the mechanism, and the direction of the injection. By appropriately setting the composition of the local part and the position and size (or planar shape) of the local part in the potential barrier insulating film so that the amount of injected charge can be controlled, the charge is transferred to the charge storage layer. The injection range can be limited to some extent, and the spread of the distribution can be suppressed.
On the other hand, it is possible to make the portion of the potential barrier insulating film other than the above-mentioned local region a composition that can obtain a desired potential barrier height from the viewpoint of charge retention without introducing nitrogen or the like into the semiconductor substrate. To.
As a result, it is possible to realize a nonvolatile semiconductor memory device that can increase the efficiency of injecting a specific charge or control the distribution of accumulated charge without degrading the characteristics of the memory transistor.

In addition, according to another nonvolatile semiconductor memory device of the present invention and its charge injection method, the injection range for one of the first charge and the second charge is limited to control the distribution of the charge during accumulation. However, if there is still a deviation from the other charge distribution, the charge can be rearranged by heating. As a result, it is possible to achieve a thermal equilibrium state as a charge amount in which any charge amount becomes zero. Since the charge amounts of the first and second charges can be controlled to be almost the same depending on the bias application conditions at the time of writing and erasing, if this is combined with the rearrangement of charges by heating, the accumulated charge after data rewriting is combined. It is possible to always keep the amount almost zero. As a result, there is an advantage that a phenomenon in which one charge gradually accumulates during data rewriting and the endurance characteristic is deteriorated can be effectively prevented.
In addition, since the data rewrite operation can be performed stably, there is no need to provide an extra margin during the read operation, and an advantage is that the injected charge amount is sufficient to obtain the threshold voltage difference (window width) necessary for the read operation. There is.

[First Embodiment]
The nonvolatile semiconductor memory device of this embodiment includes a memory transistor in which the composition of the potential barrier insulating film interposed between the semiconductor substrate and the charge storage layer is locally changed. The gate laminated film structure of this memory transistor may be FG type, and in that case, there is an advantage that the efficiency of local charge injection or extraction is improved. However, the configuration of the potential barrier insulating film is more effective for the trap gate type in which charges are injected into the charge trap. Therefore, in the following, the first embodiment will be described using a trap gate type having a MONOS memory transistor as an example.
In the following description, it is possible to replace the MONOS type memory transistor with an MNOS type or a fine particle type. In the following description, the N-channel type is described. In the case of the P-type, the following description can be applied by analogy by reversing the impurity conductivity type and the potential relationship between the source and drain during operation.

FIG. 1 shows a schematic cross-sectional structure of a MONOS memory transistor according to the first embodiment.
The memory transistor 1 is formed on a P-type semiconductor substrate 2. Here, the “semiconductor substrate” means a P-type well formed in a semiconductor substrate, or a main surface of a semiconductor or other material substrate with an insulating layer interposed therebetween, in addition to a substrate such as P-type single crystal silicon. It may be a so-called SOI structure P-type semiconductor layer formed as described above, or a thin film transistor P-type semiconductor material layer formed in a stacked structure on a substrate.
Although not particularly illustrated, the memory transistor 1 constitutes a memory cell array in which a large number of the memory transistors 1 are arranged in a matrix. The memory transistors are connected or coupled by a common line in the row direction or the column direction, for example, a bit line or a source line, and a bias voltage can be applied through these common lines. In addition, a peripheral circuit for operating the memory cell array by supplying a predetermined voltage to each common line is provided around the memory cell array.

  On the semiconductor substrate 2, a gate laminated film 3 composed of a first potential barrier insulating film 4, a charge storage layer 5, a second potential barrier insulating film 6 and a gate electrode 7 is formed. In the gate laminated film 3, at least the gate electrode 7 or a common line connecting them in common is formed in a line shape that is long in the column direction. FIG. 1 is a cross-sectional view in a direction perpendicular to the wiring direction of the common line.

  Two source / drain regions 8 and 9 are formed by introducing an N-type impurity region at a substrate position that partially overlaps with both ends of the gate laminated film 3 on the planar pattern. A channel is formed in the substrate surface portion between the two source / drain regions 8 and 9 during operation (hereinafter, this substrate surface portion is referred to as a channel formation region). Each of the two source / drain regions 8 and 9 is usually provided with a region called LDD or extension in the inner portion of the channel forming region. However, it is not essential that the two source / drain regions 8 and 9 include these regions as long as the gate electrode 7 and the end overlap each other.

The charge storage layer 5 is made of an insulating material such as silicon nitride, silicon oxynitride, or other metal oxide film having a charge trap density higher than that of silicon oxide.
The second potential barrier insulating film 6 is usually composed of a silicon oxide film.
The gate electrode 7 has a single-layer structure of doped polysilicon doped with impurities, or a two-layer structure of doped polysilicon and a refractory metal alloy (silicide) layer.

  The first potential barrier insulating film 4 has a characteristic configuration of the present embodiment, and includes a main portion 4A and a local portion 4B that overlap most of the channel formation region as a region viewed in a plane pattern. The main part 4A and the local part 4B have different compositions, and are usually formed by forming the same film and changing a part of the composition. The reason for making this composition different is that the insulating film portion (main portion 4A) in contact with the channel formation region is formed of a material that does not adversely affect the current channel and transistor characteristics (for example, silicon oxide formed by thermal oxidation), and at the same time This is to limit to a certain extent the range of charge injection points where the distribution when accumulated in the charge storage layer 5 is expanded. In order to limit the charge injection location, it is necessary to increase the charge injection efficiency at the location (local portion 4B) where the charge is desired to be limited. For this purpose, in the local portion 4B, the potential for the charge from the substrate side toward the charge storage layer 5 The barrier height is set lower than the potential barrier height of the main portion 4A.

If these requirements are satisfied, the material of the main portion 4A and the local portion 4B is arbitrary, and an appropriate material can be selected according to the charge injection method. In this example, hot electrons (HE) are injected into the drain (source / drain region 9) side portion of the charge storage layer 5 when data is written, and hot holes (HH) are generated on the drain side when data is erased. This is the case of injection into the electron injection region of the storage layer 5. When electrons are injected in the case of an N-channel type memory transistor, the threshold voltage rises. By arbitrarily selecting a memory transistor for injecting electrons in the memory cell array, data is written, and the electric field generated by the voltage applied to the gate during reading serves to weaken the injected electrons. A channel is not formed in the memory transistor that is injected, and a channel is formed in the memory transistor that is not injected. Data is read by sensing the potential of the source / drain region that changes in response to the channel current flowing or not flowing. On the other hand, in erasing data, holes are injected to cancel previously injected electrons and return the threshold voltage to the initial state.
Note that the definition of data writing and erasing may be reversed depending on the memory cell array system. That is, the state in which electrons are injected into all the memory transistors is the erased state, and data may be written by injecting holes into an arbitrary memory cell.

In the desirable first potential barrier insulating film 4 suitable for the charge injection method assumed in this example, it is desirable that the local portion 4B has a composition in which the ratio of nitrogen is larger than the composition of the main portion 4A. For example, if one configuration example of the first potential barrier insulating film 4 is given, its main portion 4A is made of silicon oxide formed by thermal oxidation, and its local portion 4B is made of silicon nitride or silicon oxynitride. It is desirable to configure. As a result, the potential barrier height when holes are injected from the substrate side is lower at the local portion 4B than at the main portion 4A. On the other hand, the potential barrier height when electrons are injected from the substrate side does not change much between the main portion 4A and the local portion 4B.
In the selection of this material, in addition to the above requirements, the charge retention characteristic of the portion of the charge storage layer 5 in contact with the local portion 4B is equal to or greater than the charge retention characteristic of the portion of the charge storage layer 5 in contact with the main portion 4A. It is more desirable to select the material in consideration of such a viewpoint.

In this example, the CHE injection method is adopted as a method for injecting electrons.
In the CHE injection method, a positive voltage is applied to the other source / drain regions 9 serving as the drain with reference to the potential of the source / drain region 8 serving as the source, and a positive voltage is applied to the gate (gate electrode 7). At this time, electrons are induced to form a channel, and electrons traveling in the channel are accelerated by a horizontal electric field to become hot electrons (HE). A part of it obtains high energy just below the boundary between the main portion 4A and the local portion 4B, and is injected into the portion near the local portion 4A of the charge storage layer 5 over the potential barrier of the first potential barrier insulating film 4. And is captured in that trap.
On the other hand, when holes are injected, a positive voltage is applied to the source / drain region 9 serving as the drain, and the source / drain region 8 serving as the source is set to a lower constant voltage (for example, ground voltage) or an electrically open state. A negative voltage is applied to the electrode 7. Since the gate voltage is negative, an accumulation layer of minority carriers (holes) is induced at the end of the source / drain region 9 below the gate voltage, and electrons in the valence band are tunneled to the conduction band, or an avalanche. Due to the effect, a pair of electrons and holes is generated, and a part of the holes is accelerated by a vertical (and horizontal) electric field to become hot holes (HH). Then, it is injected into the portion of the charge storage layer 5 near the local portion 4A over the potential barrier of the first potential barrier insulating film 4. At this time, when the source is held at a constant voltage, the lateral electric field is strengthened, and when the source is opened, the electric field is not applied in the lateral direction, so that the hole injection range can be controlled to some extent.

The CHE injection method can point out the following problems.
That is, when data is rewritten by sequentially injecting charges having different polarities, generally, the distribution of one charge in the charge storage layer is expanded even if it is smaller than the other distribution. In this example, the probability of generation of hot electrons suddenly increases with a certain electric field as a boundary, so that the distribution in the charge storage layer is relatively steep. The electron injection amount and the distribution center can be controlled to some extent by controlling the bias voltage application conditions during CHE injection. However, in the case of holes, if the source is held at a constant voltage at the time of injection, the lateral electric field is strengthened, and if the source is opened, no electric field is applied in the lateral direction. The range is narrow. Rather, in the case of holes, the distribution of holes is easier to spread than electrons because the generated part is spread in a planar shape.

  Therefore, in order to inject holes into a relatively wide range and neutralize electrons with a relatively narrow distribution and a high capture density, it is necessary to increase the amount of holes injected and inject holes excessively. . As a result, excessive holes remain in the charge storage layer 5. At the time of the next data rewriting, data is repeatedly rewritten with the state where the holes remain as the initial state. Each time data is rewritten, the injection positions of electrons and holes are usually slightly shifted, so that the remnant range of holes gradually expands while rewriting is repeated many times. The accumulated amount of holes in 5 will gradually increase.

When holes are accumulated in the charge storage layer 5, the next data rewrite cycle is performed. When data is written by injecting electrons, some of the injected electrons are neutralized, As the sum amount increases, the ratio of the accumulated amount to the electron injection amount decreases. In addition, since holes that could not contribute to neutralization at this time are continuously accumulated, the accumulated amount gradually increases. If the accumulated amount of holes increases while data is rewritten many times, the amount of accumulated electrons that contribute to the increase in threshold voltage will decrease in subsequent data writing, and the threshold after sufficient writing will be reduced. It becomes difficult to obtain a value voltage. That is, data rewrite characteristics (endurance characteristics) are degraded.
Further, since excessive hole injection is required, the film quality is deteriorated and the charge retention characteristics are likely to be deteriorated. Even if this film quality degradation does not occur, the charge diffusion rate is low, but the charges recombine and neutralize due to mutual diffusion when left for a long time, resulting in a decrease in charge amount and loss of retained charge. This leads to the same phenomenon as when the retention characteristics are low.
Further, since the hole injection efficiency is originally low, the erasing time is long, and if the endurance characteristic is prevented from being lowered, the erasing time must be further increased.

In the present embodiment, in order to solve such a problem, the composition of the first potential barrier insulating film 4 is changed from the other portions in the local portion 4B near the hole injection position. The position of the local portion 4B can be changed to an appropriate position in relation to the electron injection position, and the size in the channel direction (lateral direction in the figure) can also be changed to an appropriate one. However, as shown in FIG. 1, the local portion 4B needs to overlap at least partly with the end portion of the source / drain region 9 which is the source of holes. For this reason, when electrons are injected slightly inside the end of the charge storage layer 5 and it is not desired to put holes in the end of the charge storage layer 5, the same material as that of the main portion 4A is further formed in the outer portion of the local portion 4A. It is also possible to provide such a part.
Further, in FIG. 1, the local portions 4B are formed on both sides in the direction in which the channel current flows. As will be described later, depending on the manufacturing method, it may be formed on both sides, and the local portion 4B may be provided on both sides in a positive sense. For example, binary (or multi-valued) data can be written in each of two locations at both ends of the channel current direction by writing a plurality of times with the source and drain being switched.

  In the memory transistor structure in the present embodiment, the hole injection range is narrowed at an appropriate position in relation to the electron injection range, and the potential barrier height from the substrate side of the hole is lowered, so that the injection efficiency is improved. As a result, the electrons can be neutralized in a short time, and the remaining of holes can be prevented, or the remaining amount of holes can be greatly reduced. Thereby, it is possible to effectively prevent the endurance characteristic and the retention characteristic from being lowered.

Next, an example of a manufacturing method for obtaining this structure will be described.
FIG. 2A to FIG. 4B are cross-sectional views during the manufacturing.
For example, when a P-well formed on an N-type semiconductor substrate is used as the semiconductor substrate 2 for forming the memory transistor, the P-well is formed so as to be surrounded by an element isolation insulating layer (not shown) and the N-type semiconductor substrate. After the threshold voltage is adjusted as necessary for the semiconductor substrate 2 (P well), the surface of the P well is thermally oxidized to form a silicon oxide (SiO ₂ ) film as shown in FIG. For example, 4C is formed to a thickness of about 2 to 10 nm. This SiO ₂ film 4C is a film that will later become the first potential barrier insulating film 4 of the MONOS type memory transistor 1 (see FIG. 1).

Next, as shown in FIG. 2B, a silicon nitride (SiN) film 5A of, eg, about 4 to 20 nm is deposited by CVD. Before depositing the silicon nitride film 5A, the surface of the SiO ₂ film 4C is subjected to nitrogen treatment in a CVD furnace, thereby improving the controllability during the formation of the silicon nitride film 5A and the unevenness of the surface of the silicon nitride film 5A. It is possible to use a technique for reducing This silicon nitride film 5A is a film that will later become the charge storage layer 5 of the MONOS memory transistor 1 (see FIG. 1).
Subsequently, by performing CVD or oxidizing the surface portion of the silicon nitride film 5A, a silicon oxide (SiO ₂ ) film 6A having a thickness of about _{3 to 10} nm is formed as shown in FIG. This SiO ₂ film 6A is a film that will later become the second potential barrier insulating film 6 of the MONOS type memory transistor 1 (see FIG. 1).

A conductor film 7A serving as a gate electrode is deposited on the SiO ₂ film 6A serving as a _second potential barrier insulating film. Specific examples of the conductor film 7A include polysilicon containing impurities at a high concentration, or a film in which a silicide film containing a refractory metal such as tungsten (W) is stacked on the polysilicon. This conductor film 7A will later become the gate electrode 7 of the MONOS memory transistor 1 (see FIG. 1).

Next, by a photolithography process and a dry etching process, the conductor film 7A, the SiO ₂ film 6A serving as the second potential barrier insulating film, the SiN film 5A serving as the charge storage layer, and the SiO serving as the first potential barrier insulating film _{The two} films 4C are patterned to form the gate laminated film 3 as shown in FIG.

  Next, an N-type impurity is introduced into the surface portion of the semiconductor substrate 1 by ion implantation using the gate laminated film 3 (and an element isolation insulating layer not shown) as a self-aligned mask. The impurity introduced portions become the two source / drain regions 8 and 9 shown in FIG. 3B after the activation annealing.

Next, a protective film 10 made of a silicon oxide (SiO ₂ ) film of about 50 to 200 nm, for example, is deposited by CVD. At this time, a condition with relatively poor step coverage is selected, and as shown in FIG. 4A, the CVD deposited film (at the bottom of the step of the gate laminated film 3, that is, near the boundary where the gate laminated film 3 and the semiconductor substrate 2 are in contact). The protective film 10) is made thinnest.
Next, wet etching using, for example, a hydrofluoric acid (HF) etchant is performed to remove a certain amount of the protective film 10 from the surface. The amount of isotropic etching at this time is determined to be optimum according to the degree of step coverage of the protective film 10. Thus, in the state after etching, at least the surface of the gate electrode 7 and the end surface of the second potential barrier insulating film 6 in the gate laminated film 3 are covered with the protective film 10, and the first potential barrier insulating film and The end face of the resulting SiO ₂ film 4C is exposed.

Thereafter, thermal nitridation is performed from the exposed end face of the SiO ₂ film 4C. As the thermal nitridation process at this time, it is desirable to perform a short-term thermal nitridation (RTN) process at 1000 ° C. for about 30 seconds in an atmosphere containing ammonia (NH ₃ ), for example. As a result, as shown in FIG. 4B, local portions 4B made of silicon nitride are formed at both ends of the SiO ₂ film 4C, whereby the first potential barrier insulating film 4 has its two local portions 4B. , The composition changes with the main part 4A, which is the region between them.
Note that the size of the local 4B in the channel current direction is controlled and optimized by the conditions of the nitriding treatment. Further, when it is desired to form a region made of SiO ₂ at the end of the first potential barrier insulating film, it is preferable to oxidize a part of the SiN portion formed thereby after nitriding. Further, in the case where the local portion 4B is formed only on one side, a step of forming a second protective film that covers only the source side between the step shown in FIG. 4A and the step shown in FIG. It is good to add.

Thereafter, deposition of an interlayer insulating film and formation of electrodes (formation of contacts and common wiring) are performed to complete a MONOS type memory transistor.
By the manufacturing method as described above, the MONOS type memory transistor having various advantages shown in FIG. 1 can be easily realized by adding a simple process.

[Second Embodiment]
The present embodiment relates to a data rewrite procedure (charge injection method) including a charge rearrangement step and a nonvolatile semiconductor memory device having an additional configuration necessary for the data rewrite procedure.
This nonvolatile semiconductor memory device includes a heating electrode that heats when a current flows in the vicinity of the charge storage layer 5 shown in FIG. 1, and a circuit for applying a voltage to the heating electrode to flow a current is provided in the memory cell array. The difference from the first embodiment is that it is provided in the peripheral circuit. This heating electrode may be provided separately from the gate electrode 7, but it is desirable to use the gate electrode 7 also as the heating electrode in order to simplify the manufacturing process. The preferred embodiment will be described below.
Since the gate electrode 7 is also used as the heating electrode, the base memory transistor structure itself is the same as that in FIG. 1, and FIG. 1 can be applied to this embodiment as it is. Alternatively, the first potential barrier insulating film 4 may have a normal MONOS type memory transistor structure in which the local portion 4B having a different composition is not provided. Furthermore, the data rewriting procedure (charge injection method) of this embodiment and the configuration necessary for this can be applied to trap gate types (for example, MNOS type and fine particle type) other than the MONOS type.

FIG. 5 is a flowchart showing a data rewriting procedure.
When the peripheral circuit receives a data rewrite instruction, in step ST1, the voltage value supplied to the memory cell array and the supply destination are controlled to inject the first charge (electrons or holes). In the subsequent step ST2, the second charge (electrons or holes) is injected by controlling the voltage value supplied to the memory cell array by the peripheral circuit and the supply destination. When the first charge is an electron and the second charge is a hole, the charge is opposite in polarity to the first charge and the second charge, and there are two cases where the first charge is a hole and the second charge is an electron. In the following description, it is assumed that the same charge injection method as that of the first embodiment in which data is written by injecting electrons as the first charge and data is erased by injecting holes as the second charge. Since the specific voltage application method and charge injection mechanism have already been described in the first embodiment, description thereof is omitted here.

Next, in step ST3, heat treatment is performed for charge rearrangement. FIG. 6 illustrates a part of a peripheral circuit including a configuration for supplying a voltage to the heating electrode.
As shown in FIG. 6, the memory cell array 20 includes a large number of memory cells including the memory transistors 1 arranged in a matrix, and has n word lines WL1 to WLn as common lines in the row direction. The word lines WL1 to WLn may be an upper wiring layer that connects the isolated word electrodes 7 in common. Usually, however, the gate electrode 7 is formed as a long wiring in the row direction, and this is connected to the word lines WL1 to WLn. Used as WLn. Note that it is more desirable to use the gate electrode 7 as it is as the word lines WL1 to WLn as described above, because the heating efficiency is high when the gate electrodes 7 function as heating electrodes.

The peripheral circuit 23 includes a first voltage supply circuit 21 and a second voltage supply circuit 22.
The first voltage supply circuit 21 sequentially selects the necessary word lines WL1 to WLn during normal data writing and erasing operations corresponding to steps ST1 and ST2 shown in FIG. 5, and is necessary for the selected word line. This is a circuit for supplying a gate operating voltage of a value, and is provided here as a function of a row decoder that receives and decodes an address signal ADR.

  The second voltage supply circuit 22 is connected to the word line end opposite to the first voltage supply circuit 21 and has two functions. The first function is to allow the first voltage supply circuit 21 to apply different operating voltages to different word lines by making the word line ends electrically open during normal data write and erase operations. It is a function. In the second function, in step ST3 shown in FIG. 5, the word line to be heated is selected in cooperation with the first voltage supply circuit 21, and a predetermined value is applied to one end and the other end of the selected word line. This is a function of applying a heating voltage. Therefore, the second voltage supply circuit 22 also needs a function of a row decoder, so that the address signal ADR can be input to the second voltage supply circuit 22.

The heating voltage may be applied to all the word lines of the memory cell array 20 all at once, or may be performed for each block constituting the memory cell array 20.
Moreover, the structure which supplies heating voltage itself from the external terminal of a non-volatile memory may be sufficient.

In general, when a resistor is energized, the resistor generates heat somewhat due to Joule heat, but the amount of heat generated q [J / s] is determined by the equation q = I ² · R (I: current flowing through the resistor [A ], R: resistance value [Ω] of the resistor. Further, the temperature rise ΔT (° C.) of the resistor when heat dissipation and heat conduction are not taken into account can be obtained by the equation ΔT = (ρ · C · V · t) / q. Here, “ρ” is the density [kg / m ³ ] of the resistor, “C” is the specific heat [J / kg · K] of the resistor, “V” is the volume [m ³ ] of the resistor, and “t”. Represents energization time.

In step ST3, depending on the distribution of electrons and the distribution of holes in the charge storage layer 5 and the degree of deviation of the distribution center, for example, the charge storage layer 5 is heated at a temperature of about 300 to 600 ° C. for 1 ms to Heat for about 100 seconds.
In order to raise the charge storage layer 5 to a temperature of about 300 to 600 ° C., for example, the word lines WL1 to WLn are made of polysilicon having a thickness of 400 nm as an example on the assumption that heat dissipation and heat conduction are not considered. When the required length is 0.5 mm, the width needs to be 0.5 to 1.5 μm. This width is a realistic value, and it can be seen that heating using a word line is possible. When the word line material is tungsten silicon (WSi), the length is 1.0 mm, and the thickness is 300 nm, the width required to obtain the heating temperature is 0.2 to 1.0 μm. When the word line material is cobalt silicon (CoSi), the length is 2.0 mm, and the thickness is 300 nm, the width necessary for obtaining the heating temperature is 0.1 to 0.7 μm. Become.

  When the charge diffusion rates in the charge storage layer (nitride film) 5 are compared, the hole diffusion rate is faster than the electron diffusion rate. Of course, electrons also diffuse, but in this case, the diffusion rate of holes is faster than that of electrons. Therefore, when heated at a certain high temperature for a predetermined time or more, the electrons can be completely neutralized by the holes.

FIG. 7A and FIG. 7B schematically show how carriers are neutralized by heating.
In the state before heating, it is assumed that the electron distribution region and the hole distribution region partially overlap in the charge storage layer 5 as shown in FIG. In terms of the carrier concentration Nc, the portion where the distribution regions overlap is neutralized with the carrier concentration Nc being almost zero. For this reason, there are two concentration distributions as the carrier concentration Nc.
This is as shown in FIG. 7B after heating. Although each carrier distribution region is expanded by diffusion, since the diffusion rate of holes is high, finally, almost all electrons are neutralized by holes, and a state where the carrier concentration Nc is almost zero can be achieved.

According to the present embodiment, it is possible to rearrange charges by heating, and as a result, it is possible to realize a thermal equilibrium state as a charge amount in which the charge amount of either electrons or holes becomes zero. Since the amount of charges of electrons and holes can be controlled to be almost the same depending on the bias application conditions at the time of writing and erasing, when this is combined with the rearrangement of charges by heating, the amount of accumulated charges after data rewriting is almost the same. It is possible to always fix the zero state. As a result, there is an advantage that the phenomenon in which one charge gradually accumulates during data rewriting and the endurance characteristic and the tension characteristic deteriorate can be effectively prevented.
Further, since the data rewrite operation can be performed stably, it is not necessary to take an extra voltage margin during the read operation, and an injection charge amount sufficient to obtain a threshold voltage difference (window width) necessary for the read operation is sufficient. For this reason, in this embodiment, there is an advantage that the memory transistor can be easily reduced in voltage and miniaturized.

1 is a schematic cross-sectional structure diagram of a MONOS memory transistor according to a first embodiment of the present invention. It is sectional drawing in the middle of manufacture of the MONOS memory transistor concerning 1st Embodiment, and shows to deposition of the conductive pair film | membrane used as a gate electrode. FIG. 3 is a cross-sectional view showing a process up to formation of a source / drain region in the process following FIG. 2. FIG. 4 is a cross-sectional view showing the process up to local nitriding of the first potential barrier insulating film in the process following FIG. 3. In the 2nd Embodiment of this invention, it is a flowchart which shows the procedure of the data rewriting which applied the charge injection method. It is a block diagram which shows the structure for the heating of the non-volatile semiconductor memory device concerning the 2nd Embodiment of this invention. In the 2nd Embodiment of this invention, it is a figure which shows typically a mode that a carrier is neutralized by heating.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Memory transistor, 2 ... Semiconductor substrate, 3 ... Gate laminated film, 4 ... 1st electric potential barrier insulating film, 4A ... Main part, 4B ... Local part, 5 ... Charge storage layer, 6 ... 2nd electric potential barrier insulating film , 7 ... Gate electrodes, 8 and 9 ... Source / drain regions, 10 ... Protective film, 20 ... Memory cell array, 21 ... First voltage supply circuit, 22 ... Second voltage supply circuit, 23 ... Peripheral circuit

Claims (9)

A gate laminated film including a charge storage layer formed on the first conductive type semiconductor substrate, and two source / drain regions of the second conductive type formed on the semiconductor substrate on both ends of the gate laminated film in one direction; A non-volatile semiconductor memory device comprising:
The gate laminated film includes a potential barrier insulating film interposed between the charge storage layer and the semiconductor substrate,
The non-volatile semiconductor memory device, wherein the potential barrier insulating film has a composition in which a local portion located in a certain range in the separation direction of the two source / drain regions is different from the composition of other portions. The nonvolatile semiconductor memory device according to claim 1, wherein the local portion of the potential barrier insulating film has a composition in which a ratio of nitrogen is higher than a portion of the potential barrier insulating film other than the local portion. A local portion of the potential barrier insulating film is formed on at least one side of the two source / drain regions;
The nonvolatile semiconductor memory device according to claim 1, wherein at least a part of a local portion of the potential barrier insulating film overlaps with the source / drain region on the planar pattern. A heating electrode formed in the vicinity of the charge storage layer;
Voltage application means for applying a voltage to the heating electrode to heat the charge storage layer;
The nonvolatile semiconductor memory device according to claim 1, further comprising: A line-shaped gate electrode extending in a direction different from the separation direction of the two source / drain regions through the gate laminated film;
A first voltage supply circuit for supplying an operating voltage from one end of the gate electrode;
A second voltage supply circuit that electrically opens the other end of the gate voltage during operation and supplies a predetermined voltage from the other end of the gate voltage during heating;
The nonvolatile semiconductor memory device according to claim 1, further comprising: A non-volatile semiconductor memory device having a gate stacked film including a charge storage layer formed on a semiconductor substrate,
A heating electrode formed in the vicinity of the charge storage layer;
A non-volatile semiconductor memory device, comprising: voltage supply means for supplying a voltage between one end and the other end of the heating electrode and causing a current to flow through the heating electrode. A line-shaped gate electrode extending in a direction different from the separation direction of the two source / drain regions through the gate laminated film;
A first voltage supply circuit for supplying an operating voltage from one end of the gate electrode;
A second voltage supply circuit that electrically opens the other end of the gate voltage during operation and supplies a predetermined voltage from the other end of the gate voltage during heating;
The non-volatile semiconductor memory device according to claim 6. A gate laminated film including a charge storage layer formed on the first conductive type semiconductor substrate, and two source / drain regions of the second conductive type formed on the semiconductor substrate on both ends of the gate laminated film in one direction; A nonvolatile semiconductor memory device charge injection method for writing and erasing data by injecting charges of opposite polarity into a charge storage layer respectively for a memory transistor having
A writing step of writing data by inducing a first charge in one of the semiconductor substrate and the source / drain region and injecting the first charge into the charge storage layer;
An erasing step of erasing data by inducing a second charge having a polarity opposite to the first charge in the other of the semiconductor substrate and the source / drain region and injecting the second charge into the charge storage layer;
A method for injecting charge into a nonvolatile semiconductor memory device, comprising: a heating step in which a current is passed through a conductive layer in the vicinity of the charge storage layer to heat the charge storage layer and the charge stored in the charge storage layer is rearranged. The current storage layer is heated in the heating step by passing a current to a line-shaped gate electrode extending in a direction different from the separation direction of the two source / drain regions through the gate stacked film. Charge injection method for a nonvolatile semiconductor memory device.

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