JP2005268725A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor element in which adverse effects due to damage occurring during polishing or dry etching in a manufacturing process are eliminated, and a problem of difficulty in patterning by wet etching is solved, consequently reliability is improved. <P>SOLUTION: A p-side contact layer 21, a p-type clad layer 22, an active layer 30, n-type clad layer 41, and n-side contact layer 42 are stacked in this order on a side of one surface of a substrate 10 comprising p-type semiconductor. The p-side contact layer 21 is made as a layer to be processed having a surface 61 for recovering damage formed by wet etching after processing by dry etching. A p-side electrode 71 is provided on the damage recovery surface 61 of the p-side contact layer 21. The adverse effects due to damage occurring during dry etching is prevented, and conduction between the p-side contact layer 21 and the p-side electrode 71 is improved, consequently reliability is improved. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device using a nitride III-V compound semiconductor and a method for manufacturing the same.

  Nitride III-V group compound semiconductors such as GaN, AlGaN mixed crystal or GaInN mixed crystal are direct transition semiconductor materials and have a feature that the forbidden band width ranges from 0.8 to 6.2 eV. Yes. Therefore, these nitride-based III-V group compound semiconductors can obtain light emission from the ultraviolet region to the infrared region, and have been put into practical use as materials constituting semiconductor light emitting devices such as semiconductor lasers or light emitting diodes. . Nitride III-V compound semiconductors are also attracting attention as materials constituting electronic devices such as field effect transistors and high-frequency transistors at high electric fields and high temperatures because of their high saturation electron velocity and high breakdown electric field.

Nitride III-V compound semiconductors are generally chemically stable materials. Therefore, processing by wet etching is often difficult as compared with other semiconductor materials. For example, in the case of an elemental semiconductor such as silicon (Si) or germanium (Ge), an arsenic compound semiconductor such as GaAs, a phosphorus compound semiconductor such as InP, a selenium such as ZnSe or ZnS, or a sulfur compound semiconductor, near room temperature. Acids or alkalis have been developed which can obtain an appropriate etching rate, uniformity and selectivity. On the other hand, in the case of nitride III-V compound semiconductors, there is no suitable acid or alkali near room temperature, and reactivity using a chlorine-based gas such as chlorine (Cl ₂ ) or boron chloride (BCl ₃ ). Dry etching such as ion etching (RIE) has been mainly employed. Furthermore, physical etching such as ion milling using argon (Ar) or the like may be performed depending on the structure or purpose.

For example, as described in Patent Document 1, wet etching of a nitride-based III-V group compound semiconductor is also possible under specific conditions at a high temperature. For example, liquid phase etching using phosphoric acid (H ₃ PO ₄ ) or dephosphorized diphosphorus pentoxide (P ₂ O ₅ ) at a temperature of about 400 ° C. or 700 ° C. using hydrochloric acid (HCl). About vapor phase etching. Also, strong alkali such as potassium hydroxide (KOH) can be wet etched at high temperatures.
JP-A-9-330916

However, the wet etching method for nitride III-V compound semiconductors described in Patent Document 1 is difficult to control the etching rate, uniformity or reproducibility because the solution etc. is high temperature, and is special because of high temperature. Equipment is required. Furthermore, since a selection ratio with the mask material cannot be obtained, it is difficult to obtain an appropriate mask material. Although it is natural that a photoresist mask cannot be used at a temperature of 400 ° C. or higher, even a chemically stable oxide film mask such as silicon oxide (SiO ₂ ) is chemically stable. If the physical group III-V compound semiconductor is etched, etching may occur in the same manner, or side etching may occur in the mask. In addition, it is difficult to take the selectivity of the etching rate by the group 3B element. As described above, the wet etching method described in Patent Document 1 has a limit in patterning a step structure or the like.

  For alkalis such as potassium hydroxide, depending on the conditions, etching on the order of the outermost atomic layer is possible near room temperature. However, since this method can only perform a very small amount of etching, it is effective for surface treatment of the electrode contact surface and the like, but it is difficult to use for patterning.

  On the other hand, in dry etching or physical etching, there is a problem that damage occurs on the etched surface. Also, when the back side of the substrate is thinned by polishing or the like, the polished surface has been damaged. Such damage reaches the pn junction depending on the depth, which may damage the device.

  In particular, in the case of a p-type nitride-based III-V compound semiconductor, a portion damaged by polishing or dry etching becomes an n-type or high resistance layer, which makes it difficult to form an electrode. There were many. Also, for example, GaN-based materials are generally more difficult to obtain in p-type than in n-type. For this reason, the conventional GaN-based semiconductor laser has a structure in which an n-type semiconductor layer and a p-type semiconductor layer are sequentially formed from the substrate side on the substrate, and the outermost surface of crystal growth is the p-type semiconductor layer. ing.

  FIG. 25 shows an example of the manufacturing process of such a conventional semiconductor laser. First, as shown in FIG. 25A, an n-side contact layer 142, an n-type cladding layer 141, an active layer 130, a p-type cladding layer 122, and a p-side contact layer 121 are sequentially formed on a substrate 110 from the substrate 110 side. Form. Next, as shown in FIG. 25B, part of the p-side contact layer 121, the p-type cladding layer 122, the active layer 130, the n-type cladding layer 141, and the n-side contact layer 142 is selectively etched by dry etching. By removing, the n-side contact layer 142 is exposed. Subsequently, as shown in FIG. 25B, the p-type cladding layer 122 and the p-side contact layer 121 are selectively removed by dry etching to form a thin strip shape, thereby forming a ridge structure 150. . After that, an n-side electrode 172 is provided on the exposed surface of the n-side contact layer 142, and a p-side electrode 171 is provided on the upper surface of the protrusion structure 150. In this way, the portion of the p-side contact layer 121 where the p-side electrode 171 is provided can be prevented from being damaged by dry etching.

  However, in such a conventional structure, the resistivity of the GaN-based material is higher in the p-type than in the n-type. Therefore, when the width of the protrusion structure 150 or the width of the p-side electrode 171 is narrow, the influence on the increase of the operating voltage. There was a problem that would become larger.

That is, the carrier concentration of p-type GaN or AlGaN mixed crystal is Na≈1 × 10 ¹⁷ (cm ⁻³ ) to 1 × 10 ¹⁸ (cm ⁻³ ), and the p-side contact layer 142 and the p-side contact layer The contact resistance Rc with the p-side electrode 171 in contact with 142 having a palladium (Pd) layer or a nickel (Ni) layer is about 10 ⁻³ (Ωcm ⁻² ) to 10 ⁻⁴ (Ωcm ⁻² ) Alternatively, the resistivity is significantly higher than that of an InP-based p-side contact layer. Therefore, when the stripe width is as narrow as 1 μm to 2 μm, for example, the operating voltage may be about +1 V to +2 V due to the sheet resistance and contact resistance of the p-side contact layer 121.

  The present invention has been made in view of such problems, and its object is to solve the problem that patterning by wet etching is difficult while eliminating the adverse effects caused by damage that occurs during polishing or dry etching in the manufacturing process. An object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can improve reliability.

  The semiconductor device according to the present invention is formed of a nitride-based III-V group compound semiconductor including a substrate, at least one of group 3B elements and at least nitrogen (N) of group 5B elements, and is formed on the substrate. And a processed layer having a damage recovery surface formed by processing the substrate or the semiconductor layer by polishing or dry etching and then performing wet etching. Here, “dry etching” includes etching in which chemical etching and physical etching are combined, such as RIE, and physical etching such as ion milling, while “wet etching” refers to chemical etching in thermal equilibrium. And both gas phase etching that etches in gas and liquid phase etching that etches in liquid.

  The method of manufacturing a semiconductor device according to the present invention includes a semiconductor layer made of a nitride-based III-V compound semiconductor containing at least one of group 3B elements and at least nitrogen (N) of group 5B elements on a substrate. And a step of forming a layer to be processed having a damage recovery surface formed by processing a substrate or a semiconductor layer by polishing or dry etching and then performing wet etching.

  According to the semiconductor element of the present invention or the method of manufacturing a semiconductor element according to the present invention, after the substrate or the semiconductor layer is processed by polishing or dry etching, the damaged portion is removed by wet etching to remove the damaged surface. Since the layer to be processed is formed, an adverse effect due to damage caused by polishing or dry etching can be prevented, and the reliability of the element can be improved. In addition, the semiconductor layer can be satisfactorily patterned such as a step structure, and the problem that patterning by wet etching is difficult can be solved. Further, by performing wet etching after thinning the substrate by polishing, the film can be thinned in a shorter time than in the case of only wet etching.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(First embodiment)
FIG. 1 shows a cross-sectional configuration perpendicular to the cavity direction of the semiconductor laser according to the first embodiment of the present invention. This semiconductor laser has a p-type semiconductor layer 20, an active layer 30, and an n-type semiconductor layer 40 that are sequentially stacked from the substrate 10 side on one surface side of a substrate 10 made of a p-type semiconductor. The substrate 10, the p-type semiconductor layer 20, the active layer 30, and the n-type semiconductor layer 40 are composed of at least one of the 3B group elements in the short period type periodic table and the 5B group element in the short period type periodic table. Each is composed of a nitride III-V compound semiconductor containing at least nitrogen. Examples of the nitride III-V group compound semiconductor include GaN, InN, AlN, or a mixed crystal thereof, and a V group mixed crystal such as GaInNAs or GaInNP.

  The substrate 10 has a thickness of, for example, about 400 μm and is made of p-type GaN to which magnesium (Mg) is added as a p-type impurity.

  The p-type semiconductor layer 20 includes, for example, a p-side contact layer 21 and a p-type cladding layer 22 that are stacked in this order from the substrate 10 side. For example, the p-side contact layer 21 has a thickness of about 3 μm and is made of p-type GaN to which magnesium is added as a p-type impurity. The p-type cladding layer 22 has, for example, a thickness of about 600 nm and is composed of a p-type AlGaN mixed crystal to which magnesium is added as a p-type impurity.

The active layer 30 has, for example, a multiple quantum well structure in which Ga _x In _1-x N (where x ≧ 0) mixed crystal layers having different compositions are stacked with a thickness of about 3 nm.

  The n-type semiconductor layer 40 includes, for example, an n-type cladding layer 41 and an n-side contact layer 42 that are sequentially stacked from the active layer 30 side. The n-type cladding layer 41 has, for example, a thickness of about 600 nm and is composed of an n-type AlGaN mixed crystal to which silicon (Si) is added as an n-type impurity. For example, the n-side contact layer 42 has a thickness of about 200 nm and is made of n-type GaN to which silicon is added as an n-type impurity. Note that a part of the n-type cladding layer 41 and the n-side contact layer 42 have a protruding structure 50 extending in the direction of the resonator, and perform current confinement. The width of the protrusion structure 50 is, for example, 1 μm to several μm.

  In this semiconductor laser, the p-side contact layer 21 is a layer to be processed having a damage recovery surface 61 formed by performing dry etching and then performing wet etching, as will be described later. As a result, in this semiconductor laser, adverse effects due to damage generated in the p-side contact layer 21 by dry etching can be prevented, and the reliability can be improved.

  A p-side electrode 71 is formed on the damage recovery surface 61 formed on the p-side contact layer 21. The p-side electrode 71 has, for example, a layer made of palladium (Pd) or nickel (Ni) in the first layer, and is composed of palladium (Pd) / platinum (Pt) / gold (Au) or nickel (Ni) / It has a structure in which platinum (Pt) / gold (Au) is laminated in this order from the p-side contact layer 21 side. Note that the platinum (Pt) layer is not necessarily included and can be omitted.

  An n-side electrode 72 is formed on the upper surface of the protrusion structure 50 in the n-side contact layer 42. The n-side electrode 72 has, for example, a layer made of titanium (Ti) as a first layer, and titanium (Ti) / platinum (Pt) / gold (Au) are stacked in this order from the n-side contact layer 42 side. It has a structure. Note that the platinum (Pt) layer is not necessarily included and can be omitted.

  Further, in this semiconductor laser, a pair of side surfaces facing each other in the direction of the resonator is a resonator end surface, and a pair of reflecting mirror films (not shown) are formed on the pair of resonator end surfaces. The reflectance is adjusted so that one of the pair of reflecting mirror films has a low reflectance and the other has a high reflectance. Thereby, the light generated in the active layer 30 is amplified by reciprocating between the pair of reflecting mirror films, and is emitted as a laser beam from the reflecting mirror film having a low reflectance.

  This semiconductor laser can be manufactured, for example, as follows. Here, a case where a plurality of semiconductor lasers are manufactured will be described as an example.

  2 and 3 show the manufacturing process for one semiconductor laser forming region. First, for example, a substrate 10 having a plurality of semiconductor laser forming regions and made of a p-type semiconductor such as p-type GaN is prepared. Next, as shown in FIG. 2A, the p-side contact layer 21 made of p-type GaN, p-type is formed on the substrate 10 by, for example, MOCVD (Metal Organic Chemical Vapor Deposition). A p-type cladding layer 22 made of AlGaN mixed crystal, an active layer 30 made of GaInN mixed crystal, an n-type cladding layer 41 made of n-type AlGaN mixed crystal, and an n-side contact layer 42 made of n-type GaN are successively grown.

  Subsequently, as shown in FIG. 2B, a periodic stripe-like pattern made of an insulating material such as silicon dioxide or a photoresist is formed on the n-side contact layer 42 by using, for example, vapor deposition or sputtering. A mask 81 is formed. At this time, for example, when the width of the semiconductor laser is 400 μm, the mask 81 is formed with a width of 200 μm and an interval (pitch) of 400 μm.

  Thereafter, as shown in FIG. 2C, by using this mask 81, for example, an etching amount of about 1 μm to 3 μm by dry etching such as RIE using a chlorine-based gas such as chlorine or boron chloride. The n-side contact layer 42, the n-type cladding layer 41, the active layer 30, the p-type cladding layer 22 and part of the p-side contact layer 21 are selectively removed to expose the p-side contact layer 21 on the surface. Let At this time, the exposed surface of the p-side contact layer 21 is damaged by dry etching to form an n-type or high-resistance damage layer 82. After that, the mask 81 is removed as shown in FIG.

  After removing the mask 81, wet etching is performed as shown in FIG. Thereby, the damage layer 82 is removed, and a damage recovery surface 61 is formed on the surface of the p-side contact layer 21. At this time, as the wet etching method, for example, liquid phase etching at about 350 ° C. to 400 ° C. using phosphoric acid or gas phase etching at about 700 ° C. using hydrochloric acid can be used.

  The amount of wet etching is preferably 0.01 μm or more, for example. For example, the damage layer 82 cannot be completely removed by modifying the surface state, such as etching performed at about room temperature using potassium hydroxide, or by etching in the atomic layer order where the etching amount is, for example, 1 nm or less. is there. Furthermore, if the etching amount is set to 0.1 μm or more, for example, the damaged layer 82 can be completely removed, which is more preferable. The etching amount can be controlled by controlling the solution concentration, temperature, immersion time, and the like.

  If the etching amount by wet etching is set to several μm, for example, the position of the step formed by dry etching may be similarly shifted by about several μm. However, in the process shown in FIG. 3B, a fine structure such as the ridge structure 50 (see FIG. 1) has not yet been formed, and the distance between the planned formation position of the ridge structure 50 and the level difference. Since the distance W0 in FIG. 1 is as large as, for example, about 10 μm to 50 μm, a deviation of about several μm due to wet etching is allowed.

  Further, since the thickness of the n-side contact layer 42 is also reduced by wet etching, if the n-side contact layer 42 is formed thicker in the step shown in FIG. An electrical connection can be made satisfactorily.

  After the damage recovery surface 61 is formed on the p-side contact layer 21 by wet etching, as shown in FIG. 3C, for example, a stripe-like structure made of silicon dioxide is formed on the n-side contact layer 42 by using a vapor deposition method. A mask (not shown) is formed. Next, using this mask, a part of the n-side contact layer 42 and the n-type cladding layer 41 is selectively etched to make the upper part of the n-type cladding layer 41 and the n-side contact layer 42 into a thin strip shape, thereby forming a ridge structure. 50 is formed.

  The etching process for forming the protrusion structure 50 is preferably performed in a process different from the wet etching for removing the damaged layer 82 and forming the damage recovery surface 61. In addition, as an etching method for forming the protrusion structure 50, a method capable of performing fine patterning, that is, patterning requiring an accuracy of about 0.1 μm to several μm, is used instead of using wet etching. More specifically, for example, dry etching such as RIE is preferably used.

  After the protrusion structure 50 is formed, a layer made of, for example, palladium (Pd) or nickel (Ni) is formed on the damage recovery surface 61 formed on the p-side contact layer 21 as shown in FIG. A p-side electrode 71 is formed. Specifically, palladium (Pd) / platinum (Pt) / gold (Au) or nickel (Ni) / platinum (Pt) / gold (Au) is applied to the damage recovery surface 61 formed on the p-side contact layer 21. ) Are sequentially deposited to form the p-side electrode 71. Note that the platinum (Pt) layer may be omitted. Further, an n-side electrode 72 having a layer made of, for example, titanium (Ti) as the first layer is formed on the upper surface of the protrusion structure 50 in the n-side contact layer 42. Specifically, for example, titanium (Ti) / platinum (Pt) / gold (Au) is sequentially deposited on the upper surface of the protrusion structure 50 to form the n-side electrode 72. Note that the platinum (Pt) layer may be omitted.

  After forming the n-side electrode 72, the substrate 10 is thinned by polishing. Then, it divides perpendicularly to the resonator direction. Thereby, a pair of resonator end faces are formed. Thereafter, a reflecting mirror film (not shown) is formed on each end face of the resonator. Further, it is divided in parallel with the cavity direction so as to correspond to the formation region of each semiconductor laser. Thus, a plurality of semiconductor lasers shown in FIG. 1 are completed.

  In this semiconductor laser, when a predetermined voltage is applied between the n-side electrode 72 and the p-side electrode 71, a current is injected into the active layer 30, and light emission occurs due to electron-hole recombination. This light is reflected by a reflecting mirror film (not shown), reciprocates between them to cause laser oscillation, and is emitted to the outside as a laser beam. Here, the damage layer 82 generated by processing the p-side contact layer 21 by dry etching is removed by wet etching to form a damage recovery surface 61, and the p-side electrode 71 is formed on the damage recovery surface 61. Since it is provided, adverse effects due to the damage layer 82 are prevented, and the conductivity between the p-side contact layer 21 and the p-side electrode 71 is increased. Therefore, reliability is improved.

  Further, in this semiconductor laser, since the protrusion structure 50 is provided in the n-type semiconductor layer 40 whose resistivity or contact resistance with the electrode is lower than that of the p-type semiconductor layer 20, the width of the protrusion structure 50 is 1 μm. Even if it is as narrow as 2 μm, the influence on the increase in operating voltage is suppressed. Furthermore, since the contact area between the p-side contact layer 21 and the p-side electrode 71 is wider than that in the conventional structure shown in FIG. 25, the influence on the increase in operating voltage is reduced even if the contact resistance is slightly higher. Therefore, the operating voltage is lowered.

  In contrast, for example, in the conventional structure shown in FIG. 25, the narrow protrusion structure 50 is provided on the p-side contact layer 121 and the p-type cladding layer 122 having a high resistivity or contact resistance with the electrode. In addition, since the p-side electrode 171 and the p-side contact layer 121 are in contact with each other in a small area, the operating voltage is extremely high.

  As described above, in this embodiment, after the n-type semiconductor layer 40, the active layer 30 and the p-type semiconductor layer 20 are processed by dry etching, the damaged layer 82 generated in the p-side contact layer 21 is removed by wet etching. Thus, the damage recovery surface 61 is formed, and the p-side electrode 71 is provided on the damage recovery surface 61, so that the adverse effect of the damage layer 82 can be prevented and the reliability of the element can be improved. Further, it is possible to satisfactorily perform patterning such as a step structure on the n-type semiconductor layer 40, the active layer 30, and the p-type semiconductor layer 20 by dry etching, and solve the problem that patterning by wet etching is difficult. Can do.

  Furthermore, since the protrusion structure 50 can be provided in the n-type semiconductor layer 40 whose resistivity or contact resistance with the electrode is lower than that of the p-type semiconductor layer 20, the width of the protrusion structure 50 is as narrow as 1 μm to 2 μm. However, the influence on the increase in operating voltage can be suppressed. In addition, since the contact area between the p-side contact layer 21 and the p-side electrode 71 can be made wider than that in the conventional structure, the influence on the increase in operating voltage can be reduced even if the contact resistance is slightly increased. . Therefore, the operating voltage can be lowered.

  2 and 3 show the case where the p-side contact layer 21 is exposed on the surface during dry etching. However, the p-type cladding layer 22 is exposed on the surface by dry etching, and the p-side contact is exposed by wet etching. The layer 21 may be exposed on the surface.

  3A and 3B, the entire surface of the substrate 10, the n-side contact layer 21 and the n-side contact layer 42 is selectively etched all over the entire surface after the mask 81 is removed. Although shown, if necessary, wet etching without fine patterning may be performed. Here, “wet etching without fine patterning” refers to wet etching without patterning accuracy of 1 μm or less, for example.

(Modification of the first embodiment)
FIG. 4 shows a configuration of a semiconductor laser according to a modification of the first embodiment. In this semiconductor laser, a GaInN contact layer 21A made of a GaInN mixed crystal is formed on a part of the p-side contact layer 21, and a p-side electrode 71 is formed on a damage recovery surface 61 formed on the GaInN contact layer 21A. The semiconductor laser is the same as that of the first embodiment except that it is provided. Accordingly, the corresponding components will be described with the same reference numerals.

  In this semiconductor laser, the continuity between the GaInN contact layer 21A and the p-side electrode 71 can be improved by configuring the GaInN contact layer 21A with a GaInN mixed crystal having a band gap smaller than that of GaN. Yes. Magnesium (Mg) may be added to the GaInN mixed crystal constituting the GaInN contact layer 21A. Further, the GaInN mixed crystal constituting the GaInN contact layer 21A is more preferable if the indium composition exceeds 10% of the nitrogen composition because the band gap can be reduced and the resistivity can be lowered. However, since the crystal quality deteriorates if the indium composition is too high, it is desirable not to make it too high.

  This semiconductor laser can be manufactured, for example, in the same manner as in the first embodiment. The operation of this semiconductor laser is the same as that of the first embodiment.

  As described above, in this modification, the p-side electrode 71 is provided on the damage recovery surface 61 formed on the GaInN contact layer 21A made of GaInN mixed crystal, so that the conduction between the GaInN contact layer 21A and the p-side electrode 71 is established. Can be improved.

(Second Embodiment)
FIG. 5 shows a configuration of a semiconductor laser according to the second embodiment of the present invention. This semiconductor laser is the same as the semiconductor laser of the first embodiment, except that the p-side electrode 71 is provided on the damage recovery surface 61 formed on the back side of the substrate 10. Accordingly, the corresponding components will be described with the same reference numerals.

  In this semiconductor laser, as will be described later, the substrate 10 is a layer to be processed having a damage recovery surface 61 formed by performing wet etching after processing by polishing. As a result, in this semiconductor laser, adverse effects due to the damaged layer 82 generated on the back side of the substrate 10 due to polishing can be prevented, the conductivity between the substrate 10 and the p-side electrode 71 can be improved, and the reliability of the element can be improved. It is like that.

  This semiconductor laser can be manufactured, for example, as follows. Here, a case where a plurality of semiconductor lasers are manufactured will be described as an example.

  FIG. 6 shows the manufacturing process for one semiconductor laser forming region. First, as shown in FIG. 6A, the p-side contact layer 21, the p-type cladding layer 22, the active layer 30, the n-type cladding layer 41, and the n-side contact layer 42 are formed on the substrate 10 by MOCVD, for example. Grow sequentially.

  Next, as shown in FIG. 6B, the back side of the substrate 10 is polished to form a thin film. At this time, a damage layer 82 is formed on the back side of the substrate 10 due to mechanical damage due to polishing.

  Subsequently, as shown in FIG. 6C, wet etching is performed in the same manner as in the first embodiment. Thereby, the damage layer 82 is removed, and a damage recovery surface 61 is formed on the back side of the substrate 10.

  After that, as shown in FIG. 5, the ridge structure 50 is formed in the same manner as in the first embodiment, and the p-side electrode 71 is formed on the damage recovery surface 61 formed on the back side of the substrate 10, An n-side electrode 72 is formed on the upper surface of the protrusion structure 50. After the n-side electrode 72 is formed, the n-side electrode 72 is divided perpendicularly to the resonator direction to form a pair of resonator end faces, and a reflecting mirror film (not shown) is formed on each resonator end face. Further, it is divided in parallel with the cavity direction so as to correspond to the formation region of each semiconductor laser. Thus, a plurality of semiconductor lasers shown in FIG. 5 are completed.

  Moreover, this semiconductor laser can also be manufactured as follows.

  6A, the p-side contact layer 21, the p-type cladding layer 22, the active layer 30, the n-type cladding layer 41, and the n-side contact layer 42 are formed on the substrate 10 by MOCVD, for example. Grow sequentially.

  Next, the back side of the substrate 10 is polished and thinned by the process shown in FIG. At this time, a damage layer 82 is formed on the back side of the substrate 10 due to mechanical damage due to polishing.

  Subsequently, as illustrated in FIG. 7A, the protrusion structure 50 is formed in the same manner as in the first embodiment, and the n-side electrode 72 is formed on the upper surface of the protrusion structure 50.

  After that, as shown in FIG. 7B, a protective film 83 made of, for example, silicon dioxide or silicon nitride (SiN) and having a thickness of about several μm is formed on the entire front surface of the substrate 10. Wet etching is performed in the same manner as the embodiment. Thereby, the damage layer 82 is removed, and a damage recovery surface 61 is formed on the back side of the substrate 10. At this time, since the protective film 83 is provided on the entire front surface of the substrate 10, almost all regions except the edge of the substrate 10 are protected without being eroded by wet etching.

After the damage recovery surface 61 is formed on the back side of the substrate 10, the protective film 83 is removed by dry etching using a fluorine-based gas such as CF ₄ or SF ₆ .

  After removing the protective film 83, it is divided perpendicularly to the resonator direction to form a pair of resonator end faces, and a reflecting mirror film (not shown) is formed on the resonator end faces. Further, it is divided in parallel with the cavity direction so as to correspond to the formation region of each semiconductor laser. Thus, a plurality of semiconductor lasers shown in FIG. 5 are completed.

  The operation of this semiconductor laser is the same as that of the first embodiment.

  As described above, in this embodiment, after the back side of the substrate 10 is processed by polishing, the damage recovery surface 61 is formed by removing the damage layer 82 generated on the back side of the substrate 10 by wet etching. Since the p-side electrode 71 is provided on 61, the adverse effect of the damaged layer 82 can be prevented, and the reliability of the element can be improved. Further, by performing wet etching after thinning the substrate 10 by polishing, the thinning can be performed in a shorter time than in the case of only wet etching.

  In this embodiment, the case where the damaged layer 82 generated on the back side of the substrate 10 by polishing is removed by wet etching to form the damage recovery surface 61 is described. However, in this embodiment, physical damage such as polishing is described. The present invention is not limited to the damage layer 82 due to a general cause, but can be similarly applied to dirt or a natural oxide film attached to the back side of the substrate 10 due to the thermal history in the crystal growth step shown in FIG. .

(Third embodiment)
FIG. 8 shows a configuration of a semiconductor laser according to the third embodiment of the present invention. This semiconductor laser is the same as the semiconductor laser of the first embodiment except that the damage recovery surfaces 61 are provided on both sides of the ridge structure 50. Accordingly, the corresponding components will be described with the same reference numerals. Moreover, the part which 1st Embodiment and a manufacturing process overlap is demonstrated with reference to FIG. 2 and FIG.

  In this semiconductor laser, the damage recovery surfaces 61 are provided on both sides of the protrusion structure 50, so that the current spread in the lateral direction can be reduced and an increase in reactive current that does not contribute to light emission can be suppressed. Yes.

  This semiconductor laser can be manufactured, for example, as follows. Here, a case where a plurality of semiconductor lasers are manufactured will be described as an example.

  First, by the process shown in FIG. 2A, the p-side contact layer 21, the p-type cladding layer 22, the active layer 30, the n-type cladding layer 41, and the n-side contact layer 42 are formed on the substrate 10 by MOCVD, for example. Grow sequentially.

  2B, a mask 81 is formed on the n-side contact layer 42 using, for example, a vapor deposition method or a sputtering method.

  Thereafter, the n-side contact layer 42, n-type is formed by dry etching such as RIE using a chlorine-based gas such as chlorine or boron chloride using the mask 81 by the process shown in FIG. The cladding layer 41, the active layer 30, the p-type cladding layer 22 and the p-side contact layer 21 are selectively removed to expose the p-side contact layer 21 on the surface. After that, the mask 81 is removed by the process shown in FIG.

  After removing the mask 81, wet etching is performed by the process shown in FIG. Thereby, the damage layer 82 is removed, and a damage recovery surface 61 is formed on the surface of the p-side contact layer 21.

  After the damage recovery surface 61 is formed on the p-side contact layer 21 by wet etching, the n-side contact layer 42 and a part of the n-type cladding layer 41 are selectively etched by the process shown in FIG. A ridge structure 50 is formed. At this time, as shown in FIG. 9A, damage layers 82 by dry etching are formed on both sides of the protrusion structure 50.

  Here, the thickness d (not including the thickness of the damaged layer 82) of the n-type cladding layer 41 on both sides of the ridge structure 50 is an optical characteristic such as a refractive index difference between the ridge structure 50 and other regions. In general, the thickness is made thicker, for example, d> 0.1 μm so that the damaged layer 82 does not reach the active layer 30. However, in the present embodiment, since the protrusion structure 50 is formed in the n-side contact layer 42 and the n-type cladding layer 41 having high mobility, the current injected from the n-side electrode 72 is applied to the n-type cladding layer. The reactive current that tends to spread in the horizontal direction within 41 and does not contribute to light emission may increase. Therefore, thicker d is not preferable from the viewpoint of current confinement.

  Further, since the damage layer 82 formed on the n-type clad layer 41 on both sides of the ridge structure 50 is an n + layer, current spreading in the lateral direction is further promoted, which may cause deterioration in device characteristics.

  For this reason, as shown in FIG. 9B, wet etching is performed with an etching amount of, for example, about 0.1 μm to 0.2 μm, as in the first embodiment. As a result, the damage layer 82 is removed, and damage recovery surfaces 61 are formed on both sides of the protrusion structure 50. Therefore, the current spread in the lateral direction can be reduced, and an increase in reactive current that does not contribute to light emission can be suppressed.

  The width of the protrusion structure 50 is about 1 μm to 3 μm, and the design error ΔW = ± 0.2 μm. Therefore, even if the width of the protrusion structure 50 is reduced by wet etching, the width is controlled within the range of the design error. Is possible. Alternatively, the width of the ridge structure 50 before the wet etching may be made wider in view of the wet etching amount.

  After the damage recovery surfaces 61 are formed on both sides of the protrusion structure 50, the p-side electrode 71 is formed on the damage recovery surface 61 formed on the p-side contact layer 21 in the same manner as in the first embodiment. An n-side electrode 72 is formed on the upper surface of the strip structure 50.

  After forming the n-side electrode 72, the substrate 10 is thinned by polishing. Then, it divides perpendicularly to the resonator direction. Thereby, a pair of resonator end faces are formed. Thereafter, a reflecting mirror film (not shown) is formed on each end face of the resonator. Further, it is divided in parallel with the cavity direction so as to correspond to the formation region of each semiconductor laser. Thus, a plurality of semiconductor lasers shown in FIG. 8 are completed.

  In this semiconductor laser, when a predetermined voltage is applied between the n-side electrode 72 and the p-side electrode 71, a current is injected into the active layer 30, and light emission occurs due to electron-hole recombination. This light is reflected by a reflecting mirror film (not shown), reciprocates between them to cause laser oscillation, and is emitted to the outside as a laser beam. Here, since the damage layer 82 generated on both sides of the ridge structure 50 is removed by wet etching to form the damage recovery surface 61, the lateral current spread is reduced, and the reactive current that does not contribute to light emission is reduced. The increase is suppressed. Therefore, reliability is improved.

  As described above, in this embodiment, the damage recovery surfaces 61 are formed on both sides of the protrusion structure 50, so that the current spread in the lateral direction can be reduced and the reliability of the element can be improved.

(Fourth embodiment)
FIG. 10 shows a configuration of a semiconductor laser according to the fourth embodiment of the present invention. This semiconductor laser is the same as the semiconductor laser of the first embodiment except that the damage layer 82 formed by processing by dry etching is provided on the upper surface of the protrusion structure 50. Accordingly, the corresponding components will be described with the same reference numerals. Moreover, the part which 1st Embodiment and a manufacturing process overlap is demonstrated with reference to FIG. 2 and FIG.

  In this semiconductor laser, a damage layer 82 that is intentionally n + formed by processing by dry etching is formed on the upper surface of the ridge structure 50, whereby the n-side contact layer 42 and the n-side electrode 72 are electrically connected. It has become possible to enhance the sex. Although the thickness of the damage layer 82 is not specifically limited, For example, it is 0.1 micrometer or less.

  This semiconductor laser can be manufactured, for example, as follows. Here, a case where a plurality of semiconductor lasers are manufactured will be described as an example.

  First, by the process shown in FIG. 2A, the p-side contact layer 21, the p-type cladding layer 22, the active layer 30, the n-type cladding layer 41, and the n-side contact layer 42 are formed on the substrate 10 by MOCVD, for example. Grow sequentially.

  2B, a mask 81 is formed on the n-side contact layer 42 using, for example, a vapor deposition method or a sputtering method.

  Thereafter, the n-side contact layer 42, n-type is formed by dry etching such as RIE using a chlorine-based gas such as chlorine or boron chloride using the mask 81 by the process shown in FIG. The cladding layer 41, the active layer 30, the p-type cladding layer 22 and the p-side contact layer 21 are selectively removed to expose the p-side contact layer 21 on the surface. After that, the mask 81 is removed by the process shown in FIG.

  After removing the mask 81, wet etching is performed by the process shown in FIG. Thereby, the damage layer 82 is removed, and a damage recovery surface 61 is formed on the surface of the p-side contact layer 21.

  After the damage recovery surface 61 is formed on the p-side contact layer 21 by wet etching, the n-side contact layer 42 and a part of the n-type cladding layer 41 are selectively etched by the process shown in FIG. A ridge structure 50 is formed.

  After forming the ridge structure 50, as shown in FIG. 11, the damage layer 82 is formed on the upper surface of the ridge structure 50 by dry etching.

  After the damage layer 82 is formed on the upper surface of the ridge structure 50, as shown in FIG. 10, the damage recovery surface 61 formed on the p-side contact layer 21 is formed on the p-side as in the first embodiment. An electrode 71 is formed. Similarly, as shown in FIG. 10, the n-side electrode 72 is formed on the damage layer 82 formed on the upper surface of the protrusion structure 50 in the same manner as in the first embodiment.

  After forming the n-side electrode 72, the substrate 10 is thinned by polishing. Then, it divides perpendicularly to the resonator direction. Thereby, a pair of resonator end faces are formed. Thereafter, a reflecting mirror film (not shown) is formed on each end face of the resonator. Further, it is divided in parallel with the cavity direction so as to correspond to the formation region of each semiconductor laser. Thus, a plurality of semiconductor lasers shown in FIG. 10 are completed.

  The operation of this semiconductor laser is the same as that of the first embodiment.

  Thus, in this embodiment, since the damaged layer 82 is formed on the upper surface of the protrusion structure 50 by dry etching, the conductivity between the n-side contact layer 42 and the n-side electrode 72 is improved. Can be increased.

(Modification of the fourth embodiment)
FIG. 12 is an enlarged view of the configuration of the protrusion structure of the semiconductor laser according to the modification of the fourth embodiment of the present invention. This semiconductor laser is the same as the semiconductor laser of the fourth embodiment, except that the damage layer 82 formed on the upper surface of the protrusion structure 50 has an uneven structure 82A on the surface. Accordingly, the corresponding components will be described with the same reference numerals. Moreover, the part which 1st Embodiment and a manufacturing process overlap is demonstrated with reference to FIG. 2 and FIG.

  In this semiconductor laser, the damage layer 82 formed on the upper surface of the ridge structure 50 has the concavo-convex structure 82A, so that the contact area between the n-side contact layer 42 and the n-side electrode 72 is increased and the conductivity is further improved. In addition, the adhesion between the n-side contact layer 42 and the n-side electrode 72 can be improved.

  This semiconductor laser can be manufactured in the same manner as in the fourth embodiment. Further, the concavo-convex structure 82A of the damage layer 82 can be easily formed by using a mask when the upper surface of the protrusion structure 50 is processed by dry etching.

  The operation of this semiconductor laser is the same as that of the first embodiment.

  As described above, in this modification, since the uneven structure 82A is provided on the surface of the damage layer 82 formed on the upper surface of the protrusion structure 50, the conductivity between the n-side contact layer 42 and the n-side electrode 72 and Adhesion can be further increased.

(Fifth embodiment)
FIG. 13 shows a configuration of a field effect transistor according to a modification of the fifth embodiment of the present invention. This field effect transistor has a thickness of about 430 μm, for example, and a channel layer 212 and a gate insulating film 213 are formed on a c-plane of a substrate 210 made of sapphire (Al ₂ O ₃ ) as an insulator via a buffer layer 211. It has the structure laminated | stacked in order.

  The buffer layer 211 has a thickness of, for example, about 2 μm and is made of high-resistance intrinsic GaN. The buffer layer 211 may be made of GaN having a conductivity type different from that of the channel layer 212. The channel layer 212 has a thickness of about 500 nm, for example, and is an electron conductive layer made of n-type GaN to which silicon is added as an n-type impurity, or a hole conductive layer made of p-type Gan to which magnesium is added as a p-type impurity. It is. The gate insulating film 213 is, for example, a semiconductor insulating layer or a high resistance layer having a thickness of about 100 nm and made of aluminum nitride (AlN).

  On the gate insulating film 213, the source electrode 271 electrically connected to the channel layer 213 through the opening 213 A of the gate insulating film 213 and the channel layer 213 through the opening 213 B of the gate insulating film 213 are electrically connected. And a drain electrode 272 connected to each other. A gate electrode 273 is provided between the source electrode 271 and the drain electrode 272. The source electrode 271 and the drain electrode 272 have, for example, a layer made of titanium (Ti) in the first layer, and titanium (Ti) / aluminum (Al) / gold (Au) are stacked in this order from the channel layer 212 side. Have a structure. The gate electrode 273 is made of, for example, platinum (Pt).

  In this field effect transistor, the channel layer 212 has a damage recovery surface 61 formed by performing dry etching and then performing wet etching as in the first embodiment, as will be described later. It is a layer. Accordingly, in this field effect transistor, adverse effects due to damage generated in the channel layer 212 due to dry etching can be prevented, and the electrical continuity between the channel layer 212 and the source electrode 271 and the drain electrode 272 can be improved and the reliability can be improved. It can be done.

  This field effect transistor can be manufactured, for example, as follows.

  First, as shown in FIG. 14A, a substrate 210 made of sapphire is prepared, and the buffer layer 211, the channel layer 212 made of the above-described thickness and material are formed on the c-plane of the substrate 210, for example, by MOCVD. A gate insulating film 213 is formed.

  Next, as shown in FIG. 14B, the gate insulating film 213 is selectively removed by dry etching such as RIE to form openings 213A and 213B. At this time, a damage layer 82 is generated by dry etching on the surface of the channel layer 212 exposed in the openings 213A and 213B.

  Subsequently, as shown in FIG. 14C, wet etching is performed in the same manner as in the first embodiment. As a result, the damage layer 82 is removed, and the damage recovery surface 61 is formed on the surface of the channel layer 212.

  After that, as shown in FIG. 13, the source electrode 271 is formed on the damage recovery surface 61 in the opening 213A, and the drain electrode 272 is formed on the damage recovery surface 61 in the opening 213B. In addition, a gate electrode 273 is formed over the gate insulating film 213. Thus, the field effect transistor shown in FIG. 13 is completed.

  In this field effect transistor, the current flowing in the channel layer 212 between the source electrode 271 and the drain electrode 272 is controlled by controlling the voltage applied to the gate electrode 273. Here, the damage layer 82 generated in the channel layer 212 by dry etching is removed by wet etching to form a damage recovery surface 61, and the source electrode 271 and the drain electrode 272 are provided on the damage recovery surface 61. Therefore, the adverse effect of the damaged layer 82 is prevented, and the electrical continuity between the channel layer 212 and the source electrode 271 and drain electrode 272 is increased. Therefore, reliability is improved.

  As described above, in this embodiment, the damage recovery surface 61 is formed by removing the damage layer 82 generated in the channel layer 212 by dry etching by wet etching, and the source electrode 271 and the drain electrode 272 are formed on the damage recovery surface 61. Thus, adverse effects due to the damaged layer 82 can be prevented, and the reliability of the element can be improved.

(Sixth embodiment)
FIG. 13 shows a configuration of a bipolar transistor according to a modification of the fifth embodiment of the present invention. This bipolar transistor is of a vertical type in which a collector region 311, a base region 312 and an emitter region 313 are sequentially laminated on a substrate 310.

  For example, the substrate 310 has a thickness of about 430 μm and is made of sapphire. The collector region 311, the base region 312, and the emitter region 313 are made of, for example, GaN. The collector region 311 and the emitter region 313 have the same conductivity, and the base region 312 includes the collector region 311 and the emitter region 313. Have different conductivity.

  The collector region 311 is provided with a collector electrode 371, the base region 312 is provided with a base electrode 372, and the emitter region 313 is provided with an emitter electrode 373. For example, when the collector electrode 371, the base electrode 372, and the emitter electrode 373 are provided on a region having p-type conductivity, the first layer has a layer made of palladium (Pd) or nickel (Ni). , Palladium (Pd) / platinum (Pt) / gold (Au), or nickel (Ni) / platinum (Pt) / gold (Au) layered in this order, on the region having n-type conductivity The first layer has a layer made of titanium (Ti), and has a structure in which titanium (Ti) / platinum (Pt) / gold (Au) are sequentially stacked.

  In this bipolar transistor, as will be described later, the collector region 311 and the base region 312 have a damage recovery surface 61 formed by performing wet etching after processing by dry etching as in the first embodiment. It is a layer to be processed. As a result, in this bipolar transistor, adverse effects due to the damage generated in the collector region 311 and the base region 312 by dry etching are prevented, the electrical conductivity between the collector region 311 and the collector electrode 371, and the base region 312 and the base electrode 372 Thus, it is possible to improve the continuity and improve the reliability.

  This bipolar transistor can be manufactured as follows, for example.

  First, as shown in FIG. 16A, a substrate 310 made of the above-described material is prepared, and a collector region 311, a base region 312 and an emitter region made of the above-described material are formed on the substrate 310 by, for example, MOCVD. 313 are formed.

  Next, as shown in FIG. 16B, the emitter region 313 is selectively removed by, for example, dry etching such as RIE to expose the base region 312 on the surface. Further, as shown in FIG. 16B, the emitter region 313 and the base region 312 are selectively removed to expose the collector region 311 on the surface. At this time, a damage layer 82 is generated by dry etching on the exposed surfaces of the collector region 311 and the base region 312.

  Subsequently, as shown in FIG. 16C, wet etching is performed in the same manner as in the first embodiment. As a result, the damage layer 82 is removed, and the damage recovery surface 61 is formed on the surfaces of the collector region 311 and the base region 312.

  After that, as shown in FIG. 15, the collector electrode 371 is formed on the damage recovery surface 61 of the collector region 311, and the base electrode 372 is formed on the damage recovery surface 61 of the base region 312. In addition, an emitter electrode 373 is formed on the emitter region 313. Thus, the bipolar transistor shown in FIG. 15 is completed.

  In this bipolar transistor, the current flowing between the collector region 311 and the emitter region 313 is controlled by controlling the current flowing between the base region 312 and the emitter region 313. Here, the damage layer 82 generated in the collector region 311 and the base region 312 by dry etching is removed by wet etching to form a damage recovery surface 61, and the collector electrode 371 and the base electrode 372 are formed on the damage recovery surface 61. Therefore, the adverse effect of the damaged layer 82 is prevented, and the electrical conductivity between the collector region 311 and the collector electrode 371 and the electrical conductivity between the base region 312 and the base electrode 372 are enhanced. Therefore, reliability is improved.

  As described above, in this embodiment, the damage recovery surface 61 is formed by removing the damaged layer 82 generated in the collector region 311 and the base region 312 by dry etching by wet etching, and the collector electrode 371 is formed on the damage recovery surface 61. In addition, since the base electrode 372 is provided, adverse effects due to the damaged layer 82 can be prevented, and the reliability of the element can be improved. In addition, the emitter region 313, the base region 312 and the collector region 311 can be satisfactorily patterned with a stepped structure by dry etching, and the problem that patterning by wet etching is difficult can be solved.

(Seventh embodiment)
FIG. 17 shows a configuration of a semiconductor laser according to the seventh embodiment of the present invention. This semiconductor laser includes an n-side contact layer 42 and an n-type cladding layer 41 as an n-type semiconductor layer 40, an active layer 30 as an n-type semiconductor layer 40, and a p-type cladding layer 22 as a p-type semiconductor layer 20 Except for having the p-side contact layer 21, it is the same as in the first embodiment. Accordingly, the corresponding components will be described with the same reference numerals.

  The substrate 410 is made of, for example, n-type GaN to which oxygen or silicon is added as an n-type impurity. The n-side contact layer 42 and the n-type cladding layer 41 as the n-type semiconductor layer 40, the active layer 30, and the p-type cladding layer 22 and the p-side contact layer 21 as the p-type semiconductor layer 20 are the first embodiment. It is configured in the same way. A part of the p-type cladding layer 22 and the p-side contact layer 21 form a ridge structure 50 extending in the resonator direction.

  In this semiconductor laser, the n-side contact layer 42 is a layer to be processed having a damage recovery surface 61 formed by performing dry etching and then performing wet etching, as will be described later. As a result, in this semiconductor laser, it is possible to prevent adverse effects due to damage generated in the n-side contact layer 42 by dry etching, and to improve reliability.

  A p-side electrode 71 is provided on the upper surface of the protrusion structure 50, and an n-side electrode 72 is provided on the damage recovery surface 61 formed on the n-side contact layer 42.

  This semiconductor laser can be manufactured, for example, as follows. Here, a case where a plurality of semiconductor lasers are manufactured will be described as an example.

  First, as shown in FIG. 18A, an n-side contact layer 42, an n-type cladding layer 41, an active layer 30, a p-type cladding layer 22 and a p-side contact layer 21 are sequentially stacked on a substrate 410.

  18A, the p-side contact layer 21, the p-type cladding layer 22, the active layer 30, the n-type cladding layer 41, and the n-side contact layer are formed by dry etching using a mask (not shown). A part of 42 is selectively removed, and the n-side contact layer 42 is exposed. At this time, a damage layer 82 is generated on the surface of the n-side contact layer 442 by dry etching. The damaged layer 82 may be an n + layer depending on dry etching conditions, but may be a high resistance layer. If the damage layer 82 is a high resistance layer, the continuity with the n-side electrode 72 is affected. May cause effects.

  Therefore, as shown in FIG. 18B, wet etching is performed in the same manner as in the first embodiment. Thereby, the damage layer 82 is removed, and the damage recovery surface 61 is formed on the surface of the n-side contact layer 42.

  After that, as shown in FIG. 17, the p-type cladding layer 22 and the p-side contact layer 21 are selectively removed by dry etching to form a thin strip shape, thereby forming the ridge structure 50. After the protrusion structure 50 is formed, the p-side electrode 71 is provided on the protrusion structure 50 and the n-side electrode 72 is provided on the damage recovery surface 61 of the n-side contact layer 42 as shown in FIG. After the n-side electrode 72 is formed, the substrate 410 is thinned by polishing, and division and reflection mirror film formation are performed. Thus, a plurality of semiconductor lasers shown in FIG. 17 are completed.

  In this semiconductor laser, when a predetermined voltage is applied between the n-side electrode 72 and the p-side electrode 71, a current is injected into the active layer 30, and light emission occurs due to electron-hole recombination. This light is reflected by a reflecting mirror film (not shown), reciprocates between them to cause laser oscillation, and is emitted to the outside as a laser beam. Here, the damage layer 82 generated by processing the n-side contact layer 42 by dry etching is removed by wet etching to form a damage recovery surface 61, and an n-side electrode 72 is formed on the damage recovery surface 61. Since it is provided, adverse effects due to the damage layer 82 are prevented, and the conductivity between the n-side contact layer 42 and the n-side electrode 72 is increased. Therefore, reliability is improved.

  As described above, in this embodiment, after the p-type semiconductor layer 20, the active layer 30, and the n-type semiconductor layer 40 are processed by dry etching, the damaged layer 82 generated in the n-side contact layer 42 is removed by wet etching. Thus, since the damage recovery surface 61 is formed and the n-side electrode 72 is provided on the damage recovery surface 61, the adverse effect of the damage layer 82 can be prevented and the reliability of the element can be improved.

(Eighth embodiment)
FIG. 19 shows a configuration of a semiconductor laser according to the eighth embodiment of the present invention. This semiconductor laser is the same as that of the first embodiment except that the substrate 510 is made of sapphire which is an insulator. Accordingly, the corresponding components will be described with the same reference numerals.

  In this semiconductor laser, as in the first embodiment, the p-side contact layer 21 is a layer to be processed having a damage recovery surface 61 formed by performing wet etching after processing by dry etching. . As a result, in this semiconductor laser, adverse effects due to damage generated in the p-side contact layer 21 by dry etching can be prevented, and the reliability can be improved.

  This semiconductor laser can be manufactured in the same manner as in the first embodiment except that a substrate 510 made of an insulator is used. The operation and effect of this semiconductor laser are the same as those in the first embodiment.

  In the present embodiment, as in the first embodiment, the p-type semiconductor layer 20, the active layer 30, and the n-type semiconductor layer 40 are formed on the substrate 510 in this order from the substrate 510 side. As described above, similarly to the seventh embodiment, the n-type semiconductor layer 40, the active layer 30, and the p-type semiconductor layer 20 may be formed in this order from the substrate 510 side on the substrate 510. In this case, as in the seventh embodiment, if the n-side contact layer 42 is a layer to be processed having a damage recovery surface 61 formed by performing wet etching after processing by dry etching, the dry contact layer 42 is dry. It is possible to improve the reliability by preventing adverse effects due to the damage generated in the n-side contact layer 42 by etching.

(Ninth embodiment)
FIG. 20 shows a configuration of a light emitting diode (LED) according to the ninth embodiment of the present invention. The light emitting diode has a configuration in which a p-type semiconductor layer 620, a light-emitting layer 630, and an n-type semiconductor layer 640 are sequentially stacked on a substrate 610 made of a p-type semiconductor such as p-type GaN, for example. A p-side electrode 671 is provided on the p-type semiconductor layer 620, and an n-side electrode 672 is provided on the n-type semiconductor layer 640. The n-side electrode 672 includes a transparent electrode 672A and a pad electrode 672B, and light generated in the light emitting layer 630 is extracted through the n-type semiconductor layer 640 and the transparent electrode 672A.

  In this light emitting diode, the p-type semiconductor layer 620 is a layer to be processed having a damage recovery surface 61 formed by performing dry etching and then performing wet etching, as will be described later. As a result, in this light emitting diode, adverse effects due to damage generated in the p-type semiconductor layer 620 by dry etching can be prevented, conductivity between the p-type semiconductor layer 620 and the p-side electrode 671 can be improved, and reliability can be improved. It can be done.

  This light emitting diode can be manufactured as follows, for example.

  First, as shown in FIG. 21A, a p-type semiconductor layer 620, a light emitting layer 630, and an n-type semiconductor layer 640 are sequentially grown on a substrate 610 by, for example, MOCVD.

  Next, as shown in FIG. 21B, a part of the n-type semiconductor layer 640, the light-emitting layer 630, and the p-type semiconductor layer 620 is selectively used, for example, by dry etching such as RIE using the mask 81. By removing, the p-type semiconductor layer 620 is exposed on the surface. At this time, a damage layer 82 is generated on the exposed surface of the p-type semiconductor layer 620 by dry etching.

  Subsequently, the mask 81 is removed, and wet etching is performed as in the first embodiment, as shown in FIG. Thereby, the damage layer 82 is removed, and a damage recovery surface 61 is formed on the surface of the p-type semiconductor layer 620.

  After that, as shown in FIG. 20, the p-side electrode 671 is formed on the damage recovery surface 61 formed on the p-type semiconductor layer 620, and the n-side electrode 672 is formed on the n-type semiconductor layer 640. Thus, the light emitting diode shown in FIG. 20 is completed.

  In this light emitting diode, when a predetermined voltage is applied between the n-side electrode 672 and the p-side electrode 671, a current is injected into the light-emitting layer 630, and light emission occurs due to electron-hole recombination. This light is extracted through the n-type semiconductor layer 640 and the transparent electrode 672A. Here, the damage layer 82 generated by processing the p-type semiconductor layer 620 by dry etching is removed by wet etching to form a damage recovery surface 61, and a p-side electrode 671 is formed on the damage recovery surface 61. Since it is provided, adverse effects due to the damage layer 82 are prevented, and the conductivity between the p-type semiconductor layer 620 and the p-side electrode 671 is increased. Therefore, reliability is improved.

  As described above, in this embodiment, after the n-type semiconductor layer 640, the light emitting layer 630, and the p-type semiconductor layer 620 are processed by dry etching, the damaged layer 82 generated in the p-type semiconductor layer 620 is removed by wet etching. Thus, since the damage recovery surface 61 is formed and the p-side electrode 671 is provided on the damage recovery surface 61, adverse effects due to the damage layer 82 can be prevented, and the reliability of the element can be improved. Further, it is possible to satisfactorily perform patterning such as a step structure on the n-type semiconductor layer 640, the light emitting layer 630, and the p-type semiconductor layer 620 by dry etching, and solve the problem that patterning by wet etching is difficult. Can do.

  Note that in this embodiment, the n-side electrode 672 includes the transparent electrode 672A and the pad electrode 672B, and light generated in the light-emitting layer 630 is extracted through the n-type semiconductor layer 640 and the transparent electrode 672A. Although the case has been described, as shown in FIG. 22, the n-side electrode 672 may be formed of a metal electrode, and light generated in the light-emitting layer 630 may be extracted from the substrate 610 side.

  In this embodiment, the case where the p-side electrode 671 and the n-side electrode 672 are provided on the same surface side of the substrate 610 has been described. However, as illustrated in FIG. You may make it provide in the back side. Alternatively, as shown in FIG. 24, the n-side electrode 672 is composed of a metal electrode, the p-side electrode 671 is composed of a transparent electrode 671A and a pad electrode 671B, and light generated in the light emitting layer 630 is transmitted from the substrate 610 side. You may make it take out. Also in these cases, for example, a damage layer 82 formed on the back side of the substrate 610 due to a physical cause such as polishing, or dirt or a natural oxide film attached to the back side of the substrate 610 due to a thermal history in the crystal growth process, etc. Can be removed by wet etching to form a damage recovery surface 61, and a p-side electrode 671 can be provided on the damage recovery surface 61. Thereby, adverse effects due to the damaged layer 82 and the like generated on the back side of the substrate 610 can be prevented, the electrical conductivity between the substrate 610 and the p-side electrode 671 can be improved, and the reliability of the element can be improved.

  Furthermore, although the case where the substrate 610 is formed of a p-type semiconductor such as p-type GaN has been described in this embodiment, the substrate 610 may be formed of an insulator such as sapphire. In this case, similarly to the configuration illustrated in FIG. 22, the n-side electrode may be configured by a metal electrode, and light generated in the light emitting layer may be extracted from the sapphire substrate side.

  While the present invention has been described with reference to the embodiment, the present invention is not limited to the above embodiment, and various modifications can be made. For example, the third embodiment, the fourth embodiment, and the modification of the fourth embodiment are not limited to the first embodiment, but the modification of the first embodiment or the second embodiment. The same applies to the embodiments.

  Further, for example, the material and thickness of each layer described in the above embodiment, the film formation method and the film formation conditions are not limited, and other materials and thicknesses may be used. It is good also as a method and film-forming conditions. For example, in the seventh embodiment, the case where the substrate 410 is formed of an n-type semiconductor has been described, but the substrate 410 may be formed of an insulator such as sapphire.

  Further, in the eighth embodiment, the case where the substrate 510 has the same configuration as that of the first embodiment except that the substrate 510 is made of an insulator such as sapphire has been described. Also in the embodiment and the fourth embodiment, similarly to the eighth embodiment, a substrate made of an insulator such as sapphire may be used instead of the substrate 10 made of a p-type semiconductor.

  In addition, for example, in the sixth embodiment, the case where the collector region 311, the base region 312 and the emitter region 313 are all homo-bipolar transistors is described, but the base region 312 is, for example, a GaN or GaInN mixed layer. The present invention can also be applied to a heterobipolar transistor which is made of a crystal and whose collector region 311 and emitter region 313 are made of GaN or AlGaN mixed crystal.

  Furthermore, in the above embodiment, the configuration of the semiconductor laser, the field effect transistor, the bipolar transistor, or the light emitting diode has been specifically described. However, it is not necessary to include all layers, and further include other layers. It may be.

  The present invention can be applied not only to a semiconductor laser and a light emitting diode but also to other optical elements such as a photo detector (PD). The present invention can also be applied to electronic elements other than field effect transistors or bipolar transistors. Furthermore, the present invention can be applied to an integrated device using these optical elements or electronic elements.

It is sectional drawing showing the structure of the semiconductor laser which concerns on the 1st Embodiment of this invention. FIG. 2 is a cross-sectional view illustrating a method of manufacturing the semiconductor laser illustrated in FIG. 1 in order of steps. FIG. 3 is a cross-sectional view illustrating a process following FIG. 2. It is sectional drawing showing the structure of the semiconductor laser which concerns on the modification of 1st Embodiment. It is sectional drawing showing the structure of the semiconductor laser which concerns on the 2nd Embodiment of this invention. FIG. 6 is a cross-sectional view illustrating a method of manufacturing the semiconductor laser illustrated in FIG. 5 in order of steps. FIG. 6 is a cross-sectional view illustrating another manufacturing method of the semiconductor laser illustrated in FIG. 5 in order of steps. It is sectional drawing showing the structure of the semiconductor laser which concerns on the 3rd Embodiment of this invention. FIG. 9 is a cross-sectional view illustrating a method of manufacturing the semiconductor laser illustrated in FIG. 8 in order of steps. It is sectional drawing showing the structure of the semiconductor laser which concerns on the 4th Embodiment of this invention. FIG. 11 is a cross-sectional view illustrating a method of manufacturing the semiconductor laser illustrated in FIG. 10 in order of steps. It is a partially expanded sectional view showing the structure of the semiconductor laser which concerns on the modification of the 4th Embodiment of this invention. It is sectional drawing showing the structure of the field effect transistor which concerns on the 5th Embodiment of this invention. It is sectional drawing showing the manufacturing method of the field effect transistor shown in FIG. 13 in order of a process. It is sectional drawing showing the structure of the bipolar transistor which concerns on the 6th Embodiment of this invention. FIG. 16 is a cross-sectional view illustrating a method of manufacturing the bipolar transistor illustrated in FIG. 15 in order of steps. It is sectional drawing showing the structure of the semiconductor laser which concerns on the 7th Embodiment of this invention. FIG. 18 is a cross-sectional view illustrating a method of manufacturing the semiconductor laser illustrated in FIG. 17 in order of processes. It is sectional drawing showing the structure of the semiconductor laser which concerns on the 8th Embodiment of this invention. FIG. 20A is a plan view showing a configuration of a light emitting diode according to a ninth embodiment of the present invention viewed from the side where the light emitting layer of the substrate is formed, and FIG. It is sectional drawing along the XXB-XXB line | wire of (A). FIG. 21 is a cross-sectional view illustrating a method of manufacturing the light emitting diode illustrated in FIG. 20 in order of processes. FIG. 22A is a plan view showing a configuration of a light emitting diode according to a modification of the ninth embodiment viewed from the side on which the light emitting layer of the substrate is formed, and FIG. It is sectional drawing which followed the XXIIB-XXIIB line | wire of 22 (A). FIG. 23A is a plan view showing a configuration of a light emitting diode according to another modification of the ninth embodiment as viewed from the side where the light emitting layer of the substrate is formed, and FIG. FIG. 24 is a cross-sectional view taken along line XXIIIB-XXIIIB in FIG. FIG. 24A is a plan view showing a configuration of a light emitting diode according to still another modification of the ninth embodiment as viewed from the side where the light emitting layer of the substrate is formed, and FIG. 24A is a cross-sectional view taken along line XXIVB-XXIVB in FIG. 24A, and FIG. 24C is a configuration in which the light-emitting diode shown in FIGS. 24A and 24B is viewed from the back side of the substrate. It is a top view showing. It is sectional drawing showing the manufacturing method of the conventional semiconductor laser in order of a process.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10,610 ... Substrate (p-type semiconductor) 20,620 ... p-type semiconductor layer, 21 ... p-side contact layer, 21A ... GaInN contact layer, 22 ... p-type cladding layer, 30 ... active layer, 40,640 ... n Type semiconductor layer, 41 ... n-type cladding layer, 42 ... n-side contact layer, 50 ... ridge structure, 61 ... damage recovery surface, 71, 671 ... p-side electrode, 72, 672 ... n-side electrode, 81 ... mask, 82 ... damaged layer, 82A ... uneven structure, 83 ... protective film, 210 ... substrate _{(Al 2 O 3), 211} ... buffer layer, 212 ... channel layer, 213 ... gate insulating film, 271 ... source electrode, 272 ... drain electrode 273 ... Gate electrode, 310 ... Substrate, 311 ... Collector region, 312 ... Base region, 313 ... Emitter region, 371 ... Collector electrode, 372 ... Base electrode, 373 ... Emitter Electrode, 410 ... substrate (n-type semiconductor), 510 ... substrate (insulator), 630 ... light-emitting layer, 671A, 672A ... transparent electrode, 671B, 672B ... pad electrode

Claims (25)

A substrate,
A semiconductor layer formed of a nitride III-V compound semiconductor containing at least one of 3B group elements and at least nitrogen (N) of 5B group elements, and formed on the substrate;
And a processed layer having a damage recovery surface formed by performing wet etching after the substrate or the semiconductor layer is processed by polishing or dry etching. The semiconductor element according to claim 1, wherein the wet etching is performed using an etching solution or an etching gas containing phosphoric acid or hydrochloric acid. The semiconductor element according to claim 1, wherein the wet etching is performed with an etching amount of 0.01 μm or more. The semiconductor element according to claim 1, wherein the semiconductor layer includes a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer in order from the substrate side. The substrate is made of a p-type semiconductor, the first conductive semiconductor layer includes a p-side contact layer and a p-type cladding layer, and the second conductive semiconductor layer includes an n-type cladding layer and an n-side contact layer. The semiconductor element according to claim 4. The semiconductor element according to claim 5, wherein the p-side contact layer is a layer to be processed, and a p-side electrode is provided on a damage recovery surface formed in the p-side contact layer. The semiconductor element according to claim 5, wherein the substrate is a layer to be processed, and a p-side electrode is provided on a damage recovery surface formed on a back side of the substrate. The semiconductor element according to claim 5, wherein the n-type cladding layer and the n-side contact layer form a protrusion structure for current confinement. The semiconductor element according to claim 8, wherein the n-type cladding layer is a layer to be processed and has a damage recovery surface on both sides of the protrusion structure. The semiconductor element according to claim 8, wherein the n-side contact layer has a damage layer formed by processing by dry etching on an upper surface of the protrusion structure. The semiconductor element according to claim 10, wherein the damage layer has a concavo-convex structure on a surface thereof. The substrate is made of an n-type semiconductor, the first conductive semiconductor layer includes an n-side contact layer and an n-type cladding layer, and the second conductive semiconductor layer includes a p-type cladding layer and a p-side contact layer. The semiconductor element according to claim 4. The semiconductor element according to claim 12, wherein the n-side contact layer is a work layer, and an n-side electrode is provided on a damage recovery surface formed in the n-side contact layer. The semiconductor element according to claim 12, wherein the substrate is a layer to be processed, and an n-side electrode is provided on a damage recovery surface formed on a back side of the substrate. The substrate is made of an insulator, the first conductive semiconductor layer includes a p-side contact layer and a p-type cladding layer, and the second conductive semiconductor layer includes an n-type cladding layer and an n-side contact layer. 5. The semiconductor element according to claim 4, wherein The semiconductor element according to claim 15, wherein the p-side contact layer is a layer to be processed, and a p-side electrode is provided on a damage recovery surface formed in the p-side contact layer. The semiconductor element according to claim 1, wherein the semiconductor layer includes a channel layer made of an n-type semiconductor or a p-type semiconductor. The semiconductor element according to claim 17, wherein the channel layer is a layer to be processed, and an electrode is provided on a damage recovery surface formed in the channel layer. The semiconductor element according to claim 1, wherein the semiconductor layer includes a collector region, a base region, and an emitter region made of an n-type semiconductor or a p-type semiconductor. The semiconductor element according to claim 19, wherein the collector region and the base region are processed layers, and an electrode is provided on a damage recovery surface formed in the collector region and the base region. The semiconductor element according to claim 1, wherein the substrate is made of an insulator. The semiconductor element according to claim 1, wherein the substrate is made of a semiconductor. Forming a semiconductor layer made of a nitride III-V compound semiconductor containing at least one of group 3B elements and at least nitrogen (N) of group 5B elements on a substrate;
Forming a layer to be processed having a damage recovery surface formed by performing wet etching after processing the substrate or the semiconductor layer by polishing or dry etching, and a method for manufacturing a semiconductor element. The method of manufacturing a semiconductor element according to claim 23, wherein the wet etching is performed using an etching solution or etching gas containing phosphoric acid or hydrochloric acid. The method of manufacturing a semiconductor element according to claim 23, wherein the wet etching is performed with an etching amount of 0.01 µm or more.

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