JP2005268694A - Semiconductor integrated circuit and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit capable of realizing a high operating speed and a small leak current, and to provide a method for manufacturing the semiconductor integrated circuit capable of optimizing every applicable block in a short period of time. <P>SOLUTION: The semiconductor integrated circuit comprises a logic circuit 11 connected to a current supplying line between a power potential V<SB>DD</SB>and a reference potential V<SB>SS</SB>, and a switching transistor 12 comprising an NMOS transistor between the logic circuit 11 and the reference potential V<SB>SS</SB>. A gate width W of the power gate switching transistor 12 is set on the basis of a power consumption (a consumption current) at the time of normal operation of the semiconductor integrated circuit 10 with the switching transistor 12 applied as the power gate, an allowable value of a rate of speed deterioration attributable to the application of the power gate, and a basic property (Vds-Ids characteristic) of the switching transistor 12. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor integrated circuit to which a power gate is applied and a manufacturing method thereof, and more particularly to a technique for setting a gate width of a switch transistor applied to a power gate.

<Background of power gate application>
In the deep submicron generation LSI, there is a problem that the ratio of leakage power to the power consumption of the entire LSI increases as the threshold value of the MOS transistor decreases. This leads to restrictions on the usage time of portable devices and an increased load on the cooling system, so low power technology is essential for future LSI development.
In view of this situation, a power gate is expected to be a low power technology for reducing leakage power. Depending on the type of power switch transistor used, how to apply the gate voltage, etc., it is also called MTCMOS (Multi Threshold MOS) method, Super Cut Off CMOS (Super Cut Off CMOS) method or the like.

<Overview of power gate>
The power gate circuit technology is realized by inserting a power switch transistor between VDD (power source) and logic circuit, between logic circuit and VSS (ground), or both.
When a power switch transistor is inserted between VDD (power source) and a logic circuit, a p-channel MOS (PMOS) transistor is inserted and its gate serves as a control terminal.
When a power switch transistor is inserted between the logic circuit-VSS (ground), an n-channel MOS (NMOS) transistor is inserted and its gate serves as a control terminal.
The power switch transistor is controlled to be in an on state in a normal operation state and in an off state in a standby state.
Thereby, leakage power in the standby state is reduced.

By the way, the circuit characteristics change before and after the application of the power gate. In applying power gates, it is necessary to consider the characteristics of the following items. These items greatly depend on the power switch gate width W, and there is a trade-off relationship between the items. This trade-off relationship can be explained by the characteristic of the MOS transistor that the current driving capability increases in proportion to the gate width W (see FIG. 9).
-Regarding the operation speed, the smaller W, the greater the speed degradation.
-Regarding the leakage power reduction effect in the standby state, the smaller the W, the greater the leakage power reduction effect.

  As ideal circuit characteristics, it is ideal to achieve a large operating speed and a small leakage power. However, since there is a trade-off between the above two items, an optimum value W according to the circuit specifications is determined. This is very important.

  Compared with power reduction by power source separation, the power gate can be applied to a smaller circuit unit and to a larger number of circuit blocks (see FIG. 10). This is due to the simplicity of the circuit structure of the power gate. Power supply isolation requires measures such as well isolation, which increases design man-hours and area overhead.

By the way, although the value of the gate width W of the power switch transistor is an important value for determining the speed deterioration and the leakage power reduction effect, an efficient W determination method for optimizing the applied circuit Did not exist.
Conventionally, W is determined by executing a simulation with a power switch transistor added to each circuit to be applied, or the value of the gate width W is determined based on empirical data.

One of the advantages is that the power gate can be applied to many blocks in a small circuit unit. However, in the conventional technology using simulation, it takes a lot of time to optimize each application block. Difficult.
The conventional method of determining the gate width W based on experience tends to deteriorate the accuracy of the gate width W with respect to the optimum value. As a result, excessive W was added to reduce the leakage reduction effect, or conversely, small W was added to cause excessive speed deterioration. In such a situation, the power gate technology is not fully utilized.

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide a semiconductor integrated circuit capable of realizing a large operating speed and a small leakage power, and a semiconductor integrated circuit capable of being optimized in a short time for each application block. It is to provide a manufacturing method.

  In order to achieve the above object, a first aspect of the present invention includes a logic circuit and a power gate that is disposed in a power supply path to the logic circuit and whose conduction state is controlled according to a control signal. The power gate includes a switch transistor, and the gate width of the switch transistor includes power consumption during normal operation, an allowable amount of speed deterioration caused by applying the power gate, and basic characteristics of the switch transistor. It is set based on.

  Preferably, the gate width of the switch transistor is set in association with a value obtained by converting an allowable amount of the speed deterioration rate into an allowable voltage drop value and a basic characteristic of the switch transistor.

  The second aspect of the present invention is arranged at least one of a power supply potential, a reference potential, a logic circuit, the logic circuit and the power supply potential, and between the logic circuit and the reference potential. A power gate whose conduction state is controlled in accordance with a control signal, and the power gate includes a switch transistor, and the gate width of the switch transistor is determined based on power consumption during normal operation and the power gate. It is set based on the allowable amount of the speed deterioration rate caused by the application and the basic characteristics of the switch transistor.

  Preferably, the gate width of the switch transistor is set in association with a value obtained by converting an allowable amount of the speed deterioration rate into an allowable voltage drop value and a basic characteristic of the switch transistor.

  Preferably, the connection portion between the logic circuit and the switch transistor is connected to a virtual potential.

  A third aspect of the present invention includes a logic circuit and a switch transistor which is arranged in a power supply path to the logic circuit and whose gate width is set by a predetermined procedure in which a conduction state is controlled according to a control signal. A method of manufacturing a semiconductor integrated circuit having a power gate, wherein the setting procedure of the gate width of the switch transistor includes a first step of calculating power consumption during normal operation and a speed generated by applying the power gate. A second step of determining an allowable amount of deterioration rate, a third step of converting the allowable amount of speed deterioration rate into an allowable voltage drop value, the voltage drop value and the basic characteristics of the switch transistor, And a fourth step for setting the gate width.

  Preferably, in the first step, a current consumption value is calculated using a pattern close to an actual operation and a sufficiently high circuit activation rate.

  Preferably, in the third step, the conversion to the voltage drop value is performed based on the relationship between the power supply voltage and the circuit speed.

  Preferably, in the fourth step, the allowable average voltage drop value is set as the time average value of the potential difference generated between the drain and the source of the switch transistor, and the above logic is satisfied under the condition that the potential difference between the drain and the source is fixed. The gate width is set by determining a sufficient condition for flowing the current consumed by the circuit based on the voltage-current characteristics of the switch transistor.

  Preferably, the method further includes a fifth step of analyzing the voltage drop using physical data after placement and wiring, and verifying whether the voltage drop value is equal to or less than the initially estimated voltage drop value.

  Preferably, in the fifth step, the switch transistor is modeled as a resistor using the physical data after placement and wiring, and the voltage drop is analyzed.

According to the present invention, the setting of the gate width of the switch transistor is performed by the following procedure, for example.
For example, power consumption during normal operation of the semiconductor integrated circuit is calculated. In this case, the current consumption value that maximizes the assumed operation mode is used. In order to accurately estimate the gate width, it is necessary to calculate a current consumption value using a pattern close to actual operation and under a sufficiently high circuit activation rate.
As a circuit specification, an allowable value of the rate of speed degradation caused by power gate application is determined. Tolerance of speed degradation caused by power gate application when compared with operating speed before power gate application is determined as a specification.
The allowable amount of speed deterioration is converted as an allowable voltage drop value, for example. For example, conversion of the speed deterioration rate into a voltage drop value can be performed based on the relationship between the power supply voltage and the circuit speed.
For example, an allowable average voltage drop value is reinterpreted as a time average value of a potential difference generated between the drain and source of the switch transistor.
Considering that a potential difference equal to the average voltage drop value determined from the speed deterioration allowable value is applied between the drain and source of the switch transistor, the current consumed by the logic circuit is allowed to flow under the condition that the potential difference between the drain and source is fixed. A sufficient condition is determined on the basis of the voltage-current curve of the switch transistor, and the gate width is determined.

According to the present invention, a large operating speed and a small leakage power can be realized.
In addition, optimization can be performed in a short time for each application block.
That is, since it can be determined only by the power estimation and the basic characteristics of the transistor, it is not necessary to consider physical factors such as arrangement when determining the gate width, and can be determined at the initial stage of design.
Since the gate width value can be determined if only the current consumption value of the power gate applied circuit, the allowable value of the speed deterioration due to the power gate given as the specification, and the basic characteristics of the power switch transistor are known, the additional man-hours can be reduced.
Since the calculation of the current consumption value of the power gate applied circuit is performed regardless of whether the power gate is applied or not, there is no additional man-hour for this.
The allowable value of speed degradation due to the power gate is determined as a circuit specification, so there is no substantial work. Since the basic characteristics of the power switch transistor are always prepared when designing a circuit regardless of whether the power gate is applied or not, there is no additional man-hour for this purpose.
Since the calculation of the gate width W value is easy, it can be applied to a large number of circuit blocks. Further, since the gate width value is determined based on the basic characteristics of the switch transistor, it is highly accurate.
In the verification of the speed deterioration due to the power gate application, the switch transistor is estimated as an ideal resistance, so that the verification is easy.

  Embodiments of the present invention will be described below with reference to the drawings.

<First Embodiment>
FIG. 1 is a circuit diagram showing a first embodiment of a semiconductor integrated circuit to which a power gate according to the present invention is applied.

A semiconductor integrated circuit 10 in FIG. 1 includes a logic circuit 11 and a switch transistor 12 as a power gate. In the case of FIG. 1, the switch transistor 12 is configured by an n-channel MOS (NMOS) transistor.
The logic circuit 11 is connected to a current supply line between the power supply potential V _DD and the reference potential Vss, and a switch transistor 12 made of an NMOS transistor is inserted between the logic circuit 11 and the reference potential Vss. Specifically, the source of the switch transistor 12 is connected to the reference potential Vss, the drain is connected to the virtual reference potential VVss, and the virtual reference potential VVss is connected to the logic circuit 11.
The gate terminal of the switch transistor 12 becomes a control terminal, and the conduction state is controlled by the control signal CNT. Specifically, the semiconductor integrated circuit 10 is controlled to be in a conductive state (on state) in a normal operation state and in a non-conductive state (off state) in a standby state.
Then, the gate width W of the switch transistor 12, as will be described in detail later, power consumption (current consumption) during normal operation of the semiconductor integrated circuit 10 to which the switch transistor 12 as a power gate is applied, High operating speed is achieved by setting based on the allowable speed degradation rate caused by application and the basic characteristics (Vds-Ids characteristics) of the switch transistor 12, and the leakage power in the standby state is reduced. doing.

  2A to 2C show the operating state of the power gate in the semiconductor integrated circuit 10 of FIG. 2A shows the control signal, FIG. 2B shows the transition of the current flowing through the power gate, and FIG. 2C shows the transition of the virtual reference potential.

When the control signal CNT is at a high level (power supply voltage level), the switch transistor 12 is turned on, and a substantially constant current flows.
When the control signal CNT is switched to a low level (0 V), the switch transistor 12 is switched to an off state, and the current flowing through the switch transistor 12 is greatly reduced. At this time, electric charges are accumulated in the virtual power supply line and become a potential lower than the power supply voltage V _DD .
When the control signal CNT is switched to a high level, the switch transistor 12 is switched to an on state. At this time, it flows through the switch transistor 12 including the charge accumulated in the virtual power supply line. Therefore, the potential of the virtual power supply line is substantially equal to the reference potential.

  FIG. 3 is a block diagram showing a configuration example of an integrated circuit design apparatus for designing a semiconductor integrated circuit according to the present invention.

  As shown in FIG. 3, the integrated circuit design device 20 includes a computer 21, a program storage unit 22, a data storage unit 23, a display device 24, and an interface unit 25.

  The computer 21 reads an integrated circuit design program stored in the program storage unit 20 and executes the program, and executes a process described later related to the design of the integrated circuit, specifically operations relating to the setting of the gate width of the power gate. Perform various processes.

  The program storage unit 22 stores an integrated circuit design program to be executed by the computer 21.

  The data storage unit 23 stores data used in the process execution process in the computer 21 and execution result data. For example, an estimated value of RTL, an allowable amount of rate of deterioration caused by applying a power gate given as a specification, a voltage drop value (also referred to as an IR-Drop value) due to a current flowing when the switch transistor is in an ON state. A conversion table, a Vds-Ids characteristic table of a transistor employed as a power switch transistor, circuit data processed by an integrated circuit design program, and the like are stored.

The display unit 24 displays a predetermined image such as a Vds-Ids characteristic table under the control of the computer 21. For example, as various images associated with the execution of the integrated circuit design program, an image prompting the user to input a command, an image of a simulation execution result, and the like are displayed.
Vds is a drain-source voltage, and Ids is a current flowing between the drain and source.

  The interface unit 25 includes a device for inputting information from the user to the computer 21 such as a keyboard and a mouse. Also included are devices for inputting and outputting circuit data to be processed in the integrated circuit design device 20, such as an optical disk device and a network interface device.

The procedure for setting the gate width of the power gate in the semiconductor integrated circuit will be described below in detail with reference to FIGS.
FIG. 4 is a flowchart showing a procedure for setting the gate width of the power gate in the semiconductor integrated circuit according to the present invention.
FIG. 5 is a diagram schematically showing a procedure for setting the gate width of the power gate in the semiconductor integrated circuit according to the present invention.

Step ST1 : Calculate current consumption during normal operation of a semiconductor integrated circuit (application circuit) to which a power gate is applied.
A current consumption value of the power gate applied circuit in a state before the power gate is applied is calculated. In practice, the current consumption value is calculated by the EDA tool based on the simulation result at the RT level.
The current consumption value may be obtained as a time average value. This is because the current consumption value is calculated on the basis of the RT level simulation, so that the accuracy higher than that obtained as the time average value cannot be expected.
Use the current consumption value that maximizes the expected operation mode. In order to accurately estimate the gate width W, the current consumption value must be calculated using a pattern close to actual operation and under a sufficiently high circuit activation rate.

Step ST2 : As a circuit specification, an allowable value of a rate of rate deterioration caused by power gate application is determined.
Tolerance of speed degradation caused by power gate application when compared with operating speed before power gate application is determined as a specification.
Since power gating is equivalent to increasing the number of stacked transistors, speed degradation is an unavoidable problem.

Step ST3 : The allowable value for speed deterioration is converted as an allowable average IR-DROP value.
Conversion of the speed deterioration rate into the IR-DROP value can be performed based on the relationship between the power supply voltage and the circuit speed.
The relationship between the power supply voltage and the circuit speed is given as standard basic data in normal LSI design regardless of application / non-application of the power gate.

Step ST4 : The allowable average IR-DROP value is reinterpreted as the time average value of the potential difference generated between the drain and source of the power switch transistor.
That is, the speed deterioration due to the application of the power gate is considered as an influence of the voltage drop in the power switch transistor. This voltage drop can be regarded as equivalent to the occurrence of IR-DROP (voltage drop) when viewed from the logic circuit.

Step ST5 : Determination of Power Switch Transistor It is assumed that a potential difference equal to the average IR-DROP value determined from the speed deterioration allowable value is applied between the drain and source of the power switch transistor. A condition sufficient to allow the current consumed by the logic circuit to flow under a condition where the potential difference between the drain and the source is fixed is determined based on the Vds-Ids curve of the transistor.
Specifically, the following three items are determined. That is, (1) kind of power switch transistor, (2) gate voltage Vgs of the power switch transistor, and (3) gate width W.

Step ST6 : Placement and wiring (Place & Route: P & R)
The physical design is performed with the determined switch transistor.
In the circuit configuration that is controlled by the gate voltage Vgs of the power switch transistor (2) described above, the arrangement and wiring (P & R) are performed by applying the type (1) of the power switch transistor and the gate width W of (3). .

Step ST7 : Verification Using physical data after placement and wiring (P & R), IR-DROP analysis is performed to verify whether the IR-DROP value is less than the initially estimated value.
The IR-DROP analysis is performed including the power switch transistor. The power switch transistor is modeled as an ideal resistor R. This modeling is generally a reasonable approximation in a region where the drain-source voltage Vds is small compared to the power supply voltage. In practical use, it is assumed that the speed degradation due to application of the power gate is suppressed to 10% or less, and there is no problem in this modeling.

As described above, according to this embodiment, the logic circuit 11 connected to the current supply line between the power supply potential V _DD and the reference potential Vss, and the logic circuit 11 and the reference potential Vss are connected. The power consumption (current consumption) during normal operation of the semiconductor integrated circuit 10 to which the switch transistor 12 as a power gate is applied has a gate width W of the switch transistor 12 formed of an NMOS transistor. ) And the allowable speed deterioration rate caused by applying the power gate, and the basic characteristics (Vds-Ids characteristics) of the switch transistor 12, the following effects can be obtained.

  A large operating speed can be realized, and leakage power in the standby state can be reduced.

Further, since it can be determined only by RT-level power estimation and the basic characteristics of the transistor, it is not necessary to consider physical factors such as arrangement when determining the gate width W, and it can be determined at the initial stage of design.
Since the W value can be determined by knowing only the current consumption value of the power gate applied circuit, the allowable speed deterioration due to the power gate given as a specification, and the basic characteristics of the power switch transistor, the additional man-hours can be reduced.
Since the calculation of the current consumption value of the power gate applied circuit is performed regardless of whether the power gate is applied or not, there is no additional man-hour for this.
The allowable value of speed degradation due to the power gate is determined as a circuit specification, so there is no substantial work. Since the basic characteristics of the power switch transistor are always prepared when designing a circuit regardless of whether the power gate is applied or not, there is no additional man-hour for this purpose.
Since the calculation of the gate width W value is easy, it can be applied to a large number of circuit blocks. Further, since the W value is determined based on the basic characteristics of the switch transistor, it is highly accurate.
In the verification of the speed deterioration due to the power gate application, the switch transistor is estimated as an ideal resistance, so that the verification is easy.

Below, the modification of this invention is enumerated.
The above design flow can be applied to a large number of circuit blocks to construct an LSI having a plurality of independent power gate circuits.
The design can be automated by programming the design flow.
It may be considered in advance when selecting a switch transistor that a transistor having a large ratio of Ion and Ioff of the transistor is advantageous as a switch transistor.
Considering the increase in area due to the application of power gates, an optimization method can be considered in consideration of the trade-off between area, speed degradation, and power reduction effect.
The accuracy can be improved by calculating the delay penalty in consideration of the source bias effect of the transistor.
It is also possible to perform optimization together with the IR-DROP margin value in the power supply network.

Second Embodiment
FIG. 6 is a circuit diagram showing a second embodiment of the semiconductor integrated circuit to which the power gate according to the present invention is applied.
In FIG. 6, the same components as those in FIG. 1 are denoted by the same reference numerals for easy understanding.

The semiconductor integrated circuit 10A in FIG. 6 includes a logic circuit 11 and a switch transistor 13 as a power gate. In the case of FIG. 6, the switch transistor 13 is configured by a p-channel MOS (PMOS) transistor.
The logic circuit 11 is connected to a current supply line between the power supply potential V _DD and the reference potential Vss, and a switch transistor 13 composed of a PMOS transistor is inserted between the logic circuit 11 and the power supply potential V _DD . More specifically, the source of the switch transistor 13 is connected to the power supply potential V _DD, a drain connected to the virtual power supply voltage VV _DD, the virtual power voltage VV _DD is connected to the logic circuit 11.
The gate terminal of the switch transistor 13 becomes the control terminal, and the conduction state is controlled by the control signal CNT. Specifically, the semiconductor integrated circuit 10A is controlled to be in a conductive state (on state) in the normal operation state and in a non-conductive state (off state) in the standby state.
Then, the gate width W of the switch transistor 13 is applied to the power consumption (current consumption) during normal operation of the semiconductor integrated circuit 10A to which the switch transistor 13 as the power gate is applied as described above, and the power gate. Is set based on the permissible amount of speed degradation caused by the switching transistor 13 and the basic characteristics (Vds-Ids characteristics) of the switch transistor 13, thereby realizing a large operating speed and reducing leakage power in the standby state. .

<Third Embodiment>
FIG. 7 is a circuit diagram showing a third embodiment of the semiconductor integrated circuit to which the power gate according to the present invention is applied.
In FIG. 7, the same components as those in FIGS. 1 and 6 are denoted by the same reference numerals for easy understanding.

The semiconductor integrated circuit 10B of FIG. 7 includes a logic circuit 11 and switch transistors 12 and 13 as power gates. In the case of FIG. 7, the switch transistor 12 is configured by an NMOS transistor, and the switch transistor 13 is configured by a PMOS transistor.
The logic circuit 11 is connected to a current supply line between the power supply potential V _DD and the reference potential Vss, and a switch transistor 12 made of an NMOS transistor is inserted between the logic circuit 11 and the reference potential Vss. Specifically, the source of the switch transistor 12 is connected to the reference potential Vss, the drain is connected to the virtual reference potential VVss, and the virtual reference potential VVss is connected to the logic circuit 11.
A switch transistor 13 made of a PMOS transistor is inserted between the logic circuit 11 and the power supply potential V _DD . More specifically, the source of the switch transistor 13 is connected to the power supply potential V _DD, a drain connected to the virtual power supply voltage VV _DD, the virtual power voltage VV _DD is connected to the logic circuit 11.
The gate terminals of the switch transistors 12 and 13 become control terminals, the conduction state of the switch transistor 12 is controlled by the control signal CNT, and the conduction state of the switch transistor 13 is controlled by the inverted signal (reverse phase signal) XCNT of the control signal CNT. . Specifically, the semiconductor integrated circuit 10B is controlled to be in a conductive state (on state) in a normal operation state and in a non-conductive state (off state) in a standby state.
As described above, the gate width W of the switch transistors 12 and 13 is set so that the power consumption (current consumption) during normal operation of the semiconductor integrated circuit 10B to which the switch transistors 12 and 13 as power gates are applied, and the power gate. Is set based on the permissible amount of the speed deterioration rate caused by the application and the basic characteristics (Vds-Ids characteristics) of the switch transistors 12 and 13, thereby realizing a large operating speed and leaking in the standby state. Power is being reduced.

<Fourth embodiment>
FIG. 8 is a circuit diagram showing a fourth embodiment of a semiconductor integrated circuit to which the power gate according to the present invention is applied.
In FIG. 8, the same components as those in FIG. 7 are denoted by the same reference numerals for easy understanding.

A semiconductor integrated circuit 10C in FIG. 8 includes a logic circuit 11 and switch transistors 12 and 13 as power gates. In the case of FIG. 8, the switch transistor 12 is composed of an NMOS transistor, and the switch transistor 13 is composed of a PMOS transistor.
The logic circuit 11 is connected to two first and second current supply lines between the power supply potential V _DD and the reference potential Vss, and between the logic circuit 11 and the reference potential Vss in the first current supply line. A switch transistor 12 made of an NMOS transistor is inserted. Specifically, the source of the switch transistor 12 is connected to the reference potential Vss, the drain is connected to the virtual reference potential VVss, and the virtual reference potential VVss is connected to the logic circuit 11.
A switch transistor 13 made of a PMOS transistor is inserted between the logic circuit 11 and the power supply potential V _DD in the second current supply line. More specifically, the source of the switch transistor 13 is connected to the power supply potential V _DD, a drain connected to the virtual power supply voltage VV _DD, the virtual power voltage VV _DD is connected to the logic circuit 11.
The gate terminals of the switch transistors 12 and 13 become control terminals, the conduction state of the switch transistor 12 is controlled by the control signal CNT, and the conduction state of the switch transistor 13 is controlled by the inverted signal (reverse phase signal) XCNT of the control signal CNT. . Specifically, the semiconductor integrated circuit 10C is controlled to be in a conductive state (on state) in the normal operation state and in a non-conductive state (off state) in the standby state.
Then, as described above, the gate width W of the switch transistors 12 and 13 is set to the power consumption (current consumption) during normal operation of the semiconductor integrated circuit 10C to which the switch transistors 12 and 13 as power gates are applied, and the power gate. Is set based on the permissible amount of the speed deterioration rate caused by the application and the basic characteristics (Vds-Ids characteristics) of the switch transistors 12 and 13, thereby realizing a large operating speed and leaking in the standby state. Power is being reduced.

1 is a circuit diagram showing a first embodiment of a semiconductor integrated circuit to which a power gate according to the present invention is applied. FIG. 2 is a diagram illustrating an operation state of a power gate in the semiconductor integrated circuit of FIG. 1. 1 is a block diagram illustrating a configuration example of an integrated circuit design apparatus for designing a semiconductor integrated circuit according to the present invention. 6 is a flowchart showing a procedure for setting the gate width of the power gate in the semiconductor integrated circuit according to the present invention. It is a figure which shows typically the setting procedure of the gate width of the power gate in the semiconductor integrated circuit which concerns on this invention. It is a circuit diagram which shows 2nd Embodiment of the semiconductor integrated circuit to which the power gate which concerns on this invention is applied. It is a circuit diagram which shows 3rd Embodiment of the semiconductor integrated circuit to which the power gate which concerns on this invention is applied. It is a circuit diagram which shows 4th Embodiment of the semiconductor integrated circuit to which the power gate which concerns on this invention is applied. It is a figure for demonstrating that the trade-off relationship exists between the items which should be considered in application of a power gate. It is a figure for demonstrating that a power gate is applicable with respect to a smaller circuit unit and more circuit blocks compared with the reduction in power by power supply isolation | separation.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10, 10A-10C ... Semiconductor integrated circuit, 11 ... Logic circuit, 12, 13 ... Power switch transistor as a power gate.

Claims (11)

Logic circuit;
A power gate disposed in a power supply path to the logic circuit, the conduction state of which is controlled according to a control signal;
The power gate includes a switch transistor, and the gate width of the switch transistor depends on power consumption during normal operation, an allowable amount of rate of deterioration caused by applying the power gate, and basic characteristics of the switch transistor. Set based on semiconductor integrated circuit. The semiconductor integrated circuit according to claim 1, wherein the gate width of the switch transistor is set in association with a value obtained by converting an allowable amount of the speed deterioration rate into an allowable voltage drop value and a basic characteristic of the switch transistor. Power supply potential;
A reference potential;
Logic circuit;
A power gate disposed between at least one of the logic circuit and the power supply potential and between the logic circuit and the reference potential, the conduction state of which is controlled according to a control signal;
The power gate includes a switch transistor, and the gate width of the switch transistor depends on power consumption during normal operation, an allowable amount of rate of deterioration caused by applying the power gate, and basic characteristics of the switch transistor. Set based on semiconductor integrated circuit. The semiconductor integrated circuit according to claim 3, wherein the gate width of the switch transistor is set in association with a value obtained by converting an allowable amount of the speed deterioration rate into an allowable voltage drop value and a basic characteristic of the switch transistor. The semiconductor integrated circuit according to claim 3, wherein a connection portion between the logic circuit and the switch transistor is connected to a virtual potential. A semiconductor integrated circuit comprising: a logic circuit; and a power gate including a switch transistor disposed in a power supply path to the logic circuit and having a gate width set by a predetermined procedure in which a conduction state is controlled according to a control signal A manufacturing method of
The procedure for setting the gate width of the switch transistor is as follows:
A first step of calculating power consumption during normal operation;
A second step for determining an allowable amount of rate of degradation caused by applying a power gate;
A third step of converting the allowable speed deterioration rate into an allowable voltage drop value;
And a fourth step of setting the gate width in association with the voltage drop value and the basic characteristic of the switch transistor. The method of manufacturing a semiconductor integrated circuit according to claim 6, wherein, in the first step, the current consumption value is calculated using a pattern close to actual operation and under a sufficiently high circuit activation rate. The method for manufacturing a semiconductor integrated circuit according to claim 6, wherein in the third step, the conversion to the voltage drop value is performed based on a relationship between a power supply voltage and a circuit speed. In the fourth step, the logic circuit consumes an allowable average voltage drop value as a time average value of the potential difference generated between the drain and source of the switch transistor under the condition of fixing the potential difference between the drain and source. The method for manufacturing a semiconductor integrated circuit according to claim 6, wherein a sufficient condition for flowing a current is determined based on a voltage-current characteristic of the switch transistor, and a gate width is set. The method of manufacturing a semiconductor integrated circuit according to claim 6, further comprising a fifth step of analyzing a voltage drop using physical data after placement and wiring, and verifying whether the voltage drop value is equal to or less than an initially estimated voltage drop value. The method for manufacturing a semiconductor integrated circuit according to claim 10, wherein in the fifth step, using the physical data after arrangement and wiring, the switch transistor is modeled as a resistance and a voltage drop is analyzed.

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