JP2005260846A - Image information apparatus and image data transfer method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image information apparatus the entire processing efficiency of which can be enhanced by maximally utilizing the both side parallel read function and a parallel transfer function of an image reading means. <P>SOLUTION: The image information apparatus provided with: input devices 133 and 134 capable of reading images on both sides of an original in parallel; a local memory for temporarily storing at least one of image data read by the input devices 133 and 134; and a hard disk unit for storing the image data stored in the local memory, is configured such that a transfer section 151 and a PCI transfer controller 152 transferring the image data of both the sides read by the input devices 133 and 134 in parallel to the local memory are provided, and the transfer rate of transferring the image data of both the sides to the local memory can be changed depending on the configuration of an image input output means connected to the image information apparatus by the transfer section 151 and the PCI transfer controller 152. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an image information apparatus such as an image input / output device such as a digital copying machine, a facsimile machine, a printer, a scanner, and a network file server, and a digital multi-function peripheral having a plurality of functions of these, and more particularly to image reading. The present invention relates to a data transfer technique in an image information apparatus including image input / output means such as a primary storage means such as a semiconductor memory for temporarily storing read image data, and a large-capacity secondary storage means such as a hard disk storage device.

With the recent progress of information processing related technology, the data transfer speed with a large capacity storage device such as a hard disk storage device is improved, and the data compression rate and processing speed of the data compression means are remarkably improved. Therefore, in an image information apparatus that can connect such a large-capacity storage device as a secondary storage device, when it has a configuration that can execute input / output of a plurality of image data in parallel, the image data for the secondary storage device How to efficiently store (write) and read the image data has been an issue for improving the processing efficiency of the image information apparatus. Image input / output means connected to the image information device are also very diverse, and the control methods like the previous ones ensure the processing efficiency by making the best use of the capabilities of image input / output means and data compression means. Therefore, in order to obtain the maximum use efficiency according to the processing capacity of the secondary storage device including the primary storage device which is a semiconductor memory paired with the secondary storage device. Resource acquisition / release management technology is provided.
The related prior art disclosed in the patent document will be described below.
First, in the prior art disclosed in Patent Document 1, images on both sides of a document are read in parallel, and the read front and back image data are connected in units of one line and stored in a buffer memory, and then stored according to selection. The image data is separated from the front and back and output to the next stage, or the front and back data is output to the next stage without separation.
In the prior art disclosed in Patent Document 2, the image reading apparatus transfers dummy data to the host computer in response to a request from the host computer, and the host computer measures the transfer time to measure the accurate transfer speed. However, by causing the image to be read in accordance with the transfer speed, intermittent reading of the image is prevented.
In the prior art disclosed in Patent Document 3, images on both sides of a document are read in parallel, and the read front and back image data are connected in units of one line and stored in a buffer memory (image memory) while being read, By transferring the data to the hard disk storage device as it is, the transfer to the hard disk storage device can be started without waiting for completion of writing to the buffer memory.
In the prior art disclosed in Patent Document 4, the image reading means is provided on both sides of the document surface, and when the read image data is transferred to another device outside or inside the device, the transfer speed is set to the document speed. Change according to position.
Japanese Patent No. 2950962 JP 2001-358865 A JP 2002-135544 A JP 2002-199170 A

However, in the conventional techniques including the conventional techniques disclosed in Patent Documents 1 to 4, for example, image data from two image input means corresponding to the front and back surfaces are individually transferred to the secondary storage device side. In this case, that is, when data transfer is performed between a plurality of image input / output means side and secondary storage means side, the function / performance of each image input / output means (parallel reading, reading speed, output speed, etc.) ) Is not enough from the perspective of making the most of it. For example, when individually transferring image data from the front and back sides to the secondary storage unit side from the image reading unit capable of reading the image data on both sides in parallel, generally the image data read from both the front and back sides is sequentially 2 for each side. The current situation is that the data is transferred to the next storage means and stored.
This is an image input / output in which the transfer, storage, and readout processing for the secondary storage means operate in parallel according to the type of operation to be performed (for example, copying operation), although it is improved from the previous one. This is because it was difficult to transfer and save the image data on both sides in parallel due to speed problems depending on the combination of the means. If the image data on both sides was transferred in parallel, In this case, the transfer operation for output on paper has been delayed.
An object of the present invention is to solve such a problem of the prior art. Specifically, when a double-sided original simultaneous reading unit is connected as an image input unit, the function of the image input unit and the parallel transfer function are provided. An object of the present invention is to provide an image information apparatus that can be used to the maximum and improve the processing efficiency of the entire image information apparatus.

In order to solve the above-described problem, according to the first aspect of the present invention, there is provided an image reading unit capable of reading in parallel the images on the front and back sides of a double-sided document, and at least one image data read by the image reading unit. In an image information apparatus comprising primary storage means for temporarily storing image data and secondary storage means for storing image data stored in the primary storage means, both-side images read by the image reading means A transfer means for transferring data to the primary storage means in parallel, and the transfer speed for transferring the image data on both sides to the primary storage means by the transfer means is connected to the image information device; The configuration can be changed according to the configuration of the existing image input / output means.
According to a second aspect of the invention, in the first aspect of the invention, the image data transfer rate to the primary storage unit is changed in accordance with the transferable speed range on the image reading unit side.
According to a third aspect of the present invention, in the first or second aspect of the present invention, transferable speed range information is included as configuration information of an image input / output unit other than the image reading unit, and the transferable speed range is provided. The image data transfer speed to the primary storage means is changed according to the information.
According to a fourth aspect of the present invention, in the first, second, or third aspect of the present invention, the image reading unit according to transferable speed range information of an image input / output unit including the image reading unit. The image data transfer speed between the other image input / output means and the primary storage means is changed.
Further, in the invention described in claim 5, in the invention described in any one of claims 1 to 4, the image data transfer speed can be changed during the image data transfer.
Further, in the invention described in claim 6, in the invention described in any one of claims 1 to 4, double-sided parallel transfer is not possible at any transfer speed within a transferable speed range on the image reading means side. When possible, the image data on both sides is sequentially transferred.
According to the seventh aspect of the present invention, the front and back images of the double-sided document are read in parallel, and the read image data on both sides are transferred and stored via the image input / output interface. In the image data transfer method for performing output transfer in which the transferred image data is transferred via the image input / output interface and output, when the input transfer and the output transfer are performed, the input transferred image The difference between the amount of data and the amount of output transferred data in the image data is monitored, and if the difference exceeds a predetermined amount A, the transfer rate of the input transfer is reduced to increase the transfer rate of the output transfer. If the difference falls below a predetermined amount B, the transfer rate of the input transfer is increased and the transfer rate of the output transfer is decreased.

According to the present invention, in the first aspect of the invention, at least one image data read by the image reading unit capable of reading the front and back images of the double-sided document in parallel is temporarily stored in the primary storage unit. When storing and further storing the image data in the secondary storage means, the double-sided image data read by the image reading means is transferred to the primary storage means in parallel and the double-sided image is transferred to the primary storage means. Since the transfer speed when transferring data can be changed according to the configuration of the image input / output means connected to the image information apparatus, for example, when image output is performed in parallel with image input, image reading is performed. By slowing down the transfer speed of input, it can be used within the range where the duplex scanning function and parallel transfer function of the image scanning means can be used, and the image output side can also be balanced. Can be transferred at the transfer rate, therefore, it is possible to improve the processing efficiency of the entire image information apparatus.
Further, in the second aspect of the invention, in the first aspect of the invention, the image data transfer speed to the primary storage means can be changed according to the transferable speed range on the image reading means side. The transfer rate (bandwidth) of the channel assigned to the data transfer is not unnecessarily high (wide), and the transfer rate is too low (too narrow). No more overflowing. In addition, since the transferable speed range can be referred to when setting the actual transfer speed from the image reading means side, an appropriate transfer speed can be easily set.
According to a third aspect of the invention, in the first or second aspect of the invention, there is transferable speed range information as configuration information of the image input / output means other than the image reading means, and the transferable speed range information. Accordingly, the image data transfer speed from the image reading means side to the primary storage means can be changed, so that the transfer speed can be changed in consideration of the processing efficiency of the entire image information apparatus.
According to a fourth aspect of the present invention, in the first, second, or third aspect of the present invention, in addition to the image reading unit, the image input / output unit including the image reading unit includes information other than the transferable speed range information. Since the image data transfer rate between the image input / output unit and the primary storage unit can be changed, appropriate transfer rate distribution can be performed for each image input / output unit. For example, when image output is also performed in parallel, the image output side can be transferred at a balanced transfer speed by reducing the transfer speed of the image reading input, and the processing efficiency of the entire image information apparatus is improved. Can do.
Further, in the invention according to claim 5, in the invention according to any one of claims 1 to 4, the image data transfer speed can be changed during the image data transfer. Therefore, it is possible to further improve the processing efficiency of the entire image information apparatus.
Further, in the invention described in claim 6, in the invention described in any one of claims 1 to 4, double-sided parallel transfer is impossible at any transfer speed within a transferable speed range on the image reading means side. In this case, since the image data on both sides is sequentially transferred, the processing efficiency of the entire image information apparatus can be improved while maximally utilizing the double-sided simultaneous reading function of the image reading unit.
In the invention according to claim 7, the front and back images of the double-sided document are read in parallel, the read image data on both sides are transferred via the image input / output interface, and stored and transferred. Then, when the output data is transferred via the image input / output interface for output transfer and the output transfer is performed, the data amount of the image data transferred and the output data amount in the image data The difference is monitored, and if the difference exceeds the predetermined amount A, the transfer rate of the input transfer is decreased to increase the transfer rate of the output transfer. If the difference is less than the predetermined amount B, the transfer rate of the input transfer is increased. Since the transfer rate of output transfer is slowed down, the amount of input / output data can be more accurately balanced, and therefore the processing efficiency of the entire image information apparatus can be further improved. That.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the components, types, combinations, shapes, relative positions, and the like described in this embodiment are not merely intended to limit the scope of this description unless otherwise specified, but are merely illustrative examples. .
FIG. 1 is a block diagram of a digital copying machine showing a first embodiment of an image information apparatus of the present invention. With such a configuration, the reading unit 1 first exposes a document surface while scanning it with an exposure lamp 12 movable along the document table 11, and photoelectrically converts the reflected light by a CCD (image sensor) 13. An electric signal corresponding to the intensity of light is obtained. Then, an IPU (image processing unit) 14 performs processing such as shading correction on the electrical signal, A / D conversion to 8-bit digital data, and further performs image processing such as scaling processing and dither processing. The image data is sent to the image forming unit 2 together with the image synchronization signal. FIG. 2 shows the document table viewed from above.
The scanner control unit 15 performs detection of various sensors and control of a drive motor and the like to execute the above process, and sets various parameters in the IPU 14.
Further, in the image forming unit 2, the rotating photosensitive member 22 uniformly charged by the charging charger 21 is exposed with laser light modulated by image data from the writing unit 23. As a result, an electrostatic latent image is formed on the photosensitive member 22, and the developing device 24 develops the toner with toner so that the toner image is generated.
On the other hand, the transfer paper previously fed from the paper feed tray 26 by the paper feed roller 25 and waiting by the registration roller 27 is transported in accordance with the rotation and timing of the photoconductor 22 and is transferred onto the photoconductor by the transfer charger 28. The toner is transferred onto the transfer paper, and the transfer paper is separated from the photoreceptor 22 by the separation charger 29. Further, the toner image on the transfer paper is heated and fixed by the fixing device 30, and discharged to the discharge tray 32 by the discharge roller 31.
On the other hand, the toner image remaining on the photoconductor 22 after the transfer is removed by a cleaning device 33 that is in pressure contact with the photoconductor 22, and the photoconductor 22 is discharged by a charge removal charger 34. The plotter control unit 35 performs detection of various sensors and control of the drive motor and the like in order to execute the above process.

Next, the state of the image synchronization signal output from the IPU 14 in the reading unit 1 will be described with reference to the timing chart shown in FIG.
In FIG. 3, a frame gate signal (/ FGATE) is a signal representing an image effective range for an image region in the sub-scanning direction, and image data during which this signal is low is valid. As shown in FIG. 3, this / FGATE is asserted (to make a signal present state) or negated (to make a no signal state) at the falling edge of the line synchronization signal (/ LSYNC).
Also, / LSYNC is asserted for a predetermined number of clocks at the rising edge of the pixel synchronization signal (PCLK), and image data in the main scanning direction is validated after a predetermined clock after the rising of this signal. The sent image data is one for one cycle of PCLK and is divided into 400 DPI equivalents starting from the position where the range of the arrow in FIG. 3 ends, and is sent as raster format data. . The effective sub-scanning range of image data is usually determined by the transfer paper size.
In FIG. 1, the system control unit 3 detects an input state of the operation unit 4 by a user, and reads a reading unit 1, an image forming unit 2, a storage unit 5, a facsimile (FAX) unit 6, and an interface (I / I). F) Various parameters are set in the unit 7 and a process execution instruction is performed. The state of the entire system is displayed on the operation unit 4. The instruction to the system control unit 3 is made by key input to the operation unit 4 by the user.
The FAX unit 6 encodes the image data delivered from the system control unit 3 based on the data transfer rule of G3 or G4 facsimile communication, and sends it to the telephone line. Further, the data transferred from the telephone line to the FAX unit 6 is restored and converted into binary image data, which is sent to the writing unit 23 of the image forming unit 2.
The I / F unit 7 transmits data in the storage unit 5 to the outside according to an instruction from the system control unit 3, and stores data received from the outside in the storage unit 5.
The selector unit 8 changes the state of the selector according to an instruction from the system control unit 3, and the source of image data at the time of image formation is any of the reading unit 1, the storage unit 5, the FAX unit 6, and the I / F unit 7. Choose from.
In addition, the storage unit 5 normally stores image data of a document input from the IPU 14 and is used for a copy application such as repeat copy or rotated copy. Further, it is also used as a buffer memory for temporarily storing binary image data from the FAX unit 6, and further used as a means for storing unique information input from the input / output device via the I / F unit 7. . The system control unit 3 gives these data storage instructions.

FIG. 4 shows the configuration of the storage unit 5. Hereinafter, the function of the storage unit 5 will be described for each block with reference to FIG.
First, an image input / output DMA controller (DMAC) 51, which is composed of a CPU and a logic circuit, communicates with the memory control unit 52 to receive a command, sets an operation according to the command, It is transmitted as status information to notify the state of the input / output DMAC 51. When an image input command is received, the input image data is packed as memory data in units of 8 pixels according to the input image synchronization signal, and is output to the memory control unit 52 together with the memory access signal as needed. When an image output command is received, the image data from the memory control unit 52 is output in synchronization with the output image synchronization signal.
Next, the image memory 53 is a memory for storing image data, and is composed of a semiconductor storage element such as a DRAM. The storage capacity is 4 Mbytes for the A3 size of 400 DPI / binary image data, 4 Mbytes for electronic sort storage, 6 Mbytes for the data transfer work area, and 2 Mbytes for the image data management area, for a total of 16 Mbytes. The memory control unit 52 controls reading and writing.
The memory control unit 52 is composed of a CPU and a logic circuit, communicates with the system control unit 3 to receive a command, performs operation settings in accordance with the command, and provides status information for notifying the state of the storage unit 5 Send as. The operation commands received from the system control unit 3 include image input, image output, compression, decompression, etc. In the case of image input and image output commands, data is transmitted to the image input / output DMAC 51, and compression related commands In this case, the data is transmitted to the compression / decompression unit 56 via the image transfer DMAC 54 or the code transfer DMAC 55.

FIG. 5 shows the configuration of the address generation unit and the comparison unit of the memory control unit 52. Hereinafter, the function will be described for each block.
First, the input / output image address counter 61 is an address counter that counts up in response to an input / output memory access request signal, and outputs a 22-bit memory address indicating a storage location where the input / output image data is stored. Note that the address is initialized once at the start of memory access.
Next, the transfer image address counter 62 is an address counter that counts up in response to a transfer memory access permission signal, and outputs a 22-bit memory address indicating a storage location where the transfer image data is stored. The address is initialized once when the memory access is started.
Further, the line setting unit 63 has a value for comparing the difference between the input processing line and the transfer line output from the difference calculation unit 65 in the difference comparison unit 64 when the semiconductor memory is used as a buffer at the time of image input. Set by the control unit 3. The difference calculation unit 65 subtracts the number of input / output processing lines output from the image input / output DMAC 51 from the number of transfer processing lines output from the compression / decompression unit 56 when inputting an image, and outputs the result to the difference comparison unit 64.
Further, the difference comparison unit 64 compares the number of difference lines output from the difference calculation unit 65 during image input with the set value output from the line setting unit 63, and if the number of difference lines = the set value, an error signal is output. When the difference line number becomes 0, the transfer request mask signal of the comparison result output to the arbiter 66 is made active. Otherwise, active is not output in the state where the input / output image is not in operation. The arbiter 66 outputs a memory access permission signal for accessing the compression / decompression unit 56. The memory access permission signal is output under the condition that the address comparison signal is active and the input / output memory access signal is inactive.

The address selector 67 is a selector selected by the arbiter, and selects either the input image or the transfer image address. The request mask 68 masks the transfer memory access request signal for accessing the compression / decompression unit 56 in accordance with the comparison result from the difference comparison unit 64 (stops the transfer process), and stops the transfer process.
Further, the access control circuit 69 divides the input physical address into a row address and a column address corresponding to the image memory (for example, DRAM) 53, and outputs it to the 11-bit address bus. Further, in accordance with an access start signal from the arbiter 66, a DRAM control signal (RAS, CAS, WE, etc.) is output.
With such a configuration, the storage unit 5 is initialized by an image input instruction from the system control unit 3 and enters a standby state for image data. When image data is input to the storage unit 5 when the reading unit 1 operates, The memory control unit 52 once writes the image data into the image memory 53. At this time, the number of processing lines of the written image data is counted by the image input / output DMAC 51. At this time, the compression / decompression unit 56 receives the image transfer command and outputs a transfer memory access request signal. However, the request mask is masked by the request mask unit 68 in the memory control unit 52, and the actual memory access is performed. Is not done. Thereafter, when the data input from the image input / output DMAC 51 is completed for one line, the masking of the transfer memory access request signal is released, the reading from the image memory 53 is performed, and the transfer operation of the image data to the compression / decompression unit 56 is performed. Be started. Further, during this operation, the difference calculating unit 65 calculates the difference between the two processing lines, and when it becomes 0, the request masking unit 68 masks the transfer memory access request signal so that the address is not overtaken.

Next, the image transfer DMAC 54 will be described.
The image transfer DMAC 54 is composed of a CPU and a logic circuit, communicates with the memory control unit 52, receives a command, performs operation settings in accordance with the command, and transmits status information for informing the state. When a compression command is received, a memory access request signal is output to the memory control unit 52. When the memory access permission signal is active, image data is received and transferred to the compression / decompression unit 56. In addition, an address counter that counts up in response to a memory access request signal is built in, and a 22-bit memory address indicating a storage location where image data is stored is output.
The code transfer DMAC 55 is composed of a CPU and a logic circuit, communicates with the memory control unit 52, receives a command, sets an operation according to the command, and transmits status information for informing the state. . When an expansion command is received, a memory access request signal is output to the memory control unit 52. When the memory access permission signal is active, image data is received and transferred to the compression / decompression unit 56. In addition, an address counter that counts up in response to a memory access request signal is built in, and a 22-bit memory address indicating a storage location where image data is stored is output.
The compression / decompression unit 56 is composed of a CPU and a logic circuit, communicates with the memory control unit 52, receives a command, performs operation setting according to the command, and transmits status information for informing the state. To do. Binary data is processed by the MH encoding method.
The HDD controller 57 includes a CPU and a logic circuit, communicates with the memory control unit 52, receives a command, and sets an operation according to the command. Also, status information for notifying the state of the hard disk storage device (HDD) 58 as a secondary storage device is transmitted, the status is acquired from the HDD 58, and data transfer with the HDD 58 is performed.
The operation of the entire storage unit 5 is as follows. When inputting an image and accumulating data, the image input / output DMAC 51 writes the image data in a predetermined image area of the image memory 53 in accordance with an instruction from the system control unit 3. 53. At this time, the image transfer DMAC 54 counts the number of image lines.
In this embodiment, the image reading means described in the claims is realized by the image reading unit 1, the primary storage means is realized by the image memory 53, the secondary storage means is realized by the HDD 58, and the transfer means is memory controlled. This is realized by the unit 52, the image transfer DMAC 54, the code transfer DMAC 55, and the like.
With this configuration, in this embodiment, when reading an image, all or part of the read image data is stored in the image memory 53 provided between the reading unit 1 and the HDD 58, and the image data is stored. The image data is transferred to the compression / decompression unit 56 by the image transfer DMAC 54, where data compression is performed by MH encoding, and the encoded image data is transferred to the HDD 58 by the code transfer DMAC 55.

FIG. 6 is a software configuration diagram of a digital multi-function peripheral, showing a second embodiment of the present invention. Here, an image information device in which the functions of each device such as a printer, a copier, a facsimile device, and a scanner are housed in one housing is called a digital multifunction device (hereinafter abbreviated as a multifunction device).
As shown in the figure, this multifunction device includes a program (software) group 71 including an application program group 74 and a platform program group 75, an activation unit 72, and hardware resources 73. When the multifunction device is powered on, the activation unit 72 operates first, and starts the application program group 74 and the platform program group 75. For example, the activation unit 72 reads the application program group 74 and the platform program 75 from an HDD (Hard Disk Storage Device) or the like that is a secondary storage unit, transfers each read program to a memory area, and activates it. The hardware resource 73 includes a black and white laser printer (B & W / LP) 76, a color laser printer (Color / LP) 77, other hardware resources 78 such as a scanner and a facsimile machine, and is not shown. A hardware resource as an operating environment of the program group 71, which will be described later, includes a CPU, a semiconductor memory, and various logic circuits.
Further, the application program 74 includes programs for performing processes specific to user services relating to image reading and image formation, such as a printer application 81, a copy (copying) application 82, a fax application 83, and a scanner application 84.
Further, the platform program 75 interprets the processing request from the application program 74 and issues a request for acquiring the hardware resource 73, manages the one or more hardware resources 73, and manages the one or more hardware resources 73 from the control service program 79. A system resource manager (hereinafter referred to as SRM) 86 is provided for arbitrating acquisition requests.
The control service program 79 includes an operation panel control service program (hereinafter referred to as OCS) 93, a fax control service program (hereinafter referred to as FCS) 94, an engine control service program (hereinafter referred to as ECS) 95, and a system. A control service program (hereinafter referred to as SCS) 98 is provided. The platform program 75 includes an API (application interface) 90 that receives a processing request from the application program 74 using a predefined function.
The SRM 86 and FCUH 99 make a processing request to the hardware resource 73 via the engine I / F 101 using a predefined function.
With this configuration, in this multi-function peripheral, processing commonly required by each application program can be centrally processed by the platform program 75.

FIG. 7 is a hardware configuration diagram of the multifunction machine. Hereinafter, this hardware configuration will be described.
As shown in the figure, this multifunction device includes a controller 110, an operation panel 120, an FCU 121, a USB device 122, an IEEE 1394 device 123, an engine unit 124, and the like. The controller 110 includes a CPU 111, a system memory (MEM-P) 112, a north bridge (hereinafter referred to as NB) 113, a south bridge (hereinafter referred to as SB) 114, an ASIC (dedicated integrated circuit) 115, a local memory ( MEM-C) 116, HDD 117, and the like. The operation panel 120 is connected to the ASIC 115 in the controller 110, and the FCU 121, the USB device 122, the IEEE 1394 device 123, the engine unit 124, and the like are connected to the ASIC 115 via a PCI bus.
In the controller 110, the local memory 116 and the HDD 117 are connected to the ASIC 115, and the CPU 111 and the ASIC 115 are connected via the NB 113. By connecting the CPU 111 and the ASIC 115 via the NB 113 as described above, it is possible to cope with a case where the interface of the CPU 111 is not disclosed. Note that the ASIC 115 and the NB 113 are not connected via a PCI bus, but are connected via an AGP (Accelerated Graphics Port) 118. By connecting via the AGP 118 instead of the low-speed PCI bus in this way, performance degradation when controlling execution of one or more processes (programs) constituting the application program 74 and the platform program 75 shown in FIG. prevent.

The CPU 111 controls the entire multifunction machine. The CPU 111 starts and executes the SRM 86, NCS 91, DCS 92, OCS 93, FCS 94, ECS 95, MCS 96, UCS 97, SCS 98, FCUH 99, and IMH 100 shown in FIG. 6 as processes on the OS, and configures an application program 74. A printer application 81, a copy application 82, a fax application 83, a scanner application 84, and the like are activated and executed.
The NB 113 is a bridge for connecting the CPU 111, the system memory 112, the SB 114, and the ASIC 115, and the system memory 112 is a memory that is used as a drawing memory of the multifunction peripheral. The SB 114 is a bridge for connecting the NB 113 to a ROM (not shown), a PCI bus, and peripheral devices. The local memory 116 is a memory used as a copy image buffer and a code buffer.
The ASIC 115 is a dedicated integrated circuit for image processing having hardware elements for image processing. The HDD 117 is a secondary storage device for storing image data, document data, programs, font data, forms, and the like. The operation panel 120 accepts an input operation from the user and notifies the user. This is an operation unit that performs a directed display. The ASIC 115 has a DMA transfer function for transferring image data, and performs DMA transfer with the engine unit 124 via a PCI bus which is a bit serial communication path.
Specifically, as shown in FIG. 8, the ASIC 115 has two channels of video input DMA controllers (DMAC) and a video output DMA controller, and transfers video data of scanner input 1, scanner input 2, and plotter output in parallel. Can be done. For example, when image data read by a scanner is transferred to the local memory 116 in parallel on both sides (simultaneously), the IMH 100 secures a memory for the transfer image size in the local memory 116 in response to a request from the SRM 86 and transfers the transfer image size. Xw and Yw and the secured memory addresses are set in the video input DMA controller in the ASIC 115 to enable transfer.

FIG. 9 shows a block diagram of the configuration of the engine unit 124 when realizing simultaneous reading of both sides of a double-sided document.
In FIG. 9, an image data control IF controller (hereinafter abbreviated as controller) 131 is directly controlled by the CPU 132. Also provided are image input devices 133 and 134 such as a CCD, a frame memory 135 such as a DRAM for temporarily storing input signals, and an output device 136 such as a GAVD. The controller 131 is connected to a data bus such as PCI, and can output input data to the secondary storage device (external storage device, HDD 117) side and input data from the secondary storage device side. is there. The image input devices 133 and 134 are image reading elements such as a CCD and read simultaneously (in parallel) from both sides of the document.
The frame memory 135 temporarily stores image data from such image input devices 133 and 134. The frame memory 135 is used to adjust the input timing of the front and back surfaces and the data transfer rate to the PCI bus when reading both sides simultaneously. Note that the image data of the front and back surfaces is written in different continuous areas in the frame memory 135, respectively. The DRAM controller 140 performs addressing at the time of writing. Each transfer unit 151 corresponding to the transfer of both front and back image data takes the image data on the front side or the image data on the back side into the buffer memory and passes it to the PCI transfer controller 152 for each transfer unit.
In this embodiment, the image reading unit described in the claims is realized by the engine unit 124, the primary storage unit is realized by the local memory 116, the secondary storage unit is realized by the HDD 117, and the transfer unit is the transfer unit 151. , PCI transfer controller 152, PCI interface 153, and PCI bus.
Hereinafter, examples of the present invention will be described in the case of the second embodiment.

In the MFP of the second embodiment, writing of input image data to the frame memory 135 and reading of input image data from the frame memory 135 can be executed in parallel. It is assumed that writing of front surface image data to 135 and writing of back surface image data can be executed in parallel.
First, a data flow when reading an image on a document will be described with reference to FIG.
The image reading operation is divided into the following two operations.
(1) The image data input by the image input devices 133 and 134 is written in the frame memory 135 in parallel.
(2) Front and back image data stored in the frame memory 135 is read in parallel, image processing such as data compression (data conversion) is performed, transferred in parallel to the local memory 116 via the data bus, and further transferred to the HDD 117. Store.
However, when there is no frame memory depending on the device configuration or when the memory capacity of the frame memory is small, it is possible to transfer directly to the data bus without dividing it into two operations as in (1) and (2) above. is there. Hereinafter, (1) will be described with reference to surface reading as an example.
First, an image signal input from the front surface image input device 133 is input to the image data input IF 138 via the shading processing unit 200. Then, the image data (image signal) is transferred to the frame memory 135 via the DRAM controller 140. In the frame memory 135, the input image data is addressed by the DRAM controller 140 and sequentially written and stored in a continuous area for surface data.

Next, (2) will be described.
First, the transfer unit in the surface image data stored in the frame memory 135 is transferred to the PCI transfer controller 152 by the transfer unit 151 a via the various image data processing units 141 to 145. The image data is transferred to the local memory 116 via the PCI data bus by the PCI transfer controller 152 and stored in the HDD 117. The image data processing units include mask processing units 141 and 146, filter processing units 142 and 147, scaling processing units 143 and 148, area expansion / reduction processing units 144 and 149, and image compression processing units 145 and 150. is there. The PCI transfer controller 152 transfers the two image data output from the transfer unit 151 to the local memory 116 via the PCI data bus in a bit serial manner. At this time, it is possible to set a data capacity and an image data transfer speed necessary for outputting each image data to the local memory 116. Also, channel setting is performed so that the transfer destination via the PCI bus is, for example, DMAC1 or DMAC2 (see FIG. 8).
In this embodiment, data transfer channels are compared by using a communication means capable of transmitting and receiving a mixture of a plurality of data through a single data path, such as a PCI bus or USB, in a portion that executes image data transfer. It can be easily installed and the data transfer can be controlled. It is assumed that the image data input by the image input devices 133 and 134 has different input start timings, data capacities, image data transfer rates, and the like depending on the physical arrangement of image reading elements such as CCDs. Therefore, two transfer units 151 are provided in association with both front and back image data, and the PCI transfer controller 152 can receive transfer requests from both in parallel, and transfer image data asynchronously for each individual image data. Processing is performed. In addition to synchronously transferring a plurality of image data at the same time, they are individually transferred in parallel and asynchronously (simultaneously). With this configuration, the image data transfer method can be easily changed in accordance with the double-sided original reading function, data transfer speed, and reading timing.

FIG. 10 shows an operation flow when reading an image from a document. The operation flow will be described below with reference to FIG. This operation flow is programmed as a process (program) in the scanner application 84 and the engine unit 124, and the CPU 111 makes a request to the engine unit 124 using the platform program 75 such as the SRM 86 or ECS 95 according to the scanner application 84. The CPU 132 in the engine unit 124 continues to execute this operation flow according to the request.
First, the user instructs double-sided simultaneous reading from the operation panel 120, and the CPU 111 that recognizes the instruction notifies the CPU 132 in the engine unit 124 of the fact and also indicates the free area size of the local memory 116 and the like. Notify (S1). Here, the CPU 132 determines the transfer rate of the data transfer via the PCI bus and sets it in the PCI transfer controller 152.
Specifically, the device information of the image information apparatus is acquired from the CPU 111 side, the transfer speed range (TransRateMin_Scan to TransRateMax_Scan) that can be transferred by the image reading means, and the transfer speed range (TransRateMin_Iio) that can be transferred by other image input / output means. ~ TransRateMax_Iio) and the transfer speed range (TransRateMin_Hdd ~ TransRateMax_Hdd) that can be processed by the secondary storage means (local memory 116 and HDD 117) are compared, and the actual transfer speed from the transferable range (image reading means-storage device) TransRate1 between image input / output means and storage device TransRate2).
At this time, TransRate1 and TransRate2 are considered so that the transfer from the image reading means and the transfer of the image input / output means are performed in parallel so that TransRate1 + TransRate2 is within the transfer speed range that can be processed by the secondary storage means. To do. Also, TransRate1 and TransRate2 can be freely selected depending on the priority of the transfer processing as long as it is within the transfer speed range that can be processed by the secondary storage means. For example, if the priority of image reading is the maximum, TransRateMax_Scan is selected as TransRate1, and the remaining bandwidth is used by the image input / output means.

Subsequently, the CPU 132 activates a front side reading process (consisting of a program) and a back side reading process executed by the CPU 132 itself in order to read the front and back image data in parallel. The data transfer process shown in FIG. 11 is also started at this time. Then, in the front surface reading process, if the original is conveyed to a predetermined reading position (Y in S2), the front surface reading is started, and the DRAM controller 140 stores the image data in the frame memory 135 (S3).
Thus, when the reading of the surface image data and the transfer of the surface image data described later are completed (Y in S4), the surface reading process is terminated.
On the other hand, in the back side reading process, if the document is conveyed to a predetermined reading position (Y in S5), the back side reading is started, and the DRAM controller 140 frames the back side image data in parallel with the storage of the front side image data. Store in the memory 135 (S6).
Thus, when the reading of the back surface image data and the transfer of the back surface image data to the local memory 116 by the data transfer process are completed (Y in S7), the CPU 132 determines whether or not the front surface reading end flag set by the data transfer process is set. If it is set, the presence of the next original is confirmed (S8). If there is a next original (Y in S8), double-sided simultaneous reading is executed again from step S1, and if there is no next original, the process ends.

FIG. 11 shows the outline of the operation flow of the surface reading process and the operation flow of the data transfer process for transferring the image data of the surface. Hereinafter, this operation flow will be described. Since the back side is the same, the operation flow and description are omitted.
First, in the surface reading process, as described above, after starting, if the document is conveyed to a predetermined reading position, the surface reading is started (S11), and the DRAM controller 140 stores the read image data in the frame memory 135. To do. When the reading of the original image is completed and the reading of the surface image data is completed (Y in S12), the CPU 132 ends the surface reading process.
On the other hand, in the data transfer process, after activation, the process waits until the condition for starting data transfer is satisfied (N → S13 in S13). It is assumed that data transfer start conditions are set in advance. For example, the data transfer start condition is “the image reading process has started” or “the number of lines written to the frame memory has reached a predetermined value”.
As a result of the determination, if the data transfer start condition is satisfied (Y in S13), data transfer is started at the transfer rate (transfer rate) set in the PCI transfer controller 152 (S14). Specifically, the DRAM controller 140 reads the image data stored in the frame memory 135 in order from the top, and the image data processing units 141 to 145 perform image processing on the image data, respectively. The transfer unit 151a sequentially captures and transfers the data to the PCI transfer controller 152 for each transfer unit. Then, the PCI transfer controller 152 uses the channel whose destination is DMAC1, sets the transfer speed of the channel to a set value, and transfers the image data to the local memory 116 via the PCI bus. Thereafter, the process is continued until the surface data is transferred (N → S15 in S15). When the transfer is completed (Y in S15), the data transfer process is terminated.
Thus, according to this embodiment, the transfer speed when transferring both-side image data to the secondary storage means side is determined by the configuration (including performance) of the image input / output means and storage means connected to the image information apparatus. ), The image data read in parallel from both sides of the document is transferred to the secondary storage device side in parallel and, for example, when image output is also performed in parallel, By reducing the transfer speed, the image output side can also be transferred at a balanced transfer speed, so that the processing efficiency of the entire image information apparatus can be improved.
In addition, since the image data transfer speed to the secondary storage means can be changed according to the transferable speed range on the image reading means side, the transfer rate (bandwidth) of the channel allocated for data transfer from the image reading means side is unnecessary. Therefore, it is possible to prevent the image data from being too high (wide), and from being too low (too narrow) to transfer and to prevent the image data from overflowing from the buffer memory on the image reading means side.

In this embodiment, the transfer speed can be changed during transfer in the first embodiment. FIG. 12 shows an operation flow of the second embodiment. The operation flow will be described below with reference to FIG.
First, the user gives an instruction for copying by double-sided simultaneous reading, for example, using the operation panel 120, and the CPU 111 that recognizes the instruction notifies the CPU 132 in the engine unit 124 of that. Thereby, the CPU 132 determines, for example, the transfer speed of the transfer via the PCI bus of each input / output unit related to the copying operation, and sets it in the PCI transfer controller 152 (S21).
Specifically, the device information of the image information apparatus is acquired from the CPU 111 side, the transfer speed range (TransRateMin_Scan to TransRateMax_Scan) that can be transferred by the image reading means, and the transfer speed range (TransRateMin_Iio) that can be transferred by other image input / output means. ~ TransRateMax_Iio) and the secondary storage means side (local memory 116 and HDD 117) compare the transfer speed range (TransRateMin_Hdd to TransRateMax_Hdd) that can be input / output (written or read), and the actual transfer speed from the transferable range (TransRate1 between image reading means and storage device and TransRate2 between image input / output means and storage device) are determined.
After the setting, the input / output operation is started (S22). In the case of copying, as shown in the first embodiment, the front and back image data is transferred in parallel from the image reading unit to the local memory 116 via the PCI bus, and simultaneously from the local memory 116 to the PCI. The print data is transferred to the image forming unit in the engine unit 124 via the bus.
During transfer (N in S23), if there is a transfer speed change instruction from the CPU 111 (Y in S24), the CPU 132 instructs the PCI transfer controller 152 to change the transfer speed each time (S25) and continue the transfer. To do. The CPU 111 monitors the amount of data stored in the local memory 116 from the image reading unit side and the amount of data output to the image forming unit side from the point of time when the predetermined amount is stored. If the predetermined amount A is increased, the transfer speed from the image reading unit is reduced, and the transfer rate to the image forming unit is increased accordingly. When the value obtained by subtracting the output data amount from the stored data amount becomes equal to or less than the predetermined amount B, the transfer rate from the image reading unit is increased, and the transfer rate to the image forming unit side is decreased accordingly.
Thereafter, when the transfer is completed (Y in S23), input / output is stopped (S24), and this operation flow is terminated.
Thus, according to this embodiment, the transfer speed of image data transferred from the image reading means and the transfer speed of image data transferred to the image forming means (image output means) can be changed during transfer. The balance of the input / output data amount can be balanced according to the situation. Therefore, there is no waiting for image input or waiting for image output, and the processing efficiency of the entire image information apparatus can be further improved.

In this embodiment, when double-sided parallel transfer is impossible at any transfer speed within the transferable speed range on the image reading means side in the first or second embodiment, the image data on both sides are sequentially transferred.
FIG. 13 shows an operation flow when reading an image from a document in this embodiment. The operation flow will be described below with reference to FIG. This operation flow is programmed as a process (program) in the scanner application 84 and the engine unit 124, and the CPU 111 makes a request to the engine unit 124 using the platform program 75 such as the SRM 86 or ECS 95 according to the scanner application 84. The CPU 132 in the engine unit 124 continues to execute this operation flow according to the request.
First, in the engine unit 124, the CPU 132 resets the surface reading end flag (UpsideReadFlag) in the DRAM 155 (S31).
Thereafter, the user gives an instruction to read both sides simultaneously using the operation panel 120, and the CPU 111 that has recognized the instruction notifies the CPU 132 in the engine unit 124 of that fact (S32). Thereby, the CPU 132 determines whether or not the configuration allows simultaneous double-sided transfer (parallel transfer) using configuration information acquired in advance from the CPU 111 side (S33). For example, when the storage capacity of the local memory 116 at the transfer destination is small, and any transfer speed within the transferable speed range on the image reading means side overflows at the same time, or when there is only one channel on the bus. Therefore, it is determined that simultaneous transfer cannot be performed.
If double-sided simultaneous transfer (parallel transfer) is possible (Y in S33), the sequential transfer flag (SeqTranceFlag) in the DRAM 155 is reset (S34). If simultaneous transfer is not possible (N in S33), A sequential transfer flag (SeqTranceFlag) is set (S35).
Next, the CPU 132 activates a front side reading process and a back side reading process executed by the CPU 132 itself in order to read the front and back image data in parallel. The data transfer process shown in FIG. 14 is also started at this time. In the front surface reading process, if the document is conveyed to a predetermined reading position (Y in S36), the front surface reading is started, and the DRAM controller 140 stores the image data in the frame memory 135 (S37).
Thus, when the reading of the surface image data and the transfer of the surface image data described later are completed (Y in S38), this surface reading process is terminated.
On the other hand, in the back side reading process, if the original is conveyed to a predetermined reading position (Y in S39), the back side reading is started, and the DRAM controller 140 frames the back side image data in parallel with the storage of the front side image data. Store in the memory 135 (S40).
Thus, when the reading of the back surface image data and the transfer of the back surface image data to the local memory 116 by the data transfer process are completed (Y in S41), the CPU 132 determines whether or not the front surface reading end flag set by the data transfer process is set. If it is set, the presence of the next original is confirmed (S42). If there is a next original (Y in S42), double-sided simultaneous reading is executed again from step S31, and if there is no next original, the process is terminated.

FIG. 14 shows an outline of an operation flow of the surface reading process and an operation flow of the surface data transfer process. Hereinafter, this operation flow will be described.
First, in the surface reading process, as described above, after starting, if the document is conveyed to a predetermined reading position, the surface reading is started (S51), and the read image data is stored in the frame memory 135 by the DRAM controller 140. To do. When the reading of the document is completed and the reading of the surface image data is completed (Y in S52), the CPU 132 ends the surface reading process.
On the other hand, in the data transfer process, after starting, the process waits until the condition for starting data transfer is satisfied (N → S53 in S53). It is assumed that data transfer start conditions are set in advance. For example, the data transfer start condition is “the image reading process has started” or “the number of lines written to the frame memory has reached a predetermined value”.
As a result of the determination, if the conditions for starting data transfer are satisfied (Y in S53), data transfer is started (S54). Specifically, the DRAM controller 140 reads the image data of the front surface stored in the frame memory 135 in order from the top, and the image data processing units 141 to 145 perform image processing on the image data, respectively. The transfer unit 151a sequentially fetches data and passes it to the PCI transfer controller 152 for each transfer unit. Then, the PCI transfer controller 152 transfers the image data to the local memory 116 via the PCI bus at a set transfer speed using a channel whose destination is DMAC1. Thereafter, the process continues until the surface data is transferred (N → S55 in S55). When the transfer is completed (Y in S55), a surface reading end flag (UpsideReadFlag) is set (S56).

Next, the outline of the operation flow of the back surface reading process and the operation flow of the back surface data transfer process will be described with reference to FIG.
First, as described above, the back side reading process is started. If the document is conveyed to a predetermined reading position after startup as described above, the back side reading is started (S61), and the DRAM controller 140 stores the read image data in the frame memory 135. To do. When the reading of the original is completed and the reading of the back surface image data is completed (Y in S62), the back surface reading process is ended.
On the other hand, in the back side data transfer process, after the activation, the process waits until the data transfer start condition is satisfied (N → S63 in S63). It is assumed that data transfer start conditions are set in advance. For example, the data transfer start condition is “the image reading process has started” or “the number of lines written to the frame memory has reached a predetermined value”.
As a result of the determination, if the data transfer start condition is satisfied (Y in S63), it is determined whether or not the sequential transfer flag (SeqTranceFlag) is set. If it is set, the surface reading end flag (UpsideReadFlag) is determined. Is set until Y is set (Y → S64 in S64). On the other hand, if the sequential transfer flag is not set or the front reading end flag is set (N in S64), data transfer is started (S65). Specifically, the DRAM controller 140 reads the back side image data stored in the frame memory 135 in order from the top, and the image data processing units 146 to 150 perform image processing on the image data, respectively. The transfer unit 151b sequentially fetches data and passes it to the PCI transfer controller 152 for each transfer unit. Then, the PCI transfer controller 152 transfers the image data to the local memory 116 via the PCI bus at a set transfer speed using a channel whose destination is DMAC2. Thereafter, the process continues until the back side data is transferred (N → S66 in S66). When the transfer is completed (Y in S66), the data transfer process is terminated.
Thus, according to this embodiment, the configuration of the device is automatically determined, and when parallel transfer of double-sided data in a possible transfer speed range is possible according to the configuration, it is performed in parallel from both sides of the document. Since the read image data is transferred to the secondary storage device in parallel at the set transfer speed, and when the parallel transfer of the double-sided data in the possible transfer speed range is impossible, the sequential transfer can be performed. It is possible to maximize the function of the image input means and improve the processing efficiency of the entire image information apparatus.

1 is a configuration diagram of a digital copying machine showing a first embodiment of the present invention. FIG. 1 is an explanatory diagram of a main part of a digital copying machine showing a first embodiment of the present invention. 2 is a timing chart of the main part of the digital copying machine showing the first embodiment of the present invention. 1 is a configuration block diagram of a main part of a digital copying machine showing a first embodiment of the present invention. FIG. 3 is a block diagram showing another configuration of the main part of the digital copying machine showing the first embodiment of the present invention. FIG. 5 is a software configuration diagram of a digital multi-function peripheral showing a second embodiment of the present invention. FIG. 6 is a hardware configuration diagram of a digital multi-function peripheral showing a second embodiment of the present invention. Explanatory drawing of the principal part of a digital multi-functional peripheral showing a second embodiment of the present invention. The block diagram of the configuration of the main part of the digital multi-function peripheral showing the second embodiment of the present invention. FIG. 3 is an operation flowchart of the main part of the digital multi-function peripheral showing the first embodiment of the present invention. FIG. 9 is another operation flowchart of the main part of the digital multi-function peripheral according to the first embodiment of the present invention. FIG. 9 is an operation flowchart of the main part of the digital multi-function peripheral showing a second embodiment of the present invention. The operation | movement flowchart of the digital multifunction machine principal part which shows the 3rd Example of this invention. The other operation | movement flowchart of the digital multifunctional machine principal part which shows the 3rd Example of this invention. The other operation | movement flowchart of the digital multifunctional machine principal part which shows the 3rd Example of this invention.

Explanation of symbols

  110 controller, 111 CPU, 115 ASIC, 116 local memory, 117 hard disk storage device, 120 operation panel, 124 engine unit, 132 CPU, 133 image input device, 134 image input device, 135 frame memory, 145 image compression processing unit, 151 Transfer unit, 152 PCI transfer controller, 155 DRAM

Claims (7)

  Image reading means capable of reading the front and back images of a double-sided document in parallel, primary storage means for temporarily storing at least one image data read by the image reading means, and the primary storage means And a secondary storage means for storing the image data stored in the image data apparatus, further comprising a transfer means for transferring the image data on both sides read by the image reading means to the primary storage means in parallel. In addition, the transfer speed when the image data on both sides is transferred to the primary storage means by the transfer means can be changed according to the configuration of the image input / output means connected to the image information apparatus. An image information device.   2. The image information apparatus according to claim 1, wherein an image data transfer rate to the primary storage unit is changed in accordance with a transferable rate range on the image reading unit side.   3. The image information apparatus according to claim 1, wherein transferable speed range information is included as configuration information of image input / output means other than the image reading means, and the primary storage is performed according to the transferable speed range information. An image information apparatus characterized by changing an image data transfer speed to the means.   4. The image information apparatus according to claim 1, 2, or 3, wherein the image input / output means other than the image reading means and the image input / output means other than the image reading means according to the transferable speed range information of the image input / output means including the image reading means An image information apparatus for changing an image data transfer speed with a primary storage means.   5. The image information apparatus according to claim 1, wherein the image data transfer speed can be changed during image data transfer.   5. The image information apparatus according to claim 1, wherein when double-sided parallel transfer is impossible at any transfer speed within a transferable speed range on the image reading unit side, the double-sided image is displayed. An image information apparatus for sequentially transferring data.   In parallel with the input transfer that reads the images on the front and back sides of a double-sided document in parallel, transfers the read image data on both sides via an image input / output interface, and stores the input image data. In the image data transfer method for performing output transfer to be transferred and output via the image input / output interface, when the input transfer and the output transfer are performed, the amount of image data transferred and the The difference between the amount of data transferred and output is monitored, and if the difference exceeds a predetermined amount A, the transfer rate of the input transfer is decreased to increase the transfer rate of the output transfer, and the difference is less than the predetermined amount B. A transfer rate of the input transfer is increased, and a transfer rate of the output transfer is decreased.

Images