JP2005251780A - Semiconductor circuit component and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a small and thin semiconductor circuit component with high density, in which a degree of freedom on arrangement of a mounting component such as a semiconductor device can be improved since a support by a rigid body becomes unnecessary as a completed semiconductor circuit component, by using a flexible thin multilayer wiring board to which all wiring layers are IVH-connected without easily being crushed even if it is treated as a multilayer wiring board single body. <P>SOLUTION: In the semiconductor circuit component, all upper and lower wiring layers in the multilayer wiring board 24 formed of flexible insulating substrates 21 are IVH-connected, and the semiconductor device 25 is loaded at least on one face. In the semiconductor circuit component, support by the rigid body becomes unnecessary. Thus, operation effect that the flexibility on arrangement of the mounting component such as the semiconductor device 25 can be obtained. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a flip-chip type semiconductor circuit component in which a semiconductor element is mounted on a multilayer wiring board and a manufacturing method thereof.

  A conventional method for manufacturing a semiconductor circuit component is shown in FIG.

  7A to 7E are cross-sectional views showing a conventional method for manufacturing a semiconductor circuit component.

  In FIG. 7A, a photosensitive solder resist 2 is printed on the entire surface of the metal plate 1, and a pattern mask is placed to form an opening of the input / output terminal 3, and electrolytic copper plating is applied to the opening. Form a layer. Then, a wiring pattern 3a is formed on the surface of the solder resist 2, and a photosensitive insulating resin is applied on the solder resist 2 by screen printing, a roll coater, or the like, and the via hole 5 is opened by the pattern mask to form the first insulating film. The conductive resin layer 4 is formed. Then, the above steps are repeated using a method in which the wiring pattern 3a and the input / output terminals 3 are formed on the solder resist 2, and the first wiring pattern 6, the via conductor 7, the second insulating resin layer 8, and the via hole 5a. Then, the second wiring pattern 9 and the via conductor 7a are formed.

  Next, in FIG. 7B, the cover film formed on the surface of the metal plate 1 is peeled off, a photosensitive dry film is attached, a pattern mask is placed, and exposure and development are performed. An opening is formed in a portion corresponding to the terminal 3. Then, the metal plate 1 in the opening is removed by etching. A probe 14 is inserted into the hole 13 formed by removing the metal plate 1 to inspect the disconnection and short circuit between the input / output terminal 3 and the connection terminal of the semiconductor element 11.

  Next, in FIG.7 (c), the semiconductor element 11 is mounted on the insulating resin body via the connection member 10a, and it connects by heating by reflow etc. FIG. Then, the semiconductor element 11 is resin-sealed with a sealing resin 12.

  Next, in FIG. 7D, the entire metal plate 1 is removed by etching, and the semiconductor circuit component 10 is formed. For example, in the case of a large number of pieces, it is separated into pieces by a die-sin saw or the like.

  Next, in FIG. 7E, solder balls 15 are formed as external terminals on the input / output terminals 3 of the separated semiconductor circuit component 10.

As prior art document information related to the invention of this application, for example, Patent Document 1 is known.
JP 2002-151622 A

  However, in the above conventional configuration, the build-up insulating resin used for the build-up substrate is used as the insulating resin of the insulating resin body in which the circuit is formed by the wiring pattern 3a and the via conductors 7 and 7a laminated on the metal plate 1. Because it is used, a very thin multilayer wiring board can be formed, but the multilayer wiring board itself has a material characteristic that it is very weak in mechanical strength and is not flexible so that it is brittle and easy to break. Therefore, even when the semiconductor circuit component 10 is completed during the manufacturing process, there is always a problem that it is necessary to support the metal plate 1, the semiconductor element 11, or the sealing resin 12 after mounting with a rigid body.

  The present invention provides a completed semiconductor circuit component by using a thin multilayer wiring board that is flexible and does not easily break even when handled as a single multilayer wiring board, and all wiring layers are IVH-connected. Therefore, the object of the present invention is to provide a semiconductor circuit component having a high density, a small size, and a small thickness.

  In order to achieve this object, the present invention has the following configuration.

  The invention according to claim 1 of the present invention is a semiconductor circuit component in which all the wiring layers between the upper and lower layers of a multilayer wiring board made of an insulating base material having flexibility are IVH-connected, and a semiconductor element is mounted on at least one surface. In addition, since the semiconductor circuit component does not need to be supported by a rigid body, the operational effect that the degree of freedom of arrangement of mounting components such as semiconductor elements is improved can be obtained.

  The invention according to claim 2 is the semiconductor circuit component according to claim 1, wherein an adhesive that maintains flexibility even when the insulating substrate is cured on both sides of the organic film is applied. Even if it is handled as a single substrate, the effect of maintaining flexibility without being easily crushed can be obtained.

  The invention according to claim 3 is the semiconductor circuit component according to claim 1 or 2 in which the semiconductor element is mounted by wire bonding or flip chip bonding, and the densification and miniaturization and thinning of the semiconductor circuit component are improved. The effect is obtained.

  According to a fourth aspect of the present invention, there is provided the semiconductor circuit component according to any one of the first to third aspects, wherein the surface layer wiring is embedded so that the surface of the multilayer wiring board is flat. The effect of improving chip mountability can be obtained.

  The invention according to claim 5 is the semiconductor circuit component according to any one of claims 1 to 4, wherein at least one semiconductor element or passive component device is mounted on at least one surface of the multilayer wiring board. An effect is obtained that makes it possible to manufacture a circuit system that is difficult to realize with only elements as a single semiconductor circuit component.

  The invention described in claim 6 includes a step of forming a hole in an insulating substrate made of an organic film having an adhesive applied on both sides, a step of filling a conductive material inside the hole, and the conductive material. A step of affixing a copper foil as a wiring layer on both surfaces of an insulating base material filled with a step of forming a multilayer wiring board by repeating a step of patterning the copper foil. A step of bringing a probe into contact with the electrode terminal formed on the substrate and conducting an electrical inspection, and a step of mounting the semiconductor element on the multilayer wiring board having predetermined characteristics obtained by the electrical inspection and sealing the semiconductor element with a sealing resin A method of manufacturing a semiconductor circuit component including the above-described effects can be obtained, which makes it possible to manufacture a flexible multilayer wiring board.

  The invention according to claim 7 includes a step of forming a wiring pattern on one side of a metal plate, a step of forming a hole in an insulating base material made of an organic film coated with an adhesive on both sides, and an inside of the hole. Repeating the step of filling the conductive material and the step of removing the metal plates on both sides by pasting the surfaces on which the wiring patterns of the metal plate are formed on both sides of the insulating base material filled with the conductive material A step of forming a multilayer wiring board, a step of contacting a probe with an electrode terminal formed on the multilayer wiring board and conducting an electrical inspection, and a semiconductor element on the multilayer wiring board that has obtained predetermined characteristics by the electrical inspection. A method of manufacturing a semiconductor circuit component including a step of mounting and sealing the semiconductor element with a sealing resin, and an effect of enabling manufacture of a multilayer wiring board in which surface layer wiring is embedded is obtained.

  The invention described in claim 8 includes a step of forming a wiring pattern on one side of a metal plate, a step of forming a hole in an insulating substrate made of an organic film coated with an adhesive on both sides, and an inside of the hole. A process of filling a conductive material and a process of attaching a surface on which the wiring pattern of the metal plate is formed on both surfaces of an insulating base material filled with the conductive material and removing the metal plate on one side are repeated to form a multilayer Forming a wiring board, forming a hole in the metal plate left on the multilayer wiring board, inserting a probe into the hole, and performing an electrical inspection, and obtaining the predetermined characteristics by the electrical inspection. A method for manufacturing a semiconductor circuit component, comprising a step of mounting a semiconductor element on a multilayer wiring board and sealing the semiconductor element with a sealing resin, and a step of removing all of the remaining metal plate. To function as a body, especially Action and effect of facilitating the fabrication of semiconductor circuit components is obtained in Ndoringu surface.

  As described above, the present invention has a flexible insulating base material and uses at least one or both of one or both sides using a multilayer wiring board in which at least two wiring layers are all IVH-connected. Even though it is a thin multi-layer wiring board, it has a configuration in which a semiconductor element is mounted, so that it has flexibility, so even if it is completed as a semiconductor circuit component during the manufacturing process, it is fragile and crushed This eliminates the need for support by a rigid body such as a metal plate, a semiconductor element, or a sealing resin after mounting, and can improve the degree of freedom of placement of mounting components such as semiconductor elements. The effect that a thin semiconductor circuit component can be provided is obtained.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1)
1A to 1C are cross-sectional views showing the structure of the semiconductor circuit component according to the first embodiment of the present invention.

  The insulating substrate 21 shown in FIG. 1C has a structure in which an adhesive 21b having flexibility is applied to both surfaces of the organic film 21a even after curing, and a wiring pattern 22a is formed on the adhesive 21b. Is formed. Further, vias 23 for electrically connecting the wiring patterns 22a formed on both surfaces of the insulating base material 21 are formed, and the multilayer wiring shown in FIGS. 1A and 1B is formed by laminating the double-sided substrates. A substrate 24 is formed, and wiring connection between adjacent layers is realized.

  The organic film 21a is subjected to surface modification by discharge treatment or the like in order to improve adhesion using a polyimide film having a thickness of 12.5 μm in consideration of heat resistance in the manufacturing process and component mounting process, and cured. Even so, the adhesive 21b made of epoxy-modified polyimide having flexibility is applied to a thickness of about 5 to 10 μm. Further, an aramid film may be used as the organic film 21a having heat resistance, and an epoxy adhesive may be used as the adhesive 21b.

  The wiring pattern 22a is formed by attaching a copper foil to the adhesive 21b and performing a photolithography process and an etching process. The copper foil used at this time is an electrolytic copper foil whose both surfaces are roughened, but in order to realize the line width of the wiring pattern 22a of about 25 μm, the thickness is 9 μm, and the roughening treatment is Ra and less than 2 μm. The via 23 is formed by forming a via hole having a diameter of about 50 μm and filling with a copper conductive paste. The semiconductor element 25 is die-bonded face-up on the multilayer wiring board 24 thus formed, mounted by wire bonding with a gold wire 26, molded with a sealing resin 27, and externally attached to the back surface of the multilayer wiring board 24. By forming solder balls as the terminals 28, the semiconductor circuit component according to the first embodiment of the present invention shown in FIG.

  Although FIG. 1A shows a four-layer wiring board as the multilayer wiring board 24, the number of layers is not limited to this. Further, as the multilayer wiring board 24, a double-sided board as shown in FIG. 1A shows only one element as the semiconductor element 25, a plurality of semiconductor elements 25 and other component devices may be mounted. Although the solder balls are shown as the external terminals 28, other external terminals such as a simple electrode such as LGA or a pin terminal such as PGA may be used.

  Further, the multilayer wiring board 24 used in the first embodiment of the present invention has a very thin total thickness, and in order to take advantage of this advantage, to further reduce the total thickness as a semiconductor circuit component, FIG. As shown, a structure in which the semiconductor element 25 is flip-chip mounted via conductive bumps 29 is preferable. Although FIG. 1B also shows a four-layer wiring board as the multilayer wiring board 24, the number of layers is not limited to this. Further, as the multilayer wiring board 24, a double-sided board as shown in FIG.

  FIG. 2 is a cross-sectional view showing the structure of another semiconductor circuit component according to Embodiment 1 of the present invention. As shown in FIG. 2, a plurality of semiconductor elements 25 a and 25 b and other component devices 30 may be mounted on both surfaces of the multilayer wiring board 24. 1B shows solder balls as the external terminals 28, but external terminals of other shapes such as a simple electrode such as LGA, a pin terminal such as PGA, and an electrode using the substrate end face as shown in FIG. It goes without saying that the semiconductor circuit component according to the first embodiment of the present invention can be configured even with 28.

  Hereinafter, a method for manufacturing a semiconductor circuit component according to the first embodiment of the present invention will be described with reference to the drawings. 3A to 3G are cross-sectional views showing a method for manufacturing a semiconductor circuit component in the first embodiment of the present invention.

  In FIG. 3 (a), an epoxy-modified polyimide that is flexible even after curing by subjecting both sides of an organic film made of a polyimide film with a thickness of 12.5 μm to surface adhesion by electrical discharge treatment to improve adhesion. An insulating substrate 21 is prepared by applying an adhesive composed of 5 to 10 μm in thickness and laminating a PEN (polyethylene naphthalate) film having a thickness of 9 μm on both sides as a protective film.

  Since this insulating base material 21 is very thin with a total thickness of about 45 to 50 μm, tension is applied to the insulating base material 21 so as to remove slack and wrinkles of the insulating base material 21 as a holding method when processing the through-holes. Holding was done by calling from all sides. The through hole is processed using a YAG laser having a wavelength of 355 nm, the hole diameter on the upper surface of the PEN film is 65 to 75 μm, and the smallest hole diameter from the lower surface side of the PEN film is generated in the adhesive layer and has a shape of about 40 to 50 μm. Processing was carried out as follows. Although the YAG laser is used in the first embodiment, other processing methods such as a carbon dioxide laser and punching can be applied depending on the material, thickness, and diameter of the through hole of the insulating base material 21. It is not limited to the YAG laser method. And the processing waste adhering to the surface of a PEN film was processed after processing.

  In FIG.3 (b), the copper conductive paste was filled in the formed through-hole by the squeezing method. Here, filling is performed while performing vacuum suction from the surface opposite to the surface to be squeezed, and the filling property of the copper conductive paste is ensured while preventing the occurrence of filling failure in which air enters the copper conductive paste. In the first embodiment, two-way reciprocating squeezing is repeated to improve filling reliability.

  The copper conductive paste to be filled is composed of a mixed material composed of copper powder having a particle size of about 5 μm, an epoxy resin, and an amine curing agent. The surface of the copper powder is used for preventing oxidation and improving electrical bonding. Surface treatment is applied. Moreover, you may use the copper conductive paste which mixed copper powder with a particle size of about 1-1.5 micrometers other than copper powder with a particle size of about 5 micrometers in order to raise the filling density of copper powder. Then, the PEN film laminated as the protective film was peeled off, and the paste adhered to the surface of the insulating base material 21 other than the through holes was removed to form the vias 23.

In FIG. 3C, the copper foil 22 for forming the wiring pattern 22a is arranged on both surfaces of the insulating base material 21 in which the vias 23 are formed. The copper foil 22 used at this time was an electrolytic copper foil whose both surfaces were roughened and had a thickness of about 9 μm and a roughening treatment of Ra of less than 2 μm in order to realize wiring formation with a width of about 25 μm. . Then, the copper foil 22 is sandwiched between the SUS plates in a state where the copper foil 22 is disposed, and the copper foil 22 is applied by applying a temperature of about 200 ° C. and a pressure of about 200 kg / cm ² for about 1 hour using a vacuum hot press. At the same time, the copper foil 22 and the via 23 were electrically connected.

  Further, by compressing the copper powder in the copper conductive paste filled as the via 23, the contact point increases between the copper powder or between the copper powder and the copper foil 22, and at the same time the resin of the copper conductive paste Since the resin is cured, conduction occurs, and the compressive force applied to the via 23 is maintained by the adhesion between the copper foil 22 and the insulating base material 21 around the via 23 even when the temperature returns to room temperature. A level of continuity is ensured.

  In FIG. 3D, a photosensitive dry film resist is laminated on both sides of this circuit board, and exposure is performed using an exposure mask on which a predetermined pattern is formed, development of the resist, etching of the copper foil 22 and photosensitivity. The dry film resist is removed to form a wiring pattern 22a. The photosensitive dry film, the exposure mask, the etching solution, and the like used here were those generally used for manufacturing a circuit board without using a special material. Also for the apparatus, a shower type commonly used apparatus such as development and etching was used except that a light source that generates parallel light was used.

  In FIG. 3E, the steps shown in FIGS. 3A to 3D are repeated, and the substrate shown in FIG. The copper foil for wiring formed on the surface is roughened on one side, and the other side is made of glossy electrolytic copper foil. A wiring pattern 22a is formed, and Ni—Au or the like is formed on the surface of the wiring pattern 22a as necessary. The plating process may be performed or a solder resist may be formed. Further, the electrical inspection of the multilayer wiring board 24 manufactured before mounting the components is 100% inspected by a stylus method using a probe terminal, a probe card, or the like, thereby realizing a high yield. Further, the warpage as the multilayer wiring board 24 can be further suppressed by laminating the both sides of the board shown in FIG.

  In FIG. 3 (f), conductive bumps 29 are formed on the multilayer wiring board 24 that has become non-defective in the electrical inspection, and the semiconductor element 25 is placed through the conductive bumps 29, and an infrared reflow furnace or oven is placed. It connects by the method of heating with pressure etc., pressurizing using the pressurization jig | tool which has an area substantially equivalent to the semiconductor element 25, or heating while pressing. As a connection method, a flip chip bonding method in which solder is used for the conductive bumps 29 and heated in an infrared reflow furnace or an oven is the most preferable. However, as the conductive bumps 29, Au ball bumps or Au plating bumps using wire bonding are used. Other flip chip bonding methods used may be used. Thus, the semiconductor element 25 and the wiring pattern 22 a of the multilayer wiring board 24 are connected via the conductive bumps 29 formed on the connection pads of the semiconductor element 25. Then, the semiconductor element 25 is sealed with a sealing resin 27. The resin sealing method is not particularly limited, and the resin sealing is performed using a normal potting method, a transfer molding method, or the like.

  In FIG. 3G, when a large number of circuits for the semiconductor circuit component of the present invention are formed side by side on the multilayer wiring board 24, the semiconductor circuit component is cut by using a dicing saw, Thomson teeth, a mold or the like. Divide into pieces. Then, solder balls as external terminals 28 were formed on the wiring pattern 22a on the back side of the surface on which the semiconductor element 25 of the multilayer wiring board 24 was mounted. The solder balls were formed by heat treatment using an infrared reflow oven, oven, or the like by placing the solder balls at predetermined positions by a solder ball transfer method using flux. In the first embodiment, the solder ball is described as the external terminal 28. However, the external terminal 28 may have other shapes such as a simple electrode such as LGA, a pin terminal such as PGA, and an electrode using the substrate end face shown in FIG. May be.

(Embodiment 2)
FIG. 4 is a cross-sectional view showing the structure of another semiconductor circuit component according to Embodiment 2 of the present invention.

  The difference from the first embodiment is the structure of the semiconductor circuit component in which the wiring pattern 22a of the multilayer wiring board 24 to be used is embedded in the insulating base material 21 at least on the surface layer. By embedding the wiring pattern 22a, the surface smoothness of the multilayer wiring board 24 is improved, the injection of the sealing resin 27 becomes smooth, and the conductive bumps 29 slip from the wiring pattern 22a when the semiconductor element 25 is mounted. Dropping and positional displacement can be prevented, and a high mounting yield can be realized in the flip chip bonding method.

  The application of the materials used for the semiconductor circuit components in the second embodiment, the structure of the multilayer wiring board 10, the types of the semiconductor elements 11 and other component devices to be mounted, the types of the external terminals 14 and the like are described in the first embodiment. 4 is not particularly limited to the structure shown in FIG.

  Hereinafter, a method for manufacturing a semiconductor circuit component according to Embodiment 2 of the present invention will be described with reference to the drawings. FIG. 5 is a sectional view showing the structure of the semiconductor circuit component according to the second embodiment of the present invention.

  In FIG. 5A, the wiring pattern 22a was formed using a two-layer metal plate 31 that was electrolytically plated with copper on the entire surface of one surface of the metal plate 31. Here, the metal plate 31 was provided with rigidity necessary for handling the manufacturing process using an Al alloy having a thickness of about 50 μm. Since copper could not be electroplated directly on the Al alloy metal plate 31, a seed layer of Fe, Mn, Zn or the like was formed by plating, and the copper was electroplated with a thickness of about 9 μm. The surface of the copper was roughened, but Ra was less than 2 μm. Then, a photosensitive dry film resist is laminated, and exposure is performed using an exposure mask on which a predetermined pattern is formed. The resist is developed, the copper foil is etched, and the photosensitive dry film resist is removed to form a wiring pattern 22a. did.

  As the etching solution used here, only copper of Al and copper needs to be selectively etched, and an aqueous sulfuric acid solution was used. Others are the same as those used for general circuit board manufacturing, and the equipment used is a shower type commonly used equipment such as development and etching, except that a light source that generates parallel light is used. did.

  In FIG. 5 (b), an epoxy-modified polyimide that is flexible even after curing by applying surface modification to the both sides of an organic film made of a polyimide film having a thickness of 12.5 μm to improve adhesion, such as discharge treatment. An insulating substrate 21 is prepared by applying an adhesive composed of 5 to 10 μm in thickness and laminating a PEN (polyethylene naphthalate) film having a thickness of 9 μm on both sides as a protective film.

  Since this insulating base material 21 is very thin with a total thickness of about 45 to 50 μm, tension is applied to the insulating base material 21 so as to remove slack and wrinkles of the insulating base material 21 as a holding method when processing the through-holes. Holding was done by calling from all sides. The through hole is processed using a YAG laser having a wavelength of 355 nm, the hole diameter on the upper surface of the PEN film is 65 to 75 μm, and the smallest hole diameter from the lower surface side of the PEN film is generated in the adhesive layer and has a shape of about 40 to 50 μm. Processing was carried out as follows. Although the YAG laser is used in the second embodiment, other processing methods such as a carbon dioxide laser and punching can be applied depending on the material, thickness, and diameter of the through hole of the insulating base material 21. It is not limited to the YAG laser method. And the processing waste adhering to the surface of a PEN film was processed after processing.

  In FIG.5 (c), the copper conductive paste was filled in the formed through-hole by the squeezing method. Here, filling is performed while performing vacuum suction from the surface opposite to the surface to be squeezed, and the filling property of the copper conductive paste is ensured while preventing the occurrence of filling failure in which air enters the copper conductive paste. In the second embodiment, two-way reciprocating squeezing is repeated to improve filling reliability.

  Here, the copper conductive paste to be filled is made of a mixed material composed of a copper powder having a particle size of about 5 μm, an epoxy resin, and an amine curing agent, and the surface of the copper powder has good anti-oxidation and electrical bondability. The surface treatment is performed. Moreover, you may use the copper conductive paste which mixed copper powder with a particle size of about 1-1.5 micrometers other than copper powder with a particle size of about 5 micrometers in order to raise the filling density of copper powder. Then, the PEN film laminated as the protective film was peeled off, and the paste adhered to the surface of the insulating base material 21 other than the through holes was removed to form the vias 23.

In FIG.5 (d), the metal plate 31 in which the wiring pattern 22a was formed is arrange | positioned in alignment with the predetermined position of both surfaces of the insulating base material 21 in which the via | veer 23 was formed. The metal plate on which the wiring pattern 22a is formed is sandwiched between the SUS plates in this aligned state and is applied for about 1 hour at a temperature of about 200 ° C. and a pressure of about 200 kg / cm ² using a vacuum hot press. At the same time as 31 was bonded to the insulating substrate 21, the copper foil and the via 23 were electrically connected. Moreover, since the copper powder in the copper conductive paste filled as the via 23 is compressed, the contact point increases between the copper powder or between the copper powder and the copper foil, and at the same time, the resin of the copper conductive paste is cured. Even when the electrical conductivity is developed and the temperature returns to room temperature, the compressive force applied to the via 23 is maintained by the adhesion between the copper foil around the via 23 and the insulating base material 21, so that there is no practical problem as a circuit board. Is ensured.

  In FIG. 5 (e), the entire metal plate 31 made of an Al alloy is removed by etching, and the metal plate 31 is removed by immersing in an etching solution in which only Al of copper and Al can be selectively etched. The etching solution used here was diluted hydrochloric acid or aqueous sodium hydroxide. The metal plate 31 is removed by etching, washed with water, and the seed layer made of Fe, Mn, Zn or the like is wiped away in water, whereby a copper wiring pattern 22 a appears on the surface of the multilayer wiring board 24. Note that the seed layer made of Fe, Mn, Zn or the like may be removed by dissolving with a dedicated etching solution.

  In FIG. 5 (f), the steps shown in FIGS. 5 (a) to 5 (e) were repeated and laminated on both sides of the double-sided substrate shown in FIG. 5 (e), thereby realizing multilayer wiring. For wiring to be formed on the surface, if necessary, a plating process such as Ni—Au or a solder resist may be formed on the surface of the wiring. Further, the electrical inspection of the multilayer wiring board 24 manufactured before mounting the components is 100% inspected by a stylus method using a probe terminal, a probe card, or the like, thereby realizing a high yield. Further, the multilayer wiring board 24 can be prevented from warping by being laminated on both sides of the double-sided board.

  In FIG. 5 (g), conductive bumps 29 are formed on the multilayer wiring board 24 that has become non-defective in the electrical inspection, and the semiconductor element 25 is placed through the conductive bumps 29, and an infrared reflow furnace or oven is placed. It connects by the method of heating with pressure etc., pressurizing using the pressurization jig | tool which has an area substantially equivalent to the semiconductor element 25, or heating while pressing. As a connection method, a flip chip bonding method in which solder is used for the conductive bump 29 and heated in an infrared reflow furnace or an oven is the most preferable. Other flip chip bonding methods used may be used. Thus, the semiconductor element 25 and the wiring pattern 22 a of the multilayer wiring board 24 are connected via the conductive bumps 29 formed on the connection pads of the semiconductor element 25. Then, the semiconductor element 25 is sealed with a sealing resin 27. The resin sealing method is not particularly limited, and the resin sealing is performed using a normal potting method, a transfer molding method, or the like.

  In FIG. 5 (h), when a large number of circuits for the semiconductor circuit component of the present invention are formed side by side on the multilayer wiring board 24, the semiconductor circuit component is cut by using a dicing saw, a Thomson tooth, a mold, or the like. Divide into pieces. Then, solder balls as external terminals 28 were formed on the wiring pattern 22a on the back side of the surface on which the semiconductor element 25 of the multilayer wiring board 24 was mounted. The solder balls were formed by heat treatment using an infrared reflow oven, oven, or the like by placing the solder balls at predetermined positions by a solder ball transfer method using flux. In the second embodiment, the solder ball is described as the external terminal 28. However, the external terminal 28 may have other shapes such as a simple electrode such as LGA, a pin terminal such as PGA, and an electrode using the substrate end face shown in FIG. May be.

(Embodiment 3)
Hereinafter, a method for manufacturing a semiconductor circuit component according to Embodiment 3 of the present invention will be described with reference to the drawings. FIG. 6 is a cross-sectional view showing a method of manufacturing a semiconductor circuit component according to Embodiment 3 of the present invention.

  In FIG. 6A, the wiring pattern 22a was formed by using a two-layer metal plate 31 plated with electrolytic copper on the entire surface of one surface of the metal plate 31. Here, the metal plate 31 was provided with rigidity necessary for handling the manufacturing process using an Al alloy having a thickness of about 50 μm. Since copper could not be electroplated directly on the Al alloy metal plate 31, a seed layer of Fe, Mn, Zn or the like was formed by plating, and the copper was electroplated with a thickness of about 9 μm. The surface of the copper was roughened, but Ra was less than 2 μm. Then, a photosensitive dry film resist is laminated, and exposure is performed using an exposure mask on which a predetermined pattern is formed. The resist is developed, the copper foil is etched, and the photosensitive dry film resist is removed to form a wiring pattern 22a. did.

  As the etching solution used here, only copper of Al and copper needs to be selectively etched, and an aqueous sulfuric acid solution was used. Others are the same as those used for general circuit board manufacturing, and the equipment used is a shower type commonly used equipment such as development and etching, except that a light source that generates parallel light is used. did.

  In FIG. 6 (b), an epoxy-modified polyimide that is flexible even after curing by subjecting both sides of an organic film made of a polyimide film having a thickness of 12.5 μm to surface adhesion by electrical discharge treatment to improve adhesion. An insulating substrate 21 is prepared by applying an adhesive composed of 5 to 10 μm in thickness and laminating a PEN (polyethylene naphthalate) film having a thickness of 9 μm on both sides as a protective film.

  Since this insulating base material 21 is very thin with a total thickness of about 45 to 50 μm, tension is applied to the insulating base material 21 so as to remove slack and wrinkles of the insulating base material 21 as a holding method when processing the through-holes. Holding was done by calling from all sides. The through hole is processed using a YAG laser having a wavelength of 355 nm, the hole diameter on the upper surface of the PEN film is 65 to 75 μm, and the smallest hole diameter from the lower surface side of the PEN film is generated in the adhesive layer and has a shape of about 40 to 50 μm. Processing was carried out as follows. Although the YAG laser is used in the third embodiment, other processing methods such as a carbon dioxide laser and punching can be applied depending on the material, thickness, and diameter of the through hole of the insulating base material 21. It is not limited to the YAG laser method. And the processing waste adhering to the surface of a PEN film was processed after processing.

  In FIG.6 (c), the copper conductive paste was filled in the formed through-hole by the squeezing method. Here, filling is performed while performing vacuum suction from the surface opposite to the surface to be squeezed, and the filling property of the copper conductive paste is ensured while preventing the occurrence of filling failure in which air enters the copper conductive paste. In the third embodiment, two-way reciprocating squeezing is repeated to improve filling reliability.

  Here, the copper conductive paste to be filled is made of a mixed material composed of a copper powder having a particle size of about 5 μm, an epoxy resin, and an amine curing agent, and the surface of the copper powder has good anti-oxidation and electrical bondability. The surface treatment is performed. Moreover, you may use the copper conductive paste which mixed copper powder with a particle size of about 1-1.5 micrometers other than copper powder with a particle size of about 5 micrometers in order to raise the filling density of copper powder. Then, the PEN film laminated as the protective film was peeled off, and the paste adhered to the surface of the insulating base material 21 other than the through holes was removed to form the vias 23.

In FIG. 6D, the metal plate 31 on which the wiring pattern 22a is formed is arranged in alignment with predetermined positions on both surfaces of the insulating base material 21 on which the vias 23 are formed. The metal plate on which the wiring pattern 22a is formed is sandwiched between the SUS plates in this aligned state and is applied for about 1 hour at a temperature of about 200 ° C. and a pressure of about 200 kg / cm ² using a vacuum hot press. At the same time as 31 was bonded to the insulating substrate 21, the copper foil and the via 23 were electrically connected. Moreover, since the copper powder in the copper conductive paste filled as the via 23 is compressed, the contact point increases between the copper powder or between the copper powder and the copper foil, and at the same time, the resin of the copper conductive paste is cured. Even when the electrical conductivity is developed and the temperature returns to room temperature, the compressive force applied to the via 23 is maintained by the adhesion between the copper foil around the via 23 and the insulating base material 21, so that there is no practical problem as a circuit board. Is ensured.

  In FIG. 6 (e), in order to etch and remove all one side of the metal plate 31 made of an Al alloy, a foam release film or a dry film is laminated on the remaining metal plate 31 to protect it from contact with the etching solution. . Next, the metal plate 31 is removed by dipping in an etching solution in which only Al of copper and Al can be selectively etched. As the etching solution used here, dilute hydrochloric acid or sodium hydroxide aqueous solution was used. After the metal plate 31 is removed by etching and washed with water, the copper wiring pattern 22a appears on the surface of the multilayer wiring board 24 by wiping and removing the seed layer of Fe, Mn, Zn or the like in water. Note that the seed layer made of Fe, Mn, Zn or the like may be dissolved and removed with a dedicated etching solution. Finally, in the case of a foam release film, it was removed by heat treatment in an oven, and in the case of a dry film, it was removed by a release treatment with an aqueous sodium carbonate solution, leaving a metal plate 31 on one side.

  6 (f), the steps shown in FIGS. 6 (a) to 6 (e) were repeated and laminated on one side of the double-sided substrate shown in FIG. 6 (e), thereby realizing multilayer wiring. For wiring to be formed on the surface, a plating treatment such as Ni—Au or a solder resist may be formed on the surface of the wiring as necessary.

  In FIG. 6G, since the multilayer wiring substrate 24 is formed on the metal plate 31, the electrical inspection that should be normally performed cannot be performed. Therefore, this process is a method that enables this electrical inspection. First, a photosensitive dry film is laminated on the back surface of the metal plate 31, and exposure and development are performed using a pattern mask to form an opening that is large enough to expose the input / output terminal 32. Then, using the dry film as an etching resist, the metal plate 31 at the opening of the dry film is removed using an etchant such as dilute hydrochloric acid. The electrical inspection can be performed by inserting the probe 33 into the opened hole of the metal plate 31 and bringing another pair of probes 33 into contact with the wiring pattern 22a on the mounting surface of the semiconductor element 25.

  In FIG. 6 (h), conductive bumps 29 are formed on the multilayer wiring board 24 that has become non-defective in the electrical inspection, and the semiconductor element 25 is placed through the conductive bumps 29, and an infrared reflow furnace or oven is placed. It connects by the method of heating with pressure etc., pressurizing using the pressurization jig | tool which has an area substantially equivalent to the semiconductor element 25, or heating while pressing. As a connection method, a flip chip bonding method in which solder is used for the conductive bump 29 and heated in an infrared reflow furnace or an oven is the most preferable. Other flip chip bonding methods used may be used. Thus, the semiconductor element 25 and the wiring pattern 22 a of the multilayer wiring board 24 are connected via the conductive bumps 29 formed on the connection pads of the semiconductor element 25. Then, the semiconductor element 25 is sealed with a sealing resin 27. The resin sealing method is not particularly limited, and resin sealing was performed using a normal potting method, a transfer mold method, or the like. Here, since the metal plate 31 remains on one side, rigidity is added to the multilayer wiring board 24, and handling properties, mountability, and mounting yield can be improved.

  In FIG. 6I, in order to remove all the remaining portions of the metal plate 31 by etching, the metal plate 31 is removed by immersing in an etchant in which only Al of copper and Al can be selectively etched.

  In FIG. 6 (j), when a large number of circuits for semiconductor circuit components of the present invention are formed side by side on the multilayer wiring board 24, the semiconductor circuit components are cut by using a dicing saw, Thomson teeth, a mold or the like. Divide into pieces. Then, solder balls as external terminals 28 were formed on the wiring pattern 22a on the back side of the surface on which the semiconductor element 25 of the multilayer wiring board 24 was mounted. The solder balls were formed by heat treatment using an infrared reflow oven, oven, or the like by placing the solder balls at predetermined positions by a solder ball transfer method using flux. In the third embodiment, the solder ball is described as the external terminal 28. However, the external terminal 28 may have other shapes such as a simple electrode such as LGA, a pin terminal such as PGA, and an electrode using the substrate end face shown in FIG. May be.

  The semiconductor circuit component according to the present invention is a thin multilayer wiring that is flexible and has all the wiring layers IVH-connected without being easily crushed even if the multilayer wiring substrate on which the component is mounted is handled alone. By using a substrate, it is not necessary to support a rigid semiconductor body as a completed semiconductor circuit component, so it is possible to improve the degree of freedom of placement of mounting components such as semiconductor elements. It can be provided and is useful as a semiconductor circuit component used for small and light mobile devices such as mobile phones.

(A)-(c) Sectional drawing which shows the structure of the semiconductor circuit component in Embodiment 1 of this invention. Sectional drawing which shows the structure of another semiconductor circuit component in Embodiment 1 of this invention (A)-(g) Sectional drawing which shows the manufacturing method of the semiconductor circuit component in Embodiment 1 of this invention. Sectional drawing which shows the structure of the semiconductor circuit component in Embodiment 2 of this invention (A)-(h) Sectional drawing which shows the manufacturing method of the semiconductor circuit component in Embodiment 2 of this invention. (A)-(j) Sectional drawing which shows the manufacturing method of the semiconductor circuit component in Embodiment 3 of this invention. (A)-(e) Sectional drawing which shows the manufacturing method of the conventional semiconductor circuit component

Explanation of symbols

DESCRIPTION OF SYMBOLS 21 Insulating base material 21a Organic film 21b Adhesive agent 22 Copper foil 22a Wiring pattern 23 Via 24 Multilayer wiring board 25 Semiconductor element 25a Semiconductor element 25b Semiconductor element 26 Gold wire 27 Sealing resin 28 External terminal 29 Conductive bump 30 Other components Device 31 Metal plate 32 Input / output terminal 33 Probe

Claims (8)

A semiconductor circuit component in which all wiring layers between upper and lower layers of a multilayer wiring board made of an insulating base material having flexibility are IVH-connected and a semiconductor element is mounted on at least one surface. The semiconductor circuit component according to claim 1, wherein an adhesive that maintains flexibility even when the insulating substrate is cured on both surfaces of the organic film is applied. 3. The semiconductor circuit component according to claim 1, wherein the semiconductor element is mounted by wire bonding or flip chip bonding. The semiconductor circuit component according to claim 1, wherein the surface layer wiring is embedded so that the surface of the multilayer wiring board is flat. The semiconductor circuit component according to claim 1, wherein at least one semiconductor element or passive component device is mounted on at least one surface of the multilayer wiring board. A step of forming a hole in an insulating substrate made of an organic film coated with an adhesive on both sides, a step of filling a conductive material into the hole, and an insulating substrate filled with the conductive material. It consists of the process of affixing copper foil as a wiring layer on both sides and the process of patterning this copper foil to form a multilayer wiring board. The probe is brought into contact with the electrode terminals formed on this multilayer wiring board. A method of manufacturing a semiconductor circuit component, comprising: a step of performing an electrical inspection; and a step of mounting a semiconductor element on the multilayer wiring board that has obtained predetermined characteristics by the electrical inspection and sealing the semiconductor element with a sealing resin. . A step of forming a wiring pattern on one side of the metal plate, a step of forming a hole in an insulating substrate made of an organic film coated with an adhesive on both sides, a step of filling a conductive material into the hole, From the step of forming a multilayer wiring board by repeating the steps of pasting the surfaces of the insulating base material filled with the conductive material on both surfaces of the metal plate and removing the metal plates on both sides A step of performing electrical inspection by bringing a probe into contact with an electrode terminal formed on the multilayer wiring board, and mounting the semiconductor element on the multilayer wiring board that has obtained predetermined characteristics by the electrical inspection, and sealing the semiconductor element A method of manufacturing a semiconductor circuit component including a step of sealing with resin. A step of forming a wiring pattern on one side of the metal plate, a step of forming a hole in an insulating substrate made of an organic film coated with an adhesive on both sides, a step of filling a conductive material into the hole, A step of forming a multilayer wiring board by repeating a step of attaching a surface on which the wiring pattern of the metal plate is formed on both surfaces of the insulating base material filled with the conductive material and removing the metal plate on one side. Forming a hole in the metal plate left on the multilayer wiring board, inserting a probe into the hole and conducting an electrical inspection, and mounting a semiconductor element on the multilayer wiring board that has obtained predetermined characteristics by the electrical inspection. A method for manufacturing a semiconductor circuit component, comprising: a step of sealing a semiconductor element with a sealing resin; and a step of removing all remaining metal plates.

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