JP2005235335A - Semiconductor storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent the formation of a boundary except during word line switching even in the case of burst reading exceeding a page length. <P>SOLUTION: This device is provided with a row decoder 11 for selecting a word line according to a row address signal, a sense amplifier circuit group 14 divided by pages and constituted of a plurality of sense amplifier circuits for each page to sense data to be read-out to bit lines, column selection circuits 12 disposed between the bit line and the sense amplifier circuit group by a number equal to a page length for selecting a bit line according to an input signal to connect it to each sense amplifier circuit, a plurality of column decoders 13 disposed for each column selection circuit to output input signals supplied to the corresponding respective column selection circuits according to the column address signals, and an address control circuit 16 for controlling column address signals supplied to the plurality of column decoders according to the start page of a burst reading start among the memory cells for a plurality of pages in a memory cell array. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor memory device having a burst read function such as a nonvolatile semiconductor memory device.

  The capacity of a nonvolatile semiconductor memory device such as a flash memory or a dynamic RAM is increasing. In order to read data from this large-capacity semiconductor memory device at high speed, the memory cell array is divided into a plurality of banks, and a plurality of sense amplifier circuits are arranged in each bank to reduce the capacity of the data lines. Further, a burst read architecture using an internal address different from the external address is applied.

  Conventionally, when performing a burst read exceeding the page length, when data is read beyond the page length, a boundary depending on the start address, that is, an extra waiting time occurs. When the boundary occurs, there is a disadvantage that the average access time is delayed.

Patent Document 1 discloses a data read / write free time that occurs when the burst length is short, and enables seamless access by burst read to data of different row addresses between banks. ing.
JP 2000-195262 A

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor memory device in which no boundary is generated except for the switching of word lines even in the case of burst read exceeding the page length. is there.

  The semiconductor memory device of the present invention is a clock synchronous semiconductor memory device that performs burst read in synchronization with a clock signal. When tACC is the access time of the memory cell, tCLK is the cycle of the clock signal, and P is the page length, The page length P is set so as to satisfy tACC ≦ tCLK * P.

  The semiconductor memory device includes an address buffer that generates an internal address signal from an external address signal, a memory cell array in which a plurality of pages of memory cells connected to word lines and bit lines are arranged, and a part of the internal address signal. A row decoder that selects the word line according to a first address signal, and a sense amplifier circuit that is divided for each page and includes a plurality of sense amplifier circuits for each page, and senses data read to the bit line And a column selection circuit provided between the bit line and the sense amplifier circuit group, and provided by the number of page lengths that select the bit line according to an input signal and connect to the sense amplifier circuit Corresponding to a second address signal that is provided for each column selection circuit and is part of the internal address signal. A plurality of column decoders that respectively output the input signals supplied to a column selection circuit; and the plurality of column decoders according to a start page from which burst reading is started among memory cells for a plurality of pages in the memory cell array. And an address control circuit for controlling the second address signal supplied to.

  The address control circuit controls the change of the second address signal supplied to the plurality of column decoders independently for each of the plurality of column decoders.

  The address control circuit controls the change of the second address signal supplied to the plurality of column decoders independently for each group by dividing the plurality of column decoders into two sets of a lower page and an upper page. It is characterized by doing.

  According to the present invention, it is possible to provide a semiconductor memory device in which no boundary is generated except for the switching of word lines even in the case of burst read exceeding the page length.

(First embodiment)
FIG. 1 is a block diagram showing the overall configuration of the NOR type flash memory according to the first embodiment. It is assumed that this memory performs 8-page burst read and reads 16-bit data in parallel for each page (16 I / O × 8 pages). The memory is provided with a plurality of memory banks BNK. Each memory bank BNK is provided with a memory cell array 10 in which a plurality of memory cells are arranged. In each memory bank BNK, corresponding to each memory cell array 10, a row decoder 11 that selects a word line in the memory cell array, and a column selection circuit (CSL-SW) that includes a plurality of column switches that select bit lines in the memory cell array. ) 12, a column decoder (COL) 13 for controlling the column selection circuit 12, and a sense amplifier circuit group (S / A group) including a plurality of sense amplifier circuits for sensing data from the bit line selected by the column selection circuit 12 14 are arranged.

  An external address signal is supplied to the address buffer 15. The address buffer 15 generates an internal address signal composed of an internal row address signal and an internal column address signal according to the external address signal. The internal address signal is supplied in parallel to the row decoder 11 and the column decoder 13 in each memory bank BNK via the address control circuit 16.

  Data read from the sense amplifier circuit group 14 of each memory bank BNK is latched by the asynchronous latch circuit 17. Data latched by the asynchronous latch circuit 17 is selected by a data multiplexer (MUX) 18. The data selected by the data multiplexer 18 is latched by the synchronous latch circuit 19 in synchronization with the clock signal CLK, and the latched data is sequentially read from the output buffer circuit 20 according to the page address.

  FIG. 2 is a block diagram showing one memory bank BNK extracted in FIG. A plurality of blocks BLK are provided in the memory bank BNK. The block BLK is the smallest erase unit, and each block BLK is provided with 1024 local bit lines and 64 word lines. In each block BLK, memory cells in the memory cell array 10 and column switches in the column selection circuit 12 are arranged in a distributed manner. 128 main bit lines MBL are wired over a plurality of blocks BLK, and these 128 main bit lines MBL are connected to 128 sense amplifier circuits provided in the sense amplifier circuit group (S / A group) 14. It is connected.

  FIG. 3 is a block diagram showing an internal configuration of one block BLK in FIG. Each block BLK is divided into 8 sub-blocks SBLK. Each sub-block SBLK is provided with 16 sense amplifier circuits 21 that sense data of the same page among 128 sense amplifier circuits provided in the sense amplifier circuit group (S / A group) 14. Yes. In the notation of each sense amplifier circuit 21, for example, “# 0-0”, a numerical value immediately after # represents a page, and a numerical value after that represents an I / O number (bit). Therefore, the sense amplifier circuit 21 indicated as “# 0-0” senses the 0th page and 0th bit data, and the sense amplifier circuit 21 indicated as “# 0-15” indicates the 0th page and 15th bit. The sense amplifier circuit 21 labeled “# 7-15” senses the 7th page, 15th bit data.

  A plurality of column switches (column SW) in the column selection circuit 12 are divided into groups corresponding to the number of pages, that is, in this case, eight groups, and each group of column switches is arranged in eight sub-blocks SBLK. ing.

  On the other hand, the column decoder 13 is also divided into the number of pages, that is, in this case, eight partial column decoders (PCD) 13-0 to 13-7. These eight partial column decoders 13-0 to 13-7 are arranged in the corresponding sub-block SBLK, and supply internal column address signals to the column switch groups in the corresponding sub-block SBLK.

  FIG. 4 is a circuit diagram showing a detailed configuration of a partial circuit in FIG. In FIG. 4, one word line WL and a part of 1024 memory cells connected to the word line WL are shown together. Each memory cell is composed of a non-volatile transistor having a two-layer gate structure including a floating gate and a control gate, and the control gates of these memory cells are commonly connected to a word line WL. The drain of each memory cell is connected to the corresponding one of 1024 local bit lines LBL, and all the sources are connected to the ground potential. Here, for example, the memory cell M0-0 stores the 0th page and 0th bit data, and the memory cell M7-15 stores the 7th page and 15th bit data.

  The 128 sense amplifier circuits 21 sense data in any one of the eight memory cells connected to the eight local bit lines LBL. A column switch group in the column selection circuit 12 is used to select one of these eight memory cells.

  Ten column switches composed of NMOS transistors are provided between the main bit lines MBL connected to the 128 sense amplifier circuits 21 and the eight local bit lines LBL, respectively. Each of these ten column switches constitutes a column selection circuit 12. Of the 128 sense amplifier circuits 21, for example, the sense amplifier circuit 21 described as “# 0-0” is the 0th bit of each of pages 0, 8, 16, 24, 32, 40, 48, and 56. Sense the data. Four local bit lines LBL to which memory cells M0-0, M16-0, M32-0, and M48-0 for storing the 0th bit data of pages 0, 16, 32, and 48 are connected The column switches 22-1 to 22-4 are connected at one end between the source and the drain. The other ends between the source and drain of these four column switches 22-1 to 22-4 are connected in common. Similarly, the four local bit lines LBL to which the memory cells M8-0, M24-0, M40-0, M56-0 for storing the 0th bit data of pages 8, 24, 40, and 56 are connected are connected. Are connected at one end between the source and drain of the four column switches 22-5 to 22-8. The other ends between the source and drain of the four column switches 22-5 to 22-8 are connected in common.

  Between the other end common connection node between the source and drain of the four column switches 22-1 to 22-4 and the sense amplifier circuit 21, the source and drain of the column switch 22-9 are inserted. . The source / drain of the column switch 22-10 is inserted between the common connection node between the other ends of the source / drain of the four column switches 22-5 to 22-8 and the sense amplifier circuit 21. ing.

  In each sub-block SBLK, in order to select 8 local bit lines LBL, 16 column switches, each including the 10 column switches 22-1 to 22-10, are provided. In the sub-block SBLK, the same gate control signal is supplied to the corresponding one of the ten column switches 22-1 to 22-10. For example, the gate control signal GATE1 <0> is supplied to the column switches 22-1 and 22-5, the gate control signal GATE1 <1> is supplied to the column switches 22-2 and 22-6, and the column switch 22- The gate control signal GATE1 <2> is supplied to 3 and 22-7, and the gate control signal GATE1 <3> is supplied to the column switches 22-4 and 22-8. Further, the gate control signal GATE2 <0> is supplied to the column switch 22-9, and the gate control signal GATE2 <1> is supplied to the column switch 22-10. These gate control signals are generated by partial column decoders provided in the same block BLK among the partial column decoders 13-0 to 13-7.

As shown in Table 1 below, each of the 16 sense amplifier circuits 21 of # 0 to # 7 senses data of a plurality of predetermined pages.

  For example, the 16 sense amplifier circuits 21 of # 0, that is, the sense amplifier circuits 21 of # 0-0 to # 0-15, store the data of pages 0, 8, 16, 24, 32, 40, 48 and 56. The sixteen sense amplifier circuits 21 of # 1, that is, the sense amplifier circuits 21 of # 1-0 to # 1-15, have data of pages 1, 9, 17, 25, 33, 41, 49 and 57. In the same manner, the 16 sense amplifier circuits 21 of each page sense data corresponding to 8 different pages as shown in Table 1 below.

  5 and 6 are circuits showing a detailed configuration of one of the partial column decoders 13-0 to 13-7 arranged for each of the eight sub-blocks SBLK. Here, 3 bits A3 to A5 are used as internal column address signals for generating the previous gate control signals GATE1 <0> to GATE1 <3>, GATE2 <0>, and GATE2 <1>. . Of the internal column address signal, 3 bits composed of A0 to A2 are used as a page address for selecting a page.

  As shown in FIG. 5, the address signals A3 <0> to A5 <0> are generated by inverting the 3-bit address signals A3 to A5 by the three inverters 31, and the address signal A3 <0>. The address signals A3 <1> to A5 <1> are generated by inverting -A5 <0> by the three inverters 32. Here, for example, the address signals A3 <0> and A3 <1> are complementary signals.

  FIG. 6 shows the gate control signal GATE1 <in response to the complementary address signals A3 <0> to A5 <0>, A3 <1> to A5 <1> and the block selection signal BiEN generated by the circuit of FIG. A configuration of a circuit portion that generates 0> to GATE1 <3> and GATE2 <0> to GATE2 <1> is shown. The block selection signal BiEN is a signal that is activated when a corresponding block is selected from the plurality of blocks BLK.

  The gate control signals GATE1 <0> to GATE1 <3> are the block selection signal BiEN and the address signals A5 <0> and A4 <0>, BiEN and A5 <0> and A4 <1>, BiEN and A5 <1> and 4 NAND gates 33 to which A4 <0>, BiEN, A5 <1>, and A4 <1> are respectively input, and 4 inverters 34 that invert the outputs of these 4 NAND gates 33. Generated by the circuit.

  The gate control signals GATE2 <0> and GATE2 <1> include two NAND gates 35 to which the block selection signal BiEN and the address signal A3 <0> and BiEN and A3 <1> are input, respectively. It is generated by a circuit comprising two inverters 36 that invert the output of the NAND gate 35.

  In a memory having such a configuration, when burst read is performed, after an external address signal corresponding to the start address is input to the address buffer 15, the memory cell is accessed and data is synchronized with the clock signal CLK in synchronization with the synchronous latch circuit. The data is latched at 19 and then 16-bit width data is sequentially output from the output buffer circuit 20 by the page length. During this data output, it is necessary to read data for the next page length in the background. For this reason, in the memory, the background address (BGA) for reading the memory cell data is advanced by several clocks compared to the burst address.

  Here, tACC ≦ tCLK * P needs to be satisfied in order not to generate a boundary at the time of burst read exceeding the page length. Here, tACC is the access time of the memory cell, tCLK is the cycle of the clock signal CLK used to control the operation of the synchronous latch circuit 19, and P is the page length.

  For example, when tACC is 80 nS and tCLK is 10 nS, in order to satisfy tACC ≦ tCLK * P, tACC / tCLK = 80 nS / 10 nS ≦ P, and the page length P may be 8 or more. Since the page length P is set to 8 pages in the memory of the present embodiment, it is possible to prevent the occurrence of a boundary at the time of burst read exceeding the page length under the conditions of tACC and tCLK as described above. .

  By the way, at the time of burst read, in order to read data for 8 pages after the start address is input without depending on the start address and without generating a boundary except when the word line is switched, If the page of the start address is 0, pages 0, 1, 2,..., 7, if it is 2, pages 8, 9, 2, 3,. As described above, it is necessary to perform control so that data for eight continuous pages is read by one access. For this purpose, the gate control signals GATE1 <0> to GATE1 <3>, GATE2 <0>, and GATE2 <1> generated by the partial column decoder arranged for each block BLK need to be controlled independently for each block BLK. In order to realize this, in this embodiment, the internal column address signals supplied to the eight partial column decoders 13-0 to 13-7 arranged in each sub-block are independent for each partial column decoder. To control.

  FIG. 7 shows eight pages (128) of sense amplifier circuits 21 consisting of # 0 to # 7 shown in FIG. 4, a start address at the time of burst read, and address signals inputted to eight partial column decoders. An example of the relationship with A3-A5 is shown.

  When the start address is “0”, the internal column address signal (A3 = A4 = A5 = 0) generated by the address buffer 15 is directly input to the eight partial column decoders. In this case, both the address signal A5 <0> and the address signal A4 <0> generated by the circuit of FIG. 5 are 1 level, and the gate control signal GATE1 <0> generated by the circuit of FIG. 6 is 1 level. Thus, two column switches 22-1 and 22-5 of the 16 column switches each including 10 in each sub-block SBLK in FIG. 4 are turned on. Further, the address signal A3 <0> generated by the circuit of FIG. 5 becomes 1 level, the gate control signal GATE2 <0> generated by the circuit of FIG. 6 becomes 1 level, and each sub block in FIG. One column switch 22-9 is turned on in each of 16 column switches, each of which is 10 in SBLK.

  Therefore, in FIG. 4, for example, the sense amplifier circuit 21 labeled “# 0-0” is connected to the local memory cell M0-0 connected in series via the column switches 22-1 and 22-9. The signal of the bit line LBL is input, and the sense amplifier circuit 21 of “# 0-0” senses the 0th page, 0th bit data (data of the memory cell M0-0). Similarly, the sense amplifier circuit 21 labeled “# 0-1” has local bit lines LBL to which the memory cells M0-1 are connected via column switches 22-1 and 22-9 in series. The signal is input, and the sense amplifier circuit 21 of “# 0-1” senses the 0th page and the first bit data (data of the memory cell M0-1). Similarly, the sense amplifier circuits 21 of # 0 to # 7 sense 16-bit data from page 0 to page 7, respectively. The data sensed by the sense amplifier circuit 21 is output from the output buffer circuit 20 sequentially from the 0th page of the start address according to the page address.

  When the start address is “5”, among the eight partial column decoders, the partial column decoders in the sub-block in which the sense amplifier circuits # 5 to # 7 are provided are respectively generated by the address buffer 15. The internal column address signal (A3 = A4 = A5 = 0) is input as it is. On the other hand, each of the partial column decoders in the sub-block in which the sense amplifier circuits # 0 to # 4 are provided is not the internal column address signal generated by the address buffer 15, but the address control circuit in FIG. The internal column address signal (A3 = 1, A4 = A5 = 0) incremented by 16 is input.

  In this case, in each partial column decoder in the sub-block in which the sense amplifier circuits # 0 to # 4 are provided, the gate control signals GATE1 <0> and GATE2 <1> generated by the circuit in FIG. Thus, two column switches 22-5 and 22-10 are turned on among the 16 column switches of which 10 are provided in each sub-block SBLK in FIG. Therefore, in FIG. 4, for example, the sense amplifier circuit 21 labeled “# 0-0” is connected to the local memory cell M8-0 connected in series via the column switches 22-5 and 22-10. The signal of the bit line LBL is input, and the sense amplifier circuit 21 of “# 0-0” senses the 8th page, 0th bit data (data of the memory cell M8-0). That is, the sense amplifier circuits 21 from # 0 to # 4 sense 16-bit data from page 8 to page 12, respectively.

  In each partial column decoder in the sub-block provided with the sense amplifier circuits # 5 to # 7, the internal column address signal (A3 = A4 = A5 = 0) generated by the address buffer 15 is input as it is. In each of these partial column decoders, the gate control signals GATE1 <0> and GATE2 <0> generated by the circuit in FIG. 6 become 1, and 10 pieces are provided in each sub-block SBLK in FIG. Two column switches 22-1 and 22-9 are turned on in each of 16 column switches. Therefore, in FIG. 4, for example, # 5 sense amplifier circuit 21 labeled “# 5-0” is connected to the memory cell M5-0 via the column switches 22-1 and 22-9 in series. The signal of the local bit line LBL is input, and the sense amplifier circuit 21 of “# 5-0” senses the 5th page, 0th bit data (data of the memory cell M5-0). In this way, the sense amplifier circuits 21 from # 5 to # 7 sense 16-bit data from page 5 to page 7, respectively. The data sensed by the sense amplifier circuit 21 is output from the output buffer circuit 20 in the order of page 5, 6, 7, 8,..., 11, 12 according to the page address.

  When the start address is “14”, among the eight partial column decoders, the partial column decoders in the sub-block in which the sense amplifier circuits of # 6 and # 7 are provided are respectively generated by the address buffer 15. The internal column address signal (A3 = 1, A4 = A5 = 0) is input as it is. On the other hand, each of the partial column decoders in the sub-block in which the sense amplifier circuits # 0 to # 5 are provided is not the internal column address signal generated by the address buffer 15, but the address control circuit in FIG. The internal column address signal (A3 = A5 = 0, A4 = 1) incremented by 16 is input.

  In this case, in each partial column decoder in the sub-block in which the sense amplifier circuits # 0 to # 5 are provided, the gate control signals GATE1 <1> and GATE2 <0> generated by the circuit in FIG. Thus, two column switches 22-2 and 22-9 among the 16 column switches, each of which is provided in each sub-block SBLK in FIG. In this case, the sense amplifier circuits 21 from # 0 to # 5 sense 16-bit data from page 16 to page 21, respectively.

  The internal column address signals (A3 = 1, A4 = A5 = 0) generated by the address buffer 15 are input as they are to the partial column decoders in the sub-block in which the sense amplifier circuits # 6 and # 7 are provided. Therefore, in each of these partial column decoders, the gate control signals GATE1 <0> and GATE2 <1> generated by the circuit in FIG. 6 become 1, and are provided in each sub-block SBLK in FIG. Two column switches 22-6 and 22-10 among the 16 column switches of which 10 are one set are electrically connected. In this case, the sense amplifier circuits # 6 and # 7 sense 16-bit data on pages 14 and 15, respectively. The data sensed by the sense amplifier circuit 21 is output from the output buffer circuit 20 in the order of page 14, 15, 16, 17,.

  As described above, in the memory of the first embodiment, the address control circuit 16 independently increments (changes control) the internal column address signal supplied to the partial column decoder. Even if the address is short, no boundary is generated. The change control of the internal column address signal in the address control circuit 16 is performed by incrementing the address composed of A3 to A5 by one according to the page address composed of A0 to A2 in the external address signal inputted to the address buffer 15. This can be done easily.

(Second Embodiment)
FIG. 8 is a block diagram showing a partial configuration of the NOR type flash memory according to the second embodiment. In general, a NOR flash memory having a large storage capacity employs a redundancy function for replacing defective cells with redundant cells. Therefore, in the memory of the second embodiment, defective cells are replaced with redundant cells on a column basis. Note that portions corresponding to those in FIG. 1 are denoted by the same reference numerals and description thereof is omitted, and only portions different from FIG. 1 are described below.

  The bank BLK is provided with a redundant column 51 including redundant cells in addition to the memory cell array 10. Further, when the defective cell is replaced with the memory cell of the redundant column 51, it is necessary to store a defective address indicating which column in which sub-block is replaced, and the defective address storage circuit 52 stores the defective address. Remember. The address selection / comparison circuit 53 compares the address indicated by the internal column address signal output from the address control circuit 16 with the defective address stored in the defective address storage circuit 52. HIT is output. When the hit signal HIT is input, the data multiplexer (MUX) 54 selects the read data from the memory cell of the redundant column 51 instead of the read data from the normal memory cell, and outputs it to the asynchronous latch circuit 17.

  FIG. 9 is a block diagram showing an extracted address selection / comparison circuit 53 in FIG. The address selection / comparison circuit 53 includes # 0 to # 7 column address signals A5 to A3 (# 0-A5 to A3... # 7-A5 to A3) output from the address control circuit 16, and a defective address storage circuit 52. The hit signal HIT is generated according to the column address signals A5 to A0 (ROM-A5 to A0) stored in. As shown in FIG. 10, the address selection / comparison circuit 53 selects any one of the 3-bit address signals A5 to A3 # 0 to # 7, and selects the selected address signal and the defective address storage circuit. The three address selection / comparison units 55 for comparing the address signals of the corresponding bits stored in 52, and the hit signal HIT-A5 for each bit generated by these three address selection / comparison units 55 And AND gate 56 supplied with HIT-A3.

  11 and 12 are provided in the address selection / comparison circuit 53, and are used to select any one of the address signals # 0 to # 7 in the three address selection / comparison units 55. The structure of the circuit part which generate | occur | produces a signal is shown.

  As shown in FIG. 11, the 3-bit address signals ROM-A2 to ROM-A0 stored in the defective address storage circuit 52 are inverted by the three inverters 57, whereby the address signals A2 <0> to A0. <0> is generated, and address signals A2 <0> to A0 <0> are inverted by three inverters 58 to generate address signals A2 <1> to A0 <1>. Here, for example, the address signals A2 <0> and A2 <1> are complementary signals.

  FIG. 12 shows control signals GATE <0>, GATEB <0 in response to the complementary address signals A2 <0>, A2 <1> to A0 <0>, A0 <1> generated in the circuit portion of FIG. > To GATE <7> and GATEB <7> are shown. The control signals GATEB <0> to GATEB <7> are address signals A2 <0>, A1 <0> and A0 <0>, address signals A2 <0>, A1 <0> and A0 <1>, and address signal A2. <0>, A1 <1> and A0 <0>, address signal A2 <0>, A1 <1> and A0 <1>, address signal A2 <1>, A1 <0> and A0 <0>, address signal A2 <1>, A1 <0> and A0 <1>, address signals A2 <1>, A1 <1> and A0 <0>, address signals A2 <1>, A1 <1> and A0 <1>, respectively. Are input to the NAND gate 59, and eight inverters 60 for inverting the outputs of the eight NAND gates 59.

  13 selects one of the address signals A5 of # 0 to # 7 among the three address selection / comparison units 55 shown in FIG. 10, and this is selected as the address signal stored in the defective address storage circuit 52. FIG. 5 is a circuit diagram showing a specific configuration of an address selection / comparison unit that generates a hit signal HIT-A5 in comparison with ROM-A5. The address selection / comparison unit 55 includes eight clocked inverters 61 to which address signals A5 (# 0-A5 to # 7-A5) of # 0 to # 7 are respectively supplied, and outputs of these clocked inverters 61 And an exclusive NOR gate 63 to which the signal of the common output node of the inverter 62 and the address signal ROM-A5 are supplied. Yes. The eight clocked inverters 61 are controlled by control signals GATE <0>, GATEB <0> to GATE <7>, and GATEB <7> generated by the circuit of FIG. The other two address selection / comparison units 55 differ only in the bits of the input address signal and have the same basic configuration.

  Here, when the 3-bit address signals ROM-A2 to ROM-A0 stored in the defective address storage circuit 52 are all 0, the address signals A2 <0> to A0 <0> generated by the circuit of FIG. Are all 1, the control signal GATE <0> generated by the circuit of FIG. 12 is 1 level, and GATEB <0> is 0 level. As a result, among the eight clocked inverters 61 in FIG. 13, the clocked inverter 61 to which # 0-A <5> is supplied inverts, and the remaining seven clocked inverters 61 do not operate. As a result, the address signal # 0-A <5> is selected and compared with the address signal ROM-A5 stored in the defective address storage circuit 52 by the exclusive NOR gate 63. If the address signal # 0-A <5> is the same as the ROM-A5, the hit signal HIT-A5 is output. When the hit signals HIT-A5 to HIT-A3 are output from all the three address selection / comparison units 55, the final hit signal HIT is output from the AND gate 56 of FIG. At this time, the data multiplexer (MUX) 54 selects the read data from the memory cell of the redundant column 51 instead of the read data from the memory cell array 10 and outputs it to the asynchronous latch circuit 17. In this way, data is read from the redundant memory cell instead of the defective cell.

(Third embodiment)
In the first embodiment, the page length P is set to 8 when the memory cell access time tACC is 80 nS and the cycle tCLK of the clock signal CLK is 10 nS. On the other hand, when the memory cell access time tACC is half of 80 nS, that is, 40 nS, the page length P for satisfying the previous tACC ≦ tCLK * P is 4 or more. Under such conditions, when the page length P is set to 8 similarly to the memory of the first embodiment, that is, when a sense amplifier circuit having a page length twice the required page length is provided, one bank BNK Rather than independently controlling the internal column address signals supplied to the eight partial column decoders provided in the eight blocks BLK, the upper page (# 4-7) and the lower page (# 0-3) ) Can be divided into two groups of four pages, and the internal column address signal can be changed and controlled independently for each group.

  FIG. 14 shows, in the third embodiment, the sense amplifier circuits 21 for eight pages (128) including # 0 to # 7 shown in FIG. 4, the start address at the time of burst read, and the partial column decoder. An example of the relationship with input address signals A3 to A5 is shown.

  When the start address is “0”, the internal column address signals generated by the address buffer 15 are included in the eight partial column decoders as in the first embodiment, regardless of the lower page and the upper page. (A3 = A4 = A5 = 0) is input as it is. In this case, the sense amplifier circuits 21 of # 0 to # 7 sense 16-bit data from page 0 to page 7, respectively, and the data sensed by these sense amplifier circuits 21 is the start address according to the page address. Are sequentially output from the output buffer circuit 20.

  When the start address is “5”, out of the eight partial column decoders, the four partial column decoders in the sub-block in which the sense amplifier circuits of the upper pages # 4 to # 7 are provided are respectively addressed. The internal column address signal (A3 = A4 = A5 = 0) generated by the buffer 15 is input as it is. In this case, the sense amplifier circuits # 4 to # 7 sense 16-bit data from page 4 to page 7, respectively.

  On the other hand, each of the four partial column decoders in the sub-block in which the sense amplifier circuits for the lower pages # 0 to # 3 are provided are not internal column address signals generated by the address buffer 15, The internal column address signal (A3 = 1, A4 = A5 = 0) incremented (change control) by the address control circuit 16 in 1 is input. In this case, the sense amplifier circuits # 0 to # 3 sense 16-bit data from page 8 to page 11, respectively.

  The data sensed by the sense amplifier circuit 21 is output from the output buffer circuit 20 in the order of page 5, 6, 7, 8,.

  When the start address is “14”, out of the eight partial column decoders, the four partial column decoders in the sub-block in which the sense amplifier circuits of the upper page # 4 to # 7 are provided are respectively addressed. The internal column address signal (A3 = 1, A4 = A5 = 0) generated by the buffer 15 is input as it is. In this case, the sense amplifier circuits # 4 to # 7 sense 16-bit data from page 12 to page 15, respectively.

  On the other hand, each of the four partial column decoders in the sub-block in which the sense amplifier circuits for the lower pages # 0 to # 3 are provided are not internal column address signals generated by the address buffer 15, The internal column address signal (A3 = A5 = 0, A4 = 1) incremented by the address control circuit 16 in 1 is input. In this case, the sense amplifier circuits # 0 to # 3 sense 16-bit data from page 16 to page 19, respectively.

  The data sensed by the sense amplifier circuit 21 is output from the output buffer circuit 20 in the order of page 14, 15, 16, 17, ..., 19 pages in accordance with the page address.

  In the memory according to the third embodiment, the sense amplifier circuits # 0 to # 7 are divided into two groups of four pages, the upper page (# 4 to 7) and the lower page (# 0 to 3). Since the internal column address signal is incremented independently every time, the number of wirings of the internal column address signal can be reduced to ¼ compared to the case of the first embodiment, and wiring formation The effect that the area can be reduced is further obtained.

  Note that the third embodiment may have a redundancy function for replacing a defective cell with a redundant cell, as in the second embodiment.

(Fourth embodiment)
In the memory according to the first embodiment, a boundary (64-word boundary) is always generated when the word line is switched once except when the start address is 0. In order to prevent this, as shown in the timing chart of FIG. 15, the address control circuit 16 may perform control (reset) to return the internal column address signal once incremented. FIG. 15 illustrates the read operation when the start address is “7”.

  A start address (ex-ADD) supplied from the outside is taken in response to a signal AVD synchronized with the clock signal CLK. When the start address is “7”, the sense amplifier circuits of # 4 to # 7 on the upper page sense data on pages 4 to 7. The sense amplifier circuits of the lower pages # 0 to # 3 sense the data of the 8th page to the 11th page by being supplied with the incremented internal column address signal. Thereafter, the sense amplifier circuits of # 4 to # 7 on the upper page sense data on pages 12 to 15 which is the next page of page 11. The sense amplifier circuits of # 0 to # 3 on the lower page are supplied with the incremented internal column address signal, and thereafter sense data on pages 16 to 19 but are incremented. By returning the internal column address signal, the data of the 8th to 11th pages is sensed.

  On the other hand, the output signal ATD of an address transition detection circuit (not shown) becomes 1 level in response to the change of the address signal, and after this signal ATD becomes 1 level, the data for 8 pages is latched by the synchronous latch circuit 19 (SA_LATCH). Thereafter, the data DOUT is output in synchronization with the clock signal CLK.

  In the memory of the fourth embodiment, the internal column address signal that has been incremented once is reset and returned to the original state, so that the data for 8 pages becomes the data of continuous pages, and the word line switching is performed in the subsequent read operations. Boundaries will not occur except at times.

  In the memories of the second and third embodiments, as in the fourth embodiment, the internal column address signal incremented once may be reset and returned to the original.

  FIG. 16 shows a circuit configuration of a part of the address control circuit 16 in the third embodiment. The circuit shown in FIG. 16 controls the internal column address signals A3 to A5 in accordance with the internal column address signals A0 to A5 latched in the address control circuit 16. In FIG. 16, column address signals input to the address control circuit 16 are indicated by A0 to A5, and internal column address signals output from the address control circuit 16 are CA0 to CA2, CA4 (L), and CA4 (U). -CA5 (L) and CA54 (U).

  A circuit composed of the inverters 71 to 73 generates twist signals TWIST and TWISTB based on the address signal A2 latched in the address control circuit 16.

  The counter circuits 75, 76, and 77 count the address signals A0 to A2 latched in the address control circuit 16 in synchronization with the clock signal CLK. The carry-out terminals CO of the counter circuits 75, 76, and 77 Is supplied to each carry-in terminal CI of the counter circuit for the upper bits. The outputs of these counter circuits 75, 76, 77 are sequentially inverted through two inverters 78, 79, 80, 81, 82, 83, respectively, thereby generating address signals CA0-CA2. .

  A circuit composed of two counter circuits 84 and 85, four inverters 86 to 89, and two clocked inverters 90 and 91 includes an address signal A3 (L) of the lower page and an address signal of the upper page from the address signal A3. A3 (U) is generated, and the address signal A3 is counted by the two counter circuits 84 and 85 in synchronization with the clock signal CLK. The carry-in terminal CI of the two counter circuits 84 and 85 is supplied in parallel with the signal of the carry-out terminal CO of the lower-bit counter circuit 77.

  The output of the one counter circuit 84 is inverted by an inverter 86. The output of the inverter 86 is supplied to a clocked inverter 90 which operates when the twist signal TWISTB is 0 level and the twist signal TWIST is 1 level and inverts the input signal. Further, the output of the clocked inverter 90 is the inverter 87. To be supplied.

  Further, the output of the one counter circuit 84 is supplied to a clocked inverter 91 which operates when the twist signal TWIST is 0 level and the twist signal TWISTB is 1 level and inverts the input signal. The output node of the clocked inverter 91 is connected to the input node of the inverter 87. The inverter 87 generates a lower page address signal CA3 (L).

  The output of the other counter circuit 85 is sequentially inverted by two inverters 88 and 89 to generate an upper page address signal CA3 (U).

  A circuit for generating lower page address signals CA4 (L) and CA5 (L) based on the address signals A4 and A5 includes two counter circuits 92 and 93 and four inverters 94 to 97. . An address signal CA3 (L) is supplied to the carry-in terminal of the counter circuit 92. The counter circuit 92 counts the address signal A4 in synchronization with the clock signal CLK. The output of the counter circuit 92 is sequentially inverted by the two inverters 94 and 95 to generate the lower page address signal CA4 (L). The carry-in terminal of the counter circuit 93 is supplied with a signal at the carry-out terminal of the counter circuit 92. The counter circuit 93 counts the address signal A5 in synchronization with the clock signal CLK. The output of the counter circuit 93 is sequentially inverted by the two inverters 96 and 97 to generate the lower page address signal CA5 (L).

  The circuit for generating the upper page address signals CA4 (U) and CA5 (U) based on the address signals A4 and A5 is composed of two counter circuits 98 and 99 and four inverters 100 to 103. . An address signal CA3 (U) is supplied to the carry-in terminal of the counter circuit 98, and the counter circuit 98 counts the address signal A4 in synchronization with the clock signal CLK. The output of the counter circuit 98 is sequentially inverted by the two inverters 100 and 101 to generate the upper page address signal CA4 (U). The carry-in terminal of the counter circuit 99 is supplied with a signal at the carry-out terminal of the counter circuit 98. The counter circuit 99 counts the address signal A5 in synchronization with the clock signal CLK. The output of the counter circuit 99 is sequentially inverted by the two inverters 102 and 103 to generate the upper page address signal CA5 (U).

  In the circuit configured as shown in FIG. 16, when the address signal A2 is 0 level, the twist signal TWIST is 0 level and the twist signal TWISTB is 1 level.

  At this time, a signal having the same level as the address signal A3 counted by the counter circuit 85 is output from the inverter 89 as the upper page address signal A3 (U). Since the twist signal TWIST is 0 level and the twist signal TWISTB is 1 level, the clocked inverter 91 operates, and a signal having the same level as the address signal A3 counted by the counter circuit 84 is output as the address signal A3 (L) of the lower page. Is done.

  That is, when the address signal A2 is 0 level, the address signals CA3 (L) and CA3 (U) of the lower page and the upper page are the same level. For example, when the address signal A3 is 0 level, CA3 (L) and CA3 (U) Both become 0 level.

  On the other hand, when the address signal A2 latched in the address control circuit 16 is 1 level, the twist signal TWIST is 1 level and the twist signal TWISTB is 0 level.

  At this time, a signal having the same level as the address signal A3 counted by the counter circuit 85 is output as the upper page address signal A3 (U). Since the twist signal TWIST is 1 level and the twist signal TWISTB is 0 level, the clocked inverter 90 operates, and the inverted signal of the address signal A3 counted by the counter circuit 84 is sent from the inverter 87 as the address signal A3 (L) of the lower page. Is output.

  That is, when the address signal A2 is at 0 level and A3 is at 0 level, the upper page address signal A3 (U) remains at 0 level, but the lower page address signal A3 (L) is incremented to 1 level. become.

  FIG. 17 shows a circuit configuration of part of the address control circuit 16 used in the fourth embodiment. Since the basic configuration of the address control circuit 16 used in this embodiment is the same as that shown in FIG. 16, only the points different from FIG. 16 will be described below.

  In the address control circuit 16, the circuit for generating the twist signal TWIST and the signal TWISTB is changed to that shown in FIG. This circuit includes a NAND gate 111 to which an address signal A2 and a reset signal RSTB are supplied, an inverter 112 that inverts an output of the NAND gate 111 and outputs a twist signal TWIST, and an output of the inverter 112 that is inverted. And an inverter 113 that outputs a twist signal TWISTB.

  Further, a circuit shown in FIG. 17B is newly added. The circuit of FIG. 17B generates a reset signal RSTB used in the circuit of FIG. 17A. The NAND gate 121 to which the twist signal TWIST and the address signals A0 to A2 are supplied, and the clock signal CLK And a D-type flip-flop circuit 122 that captures the output of the NAND gate 121 in synchronization with.

  In the memory according to the fourth embodiment, after the twist signal TWIST is set to 1 level and the address signal CA3 (L) is incremented, all the address signals A0 to A3 are set to 1 level. The output of the NAND gate 121 becomes 0 level, and this 0 level signal is latched by the flip-flop circuit 122 in synchronization with the clock signal CLK, so that the reset signal RSTB becomes 0 level. When the reset signal RSTB becomes 0 level, the output of the NAND gate 111 in FIG. 17A becomes 1 level, the twist signal TWIST becomes 0 level, and the twist signal TWISTB becomes 1 level. At this time, in the circuit of FIG. 16, the clocked inverter 91 of the two clocked inverters 90 and 91 operates, and the signal having the same level as the address signal A3 counted by the counter circuit 84 is the address signal CA3 of the lower page. (L) is output from the inverter 87.

  That is, after reset, the address signal CA3 (L) of the lower page is returned to the same level as the address signal CA3 (U) of the upper page.

  In addition, this invention is not limited to said each embodiment, A various deformation | transformation is possible. For example, in each of the above embodiments, the case where the present invention is implemented in a NOR flash memory has been described. However, the present invention can also be implemented in other nonvolatile semiconductor memory devices such as a NAND flash memory and semiconductor memory devices such as a DRAM. Needless to say.

1 is a block diagram showing the overall configuration of a NOR flash memory according to a first embodiment. FIG. 2 is a block diagram showing one memory bank extracted in FIG. 1. The block diagram which shows the internal structure of one block in FIG. FIG. 4 is a circuit diagram showing a detailed configuration of a partial circuit in FIG. 3. The circuit diagram which shows the detailed structure of the partial circuit of a partial column decoder. FIG. 6 is a circuit diagram showing a detailed configuration of a partial circuit of the partial column decoder different from FIG. 5. FIG. 4 is a diagram illustrating an example of a relationship among a sense amplifier circuit, a burst read start address, and an address signal input to a partial column decoder in the memory according to the first embodiment. FIG. 5 is a block diagram showing a partial configuration of a NOR flash memory according to a second embodiment. FIG. 9 is a block diagram showing an extracted address selection / comparison circuit in FIG. 8. FIG. 10 is a block diagram showing a specific configuration of the address selection / comparison circuit of FIG. 9. FIG. 9 is a diagram showing a configuration of a circuit portion that generates a control signal provided in the address selection / comparison circuit in FIG. 8; FIG. 13 is a diagram showing a configuration of a circuit portion that is provided in the address selection / comparison circuit in FIG. 8 and generates a control signal different from that in FIG. 11. FIG. 11 is a circuit diagram showing a specific configuration of an address selection / comparison unit shown in FIG. 10. The figure which shows an example of the relationship between the sense amplifier circuit in the memory of 3rd Embodiment, the start address at the time of burst read, and the address signal input into a partial column decoder. 10 is a timing chart illustrating an example of the operation of the memory according to the fourth embodiment. FIG. 9 is a circuit diagram showing a configuration of part of an address control circuit in a memory according to a third embodiment. FIG. 10 is a circuit diagram showing a partial configuration of an address control circuit in a memory according to a fourth embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Memory cell array, 11 ... Row decoder, 12 ... Column selection circuit (CSL-SW), 13 ... Column decoder (COL), 14 ... Sense amplifier circuit group (S / A group), 15 ... Address buffer, 16 ... Address Control circuit, 17 ... Asynchronous latch circuit, 18 ... Data multiplexer (MUX), 19 ... Synchronous latch circuit, 20 ... Output buffer circuit, 21 ... Sense amplifier circuit, 51 ... Redundant column, 52 ... Defective address storage circuit, 53 ... Address Selection / comparison circuit, BNK ... bank, BLK ... block, SBLK ... sub-block.

Claims (5)

In a clock synchronous semiconductor memory device that performs burst read in synchronization with a clock signal,
A page length P is set so as to satisfy tACC ≦ tCLK * P, where tACC is a memory cell access time, tCLK is a clock signal period, and P is a page length. The semiconductor memory device
An address buffer that generates an internal address signal from an external address signal;
A memory cell array in which a plurality of pages of memory cells connected to word lines and bit lines are arranged;
A row decoder that selects the word line in response to a first address signal that is part of the internal address signal;
A sense amplifier circuit group that is divided for each page and includes a plurality of sense amplifier circuits for each page, and senses data read to the bit line;
A column selection circuit provided between the bit line and the sense amplifier circuit group, provided by the number of page lengths that select the bit line according to an input signal and connect to the sense amplifier circuit;
A plurality of column decoders provided for each column selection circuit, each of which outputs the input signal supplied to each column selection circuit corresponding to a second address signal that is a part of the internal address signal;
An address control circuit for controlling the second address signal supplied to the plurality of column decoders in response to a start page in which burst read is started among memory cells for a plurality of pages in the memory cell array. The semiconductor memory device according to claim 1.   3. The semiconductor memory device according to claim 2, wherein the address control circuit controls to change the second address signal supplied to the plurality of column decoders independently for each of the plurality of column decoders.   The address control circuit controls the change of the second address signal supplied to the plurality of column decoders independently for each group by dividing the plurality of column decoders into two sets of a lower page and an upper page. 3. The semiconductor memory device according to claim 2, wherein:   5. The semiconductor memory device according to claim 3, wherein the address control circuit performs control to restore the second address signal that has been changed once during burst read.

Images