JP2005233698A - Semiconductor device and failure detection method used therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of executing easily failure detection of a large-scale analog integrated circuit. <P>SOLUTION: Voltage inspection points 12-1 to 12-N are connected to a common voltage measuring wire 101 through an analog switch of combinational circuits 13-1 to 13-N. The analog switch is on-off controlled by an output from a corresponding D flip-flop. Each D flip-flop of the combinational circuits 13-1 to 13-N is operated when an enable signal 102 outputted from a controller 15 is "1". The voltage of each voltage inspection point 12-1 to 12-N appears successively in the voltage measuring wire 101 by operation of the controller 15. An A/D converter 14 converts the voltage into a four-bit digital signal, synchronizes the conversion result with a clock signal 105 which is a clock from the outside, and outputs it to the outside through a data line 104. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a failure detection method used therefor, and more particularly to a method of detecting a failure of an integrated circuit by measuring and reporting voltages at a large number of points in a large-scale analog integrated circuit.

  In recent years, progress in integrated circuits has been remarkable, and large-scale integration has become possible even in analog circuits such as high-frequency circuits. For example, it has become possible to achieve such a degree of integration that all transmission / reception circuits of a mobile phone can be accommodated in a single chip. Furthermore, as the degree of integration increases, the number of input / output terminals has also increased dramatically, with some pins reaching 81 pins.

  However, in the integrated circuit as described above, there is a strong demand for miniaturization, and it is necessary to reduce the size of the package. Therefore, a high-density mounting technique such as BGA (Ball Grid Array) is used.

  In conventional analog integrated circuits, high-density mounting technology such as BGA is used. However, with such a mounting method, if the package is mounted on the substrate, it is impossible to inspect the soldered portion from the outside. Therefore, it is becoming increasingly difficult to detect failures in integrated circuits.

JP 2001-85622 A

  In the conventional analog integrated circuit described above, it is becoming increasingly difficult to detect a failure in the integrated circuit, and in the future, a method capable of easily detecting the failure from the outside will be required.

  In a digital circuit, it is possible to detect a failure to some extent by operating a predetermined test pattern inside and notify an external CPU (central processing unit) or the like. However, such methods cannot be used in analog integrated circuits.

  Further, in an analog integrated circuit, depending on the failure detection method, there is a risk of adverse effects such as performance degradation. Therefore, as the failure detection method, a method that does not affect the analog signal as much as possible is desirable. Furthermore, in an analog integrated circuit, it is necessary to minimize the circuit scale and wiring amount required for failure detection.

  In the technique described in Patent Document 1, a failure can be easily detected from the outside, but a voltage generation circuit capable of generating an input voltage for testing an analog circuit or an output voltage of the analog circuit can be measured. A voltage measurement circuit must be installed, and the circuit scale and wiring amount cannot be minimized.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor device and a failure detection method used therefor that can solve the above-described problems and can easily detect a failure of a large-scale analog integrated circuit.

  A semiconductor device according to the present invention is a semiconductor device in which wiring for voltage measurement is provided in a circuit, wherein a plurality of voltage measurement points provided in the circuit and the plurality of voltage measurement points are respectively connected to the voltage. A plurality of switch means connected to the measurement wiring, a control circuit for sequentially turning on each of the plurality of switch means in response to an external control command, and a voltage on the voltage measurement wiring are converted into digital data. Conversion means for converting the digital data to the digital data.

  A failure detection method according to the present invention is a failure detection method for a semiconductor device in which wiring for voltage measurement is provided in a circuit, and a plurality of voltage measurement points provided in the circuit and the plurality of voltage measurements. The voltage generated on the voltage measurement wiring by connecting the points to the voltage measurement wiring by corresponding switch means, and sequentially turning on each of the switch means in response to an external control command. Is converted into digital data and sequentially output to the outside.

  That is, in the semiconductor device of the present invention, a large number of voltage measurement points are provided in the integrated circuit, and each of these voltage measurement points is connected to a voltage measurement wiring extending inside the integrated circuit through a switch. ing. The semiconductor device of the present invention includes a control circuit for sequentially turning on these switches in response to an external control command, and converts the voltage on the voltage measurement wiring into digital data by an A / D converter. Are output sequentially.

  Thus, in the semiconductor device of the present invention, it is possible to measure the voltage values of a large number of inspection points in the integrated circuit with the necessary minimum circuit scale and wiring amount, and to report to the outside. This makes it possible to easily detect a failure in an analog integrated circuit.

  In the semiconductor device of the present invention, each of the above switches is on / off controlled by the output of the D flip-flop connected in series, and only one switch is turned on by the shift clock supplied from the control circuit. Thus, the output signal of each D flip-flop is shifted.

  Furthermore, in the semiconductor device of the present invention, control means such as a CPU is provided outside the integrated circuit, and a failure detection operation is started by transmitting a control command from the CPU to the control circuit.

  Furthermore, in the semiconductor device of the present invention, the CPU receives digital data sequentially output from the integrated circuit to the outside, and determines whether it is within a predetermined allowable data range, The failure of the integrated circuit is determined.

  Here, in the semiconductor device of the present invention, in order to identify whether or not the plurality of inspection points are in a floating state, the failure detection is performed with the voltage measurement wiring intentionally connected to the power source or the ground with a resistor. Yes.

  According to the present invention, the configuration and operation described below can provide an effect that a failure detection of a large-scale analog integrated circuit can be easily performed.

  Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a semiconductor device (integrated circuit) according to an embodiment of the present invention. In FIG. 1, an integrated circuit 1 includes an internal circuit 11 such as a large-scale analog integrated circuit, a plurality of voltage inspection points (T1 to TN) 12-1 to 12-N arranged in the internal circuit 11, a plurality of The circuit is composed of combinational circuits 13-1 to 13-N corresponding to voltage inspection points (T1 to TN) 12-1 to 12-N, an A / D (analog / digital) converter 14, and a controller 15. .

  FIG. 2 is a block diagram illustrating a configuration example of the combinational circuits 13-1 to 13-N in FIG. In FIG. 2, the combination circuit 13 includes an analog switch 131 and a D flip-flop 132. Although not shown, the combinational circuits 13-1 to 13-N have the same configuration as the combinational circuit 13.

  FIG. 3 is a time chart showing a failure detection operation in the integrated circuit 1 according to one embodiment of the present invention. The failure detection operation in the integrated circuit 1 will be described with reference to FIGS. The voltages at the voltage inspection points (T1 to TN) 12-1 to 12-N are set to V1 to VN.

  These voltage inspection points (T1 to TN) 12-1 to 12-N are connected to the common voltage measurement wiring 101 via the analog switches 131 of the combinational circuits 13-1 to 13-N. The analog switch 131 is ON / OFF controlled by the outputs Q and QB of the corresponding D flip-flop 132. For example, when the Q output is “1”, it is turned on, and when it is “0”, it is turned off.

  Combination circuits 13-1 to 13-N of such analog switches 131 and D flip-flops 132 are provided corresponding to the respective voltage inspection points (T1 to TN) 12-1 to 12-N. The D flip-flops 132 of the circuits 13-1 to 13-N are connected in series (subordinate connection).

  The D flip-flops 132 of the combinational circuits 13-1 to 13 -N operate when the enable signal 102 output from the controller 15 is “1”. When the enable signal 102 is “0”, all except the D flip-flop 132 of the first combinational circuit 13-1 are reset, and the corresponding analog switch 131 is turned off.

  Only the D flip-flop 132 of the first combinational circuit 13-1 is set when the enable signal 102 is "0", and the corresponding analog switch 131 is on. That is, in a normal state, only the voltage inspection point (T1) 12-1 is connected to the voltage measurement wiring 101. In order to prevent performance degradation, the voltage inspection point (T1) 12-1 should be a point that is not easily affected by measurement such as a power source or a ground.

  When the enable signal 102 is “1”, the D flip-flop 132 of each of the combinational circuits 13-1 to 13 -N is in a state from the preceding D flip-flop 132 by the rising edge of the clock 2 signal 103. Works to shift. As a result, in each of the combinational circuits 13-1 to 13-N, the analog switches 131 are sequentially turned on sequentially from the front.

  In this way, the voltage at each of the voltage inspection points (T1 to TN) 12-1 to 12-N appears in the voltage measurement wiring 101 sequentially by the action of the controller 15. The A / D converter 14 converts this voltage into a 4-bit digital signal, and the conversion result is synchronized with a clock 1 signal 105, which is an external clock, via the data line 104 [for example, CPU ( To the central processing unit)].

  The above operation is started by activating the controller 15 by an inspection command from an external CPU or the like. This inspection command is transmitted to the controller 15 from an external CPU or the like via a 3-wire serial bus including a data battle 104, a clock 1 signal 105, and a strobe (STROBE) line 106.

  The data line 104 is bidirectional, and when a test command is received, a signal is passed from the external CPU or the like to the controller 15, and digital data of voltages at voltage test points (T1 to TN) 12-1 to 12-N is received. Conversely, the data is transmitted from the controller 15 to a control means such as an external CPU via the data line 104.

  As described above, in this embodiment, by transmitting a test command from the outside to the integrated circuit 1, the voltages of a large number of voltage test points (T1 to TN) 12-1 to 12-N inside the integrated circuit 1 are collected. be able to.

  FIG. 4 shows a minimum value (Min) and a maximum value (Max) corresponding to normal values of voltages at voltage test points (T1 to TN) 12-1 to 12-N stored in advance in the control means according to an embodiment of the present invention. ). The operation of a control means such as a CPU will be described with reference to FIG. Hereinafter, the operation of the CPU will be described.

  In the CPU, as shown in FIG. 4, a minimum value (Min) and a maximum value (Max) corresponding to normal values of the voltages at the voltage inspection points (T1 to TN) 12-1 to 12-N are previously stored. It is remembered. Such data is determined at the time of design, for example, and written in a nonvolatile memory (not shown) or the like at the time of factory shipment.

  After the CPU transmits the inspection command to the integrated circuit 1, it receives the digital value of the measured voltage at each of the voltage inspection points (T1 to TN) 12-1 to 12-N from the integrated circuit 1 through the same 3-wire serial bus. Store in a memory (not shown). When the word length of the A / D converter 14 is 4 bits, data can be written in hexadecimal code for the table shown in FIG.

  FIG. 5 is a flowchart showing a failure detection operation of the integrated circuit 1 shown in FIG. With reference to FIG. 1 to FIG. 5, the operation of detecting a failure of the integrated circuit 1 by the CPU described above in one embodiment of the present invention will be described.

  When the inspection is started, the CPU sequentially reads the measured voltage values at the voltage inspection points (T1 to TN) 12-1 to 12-N by the above-described processing (steps S1 and S2 in FIG. 5).

  The CPU compares the measured voltage values of the read voltage inspection points (T1 to TN) 12-1 to 12-N with the maximum value (Max) and the minimum value (Min) previously stored in the nonvolatile memory, If there is something exceeding this range (minimum value ≦ data ≦ maximum value) (step S3 in FIG. 5), it is determined that there is a failure (step S7 in FIG. 5).

  Further, the CPU compares the read measurement voltage values of the respective voltage inspection points (T1 to TN) 12-1 to 12-N with the maximum value (Max) and the minimum value (Min) stored in the nonvolatile memory in advance. If there is nothing exceeding this range (minimum value ≦ data ≦ maximum value) (steps S3 to S5 in FIG. 5), it is determined as normal (step S6 in FIG. 5).

  As described above, in this embodiment, the voltage values of a large number of voltage test points (T1 to TN) 12-1 to 12-N in the integrated circuit 1 are measured with the minimum necessary circuit scale and wiring amount, and externally. Therefore, failure detection of a large-scale analog integrated circuit can be easily performed.

  FIG. 6 is a block diagram showing a configuration of a semiconductor device (integrated circuit) according to another embodiment of the present invention. 6, another embodiment of the present invention has the same configuration as that of the integrated circuit 1 according to another embodiment of the present invention shown in FIG. 1 except that a changeover switch 21 and resistors 22 and 23 are provided in the integrated circuit 2. The same components are denoted by the same reference numerals. In another embodiment of the present invention, the above-described configuration provides a wider range of failure detection.

  In one embodiment of the present invention, for example, it is assumed that the voltage inspection point (Ti) 12-i is a high impedance input terminal, and that terminal is poorly soldered. In such a case, since the voltage inspection point (Ti) 12-i is in a floating state, there is a possibility that the power supply voltage becomes unstable and happens to be in the normal range.

  In this embodiment, as a method for preventing a failure in failure detection due to such a reason, as shown in FIG. 6, a state where the power supply or the ground line is intentionally connected via the changeover switch 24 and resistors 25 and 26. It is conceivable to perform measurement with

  For example, if soldering is performed correctly and an external bias is applied, the voltage value does not change much even if it is connected to the power supply or the ground with a few resistors. On the other hand, when the connection is not established due to a defective solder, it sticks to the power supply or the ground, so that a failure can be detected.

1 is a block diagram showing a configuration of a semiconductor device (integrated circuit) according to an embodiment of the present invention. It is a block diagram which shows the structural example of the combinational circuit of FIG. It is a time chart which shows the operation | movement of the fault detection in the integrated circuit by one Example of this invention. It is a figure which shows the minimum value (Min) and maximum value (Max) corresponding to the normal value of the voltage of the voltage test | inspection point (T1-TN) memorize | stored beforehand by the control means by one Example of this invention. 2 is a flowchart showing a failure detection operation of the integrated circuit shown in FIG. It is a block diagram which shows the structure of the semiconductor device (integrated circuit) by the other Example of this invention.

Explanation of symbols

1, 2 Integrated circuit
11 Internal circuit 12-1 to 12-N Voltage inspection point (T1 to TN)
13-1 to 13-N combinational circuit
14 A / D converter
15 Controller
131 Analog switch
132 D flip-flop

Claims (14)

  A semiconductor device in which wiring for voltage measurement is arranged inside a circuit, wherein a plurality of voltage measurement points provided in the circuit and the plurality of voltage measurement points are respectively connected to the voltage measurement wiring A plurality of switch means, a control circuit for sequentially turning on each of the plurality of switch means in response to an external control command, and a conversion means for converting the voltage on the voltage measurement wiring into digital data. And a semiconductor device for sequentially outputting the digital data to the outside.   2. The semiconductor device according to claim 1, wherein the digital data is a value corresponding to voltages at the plurality of voltage measurement points.   A plurality of flip-flop circuits that control the on / off of each of the plurality of switch means according to a signal from the control circuit and that are each connected in cascade; the plurality of flip-flop circuits being supplied from the control circuit; 3. The semiconductor device according to claim 1, wherein a shift operation is performed by turning on one of the plurality of switch means with the output thereof.   4. The semiconductor device according to claim 1, wherein the control circuit starts a failure detection operation of the device itself in response to the reception of the control command.   2. The apparatus according to claim 1, wherein it is determined whether or not the digital data sequentially output to the outside is within a preset allowable range, and the presence or absence of a failure in the own apparatus is detected according to the determination result. Item 5. The semiconductor device according to any one of Items 4 to 4.   2. The apparatus according to claim 1, further comprising switching means for setting the voltage measurement wiring to a stable voltage state, wherein the switching means detects the presence or absence of a failure in the own apparatus as the stable voltage state. The semiconductor device according to claim 5.   7. The semiconductor device according to claim 6, wherein the switching unit connects the voltage measurement wiring to one of a power supply and a ground.   A failure detection method for a semiconductor device in which wiring for voltage measurement is provided in a circuit, wherein a plurality of voltage measurement points provided in the circuit and the plurality of voltage measurement points are respectively used as corresponding switch means Are connected to the voltage measurement wiring, and the switch means are sequentially turned on exclusively in response to a control command from the outside, thereby converting the voltage generated on the voltage measurement wiring into digital data and A failure detection method characterized by sequentially outputting to a fault.   9. The failure detection method according to claim 8, wherein the digital data is a value corresponding to voltages at the plurality of voltage measurement points.   A plurality of flip-flop circuits each controlling the on / off of each of the switch means and being cascade-connected, and the plurality of flip-flop circuits at the output when performing a shift operation by a shift clock supplied from the control circuit 10. The failure detection method according to claim 8, wherein one of the switch means is turned on.   11. The failure detection method according to claim 8, wherein a failure detection operation of the semiconductor device is started in response to reception of the control command.   9. The method according to claim 8, wherein it is determined whether or not the digital data sequentially output to the outside is within a preset allowable range, and whether or not there is a failure in the semiconductor device is detected according to the determination result. The failure detection method according to claim 11.   13. The failure detection method according to claim 8, wherein the presence or absence of a failure in the semiconductor device is detected by setting the voltage measurement wiring to a stable voltage state. 14. The failure detection method according to claim 13, wherein the voltage measurement wiring is connected to one of a power supply and a ground to achieve the stable voltage state.

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