JP2005218714A - Game table - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent an illegal action in a game table for determining the content of a game, based on the result in a random number lot, by performing the random number lot such as an internal lot through the use of a random number generating circuit. <P>SOLUTION: This game table for determining the content of the game, based on the result in the random number lot, comprises: a CPU (central processing unit, 200) to be functioned as an output means for outputting a random number holding command; the random number generating circuit (220) for counting a clock signal to be periodically changed and holding the count value at the time when the holding command is outputted from the CPU (200) as a random number value; and the CPU (200) to be functioned as a lotting means for acquiring the random number value which is held by the random number generating circuit (220) and performing the random number lot, based on the acquired random number value. The CPU (200) to be functioned as the output means delays the output timing of the holding command in response to the value of a refresh register. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a game machine represented by a slot machine (pachislot).

  The slot machine has a plurality of reels displaying a plurality of symbols, rotates the reels by inserting medals, etc., and operates the stop switch provided for each reel to stop and stop the corresponding reel. It is determined whether the symbol combination of each reel is a predetermined winning combination, and if the determination result is the winning combination, the number of medals according to the type of the winning combination Etc. are paid out.

  In a recent slot machine, the above gaming machine is controlled by an electronic computer. For example, the internal lottery of a winning combination is performed by acquiring a counter value output from a random number generation circuit (counter) of the control unit when the start lever is operated.

  However, the random number generation circuit generally uses a counter IC that updates a value by periodically incrementing a value in a predetermined range (for example, 0 to 65535).

  Therefore, by remodeling the low-frequency treatment device, synchronize the cycle of the electrical stimulation output to the electrical pad affixed to the arm and the random number generation circuit, and use the movement of the arm muscle by the electrical stimulation. By operating the start lever, illegal acts that continue to win big hits (internal wins) are starting to occur.

In order to prevent such illegal activities, for example, Patent Document 1 proposes a technique for performing an internal lottery using calculation results based on values of a basic counter and an auxiliary counter.
JP 2003-93660 A

  However, since the arithmetic processing disclosed in Patent Document 1 uses two counters, a basic counter and an auxiliary counter, many instructions are executed (that is, the arithmetic processing load is high), and the memory capacity is reduced. There was a problem that.

  The present invention has been made in view of such a problem. First, a game machine that performs random lottery such as internal lottery using a random number generation circuit and determines the contents of the game based on the result of the random lottery. The purpose is to prevent the occurrence of illegal activities.

  Secondly, an object of the present invention is to prevent the occurrence of illegal activities without increasing the calculation processing load.

In order to achieve the above object, a game machine according to the present invention has the following configuration. That is,
A game machine that determines the content of the game based on the result of random number lottery,
An output means for outputting a command for acquiring a random value on the basis of a predetermined condition;
Random number generating means for counting a periodically changing clock signal and generating the counted value as a random value based on a command for acquiring the random value from the output means;
Lottery means for obtaining a random value generated by the random number generation means, and performing the random number lottery based on the acquired random number value,
The output means includes
In response to the predetermined condition, a command for obtaining the random number value with an irregular delay amount is output.

In order to achieve the above object, another game machine according to the present invention has the following configuration. That is,
A game machine that determines the content of the game based on the result of random number lottery,
An output means for outputting a command for acquiring a random value on the basis of a predetermined condition;
Random number generating means for counting a periodically changing clock signal and generating the counted value as a random value based on a command for acquiring the random value from the output means;
Lottery means for acquiring a random value generated by the random number generator and performing the random number lottery based on the acquired random value;
And at least count-up means for counting up at a period different from that of the clock signal,
The output means includes
The output timing of a command for obtaining the random number value is delayed according to the value counted up by the count-up means.

In order to achieve the above object, another game machine according to the present invention has the following configuration. That is,
A game machine that determines the content of the game based on the result of random number lottery,
An output means for outputting a random value holding instruction in response to a predetermined condition;
Random number generating means for counting periodically changing clock signals and holding the count value when the holding command is output from the output means as a random value;
Lottery means for acquiring a random number value held in the random number generation means and performing the random number lottery based on the acquired random number value;
And at least count-up means for counting up at a period different from that of the clock signal,
The output means includes
The output timing of the holding command is delayed according to the value counted up by the count-up means.

  In the gaming machine, the count-up means counts up in association with processing in the gaming machine, and the value counted up in association with processing in the gaming machine is the It is a value of a refresh register provided in an arithmetic processing unit that executes control processing of a game machine.

  According to the present invention, it is possible to prevent the occurrence of illegal activities in a game machine that performs random lottery such as internal lottery using a random number generator and determines the contents of the game based on the result of the random lottery.

  Furthermore, according to the gaming table, it is possible to prevent the occurrence of illegal activities without increasing the calculation processing load.

  First, the outline of each embodiment will be briefly described. Like a general slot machine, the ON signal from the start operation unit is directly input to one counter that periodically counts up, and internal lottery is performed based on the count value of the counter when there is an input. If this is done, it is possible to make an internal winning every time by matching the timing of turning on the start operation unit with the cycle of the counter.

  On the other hand, in each of the following embodiments, an irregular delay amount is added to the ON signal from the start operation unit and then input to the random number generation circuit (counter) to avoid such a state. To do. In other words, by adding an irregular amount of delay, even if the start operation unit is turned on at regular intervals, the timing input to the counter does not become regular intervals, and as a result, the above-mentioned illegal activities can be avoided. Details of preferred embodiments of the present invention will be described below with reference to the drawings.

[First Embodiment]
1. Overall Configuration of Slot Machine FIG. 1 is a perspective view of a slot machine 100 according to an embodiment of the present invention. In general, the slot machine 100 includes a plurality of reels provided with a plurality of types of symbols, lottery means for determining whether or not an internal winning of a plurality of types of winning combinations is won by a random number lottery, and rotation of the reels. A combination of a start operation unit, a stop button provided for each of the reels, for individually stopping the rotation of the reels, and the symbols displayed by the reels at the time of the stop is determined in advance. Determination means for determining a winning based on whether or not a combination of symbols.

  In the present embodiment, a technique for preventing a fraudulent act against a random number lottery mainly for determining whether or not an internal winning of a winning combination is successful, a random number lottery for drawing in, and a random number lottery for mode transition will be described. Needless to say, the technology can be applied to other random lotteries.

  In the center of the slot machine 100 shown in FIG. 1, three reels (left reel 110, middle reel 111, and right reel 112) having a plurality of types of symbols arranged on the outer peripheral surface are stored. It is configured to be able to rotate. In the present embodiment, each symbol is printed on the belt-like member at an appropriate interval (for example, 21 symbols), and this reel-like member is attached to a predetermined circular frame member to constitute each reel 110 to 112. When viewed from the player, the symbols on the reels 110 to 112 are generally displayed three in the vertical direction from the symbol display window 113 so that a total of nine symbols can be seen. Then, by rotating the reels 110 to 112, the combination of symbols that can be seen by the player varies. In the present embodiment, three reels are provided in the center of the slot machine 100, but the number of reels and the installation position of the reels are not limited to this.

  In addition, a backlight (not shown) for illuminating each symbol displayed on the symbol display window 113 is disposed on the back of each reel 110 to 112. It is desirable that the backlight is shielded for each symbol so that the individual symbols can be illuminated evenly. In the slot machine 100, an optical sensor (not shown) including a light projecting unit and a light receiving unit is provided in the vicinity of each of the reels 110 to 112. The light projecting unit and the light receiving unit of the optical sensor are provided. A light shielding piece of a certain length provided on the reel passes between the parts. Based on the detection result of this sensor, the position of the symbol on the reel in the rotation direction is determined, and the reels 110 to 112 are stopped so that the target symbol is displayed on the winning line 114.

  The winning line display lamp 120 is a lamp that indicates an effective winning line. An effective pay line is determined in advance by the number of game media (in this embodiment, medals are assumed) inserted into the slot machine 100. Of the five winning lines 114, for example, when one medal is inserted, the middle horizontal winning line is valid, and when two medals are inserted, the upper horizontal winning line and the lower horizontal winning line are added. When three medals are inserted and three medals are inserted, the five added with the right-down winning line and the upper-right winning line become effective as the winning line. Note that the number of winning lines 114 is not limited to five.

  The start lamp 121 is a lamp that informs the player that the reels 110 to 112 are in a state of being able to rotate. The re-game lamp 122 is a lamp for notifying the player that the current game can be re-played (the medal need not be inserted) when winning a re-game which is one of the winning combinations in the previous game. . The notification lamp 123 is a lamp that informs the player that a specific winning combination (specifically, a bonus such as a big bonus or a regular bonus) is won internally in an internal lottery described later. The medal insertion lamp 124 is a lamp that notifies that a medal can be inserted. The reel panel lamp 128 is an effect lamp. The medal insertion buttons 130 and 131 are buttons for inserting a predetermined number of medals stored electronically in the slot machine 100.

  In this embodiment, every time the medal insertion button 130 is pressed, a maximum of three are inserted one by one, and when the medal insertion button 131 is pressed, three are inserted. The medal slot 134 is an slot for a player to insert a medal when starting a game. That is, the medal can be inserted electronically by the medal insertion button 130 or 131, or an actual medal can be inserted from the medal insertion slot 134. The payout number display 125 is a display for displaying the number of medals to be paid out to the player as a result of winning a winning combination.

  The game number display 126 is a display for displaying the number of games during the big bonus game (in the BB game), the number of winnings of a predetermined winning combination, and the like. The stored number display 127 is a display for displaying the number of medals electronically stored in the slot machine 100. The start operation unit 135 is a unit for starting the rotation of the reels 110 to 112. When a desired number of medals is inserted into the medal insertion slot 134 and the start operation unit 135 is operated, an internal lottery of a winning combination and the rotation of the reels 110 to 112 are started.

  The stop button unit 136 is provided with stop buttons 137 to 139. The stop buttons 137 to 139 are button-type switches for individually stopping the reels 110 to 112 that have started rotating by the operation of the start operation unit 135. Note that a light emitter may be provided inside each stop button 137 to 139, and when the stop button 137 to 139 can be operated, the light emitter may be turned on to notify the player.

  The storage / settlement button 132 settles a medal electronically stored in the slot machine 100 and discharges it to the tray 210 from the medal payout outlet 155, and the four or more sheets inserted into the medal slot 134. This is a button for switching between a storage function for electronically storing up to 50 medals and medals obtained by winning.

  The door key 140 is a hole into which a key for unlocking the front door 102 of the slot machine 100 is inserted. The medal payout exit 155 is a payout exit for paying out medals. The medal tray 210 is a container for collecting medals paid out from the medal payout opening 155. In this embodiment, the medal tray 210 employs a tray that can emit light, and may be hereinafter referred to as a tray lamp.

  The sound hole 160 is a hole for outputting the sound of a speaker provided inside the slot machine 100 to the outside. The upper lamp 150, the side lamp 151, the center lamp 152, the waist lamp 153, and the lower lamp 154 are decorative lamps for exciting games. The rendering device 170 includes a liquid crystal display device that displays various types of information.

2. Configuration of Main Control Unit Next, the configuration of the control unit of the slot machine 100 will be described in detail with reference to FIG. The slot machine 100 includes a main control unit that controls the central part of the game, and a sub-control unit (not shown) that controls various devices in accordance with signals transmitted from the main control unit. The sub-control unit performs, for example, a process related to the effect such as the control of the effect device 170. However, in this embodiment, the sub-control unit is not directly involved in preventing fraud against random lottery, so the description is omitted. Will be described.

  The main control unit includes a CPU 200 that is an arithmetic processing unit for controlling the whole, a data bus and an address bus for the CPU 200 to transmit and receive signals to and from each IC and each circuit, and has the following configuration: . The clock circuit 202 divides the clock signal oscillated from the crystal oscillator 201 and supplies it to the CPU 200. For example, when the frequency of the crystal oscillator 201 is 12 MHz, the divided clock signal is 6 MHz. The CPU 200 operates by receiving the clock signal divided by the clock circuit 202 as a system clock. The CPU 200 is connected to a timer circuit 203 for setting a monitoring cycle for constantly monitoring the states of sensors and switches, which will be described later, and a transmission cycle of motor drive pulses, via a bus.

  The timer circuit 203 determines a fixed interrupt time based on the received frequency division data, and transmits an interrupt request to the CPU 200 for each interrupt time. In response to this interrupt request, the CPU 200 executes monitoring of each sensor and transmission of drive pulses. For example, when the system clock of the CPU 200 is set to 6 MHz, the frequency division value of the timer circuit 203 is set to 1/256, and the data for frequency division of the ROM 204 is set to 44, the reference time for this interrupt is 256 × 44 ÷ 6 MHz = 1. It becomes 877 ms and becomes a fixed cycle.

  Also connected to the CPU 200 are a program for controlling each IC, a lottery data used in the internal lottery of the winning combination, a ROM 204 for storing reel stop positions, and a RAM 205 for storing temporary data. Has been. Other storage means may be used for these ROM 204 and RAM 205.

  The CPU 200 is connected to an input interface 206 for receiving an external signal. The medal acceptance sensor 207, the stop button sensor 208, and the start operation detection are detected via the input interface 206 every interrupt time of the interrupt cycle described above. The state of the sensor 209 or the like is detected, and the detection result of each sensor is monitored.

  Two medal acceptance sensors 207 are installed in the passage inside the medal insertion slot 134 and detect whether or not a medal has passed. The start operation detection sensor 209 is installed in the start operation unit 135 and detects a start operation by the player. The stop button sensor 208 is installed in each of the stop buttons 137 to 139 and detects the operation of the stop button by the player.

  An index sensor 217 is connected to the input interface 219. The index sensor 217 is installed at a predetermined position on the mounting base of each of the reels 110 to 112, and becomes H level each time the light shielding piece provided on the reel passes through the index sensor 217. When detecting this signal, the CPU 200 determines that the reel has made one rotation and resets the rotational position information of the reel to zero.

  The output interface 218 is configured to drive a reel motor driving unit 213 for driving a reel and a motor of a hopper (a device for paying out medals accumulated in a bucket from a medal payout outlet 155). Hopper motor driving unit 214, a game lamp 215 (specifically, a winning line display lamp 120, a start lamp 121, a replay lamp 122, a notification lamp 123, a medal insertion lamp 124, etc.), and a 7-segment indicator 216 (payout) A number display device 125, a game number display device 126, a stored number display device 127, etc.) are connected. An output interface 210 for transmitting a command to the sub control unit is connected to the data bus of the CPU 200.

  In addition, a random number generation circuit 220 is connected to the CPU 200 via a data bus. The random number generation circuit 220 counts clock signals oscillated from the crystal oscillator 211. When a latch signal is input from the CPU 200, the count value at that time is held as a random value. Further, the CPU 200 selects the random number generation circuit 220 via the address decoding circuit 212 (that is, inputs a chip select signal), thereby acquiring the held random number value. The acquired random number value is used for random lottery such as internal lottery of a winning combination.

3. Flow diagram of the overall game processing 3 is a flowchart showing the basic control of the game in the slot machine 100 of the present embodiment. The basic control of the game is performed mainly by the CPU 200, and the game process shown in FIG. Hereinafter, this game process will be described.

  After the power is turned on and various initialization processes are performed, in step S300, a process related to medal reception is performed. Here, it is checked whether or not medals have been inserted, and the winning line display lamp 120 is turned on according to the number of medals inserted. It is not necessary to insert a medal when winning the re-game in the previous game. In step S310, a process related to accepting a game start operation is performed. Here, it is checked whether or not the start operation unit 135 has been operated. If it is determined that the start operation unit 135 has been operated, the number of inserted medals is determined, and an effective pay line 114 is determined.

  In step S320, a delay process is performed. The delay process is a process for adjusting a time from when it is determined that the start operation unit 135 is operated until a latch signal (a signal for internally holding a counter value) is input to the random number generation circuit 220. is there. Each time the start operation unit 135 is operated, delay processing is performed with a different delay time. Details will be described later.

  In step S330, the latch signal is input to the random number generation circuit 220 at the timing when the delay process (step S320) is completed, and the random number acquisition process 1 is performed. The random number acquisition process 1 is a process for acquiring a counter value when the latch signal is input as a random value for performing an internal lottery of a winning combination. Details of the random number acquisition process 1 will be described later.

  Similarly, in step S340, the latch signal is input to the random number generation circuit 220 at the timing when the delay process (step S320) is completed, and the random number acquisition process 2 is performed. The random number acquisition process 2 is a process for acquiring a counter value when the latch signal is input as a random value used for symbol drawing and mode transition lottery. Details of the random number acquisition process 2 will be described later.

  In step S350, an internal lottery of a winning combination is performed using the random value acquired in step S330 and a winning combination lottery table stored in the ROM 204. Further, an effect lottery for selecting an effect mode of the slot machine 100 is also performed, and the selected effect is executed. Further, based on the random number values acquired in step S340 (specifically, there are two types), a symbol drawing lottery when selecting the reel stop control table and a mode transition lottery when determining the number of rights, etc. are performed. .

  In step S360, rotation of all reels 110 to 112 is started. At this time, one reel stop control table is selected by referring to the reel stop control table selection table stored in the ROM 204 on the basis of the symbol drawing lottery result in step S350. The selected reel stop control table number is stored in a command and transmitted to the sub-control unit.

  In step S370, the stop buttons 137 to 139 can be received. When any one of the stop buttons is pressed, any of the reels 110 to 112 corresponding to the pressed stop button is selected as the reel stop selected in step S360. Stop based on the control table. In step S380, a winning determination is performed. Here, it is determined that the winning combination is won when the symbol combination corresponding to the winning combination that has been won internally or the winning combination with the flag carried over is displayed on the activated winning line 114.

  In step S390, if any winning combination with payout is won, the number of medals corresponding to the winning combination is paid out. As described above, one game is completed, and the game progresses by repeating this thereafter. In the following, details of each process of the game process shown in FIG. 3 will be described.

4). 4. Details of Delay Processing (Step S320) 4.1 Acquisition of Counter Value for Delay Time Calculation In this embodiment, the counter value acquired as an internal register of CPU 200 is used for the delay processing. First, the internal configuration of the CPU 200 will be described.

  FIG. 4 is a diagram illustrating an internal configuration of the CPU 200. The address signal is output to the address bus via the address bus output circuit 400. The data bus controls input / output via the data bus interface 402.

  The operation code read from the memory (ROM 204) through the data bus is written to the instruction register 403. This opcode is decoded by the instruction decoder 404. The operation code decoded by the instruction decoder 404 is output from the basic control signal generation unit 406 to each unit as a control signal. The ALU 401 executes various arithmetic processes according to the control signal. The register group 405 is used for temporarily storing data information in the arithmetic processing, and is composed of static RAM and 18 8-bit registers and 4 16-bit registers. In the present embodiment, the value of an 8-bit memory refresh register (R register) in the register group 405 is used for delay processing described later.

  Here, the function of the R register will be briefly described. The R register is used as a memory refresh counter when a dynamic RAM is used as the memory. Thereby, it can be used for dynamic memory in the same way as static memory. Of the 8 bits, the lower 7 bits are automatically incremented for each instruction fetch. The contents of the R register are sent to 8 bits of the address bus in synchronization with the refresh signal while the instruction fetched by the CPU 200 is decoded and executed. That is, the R register functions as a counter that automatically increments a value from 0 to 127 for each operation code fetch cycle of each instruction.

  As described above, since the value is incremented every operation code fetch cycle, the count-up timing of the value of the R register is random (irregular).

4.2 Flow of Delay Processing FIG. 5A shows a detailed flow of delay processing in the CPU 200 using the value of the R register.

  When delay processing is started in accordance with the operation of the start operation unit 135, in step S500, the value of the R register is acquired with input of a signal from the start operation detection sensor 209, and in step S501, the acquired acquisition is performed. The value of the R register is written into a predetermined area (RT0) of the RAM 205. Note that the value of the R register is automatically incremented for each instruction such as a process waiting for a start operation and an interrupt process. Therefore, even if a signal from the start operation detection sensor 209 is input at regular intervals, The value obtained from the R register is irregular.

  In step S502, the value of RT0 written in the RAM 205 in step S501 is monitored. Here, the value written in RT0 of the RAM 205 is subtracted by the interrupt process shown in FIG. FIG. 5B is a diagram showing the flow of interrupt processing for the CPU 200, and executes processing by interrupting every interrupt cycle (1.877 msec). In step S503, it is determined whether RT0 is larger than 0. If larger, it is subtracted (decremented) in step S504.

  When the value of RT0 in the RAM 205 becomes 0 as a result of the subtraction by the interrupt process, “YES” is determined in the step S502, and the delay process is ended.

  As described above, the delay time is counted by an interrupt process with an interrupt period of 1.877 msec, and the main process only determines whether RT0 = 0. As is clear from the above description, the delay time due to such delay processing also takes a random value due to the irregularity of the R register.

5. Details of Random Number Acquisition Processing (Steps S330 and 340) 5.1 Configuration of Random Number Generation Circuit First, the detailed configuration of the random number generation circuit 220 for executing the random number acquisition processing will be described. FIG. 6 is a diagram showing a circuit configuration of the random number generation circuit 220. The random number generation circuit 220 includes five counters 601 to 605. Each of the counters 601 to 605 is an 8-bit binary counter (IC, for example, HD74HC590P), and the counters 601 to 603 are based on a random number value (that is, 0) based on a clock signal oscillated from the crystal oscillator 201. Counters 604 and 605 output 16-bit random values (that is, values in the range of 0 to 65535), respectively, based on the clock signal oscillated from the crystal oscillator 211. The 24-bit random value output by the counters 601 to 603 is used for symbol drawing and mode transition lottery, and the 16-bit random value output by the counters 604 and 605 is used for internal winning lottery. Is done. In the present embodiment, the number of clocks is different from that of the crystal oscillators 201 and 211 (crystal oscillator 201 = 12 MHz, crystal oscillator 211 = 14.331818 MHz).

  A chip select signal for the counter 601 is input to the counters 601 to 603 in parallel as a latch signal. The counters 601 to 603 acquire the values of the internal counters when the chip select signal for the counter 601 is turned ON (Low → High; in the state of signal rising), and the counter values are stored in the internal registers of the counters 601 to 603. Hold on.

  In the case of the counter 601, the counter value held in the internal register is output at the timing when the chip select signal for the counter 601 is turned OFF, and is stored in the RAM 205 as an 8-bit (D0 to D7) signal.

  In the case of the counters 602 and 603, the counter value held in the internal register is output at the timing when each chip select signal for the counters 602 and 603 is changed from OFF to ON to OFF, and each has 8 bits (D0 to D0). D7) is stored in the RAM 205.

  Similarly, a chip select signal for the counter 604 is input in parallel to the counters 604 and 605 as a latch signal. In the counters 604 and 605, when the chip select signal for the counter 604 is turned ON (Low → High; signal rising), the values of the internal counters are respectively acquired, and the counter values are held in the internal registers of the counters 604 and 605. .

  In the case of the counter 604, the counter value held in the internal register is output at the timing (signal falling) when the chip select signal for the counter 604 is turned OFF, and stored in the RAM 205 as an 8-bit (D0 to D7) signal. . In the case of the counter 605, the counter value held in the internal register is output at the timing when the chip select signal for the counter 605 changes from OFF to ON to OFF, and is output to the RAM 205 as an 8-bit (D0 to D7) signal. Stored.

5.2 Random Number Acquisition Process Flow FIG. 7 shows the flow of random number acquisition processes 1 and 2 in the random number generation circuit. As described above, after the delay process (step S320) is executed in response to the acceptance of the start operation (step S310), the random number acquisition process 1 (random number acquisition process for internal lottery of the winning combination) shown in FIG. The CPU 200 executes a port input command (an input command to each port of the random number generation circuit 220). When a chip select signal for the counter 604 is output from the address decoding circuit 212 in accordance with the port input command, the counters 604 and 605 hold (latch) the value of the internal counter in the internal register (step S700).

  Thereafter, the value of the internal counter held (latched) in the internal register of the counter 604 is output to the RAM 205 (step S701).

  Further, when the chip select signal for the counter 605 is output, the value of the internal counter held (latched) in the internal register of the counter 605 is output to the RAM 205 (step S702). Thus, the stored 16-bit counter value is used for the internal lottery of the winning combination in the lottery process in step S350 of FIG.

  Similarly, as shown in FIG. 7B, when the random number acquisition process 2 (table lottery and mode transition random number acquisition process) is started and a chip select signal for the counter 601 is output, the counters 601 to 603 are output. Holds (latches) the value of the internal counter in the internal register (step S710).

  Thereafter, the value of the internal counter held (latched) in the internal register of the counter 601 is output to the RAM 205 (step S711).

  Further, when the chip select signals for the counters 602 and 603 are sequentially output, the values of the internal counters held (latched) in the internal registers of the counters 602 and 603 are output to the RAM 205 (steps S712 and 713). .

5.3 Detailed Description of Counter Next, the counters (601 to 605) used in the random number generation circuit 220 will be described. FIG. 8 is a diagram for explaining the function of the counter 601 (configuration of input ports and signals of each port) (counters 602 to 605 are basically the same as the counter 601 and are representatively shown here). The counter 601 will be described). In FIG. 5A, the counter 601 is counted up by the rising signal of the counter clock (CCLK) when the counter clock enable (CCLKEN) becomes “Low”.

  The counter value of the counter 601 is held (latched) in the internal register by turning on the rising signal of the register clock (RCLK), that is, the chip select signal for the counter 601 (801 in FIG. 8B). When the enable control (G: gate) becomes “Low” (802 in FIG. 8B), the counter value is output to the RAM 205.

  Each counter (601 to 605) increments the counter when the clock signal (CCLKEN) is Low, and stops incrementing when the signal is “High” (803 in FIG. 8B). However, as shown in the figure, in the case of the counters 601 and 604, since CCLKEN is at the ground, it is always incremented.

  Each counter turns the RCO signal from ON to OFF when 0 → 255 (maximum value). At this time, since the clock signal (CCLKEN) of the counter 602, 603, or 605 (higher counter) becomes Low, the higher counter is incremented. In this way, a 16-bit counter value can be acquired from the counters 604 and 605, and a 24-bit counter value can be acquired from the counters 601 to 603, respectively.

6). Embodiments The operation of each section when processing is actually executed using a main control section having the above-described configuration will be briefly described.

  When the start operation unit 135 is turned on (901), the reels 110, 111, and 112 start to rotate (902, 903, and 904). At the same time, the value of the R register is acquired, the value of the R register is set in RT0 of the RAM 205, and delay processing is started (905). When RT0 becomes 0, a latch signal is input to the counters 601 to 605 of the random number generation circuit 220, and the counter value at that time is held in the internal register (906). The internal lottery for winning combination, the lottery for drawing-in, and the mode shift lottery are performed using the counter values held in the counters 601 to 605.

  As shown in FIG. 9, acquisition of counter values (counter values output from counters 601 to 603) used for symbol drawing lottery and mode transition lottery is executed in response to an operation of the start operation unit 135. Not limited to. For example, when each stop button (137 to 138) is pressed, a delay process may be executed to obtain a counter value.

  Specifically, when the stop button 137 is turned on (907), the value of the R register is acquired, the value of the R register is set in RT0 of the RAM 205, and delay processing is started (910). When RT0 becomes 0 (911), a latch signal is input to the counters 601 to 603 of the random number generation circuit 220, and the counter value at that time is held in the internal register (912). The lottery for drawing the reel 110 is performed using the counter value.

  Similarly, when the stop button 138 is turned on (908), the value of the R register is acquired, the value of the R register is set in RT0 of the RAM 205, and delay processing is started (913). When RT0 becomes 0 (914), a latch signal is output to the counters 601 to 603 of the random number generation circuit 220, and the counter value at that time is held in the internal register (915). The lottery for drawing the reel 111 is performed using the counter value. Since the stop button 137 and the stop button 138 are turned on at different timings, the value of the acquired R register is also different. As a result, the delay time is also different as shown in FIG.

  Similarly, when the stop button 139 is turned on (909), the value of the R register is acquired, the value of the R register is set in RT0 of the RAM 205, and delay processing is started (916). When RT0 becomes 0 (917), a latch signal is input to the counters 601 to 603 of the random number generation circuit 220, and the counter value at that time is held in the internal register (918). The lottery for drawing the reel 112 is performed using the counter value.

  As is clear from the above description, according to the slot machine according to the present embodiment, by performing delay processing using the R register in the CPU, a latch signal can be obtained with an irregular delay time without providing a dedicated counter. It is possible to delay the output timing of the chip select signals for the counter 601 and 604 (actually). As a result, it is possible to prevent the occurrence of illegal activities without increasing the calculation processing load.

[Second Embodiment]
In the first embodiment, the counter value is stored in the internal register in the random number generation circuit at the timing when the chip select signal output after the delay process is input. The register may be held, and the counter value held in the internal register may be output at the timing when the chip select signal output after the delay process is input. Details of the random number acquisition process in the slot machine according to the present embodiment will be described below.

1. Random Number Acquisition Processing 1.1 Configuration of Random Number Generation Circuit A detailed configuration of a random number generation circuit for executing the random number acquisition processing according to the present embodiment will be described. FIG. 10 is a diagram showing a circuit configuration of a random number generation circuit according to the present embodiment. Similar to the random number generation circuit 220 according to the first embodiment, the random number generation circuit 1000 includes five counters 601 to 605. Each of the counters 601 to 605 is an 8-bit binary counter, and the counters 601 to 603 are based on a clock signal oscillated from the crystal oscillator 201 and generate a random value for 24 bits (that is, a value in the range of 0 to 16777215). The counters 604 and 605 output 16-bit random values (that is, values in the range of 0 to 65535) based on the clock signal oscillated from the crystal oscillator 211, respectively. The 24-bit random value output by the counters 601 to 603 is used for symbol drawing and mode transition lottery, and the 16-bit random value output by the counters 604 and 605 is used for internal winning lottery. Is done.

  The difference from the random number generation circuit 220 according to the first embodiment is that a crystal oscillator (14.7456 MHz) is newly provided at a port for inputting a latch signal and a clock signal is inputted. As a result, the counter value held (latched) in the internal register is rewritten at the clock cycle of the crystal oscillator (14.7456 MHz) (that is, the latched counter value is rewritten periodically). Therefore, the counter value output to the RAM 205 is determined depending on the input timing of the chip select signal.

  Since the chip select signal from the CPU 200 is output after delay processing is performed, the output timing of the chip select signal does not become a constant cycle even if the start operation unit 135 is turned on at a constant cycle. Same as in the first embodiment (in the first embodiment, the chip select signal output after delay processing is used as a latch signal. In this embodiment, the latched counter value is acquired. Command (output command to RAM 205)).

1.2 Random Number Acquisition Process Flow FIG. 11 shows the flow of random number acquisition processes 1 and 2 in the random number generation circuit in the case of this embodiment. When the random number acquisition process 1 (random number acquisition process for internal lottery for winning combination) shown in FIG. 11A is started, the CPU 200 executes a port input command (input command to each port of the random number generation circuit 1000). . In response to the port input command, a chip select signal for the counter 604 is output from the address decoding circuit 212. The counter 604 outputs the counter value held in the internal register to the RAM 205 (step S1100).

  Next, a chip select signal for the counter 605 is output. The counter 605 outputs the counter value held in the internal register to the RAM 205 (step S1101).

  Similarly, as shown in FIG. 11B, when the random number acquisition process 2 (table lottery and mode transition random number acquisition process) is started and a chip select signal for the counter 601 is output, the counter 601 is internally The counter value held in the register is output to the RAM 205 (step S1110).

  Next, by sequentially outputting chip select signals for the counters 602 and 603, each counter 602 and 603 outputs the value of the internal counter held (latched) in the internal register to the RAM 205 (step S1111, 1112).

1.3 Detailed Description of Counter Next, the counters (601 to 605) used in the random number generation circuit 1000 will be described. FIG. 12 is a diagram for explaining the function of the counter 601 used in the random number generation circuit 1000 (the configuration of the input port and the signal of each port) (the configuration of the counter itself is the random number generation circuit 220 in the first embodiment). This is the same as the counter used in the first embodiment, and the input signal is different from that in the first embodiment.)

  In FIG. 5A, the counter 601 is counted up by the rising signal of the counter clock (CCLK) when the counter clock enable (CCLKEN) becomes “Low”.

  The counter value of the counter 601 is changed every time the rising signal of the register clock (RCLK), that is, the clock signal (14.7456 MHz) from the newly added crystal oscillator is “ON” (FIG. 12B). 1201) and held (latched) in the internal register. When the chip select signal for the counter 601 is turned ON and the enable control (G: gate) is set to “Low” (1202 in FIG. 12B), the counter value held in the internal register is output to the RAM 205. Is done.

  Each counter (601 to 605) increments the counter when the clock signal (CCLKEN) is Low, and stops incrementing when the signal is “High” (1203 in FIG. 12B). However, in the case of the counters 601 and 604, since CCLKEN is at ground, it is always incremented.

  Each counter turns the RCO signal from ON to OFF when 0 → 255 (maximum value). At this time, since the clock signal (CCLKEN) of the counter 602, 603, or 605 (higher counter) becomes Low, the higher counter is incremented. In this way, a 16-bit counter value can be acquired from the counters 604 and 605, and a 24-bit counter value can be acquired from the counters 601 to 603, respectively.

  As is clear from the above description, even when a random number generation circuit having a circuit configuration different from that of the first embodiment is used, the value of the R register in the CPU is changed as in the first embodiment. By using the delay processing, delay can be performed with an irregular delay time without providing a dedicated counter.

[Third Embodiment]
In the first and second embodiments, the delay process is performed based on the value of the R register. However, the delay process method is not limited to this. The random number generation circuit (220, 1000) described above has a feature of holding or acquiring a counter value by a chip select signal from the CPU 200. Since the output timing of the chip select signal output based on the instruction from the CPU 200 can be arbitrarily adjusted by software, the value of the R register is used when the random number generation circuit is used. Needless to say, the random value can be acquired by delaying the output timing of the chip select signal in software.

[Fourth Embodiment]
In the first to third embodiments, the value of the R register in the CPU or the value obtained in software is used for the delay process. However, the present invention is not limited to this, and a dedicated counter (clock signal is used). A count-up means for counting (for example, a clock IC or the like) may be separately provided to perform the delay process. That is, as shown in the first to third embodiments, a value that is counted up regardless of the processing of the gaming table is used instead of a value that is counted up in association with the internal processing of the gaming table. You may do it.

  The counter used at this time may be counted up aperiodically or may be counted up periodically. However, when a counter that is periodically counted up is used, the count cycle needs to be different from the count cycle of the random number generation circuit. If the player has a count cycle different from the count cycle of the random number generator circuit, even if the player operates the start operation unit at regular intervals in synchronization with the count cycle of the random number generator circuit, the delay time will not be constant. As a result, the timing of the hold (or acquisition) command input to the random number generation circuit is not constant.

  In addition, when a counter that is counted up aperiodically is used, the counter may be a counter in which the countup interval for each count is aperiodic, or the countup interval for each count. The counter may be periodic, but the update period (for example, in a counter that counts from 0 to 255, the period from 0 to 255 is counted and the count is started again from 0) may be a non-periodic counter. .

It is a front view showing an appearance of a slot machine according to an embodiment of the present invention. It is a figure which shows the structure of the main control part of a slot machine. It is a flowchart which shows the basic control of the game in the slot machine which concerns on one Embodiment of this invention. It is a figure which shows the internal structure of CPU in the main control part of a slot machine. 14 is a flowchart showing details of delay processing in the slot machine. It is a figure which shows the structure of the random number generation circuit in the slot machine concerning the 1st Embodiment of this invention. It is a flowchart which shows the detail of the random number acquisition process in a slot machine. It is a figure for demonstrating the structure and operation | movement of a counter used for a random number generation circuit. It is a figure which shows the flow of a process from turning ON a start operation unit to turning ON a stop button. It is a figure which shows the structure of the random number generation circuit in the slot machine 100 concerning the 2nd Embodiment of this invention. It is a flowchart which shows the detail of the random number acquisition process in a slot machine. It is a figure for demonstrating the structure and operation | movement of a counter used for a random number generation circuit.

Claims (10)

A game machine that determines the content of the game based on the result of random number lottery,
An output means for outputting a command for acquiring a random value on the basis of a predetermined condition;
Random number generating means for counting a periodically changing clock signal and generating the counted value as a random value based on a command for acquiring the random value from the output means;
Lottery means for obtaining a random value generated by the random number generation means, and performing the random number lottery based on the acquired random number value,
The output means includes
A game machine that outputs a command for acquiring the random value with an irregular delay amount in response to the predetermined condition. A game machine that determines the content of the game based on the result of random number lottery,
An output means for outputting a command for acquiring a random value on the basis of a predetermined condition;
Random number generating means for counting a periodically changing clock signal and generating the counted value as a random value based on a command for acquiring the random value from the output means;
Lottery means for acquiring a random value generated by the random number generator and performing the random number lottery based on the acquired random value;
And at least count-up means for counting up at a period different from that of the clock signal,
The output means includes
A game table characterized by delaying an output timing of a command for obtaining the random number value in accordance with a value counted up by the count-up means. A game machine that determines the content of the game based on the result of random number lottery,
An output means for outputting a random value holding instruction in response to a predetermined condition;
Random number generating means for counting periodically changing clock signals and holding the count value when the holding command is output from the output means as a random value;
Lottery means for acquiring a random number value held in the random number generation means and performing the random number lottery based on the acquired random number value;
And at least count-up means for counting up at a period different from that of the clock signal,
The output means includes
A game machine characterized by delaying the output timing of the holding command in accordance with a value counted up by the count-up means. In the random number generation circuit, the holding command output from the output means is:
The input to a port for inputting a command for holding the count value as a random number value and a port for inputting a command for outputting the held random value. The listed game table. A game machine that determines the content of the game based on the result of random number lottery,
An output means for outputting an acquisition command of a random value, triggered by a predetermined condition;
Random number generating means for counting periodically changing clock signals and periodically holding the counted value as a random value;
When the acquisition command is output from the output unit, the random number value stored in the random number generation unit is acquired, and the lottery unit performs the random number lottery based on the acquired random number value;
And at least count-up means for counting up at a period different from that of the clock signal,
The output means includes
A game machine characterized by delaying the output timing of the acquisition command in accordance with a value counted up by the count-up means. In the random number generation circuit,
A clock signal for a predetermined holding command is input to a port for inputting a command for holding the count value as a random value,
6. The gaming table according to claim 5, wherein an acquisition command output from the output means is input to a port for inputting a command for outputting the held random number value.   7. The game table according to claim 6, wherein a cycle of the predetermined holding command clock signal is shorter than a cycle of the clock signal counted in the random number generation circuit.   The game table according to claim 2, wherein the count-up unit counts up in association with processing in the game table.   9. The gaming table according to claim 8, wherein the value counted up in association with the processing in the gaming table is a value of a refresh register provided in an arithmetic processing unit that executes control processing of the gaming table. .   The gaming table according to claim 1, wherein the predetermined condition is a predetermined operation of a player on the gaming table.

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