JP2005218068A - Semiconductor switching circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor switching circuit, making compatible reducing of the noise and increasing of the switching speed in the switching circuit, which performs on/off control of a field effect output transistor, by applying voltage to the gate of the field effect output transistor via a prebuffer. <P>SOLUTION: The semiconductor switching circuit 1 comprises the prebuffer 6 and a charge extraction circuit 7, and the prebuffer 6 is turned ON. A transistor MN1 for extracting the gate charge of an output transistor MP2 is also provided, and a transistor MN2 for pulling out a second gate charge is provided between the transistor MN1 and the output transistor MP2, in parallel with the transistor MN1 so as to conduct on/off control, based on the voltage of the prebuffer 6 at its input terminal and the gate voltage of the output transistor MP2. When the transistor MN1 is at ON-state and after the change of the gate voltage of the output transistor MP2 has subsided, generated when the gate voltage of the output transistor MP2 exceeds the threshold, the transistor MN2 is turned on, and the gate charge of the output transistor MP2 is extracted by the transistors MN1 and MN2. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a switching circuit that controls on / off of a field effect output transistor by applying a voltage to a gate of the field effect output transistor via a pre-buffer.

  In general, noise generated in the output stage of the switching circuit is mainly caused by a parasitic inductor, and is generated in accordance with the on / off operation of the output transistor. Since the magnitude of this noise is proportional to the current change per time, the noise increases as the on / off switching speed increases. Therefore, if the rise time and fall time of the output transistor are increased, the current change per time can be reduced, so that the noise can be reduced. However, if the rise time and fall time of the output transistor are increased, the full-on time is shortened, so that the switching loss is increased and the efficiency is lowered. For example, conventionally, in order to reduce noise, a configuration in which a resistor is inserted between the gate of a field effect output transistor and a pre-buffer is known, but in this configuration, the switching speed of the field effect output transistor is slow. As a result, the efficiency is lowered.

Conventionally, as a circuit configuration for achieving both noise reduction and high switching speed, a semiconductor integrated circuit receives a single data signal, and has a voltage value equal to or lower than a power supply voltage and having a plurality of timings different from each other. A multi-stage voltage control type pre-driver circuit for generating a pulse, a buffer MOS transistor whose gate electrode is connected to the output of the pre-driver circuit, and one of the other electrodes than the gate of the buffer MOS transistor connected between the power supply voltage A driver circuit having a load means, which first drives the gate of the buffer MOS transistor with a voltage pulse lower than the power supply voltage, suppresses noise, and outputs a higher voltage pulse through the delay circuit after the output voltage changes. The one applied to the gate is known.
JP-A-5-67960

  However, in this conventional circuit, the generation of noise is suppressed by driving the buffer MOS transistor at a low voltage at the start of switching, and the output voltage is lowered by extracting charges from the output terminal, so that noise due to switching at the output terminal is suppressed. Later, a high gate voltage was applied via a delay circuit, so there was a problem that charge removal was slow, it took time until noise was reduced, and it was still insufficient to achieve both noise reduction and high switching speed. . It is an object of the present invention to provide a semiconductor switching circuit that solves such conventional problems.

  In order to achieve this object, a semiconductor switching circuit according to the present invention is a switching circuit that controls on / off of a field effect output transistor by applying a voltage to a gate of the field effect output transistor through a pre-buffer. The gate voltage of the field effect output transistor is fed back, and the output resistance of the prebuffer until the gate voltage change due to the gate-drain capacitance of the field effect output transistor generated when the gate voltage exceeds a threshold value is suppressed. And the output resistance decreases after the change in the gate voltage is suppressed.

  More specifically, when the pre-buffer is turned on, the prebuffer includes a switching element that extracts the gate charge of the field effect output transistor, and the switching element is interposed between the switching element and the gate of the field effect output transistor. In parallel with the device, the switching device is turned on, and the gate voltage of the field effect output transistor caused by the gate voltage of the field effect output transistor exceeding the threshold is suppressed. Later, a second switching element is provided to turn on and extract the gate charge of the field effect output transistor.

  The second switching element may be configured to be on / off controlled based on the voltage at the input terminal of the prebuffer and the gate voltage of the field effect output transistor.

  It is preferable that a plurality of the second switching elements described above are provided in parallel with each other so that the switching element on the field effect output transistor side does not turn on earlier than the switching element on the pre-buffer side. It is preferable that each switching element for extracting the gate charge of the field effect output transistor is constituted by a field effect transistor.

  According to the semiconductor switching circuit of the present invention, the gate charge of the field-effect output transistor is expedited, the time until the noise is reduced is shortened, and it is possible to simultaneously reduce the noise and increase the switching speed. There is an effect. When the on / off control of the second switching element is performed based on the voltage at the input terminal of the pre-buffer and the gate voltage of the field effect output transistor, the power supply voltage, the output voltage, etc. change, and the switching state changes. Even if it changes, the gate voltage of the field-effect output transistor can surely reduce the current change per time near the threshold value.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the invention will be described with reference to the accompanying drawings. First, a first embodiment applied to a DC-DC converter will be described with reference to FIGS. As shown in FIG. 1, which is a block diagram showing the whole, the output terminal of the comparator 1 is connected to one input terminal of each of the NOR circuit 2 and the NAND circuit 3, and the other input terminal of the NOR circuit 2 is connected to an N-channel electric field. It is connected to the gate of an effect output transistor MN3 (hereinafter referred to as output transistor MN3), and the other input terminal of the NAND circuit 3 is connected to the gate of a P-channel field effect output transistor MP2 (hereinafter referred to as output transistor MP2). .

  The output terminal of the NOR circuit 2 is connected to the gate of the output transistor MP2 via three stages of pre-buffers 4, 5, and 6 comprising inverters. As will be described later, the third-stage pre-buffer 6 has a field effect transistor that is a switching element for extracting the gate charge of the output transistor MP2, and in parallel with the pre-buffer 6, as described later, A gate charge extraction circuit 7 including a field effect transistor which is a switching element for extracting the gate charge is provided. The pre-buffer 6 and the gate charge extracting circuit 7 constitute a switching circuit 11.

  On the other hand, the output terminal of the NAND circuit 3 is connected to the gate of the output transistor MN3 through three stages of pre-buffers 12, 13, and 14 formed of inverters. As will be described later, the third-stage prebuffer 14 includes a field effect transistor that is a switching element that extracts the gate charge of the output transistor MN3, and in parallel with the prebuffer 14, There is provided a gate charge extraction circuit 15 including a field effect transistor which is a switching element for extracting the gate charge. The pre-buffer 14 and the gate charge extraction circuit 15 constitute a switching circuit 16.

  Here, details of the switching circuit 11 will be described with reference to FIG. The third-stage pre-buffer 6 is composed of a P-channel field effect transistor MP1 (hereinafter referred to as transistor MP1) and an N-channel field effect transistor MN1 (hereinafter referred to as transistor MN1) connected in parallel, and the gates are connected to each other. Then, the input terminal is connected to the output terminal of the pre-buffer 5, the drains are connected to each other, and the output terminal is connected to the gate of the output transistor MP 2. The source of the transistor MP1 is connected to the power supply, while the source of the transistor MN1 is grounded, and the gate charge of the output transistor MP2 is extracted by turning on the transistor MN1.

  A gate charge extraction circuit 7 provided in parallel with the prebuffer 6 includes a second field effect transistor MN2 (hereinafter referred to as transistor MN2) that extracts the gate charge of the output transistor MP2 when turned on, and the transistor MN2 is connected to the prebuffer. 6 and a drive control circuit that is turned on / off based on the voltage at the input terminal and the gate voltage of the output transistor MP2.

  The gate charge extracting circuit 7 connects the drain of the transistor MN2 between the output terminal of the pre-buffer 6 and the gate of the output transistor MP2, the source of the transistor MN2 is grounded, and the gate thereof has an output terminal of the inverter 8. Is connected. The input terminal of the inverter 8 is connected to the output terminal of the NAND circuit 9, and one input terminal of the NAND circuit 9 is connected to the gate of the output transistor MP2 via the inverter 10, and the other input terminal is connected to the input terminal. The input end of the prebuffer 6 is connected.

  Next, the switching circuit 16 will be described. As shown in FIG. 1, the pre-buffer 14 at the third stage includes a field effect transistor that pulls out the gate charge of the output transistor MN3 by an on operation, as in the above-described prebuffer 6, although not shown. . Similarly to the gate charge extraction circuit 7 described above, the gate charge extraction circuit 15 is a second field effect transistor (not shown) that extracts the gate charge of the output transistor MN3 in parallel with the pre-buffer 14 when turned on. And a drive control circuit for turning on / off the second field effect transistor based on the voltage at the input terminal of the pre-buffer 14 and the gate voltage of the output transistor MN3. As described above, the switching circuit 16 is for extracting the gate charge of the output transistor MN3, and its configuration corresponds to the switching circuit 11 for the output transistor MP2 described above, and thus detailed description thereof is omitted.

  As shown in FIG. 1, either one of the output transistor MP2 and the output transistor MN3 is turned on according to the output of the comparator 1 and outputs it. When the output transistor MP2 is turned on, the output transistor MP2 and the output transistor MN3 are turned on. When MN3 is turned on, the ground voltage is output. The outputs of the output transistors MP2 and MN3 are taken out via the inductor 17. 18 is a load capacity, 19 and 20 are load resistors, 21 is an amplifier, and 22 is a power supply battery.

  Subsequently, the operations of the switching circuits 11 and 16 will be described. Since the operations of the switching circuits 11 and 16 are basically the same, only the operation of the switching circuit 11 will be described. When the output of the comparator 1 changes from “H” to “L”, the output of the NOR circuit 2 becomes “H”, and the output of the prebuffer 5 (the output at point A in FIG. 2) also becomes “H”. Therefore, the transistor MP1 is turned off, the transistor MN1 is turned on, and the gate charge of the output transistor MP2 begins to be extracted by the drive capability of the transistor MN1 (see FIG. 3 (1)). When the gate voltage of the output transistor MP2 exceeds a threshold value, the output transistor MP2 is turned on, the potential on the drain side thereof rises, and the gate voltage also rises due to the gate-drain capacitance (see FIG. 3 (2)). .

  The increased gate voltage begins to drop with a time constant determined by the gate capacitance and the output resistance of the prebuffer 6, and when the threshold voltage of the inverter 10 is reached, the output of the inverter 10 (the output at point B in FIG. 2) becomes “H”. The output of the NAND circuit 9 is “L”, the output of the inverter 8 (the output at point C in FIG. 2) is “H”, and the transistor MN2 is turned on. When both the transistors MN1 and MN2 are turned on, the output resistance of the prebuffer 6 is reduced, and the gate charge of the output transistor MP2 is rapidly extracted. If the transistor MN2 does not exist, the gate charge removal of the output transistor MP2 is delayed as shown by the broken line in FIG.

  As described above, the output transistor MP2 is turned on, the potential on the drain side thereof rises, and noise is generated while the gate voltage rises due to the gate-drain capacitance (see FIG. 3 (2)). Therefore, the gate charge is extracted only by the transistor MN1, and the occurrence of noise is suppressed by reducing the current change per time. After the increase in the gate voltage is stopped, the transistor MN2 is turned on, and the two transistors MN1, The gate charge of the output transistor MP2 is abruptly extracted by MN2, and the switching operation can be speeded up.

  Subsequently, a second embodiment of the present invention will be described with reference to FIG. This embodiment is different from the first embodiment described above only in that a field effect transistor is added as a third switching element for extracting the gate charges of the output transistors MP2 and MN3. About another structure, it attaches to the corresponding component and attaches | subjects the same code | symbol as the above-mentioned 1st Embodiment, The description is abbreviate | omitted. FIG. 4 shows only the output transistor MP2 side, and does not show the output transistor MN3 side.

  The gate charge extraction circuit 27 connects the drain of a field effect transistor MN4 (hereinafter referred to as transistor MN4), which is a third switching element, between the drain of the transistor MN2 and the gate of the output transistor MP2, and the source of the transistor MN4. Is grounded, and the output terminal of the inverter 28 is connected to its gate. The input terminal of the inverter 28 is connected to the output terminal of the NAND circuit 29. One input terminal of the NAND circuit 29 is connected to the gate of the output transistor MP2 through the inverter 30, and the other input terminal is connected to the pre-terminal. The input end of the buffer 6 is connected.

  In this embodiment, the threshold value of the inverter 30 is set to be equal to or lower than the threshold value of the inverter 10 so that the transistor MN4 is not turned on earlier than the transistor MN2. By providing the gate charge extraction circuit 27 including the transistor MN4 as the third switching element, the output resistance of the pre-buffer 6 can be changed in more stages, and the switching operation speed can be further improved.

  The present invention is not limited to the above-described embodiments, and four or more switching elements for extracting the gate charge of the output transistor MP2 may be provided. Needless to say, the present invention can be applied to other than the DC-DC converter.

The block diagram which shows the whole structure of 1st Embodiment. The block diagram which shows the switching circuit which is a principal part. 6 is a timing chart showing a gate charge extraction operation. The block diagram which abbreviate | omits and shows 2nd Embodiment.

Explanation of symbols

MP1 P-channel field-effect transistor MP2 P-channel field-effect output transistor MN1,2,4 N-channel field-effect transistor MN3 N-channel field-effect output transistor 1 Comparator 2 NOR circuit 3,9,29 NAND circuit 4,5 6, 12, 13, 14 Pre-buffer 7, 15, 27 Charge extraction circuit 8, 10, 30 Inverter 11, 16 Switching circuit

Claims (5)

A switching circuit for controlling on / off of the field effect output transistor by applying a voltage to the gate of the field effect output transistor via a prebuffer,
The gate voltage of the field effect output transistor is fed back, and the output resistance of the prebuffer increases until the gate voltage change caused by the gate-drain capacitance of the field effect output transistor generated when the gate voltage exceeds a threshold value is suppressed. The semiconductor switching circuit is configured such that the output resistance decreases after the gate voltage change is suppressed. A switching circuit for controlling on / off of the field effect output transistor by applying a voltage to the gate of the field effect output transistor via a prebuffer,
When the pre-buffer is turned on, the pre-buffer includes a switching element that extracts a gate charge of the field-effect output transistor, and between the switching element and the gate of the field-effect output transistor, in parallel with the switching element, The switching element is in an ON state, and after the gate voltage change due to the gate-drain capacitance of the field effect output transistor generated when the gate voltage of the field effect output transistor exceeds a threshold value, the ON operation is performed. A semiconductor switching circuit, comprising: a second switching element for extracting a gate charge of the field effect output transistor. A switching circuit for controlling on / off of the field effect output transistor by applying a voltage to the gate of the field effect output transistor via a prebuffer,
The prebuffer includes a switching element that extracts the gate charge of the field effect output transistor when turned on, and in parallel with the switching element, a second switching that extracts the gate charge of the field effect output transistor when turned on. An element is provided, and the second switching element is ON / OFF controlled based on the voltage at the input end of the prebuffer and the gate voltage of the field effect output transistor.   3. A plurality of second switching elements are provided in parallel to each other so that switching on the field effect output transistor side does not turn on earlier than switching elements on the pre-buffer side. Item 4. A semiconductor switching circuit according to Item 3. 5. The semiconductor switching circuit according to claim 2, wherein each switching element that draws out a gate charge of the field-effect output transistor is a field-effect transistor.

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