JP2005216941A - Chip-sized semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the dampproofness of a chip-sized semiconductor device, and to prevent the breaking of the semiconductor device. <P>SOLUTION: The chip-sized semiconductor device has a surface protective film 3 coating the top face of the forming section of an element for a semiconductor substrate 1, electrodes 2 exposed from windows bored to the surface protective film 3, and an upper-layer resin 7 coating the top face and functioning as a package. The semiconductor device further has solder bumps 5 and 6 formed on the electrodes 2 and exposed from the upper-layer resin 7 to the outside. In the semiconductor device, a stepped section 1a is formed to the upper section of the periphery of the semiconductor substrate 1, and the stepped section 1a is coated with the upper-layer resin 7. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a chip size semiconductor device that improves moisture resistance and prevents chipping, and a method of manufacturing the same.

  A chip size semiconductor device is formed by forming solder bumps after forming elements such as transistors and resistors on a silicon wafer, forming wiring / electrodes, and forming a surface protective film, and then dividing the chip size with a dicing blade. (For example, refer to Patent Document 1).

  FIG. 14 is a cross-sectional view of a conventional chip size semiconductor device. 101 is a semiconductor (silicon) substrate, 102 is an electrode made of aluminum or the like connected to wiring for electrically connecting elements such as transistors and resistors formed on the semiconductor substrate 1, and 103 is a semiconductor substrate 101. A surface protective film for protecting the upper surface, 104 is a barrier metal made of a refractory metal formed so as to be connected to the electrode 102 facing the window formed in the surface protective film 103, and 105 is formed on the upper surface of the barrier metal 4 The lower layer solder bump 106, an upper layer solder bump 106 protruding from the upper surface of the lower layer solder bump 105, 107 is an upper layer resin that covers the upper surface of the semiconductor substrate 101, and 108 is a lower layer resin that covers the lower surface of the semiconductor substrate 1. The barrier metal 104 serves as a stopper that prevents metal atoms from diffusing between the electrode 2 and the solder bump 105 during heating. Note that the wiring is formed so as to be continuous with the electrode 102, but is omitted in FIG. The upper solder bump 106 is formed by forming the upper layer resin 107 after forming the lower layer solder bump 106 on the barrier metal 104, and then grinding the upper surface to a flat surface to expose the ground top portion of the lower layer solder bump 106. , Formed on the exposed surface.

Conventionally, after a plurality of semiconductor devices having such a structure are formed on a wafer, a dicing tape 109 is pasted on the back surface of the lower layer resin 108 as shown in FIG. The blade 110 is divided into individual chip sizes, and the tester probe 111 is applied to the upper solder bump 106 as shown in FIG. The chip size semiconductor devices were separated and stored in carrier tape.
JP 2003-338515 A

  However, in the chip size semiconductor device in which the silicon wafer is divided by the dicing blade as described above, the cut end face is exposed to the side face as it is, so that the moisture resistance of the end face is deteriorated and a short circuit failure is likely to occur. There is a possibility that chipping is likely to occur at the end face corners, which may cause a problem in reliability.

  An object of the present invention is to provide a chip size semiconductor device in which an important part of a cut end face is protected with a resin so that the above-mentioned problems do not occur, and a manufacturing method thereof.

  According to a first aspect of the present invention, there is provided a chip size semiconductor device comprising: a semiconductor substrate on which an element is formed; a surface protective film covering at least an upper surface of a formation portion of the semiconductor substrate; and a part of the surface protective film. In a chip size semiconductor device having an electrode exposed from an opened window, an insulating layer covering the upper surface and acting as a package, and a bump formed on the electrode and exposed to the outside from the insulating layer, the periphery of the semiconductor substrate A step portion is provided at an upper portion of the portion, and the step portion is covered with the insulating layer.

  According to a second aspect of the present invention, in the chip size semiconductor device according to the first aspect, a side wall of the step portion is formed in a tapered shape.

  According to a third aspect of the present invention, in the chip size semiconductor device according to the first or second aspect, the insulating layer is made of a resin.

  According to a fourth aspect of the present invention, in the chip size semiconductor device according to the first or second aspect, the insulating layer is made of SOG.

  According to a fifth aspect of the present invention, in the chip size semiconductor device according to the first or second aspect, the insulating layer includes a lower insulating layer made of SOG and an upper insulating layer made of a resin formed on the lower insulating layer. It has a two-layer structure with a layer.

  According to a sixth aspect of the present invention, there is provided a chip size semiconductor device manufacturing method comprising: forming an element on a wafer; forming an electrode on the upper surface of the wafer; and forming a surface protective film on the upper surface of the wafer; Forming bumps on the electrodes; forming a wide groove on the wafer along a predetermined dividing line to a depth substantially at the center of the width of the wafer; and the bumps on the surface of the wafer. A step of covering with an insulating layer so as to be exposed to the outside, and a step of cutting the wafer from the insulating layer with a narrow dicing blade so as to pass through substantially the center of the wide groove and separating the wafer into a plurality of chips. It is characterized by comprising.

  According to a seventh aspect of the present invention, in the method for manufacturing a chip size semiconductor device according to the sixth aspect, in the step of forming the wide groove, the wide groove having a rectangular cross section or a wedge shape is formed using a wide dicing blade. It is a process to form.

  A manufacturing method of a chip size semiconductor device according to an eighth aspect of the present invention includes a step of forming an element on a wafer, forming an electrode on the upper surface of the wafer, forming a surface protective film on the upper surface of the wafer, Forming a wide groove to a depth substantially at the center of the width of the wafer by etching along a predetermined dividing line; forming a bump on the electrode of the wafer; and A step of covering with an insulating layer so as to be exposed to the outside, a step of cutting the wafer from the insulating layer with a narrow dicing blade so as to pass through substantially the center of the wide groove, and separating the wafer into a plurality of chips, It is characterized by comprising.

  According to a ninth aspect of the present invention, in the method for manufacturing a chip size semiconductor device according to the eighth aspect, the step of forming the wide groove by the etching includes a wide groove having a rectangular cross section or isotropic etching by anisotropic etching. This is a step of forming a wide groove having a wedge shape in cross section.

  According to a tenth aspect of the present invention, in the method for manufacturing a chip size semiconductor device according to any one of the sixth to ninth aspects, the step of covering with the insulating layer is performed by applying a resin or by spin coating / firing of SOG. It is characterized by carrying out by applying a resin after, or by spin coating and baking of SOG.

  According to the present invention, since the upper periphery of the cut end face when divided into chips is protected by the insulating layer filled in the stepped portion, the moisture resistance of the important part can be improved and the upper corner part can be prevented from being chipped, Furthermore, the adhesion of the insulating layer is improved. In addition, when SOG is used as all or part of the insulating layer, warpage of the semiconductor substrate can be prevented.

  In the present invention, when a semiconductor device formed on a silicon wafer is divided and separated into a plurality of chips, an important part of the cut end surface is protected by an insulating layer (a resin layer functioning as a package). It is intended to improve the moisture resistance of the divided end faces and prevent chipping, and to obtain a highly reliable chip size semiconductor device. This will be described in detail below.

  FIG. 1 is a cross-sectional view of the chip size semiconductor device according to the first embodiment. 1 is a semiconductor (silicon) substrate, 2 is an electrode made of aluminum, polysilicon, etc. connected to wiring for electrically connecting elements such as transistors and resistors formed on the semiconductor substrate 1, and 3 is a semiconductor A surface protective film such as silicon oxide or polyimide for protecting the upper surface of the substrate 1, 4 is a barrier metal made of a refractory metal formed so as to be connected to the electrode 2 facing from a window formed in the surface protective film 3, 5 Is a lower solder bump formed on the upper surface of the barrier metal 4, 6 is an upper solder bump formed on the upper surface of the lower solder bump 5, and 7 is an upper package that covers a part of the upper surface and side surfaces of the semiconductor substrate 1. Upper layer resin (insulating layer) 8 is a lower layer resin (insulating layer) as a lower package covering the lower surface of the semiconductor substrate 1. The barrier metal 4 functions as a stopper that prevents metal atoms from diffusing between the electrode 2 and the solder bump 5 during heating.

  In the chip size semiconductor device according to the first embodiment, a stepped portion 1a is formed in the upper portion around the semiconductor substrate 1, and the upper layer resin 7 is filled and covered to that portion. For this reason, the resin 7 of the stepped portion 1a prevents moisture from entering the interfaces of the semiconductor substrate 1, the surface protective film 3, the wiring, the electrode 2, and the like from the outside, and the moisture resistance is improved. Moreover, since the upper corner portion of the semiconductor substrate 1 is also covered with the resin 7, it is possible to prevent the upper corner portion from being chipped. Furthermore, the adhesion of the upper layer resin 7 is also improved.

  2 is an explanatory view of a manufacturing process for manufacturing the chip size semiconductor device shown in FIG. 1, and FIG. 3 is a specific example of a part of the manufacturing process. First, an element such as a transistor or a resistor is formed on the silicon wafer 1A, wirings and electrodes 2 are formed on the upper surface thereof, the upper surface of the silicon wafer 1A and the upper surface of the wiring are covered with a surface protective film 3, and the surface protective film 3 When the barrier metal 4 is formed on the upper surface of the electrode 2 exposed from the window formed in FIG. 3 and the lower solder bump 5A is formed on the upper surface of the barrier metal 4, the result is as shown in FIG. 3A (step S1).

  Next, a wide dicing blade 11 is cut from a dividing line that is divided into a plurality of chips to a substantially central depth of the width of the silicon wafer 1A. As shown in FIG. Form (step S2).

  Next, when the upper layer resin 7A is applied and formed, the wide groove 12 is filled with the upper layer resin 7A. At this time, the lower layer resin 8A is also applied and formed (step S3). Then, when the upper surfaces of the upper layer resin 7A and the lower layer solder bump 5A are ground so that the ground surface of the lower layer solder bump 5A is the same as the ground surface of the upper layer resin 7A, as shown in FIG. A lower solder bump 5 having a flat upper surface is formed (step S4). Further, when the upper layer solder bump 6 is formed to protrude on the upper surface of the lower layer solder bump 5, it is as shown in FIG. 3D (step S5).

  By passing through the above steps S1 to S5, each chip block that finally functions as a chip size semiconductor device becomes functionally independent from each other. Therefore, a tester probe is applied to each upper solder bump 5. Then, an electrical test is performed, and a mark indicating the model number of each chip size semiconductor device is printed on the back surface of the lower layer resin 8A (step S6).

  Next, after the lower surface of the lower layer resin 8A is attached to the dicing tape 13, a cut is made by the narrow dicing blade 14 from the upper surface of the upper layer resin 7A toward the center of the wide groove 12 to the lower surface of the lower layer resin 8A. When it is cut and separated into a plurality of chips (step S7, FIG. 3 (e)), an independent chip size semiconductor device as shown in FIG. 1 is obtained. This chip size semiconductor device is put in a carrier tape (not shown) and is transported / stored.

  FIG. 4 is a cross-sectional view of the chip size semiconductor device according to the second embodiment. The same code | symbol was attached | subjected to the thing similar to FIG. 1 (Example 1). In the chip size semiconductor device of the second embodiment, an SOG (Spin-on-glass) film 21 mainly composed of silicon dioxide formed by coating and baking is interposed on the lower surface of the upper resin 7. When the upper layer resin 7 is directly filled on the upper surface of the semiconductor substrate 1 or the surface protective film 3, stress is applied to the semiconductor substrate 1 when the resin is cured, but the expansion coefficient of the SOG film 21 is smaller than that of the resin (same as that of the silicon substrate). Therefore, even if it is a thin film, this stress can be relieved, which is effective in improving the yield.

  FIG. 5 is an explanatory view of a manufacturing process for manufacturing the chip size semiconductor device of the embodiment 2 shown in FIG. 4, and FIG. 6 is a specific example of a part of the manufacturing process. First, an element such as a transistor or a resistor is formed on the silicon wafer 1A, wirings and electrodes 2 are formed on the upper surface thereof, and the upper surface of the silicon wafer 1A and the upper surface of the wiring are covered with the surface protection film 3, FIG. (Step S11).

  Next, after covering the entire area except for the dividing line with a mask, the dividing line is anisotropically etched, and as shown in FIG. A rectangular wide groove 22 is formed (step S12).

  Next, when the SOG film 21A is applied to the upper surfaces of the silicon wafer 1A, the surface protective film 3, and the wide groove 22 by a high-speed spin coating method and baked (700 ° C. to 900 ° C.), the result is as shown in FIG. . At this time, the SOG film 21A covers the wide groove 22 including the side wall (step S13).

  Next, a window is formed in the surface protection film 3 and the SOG film 21A on the upper surface of the electrode 2, a barrier metal 4 is formed thereon, and further, a lower layer solder bump 5A is formed on the upper surface of the barrier metal 4, and FIG. (Step S14).

  Next, when the upper layer resin 7A is applied and formed, the wide groove 12 covered with the SOG film 21A is also filled with the upper layer resin 7A. At this time, the lower layer resin 8A is also formed (step S15). Then, when the upper layer resin 7A and the lower layer solder bump 5A are ground so that the ground surface of the lower layer solder bump 5A is the same as the ground surface of the upper layer resin 7A, the upper surface becomes as shown in FIG. 6 (e). A planar lower solder bump 5 is formed (step S16).

  Next, when the upper layer solder bump 6 is formed to protrude on the upper surface of the lower layer solder bump 5, it is as shown in FIG. 7 (f) (step S17).

  By going through the above steps S11 to S17, the blocks finally functioning as the chip size semiconductor device become functionally independent from each other. Therefore, the tester probe is applied to each upper solder bump 5. An electrical test is performed, and a mark indicating the model number of each chip size semiconductor device is printed on the back surface of the lower layer resin 8A (step S18).

  Next, as shown in FIG. 7 (g), the lower surface of the lower layer resin 8A is affixed to the dicing tape 13, and then cut by the narrow dicing blade 14 from the upper surface of the upper layer resin 7A toward the center of the wide groove 12. , Cut to the lower surface of the lower layer resin 8A, and separated into a plurality of chips (step S19), an independent chip size semiconductor device as shown in FIG. 4 is obtained. This chip size semiconductor device is put in a carrier tape (not shown) and is transported / stored.

  As described above, in this manufacturing method, since the wide groove is formed by etching, the wide groove can be formed in a part of the normal wafer process, and the wide groove is formed using a dicing blade. In comparison, the process time can be shortened. Similarly, the SOG film 21A can be formed as a part of a normal wafer process and has the same advantages.

  FIG. 8 is a cross-sectional view of the chip size semiconductor device according to the third embodiment. Components similar to those shown in FIG. 1 (Example 1) are denoted by the same reference numerals. Here, the stepped portion 1a in FIG. 1 is transformed into a tapered stepped portion 1b having a side wall formed in a tapered shape. As shown in FIG. 9, such a tapered step portion 1b can be formed by forming a wide groove 12 'having a wedge-shaped cross section by a wide dicing blade 23 having a tapered portion 23a at the tip. By replacing the step of FIG. 9 with the step of FIG. 3B, the chip size semiconductor device of FIG. 8 can be formed. Such a tapered step portion 1b is effective in preventing the occurrence of chipping at the corner portion because the upper corner of the semiconductor substrate 1 is 90 degrees or more.

  FIG. 10 is a cross-sectional view of the chip size semiconductor device according to the fourth embodiment. Components similar to those shown in FIG. 4 (Example 2) are denoted by the same reference numerals. Here, the stepped portion 1a in FIG. 4 is transformed into a tapered stepped portion 1b having a side wall formed in a tapered shape. As shown in FIG. 11, such a tapered step portion 1 b can be formed as a wide groove 22 ′ having a wedge-shaped cross section by performing isotropic etching when the wide groove is formed by etching. . By replacing the step of FIG. 11 with the step of FIG. 6B, the chip size semiconductor device of FIG. 10 can be manufactured. When such a tapered step portion 1b is formed, the upper angle of the semiconductor substrate 1 becomes 90 degrees or more, which is effective in preventing the occurrence of chipping at the corner portion.

  The first to fourth embodiments described above are not limited, and the formation of the wide grooves 22, 22 ′ and the like by etching is naturally applicable to the manufacture of a chip size semiconductor device that does not use the SOG film 21. Is possible. Further, the upper layer solder bumps 6 are not necessarily required. As shown in FIG. 12, even if the upper layer solder bumps 6 are omitted and the lower layer solder bumps 5 ′ are left exposed in the top planar state, As shown in FIG. 13, the lower layer solder bumps 5 may protrude from the upper layer resin 7. Furthermore, although the lower layer resin 8 was provided in the above Examples 1-4, this is not necessarily required. Furthermore, the barrier metal 4 is for preventing the diffusion of metal atoms between the lower solder bump 5 and the electrode 2 as described above, and is necessarily required depending on the material used for the bump material and the electrode material. It is not a thing. Furthermore, in the second embodiment, the SOG film 21 is used as a thin film, but the upper resin 7 of the first embodiment can be replaced with the SOG film 21 in its entirety.

1 is a cross-sectional view of a chip size semiconductor device of Example 1. FIG. 3 is a flowchart of a manufacturing method of the chip size semiconductor device according to the first embodiment. FIG. 6 is an explanatory diagram of a specific example of part of the manufacturing process of the chip-size semiconductor device according to the first embodiment. 6 is a cross-sectional view of a chip size semiconductor device of Example 2. FIG. 6 is a flowchart of a manufacturing method of a chip size semiconductor device of Example 2. FIG. 10 is an explanatory diagram of a specific example of part of the manufacturing process of the chip-size semiconductor device according to the second embodiment. FIG. 10 is an explanatory diagram of a specific example of part of the manufacturing process of the chip-size semiconductor device according to the second embodiment. 6 is a cross-sectional view of a chip size semiconductor device of Example 3. FIG. FIG. 10 is an explanatory diagram of a specific example of part of the manufacturing process of the chip-size semiconductor device according to the third embodiment. 6 is a cross-sectional view of a chip size semiconductor device of Example 4. FIG. FIG. 10 is an explanatory diagram of a specific example of part of the manufacturing process of the chip-size semiconductor device according to the fourth embodiment. 10 is a cross-sectional view of a chip size semiconductor device of one example of Example 5. FIG. FIG. 10 is a cross-sectional view of another example chip size semiconductor device of Example 5. It is sectional drawing of the conventional chip size semiconductor device. It is explanatory drawing of the one part specific example of the manufacturing process of the conventional chip size semiconductor device. It is explanatory drawing of the electrical test of the conventional chip size semiconductor device.

Claims (10)

A semiconductor substrate on which an element is formed, a surface protective film covering at least the upper surface of the element formation portion of the semiconductor substrate, an electrode exposed from a part of the window opened in the surface protective film, and an upper surface In a chip size semiconductor device having an insulating layer serving as a package, and a bump formed on the electrode and exposed to the outside from the insulating layer,
A chip size semiconductor device, wherein a step portion is provided at an upper portion of a peripheral portion of the semiconductor substrate, and the step portion is covered with the insulating layer. The chip size semiconductor device according to claim 1,
A chip-size semiconductor device, wherein the stepped portion has a side wall formed in a tapered shape. The chip size semiconductor device according to claim 1 or 2,
The chip size semiconductor device, wherein the insulating layer is made of a resin. The chip size semiconductor device according to claim 1 or 2,
The chip size semiconductor device, wherein the insulating layer is made of SOG. The chip size semiconductor device according to claim 1 or 2,
2. The chip size semiconductor device according to claim 1, wherein the insulating layer has a two-layer structure of a lower insulating layer made of SOG and an upper insulating layer made of a resin formed on the lower insulating layer. Forming an element on the wafer, forming an electrode on the upper surface of the wafer, and forming a surface protective film on the upper surface of the wafer;
Forming bumps on the electrodes of the wafer;
Forming a wide groove on the wafer along a predetermined dividing line to a depth substantially at the center of the width of the wafer;
Coating the surface of the wafer with an insulating layer so that the bumps are exposed to the outside;
Cutting the wafer from the insulating layer with a narrow dicing blade so as to pass through substantially the center of the wide groove and separating it into a plurality of chips;
A method for manufacturing a chip-sized semiconductor device, comprising: In the manufacturing method of the chip size semiconductor device according to claim 6,
The method of manufacturing a chip size semiconductor device, wherein the step of forming the wide groove is a step of forming a wide groove having a rectangular cross section or a wedge shape using a wide dicing blade. Forming an element on the wafer, forming an electrode on the upper surface of the wafer, and forming a surface protective film on the upper surface of the wafer;
Forming a wide groove on the wafer by etching along a predetermined dividing line to a depth substantially at the center of the width of the wafer;
Forming bumps on the electrodes of the wafer;
Coating the wafer surface with an insulating layer so that the bumps are exposed to the outside;
Cutting the wafer from the insulating layer with a narrow dicing blade so as to pass through substantially the center of the wide groove and separating it into a plurality of chips;
A method for manufacturing a chip-sized semiconductor device, comprising: In the manufacturing method of the chip size semiconductor device according to claim 8,
The step of forming the wide groove by the etching is a step of forming a wide groove having a rectangular cross section by anisotropic etching or a wide groove having a wedge shape by isotropic etching. Production method. In the manufacturing method of the chip size semiconductor device according to any one of claims 6 to 9,
The step of coating with the insulating layer is carried out by applying a resin, or by applying a resin after spin coating / firing of SOG, or by spin coating / firing of SOG. Method.

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