JP2005216194A - Power supply - Google Patents

Abstract

A power supply apparatus capable of reliably starting up a power supply output voltage even when the power supply input voltage or the power supply output voltage drops for a moment, and accurately restoring the power supply output voltage when the output ground fault is released. I will provide a.
A second output voltage detection circuit (39) stops an operation of an error amplifying unit (37) when a voltage at a voltage output terminal (D1) to be detected becomes equal to or lower than a second output voltage, thereby causing an overcurrent during a ground fault. The first output voltage detection circuit 38 turns on the NPN transistor 20 when the voltage at the voltage output terminal D1, which is the detection voltage, becomes equal to or lower than the first output voltage, thereby outputting the voltage at the voltage output terminal D1. Raise the voltage.
[Selection] Figure 1

Description

  The present invention relates to a power supply apparatus having a function of stopping a power supply operation when the output voltage becomes a predetermined voltage or less due to, for example, a ground fault of a power supply output terminal.

  As a conventional power supply device, the secondary output terminal is detected except for a certain period set by the charge time to the capacity when the voltage of the secondary output terminal is detected and the power supply to the primary input terminal rises. When the voltage of the power supply becomes lower than a predetermined voltage, the operation of the power supply device is stopped.

A “stabilized power supply circuit” will be described below with reference to the drawings as a conventional power supply device as described above (see, for example, Patent Document 1).
FIG. 3 is a circuit block diagram showing a configuration of a conventional power supply apparatus. In FIG. 3, 71 is an initial reset circuit, 72 is a short circuit detection circuit, 73 is a flip-flop circuit, 74 is an error amplifier, 75 to 80 are current sources, 81 is a constant voltage circuit, 82 and 83 are capacitors, 84 to 91 is a resistor, 92 to 100 are NPN transistors, 101, 102 and 103 are PNP transistors, 104 is a power PNP transistor, 105 and 106 are diodes, VIN is a power supply input voltage applied to the primary side input terminal, and VO is 2 The power supply output voltages A, B, and C output to the secondary output terminal are terminals.

First, the case where the power supply input voltage VIN rises sharply first will be described.
When the power supply input voltage VIN is applied to the primary side input terminal, immediately after that, the voltage VB of the terminal B becomes as shown in Equation (5), where the resistance values of the resistors 85 and 86 are R85 and R86, respectively.

VB = VIN × R86 / (R85 + R86) --- (5)

The voltage at the terminal A is 0V, the current value of the current source 76 is I76, the capacitance value of the capacitor 82 is C82, the voltages at the terminals A and B are the same, and the NPN transistor 94 is turned off from the on state. Time ta until switching to the state is as shown in Equation (6).

ta = C82 × VB / I76 (6)

That is, since the NPN transistor 94 is in the on state and the terminal C is in the L state until the time ta elapses after the power supply input voltage VIN is applied to the primary side input terminal, the NPN transistor 100 is in the forced off state. Regardless of the signal from the flip-flop circuit 73 that operates in response to the signal from the short-circuit detection circuit 72, the power supply device tries to generate VO as a set value at the secondary output terminal while the NPN transistor 100 is off. Operate.

  On the other hand, after the time ta has elapsed since the power supply input voltage VIN was applied to the primary side input terminal, the NPN transistor 94 is off and the secondary side output terminal is not grounded. 103 is turned off, and the NPN transistor 97 is also turned off. When the VO rises, the NPN transistor 94 is switched from on to off after the NPN transistor 97 is switched from on to off (initial reset circuit). By setting R85, R86, I76, C82, etc., the state of the flip-flop 73 is the state when the initial reset circuit 71 is operating, that is, NPN. The transistor 100 can be kept off.

For this reason, when the output voltage of the constant voltage circuit 81 is V81, and the resistance values of the resistors 88 and 89 are R88 and R89, the power supply output voltage VO generated at the secondary output terminal is the voltage of Expression (7).

VO = V81 × (R88 + R89) / R89 (7)

Next, when the secondary output terminal changes from the state of Expression (7) to the ground fault state, a current flows from the base of the PNP transistor 103 to the resistor 88 and the resistor 89 via the diode 105, the PNP transistor 103 is turned on, Since the NPN transistor 97 is also turned on and the collector voltage of the NPN transistor 97 is in the L state, the base voltage of the NPN transistor 100 is in the H state and the NPN transistor 100 is turned on.

  Therefore, since the base voltages of the NPN transistors 95 and 96 are in the L state, no current flows through the base of the power PNP transistor 104, and the power PNP transistor 104 is turned off.

  As described above, even if the secondary output terminal is grounded, the power PNP transistor 104 is turned off, so that no overcurrent flows through the power PNP transistor 104 and heat generation due to the overcurrent is prevented.

Next, a case where the power supply input voltage VIN rises gently will be described.
When the power supply input voltage VIN rises gently, the voltage at the terminal A is always higher than the terminal B. In such a case, the NPN transistor 94 is always in the OFF state, and the base voltage of the NPN transistor 100 is changed from the initial reset circuit 71 to the L state. As a matter of fact, the flip-flop circuit 73 cannot be reset.

However, by providing a capacitor 83 and a resistor 91 for initial setting of the flip-flop circuit 73 when the power supply input voltage VIN is applied, the voltage between the terminals of the capacitor 83 is in the L state immediately after the VIN is applied due to the time constant by them. Therefore, since it takes time to increase the voltage to turn on the NPN transistor 98, the NPN transistor 98 is turned off, the NPN transistor 99 is turned on, the base voltage of the NPN transistor 100 is in the L state, and the rise of the power supply output voltage VO Is possible.
Japanese Patent No. 3284147 (Japanese Patent Laid-Open No. 7-104871)

  However, in the conventional power supply device as described above, the rise of the power supply output voltage VO is delayed by a load or a smoothing capacitor connected to the secondary output terminal, so that the PNP transistor 103 and the NPN transistor 97 are turned off from on. Is switched later than the NPN transistor 94 is switched from on to off, and the capacitor 83 is charged from the current source 80 via the resistor 91 and the NPN transistor 98 is turned on, and then the NPN transistor 97 is turned on. Switch from OFF to OFF, the NPN transistor 99 is turned OFF, the NPN transistor 98 is turned ON, and the NPN transistor 100 is turned ON when the base voltage is H. Therefore, even if the power supply input voltage VIN is applied, the power supply output voltage VO There was a problem that did not stand up.

  Also, if the power supply input voltage VIN drops momentarily due to turning on / off of the power supply of the primary side input terminal (input chattering) or momentary stop of the power supply, etc., the power supply output voltage VO also drops momentarily. Since A holds the voltage by the capacitor 82, the NPN transistor 94 is kept off, and a signal for resetting the flip-flop circuit 73 is not sent, and the PNP transistor 103, the NPN transistor are caused by an instantaneous drop in the power supply output voltage VO. When 97 is turned on and the voltage of the capacitor 83 reaches a voltage for turning on the NPN transistor 98, the base voltage of the NPN transistor 100 is in the H state, the NPN transistor 100 is kept in the on state, and VO remains even when VIN is restored. There is also a problem that it is prone to malfunction such as not returning. .

  Further, once the ground fault protection is activated while the NPN transistor 100 is turned on by the flip-flop circuit 73, even if the ground fault state of the secondary output terminal is subsequently released, the voltage of the power supply output voltage VO is There was also a problem that the circuit operation did not return without increasing.

  The present invention solves the above-described conventional problems. The power supply output voltage can be accurately raised regardless of the rise time of the power supply input voltage or the rise time of the power supply output voltage, and the power supply can be turned on. -When the power supply output voltage drops momentarily due to off (input chattering) or momentary stop of the power supply, etc., the output voltage can be accurately restored without malfunction, etc. In the event of a ground fault at the output end, the ground fault protection function prevents overcurrent from flowing and prevents overheating, and when the ground fault condition is released, the power supply output voltage is accurately restored. Provided is a power supply capable of

  In order to solve the above problem, a power supply device according to claim 1 of the present invention is connected between a voltage input terminal and a voltage output terminal, and outputs to a load circuit connected to the voltage output terminal. A power supply device comprising: a transistor for controlling a voltage; and an error amplifying unit for performing error comparison between the output voltage and a predetermined reference voltage to control a control terminal of the transistor, wherein the voltage at the voltage output terminal is A first output voltage detection circuit that switches an output logic state when detecting that the voltage is equal to or lower than a first output voltage and changes a current drawn from the control terminal of the transistor to a predetermined value or less; and a voltage at the voltage output terminal Is detected to be lower than the second output voltage, which is smaller than the first output voltage, the output logic state is switched to stop the control of the transistor by the error amplifying unit. Further and a second output voltage detection circuit.

  According to a second aspect of the present invention, in addition to the configuration of the first aspect, the power supply apparatus detects a voltage at the voltage output terminal, and the voltage is larger than the second output voltage. And a third output voltage detection circuit that switches the output logic state when detecting that the output voltage is 3 or less, and switches the operation state of the load circuit to reduce the current consumption in the load circuit. .

  Moreover, the power supply device according to claim 3 of the present invention is the power supply device according to claim 1 or claim 2, wherein the power supply device is primary according to a voltage relationship between the voltage input terminal and the voltage output terminal. A means for stopping the operation of pulling a predetermined current or less from the control terminal of the transistor by the first output voltage detection circuit and secondarily stopping the control of the transistor by the error amplifying unit; It is characterized by that.

  A power supply device according to claim 4 of the present invention is the power supply device according to claim 1, claim 2, or claim 3, wherein the first output voltage detection circuit has the voltage output terminal connected to the power supply device. A switch element that switches the output logic state when the voltage is equal to or lower than the first output voltage is provided between a resistor connected to the control terminal of the transistor and the ground, and the voltage output terminal is equal to or lower than the first output voltage. When detecting this, the output logic state is switched by the switch element, and a current equal to or less than a predetermined value is drawn from the control terminal of the transistor through a current path formed by the resistor and the switch element. To do.

  As described above, when the voltage output terminal is equal to or lower than the second output voltage that is the detection voltage in the second output voltage detection circuit, the error amplifying unit is stopped to prevent overcurrent due to the output voltage at the time of the ground fault. When the voltage output terminal is equal to or lower than the first output voltage that is the detection voltage in the first output voltage detection circuit, the voltage output from the voltage output terminal can be activated by turning on the switch element.

  As described above, according to the present invention, when the voltage output terminal is equal to or lower than the second output voltage that is the detection voltage in the second output voltage detection circuit, the output voltage at the time of the ground fault is stopped by stopping the error amplifying unit. The voltage output from the voltage output terminal is activated by turning on the switch element when the voltage output terminal is equal to or lower than the first output voltage that is the detection voltage in the first output voltage detection circuit. can do.

  Therefore, even if the output voltage rise time becomes slow or fast due to the influence of a heavy load or a smoothing capacitor connected to the output terminal, the output voltage is output regardless of the rise time of the input voltage or the rise time of the output voltage. The voltage can be raised accurately.

  In addition, even when the output voltage drops momentarily due to a momentary drop in the input voltage due to power supply on / off to the input terminal, input chattering to the input terminal, instantaneous power supply to the input terminal, etc. Can be accurately restored without malfunction.

  In addition, the ground fault protection function prevents overcurrent from flowing even when a ground fault occurs at the output end, and can prevent overheating, and when the ground fault condition is canceled, the output voltage is accurately restored. be able to.

Hereinafter, a power supply device according to an embodiment of the present invention will be specifically described with reference to the drawings.
FIG. 1 is a circuit block diagram showing the configuration of the power supply device according to the present embodiment. Here, a case will be described in which a power PNP transistor 2 is used as a control element in a series control type power supply device that stabilizes an output voltage by connecting a control element and a load circuit in series.

  In FIG. 1, reference numeral 1 denotes a power supply as a power supply voltage supply source, 2 denotes a power PNP transistor as a control element, 3 denotes a smoothing capacitor for smoothing the voltage waveform of the voltage output terminal D1, 4 to 15, 27 and 50 denote resistors, 16 , 17 are capacitors, 18 to 23 are NPN transistors, 24, 25 and 26 are reference voltage sources, 28, 29 and 30 are current sources, 31 are amplifiers, 32, 33 and 34 are comparators, and 35 is a voltage output terminal D1. , A load circuit connected to, 36 is a third output voltage detection circuit for detecting that the voltage output terminal D1 has become the third output voltage, and 37 is an error amplifier for comparing the error between the power supply output voltage and the reference voltage , 38 is a first output voltage detection circuit for detecting that the voltage output terminal D1 has become the first output voltage, and 39 is a second output for detecting that the voltage output terminal D1 has become the second output voltage. Output power Detection circuit, 40 is a input-output potential difference detection circuit for detecting a potential difference between the voltage input terminal D2 and the voltage output terminal D1, a code indicating the respectively 41-49 nodes.

  The load circuit 35 and the power PNP transistor 2 are connected in series with the power source 1, and the amplifier 31 constituting the error amplifying unit 37 receives the power source output voltage VO output to the voltage output terminal D 1 through the resistors 4 and 5. An error is compared between the voltage divided by the resistance in the series circuit and the voltage of the reference voltage source 24, and an error output signal corresponding to the error voltage is output. The error output signal is further amplified by NPN transistors 18 and 19 to drive the base which is the control terminal of the power PNP transistor 2. These elements constitute a negative feedback loop, and are controlled so that the error voltage becomes zero, and a stable DC voltage is output from the voltage output terminal D1. As a result, the operation of stabilizing the output voltage, which is the basic operation of the DC voltage power supply device in a steady state, is performed. The circuit operation when the power is turned on, which is a problem of the present invention, will be described below.

  FIG. 2 is a diagram for explaining the circuit operation of the power supply device according to the present embodiment, and shows voltage waveforms at the nodes 41 and 42 when the power is turned on. In FIG. 2, a period 51 is a period during which the NPN transistor 20 is turned on and the node 48 is about 0.2 V, a period 52 is a period during which the NPN transistor 21 is turned off and the base of the power PNP transistor 2 can be driven by the error amplifier 37. 53 is a period during which the current consumption of the load circuit 35 is reduced by the third output voltage detection circuit 36, V1 is the voltage at the node 42 when the output of the comparator 32 is switched, and V2 is the output of the comparator 33. The voltage of the node 42 at the time, V3 is the voltage of the node 42 when the node 49 switches. Here, V1, V2, and V3 are set to have a magnitude relationship represented by V1> V3> V2, respectively.

First, the rise of the node 42 when a voltage is applied to the node 41 by the power supply 1 will be described with reference to FIG.
When a voltage is applied to the node 41, the initial value of the node 42 is 0V. However, when the node 42 is equal to or lower than V2, the node 45 which is the output of the comparator 32 is H, the NPN transistor 20 is turned on, and the node 48 is about 0. When the voltage of the node 41 is V41, the voltage between the emitter and base of the power PNP transistor 2 is VBE2, and the resistance value of the resistor 15 is R15, the base current IB2 of the power PNP transistor 2 is as shown in Equation (1). Become.

IB2 = (V41−VBE2−0.2V) / R15 −−− (1)

When the node 42 is equal to or lower than V2, the node 47 is H, the NPN transistor 21 is turned on, and the node 46 is set to L. Therefore, the error amplifying unit 37 does not drive the base current of the power PNP transistor 2, and The current consumption of the load circuit 35 is reduced by the third output voltage detection circuit 36.

From the above, when the node 42 is equal to or lower than V2, the voltage of the node 42 increases due to the base current of the power PNP transistor 2 shown in Expression (1). Assuming that hfe of the power PNP transistor 2 is hfe2, the current consumption when the node 42 is V3 or less and the current consumption of the load circuit 35 is reduced is I35, in order for the node 42 to rise, the formula (2) must be satisfied. is there.

I35 <hfe2 × IB2 --- (2)

However, if the value of IB2 is set too large as will be described later, the current flowing through the power PNP transistor 2 at the time of the ground fault is increased by the node 42 and generates heat, so that an optimal value within the range satisfying the expression (2) is satisfied. Must be set to

  The reason why the current consumption of the load circuit 35 is reduced when the node 42 is less than V3, which is larger than V2, is to make I35 in the equation (2) as small as possible and to make the set value of IB2 as small as possible. It is. As a specification, it is assumed that when the node 42 is equal to or lower than V3, the load circuit 35 is set in a standby state or stopped in operation by the node 49 from the third output voltage detection circuit 36. Even if the current consumption of the load circuit 35 is not reduced at V3 or less, the third output voltage detection circuit is satisfied if the relationship of the expression (2) and the standard for the heat generation (overcurrent) at the time of the ground fault of the node 42 can be satisfied. The current consumption in the load circuit 35 by 36 may not be reduced.

  When the voltage of the node 42 becomes V2 or higher, the node 47, which is the output of the comparator 33, switches to L, the NPN transistor 21 is turned off, the error amplifying unit 37 operates, and the base current driving capability of the power PNP transistor 2 is increased. Since it increases, the rising speed of the node 42 increases.

  When the node 42 becomes V3, the current consumption of the load circuit 35 is switched from the reduced mode to the normal mode. At this time, since the error amplifying unit 37 is operating, even if the current consumption in the load circuit 35 increases, the rise of the node 42 is slightly delayed and no problem occurs. In FIG. 2, V3 is set between V1 and V2, but there is no particular problem as long as it is V2 or more. Further, when the node 42 becomes V1, the node 45 which is the output of the comparator 32 becomes L and the NPN transistor 20 is turned off. At this time, since the error amplifying unit 37 is in the operating state, There will be no hindrance.

  As described above, when a voltage is applied to the node 41 from the power supply voltage supply source, the node 42 rises. In FIG. 2, the reason for overlapping the period 51 and the period 52 is that the voltage of the node 42 is changed when the period is switched. This is to prevent the rise from stopping (locking) in the middle. If there is a period that does not belong to both the period 51 and the period 52, there is a period in which the base current of the power PNP transistor 2 is not driven. The node 42 stops at a voltage in the middle, and the capacitor 16 for taking a phase margin is provided in the error amplifying unit 37 even in the case where the switching of the period 51 and the period 52 is performed simultaneously. 17 and so on, the NPN transistor 20 is switched from on to off, and at the same time, the error amplifying unit 37 determines whether the base of the power PNP transistor There is no fast response capability to draw current, the node 42 is slightly lowered, the error amplifying unit 37 is stopped again, and the NPN transistor 20 is turned on again. The above operation is repeated in the vicinity of switching between the period 51 and the period 52. Thus, the node 42 cannot rise to the original value.

  In the period 51, the current flowing from the base of the power PNP transistor 2 through the resistor 15 to the NPN transistor 20 is set as shown in the expression (1) in the configuration of FIG. This is also the case where the constant current is drawn from the collector of the NPN transistor 20 and there is a merit that the influence of the voltage of the node 41 can be reduced. However, when the current value is determined by the resistor 15, as shown in FIG. It can be configured relatively easily.

Next, the operation when the node 42 is grounded in a state where a predetermined voltage is generated at the node 42 by applying a voltage to the node 41 with the power source 1 will be described.
When the node 42 is equal to or lower than V2 in FIG. 2, that is, when the resistance values of the resistors 9 and 10 are R9 and R10, the voltage of the reference voltage source 26 is V26, and the node 42 is in the state of Expression (3),

V42 <V26 × (R9 + R10) / R10 −−− (3)

The node 46 is set to L by the second output voltage detection circuit 39 and the error amplifying unit 37 is stopped. At this time, since the NPN transistor 20 in the first output voltage detection circuit 38 is on, the power PNP transistor 2 The base current is expressed by the above-described formula (1). In addition, the collector current IC2 of the power PNP transistor 2 at this time is expressed by Expression (4), where hfe of the power PNP transistor 2 is hfe2.

IC2 = hfe2 × IB2 (4)

For this reason, the collector current of the power PNP transistor 2 when the node 42 is grounded can be reduced as the resistance value of the resistor 15 is increased. However, as described above, in order to reliably start the node 42 in a normal state that is not grounded, the power PNP transistor 2 can be supplied with the current consumption in the load circuit 35. The base current needs to be set by the resistor 15.

Next, the case where the ground fault state is canceled due to some factor from the state where the node 42 is grounded as described above (the state where the ground fault protection is activated) will be described.
When the ground fault is released from the state in which the node 42 is grounded, the current IC2 shown in the equation (4) flows through the load circuit 35 and the smoothing capacitor 3, so that the voltage at the node 42 increases and the ground fault is reduced. The node 42 after being released becomes the same as the rising waveform of the node 42 when a voltage is applied to the node 41 shown in FIG. 2 described first, and the node 42 can return to the original set voltage. .

  As described above, the rise of the node 42 when the voltage is first applied to the node 41, the operation when the node 42 is grounded second, the node when the ground fault of the node 42 is released third In the normal state in which the node 42 is not in the ground fault state, the rise of the voltage of the node 41 may be late or early, and the smoothing capacitor 3 and the load circuit 35 Even if the rise of the node 42 is late or early due to the influence, or even if the node 42 falls momentarily due to the instantaneous stop or chattering of the node 41, the voltage of the node 42 may be in the period 51 of FIG. For example, if the current of the formula (1) is subtracted from the base of the power PNP transistor 2 and the voltage of the node 42 is in the period 52 of FIG. By pulling the node 42 can rise always to the original settings.

The purpose and operation of the input / output potential difference detection circuit 40 are as follows.
If there is no inter-input / output potential difference detection circuit 40, for example, when the operation specification is such that the load circuit 35 is operated by applying a voltage to the node 41 when the AC adapter is used, and the node 42 when the battery is used, to the node 41 If the voltage drop of the node 41 is slow after switching from the application of the AC adapter voltage to the node 42, the node 41 will be momentarily caused by some factor when the battery voltage is applied to the node 42. When a voltage is applied, a current flows from the node 42 to the collector of the power PNP transistor 2, and a reverse flow occurs in the power PNP transistor 2 such that a current flows from the emitter of the power PNP transistor 2. In this case, the battery voltage is applied to the node 42 to operate the load circuit 35. However, current is supplied to the circuit connected to the node 41, and wasteful current is consumed. Will shorten the lifespan.

  However, by providing the inter-input / output potential difference detection circuit 40 and setting the inter-input / output potential difference detection circuit 40 so that the NPN transistors 22 and 23 are turned on when the voltage at the node 42 becomes larger than the voltage at the node 41, error amplification is performed. Since the unit 37 is stopped and the NPN transistor 20 of the first output voltage detection circuit 38 is also turned off, no current is drawn from the base of the power PNP transistor 2 and no current flows through the power PNP transistor 2.

  In the power supply device of the present invention, the power supply output voltage rises reliably and the output terminal is grounded regardless of the rising speed of the power supply input voltage or power supply output voltage, or even if the input voltage or output voltage drops momentarily. The power supply output voltage can be accurately restored even when released from the fault state, and can be applied to a protection technique at the time of a ground fault of the output terminal in the power supply device.

The circuit block diagram which shows the structure of the power supply device of embodiment of this invention Voltage rising waveform diagram of node 42 when voltage is applied to node 41 in the power supply device of the embodiment Circuit block diagram showing the configuration of a conventional power supply device

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Power supply 2 Power PNP transistor 3 Smoothing capacitor 4-15, 27, 50 Resistance 16, 17 Capacitor 18-23 NPN transistor 24-26 Reference voltage source 28-30 Current source 31 Amplifier 32-34 Comparator 35 Load circuit 36 3rd Output voltage detection circuit 37 error amplifier 38 first output voltage detection circuit 39 second output voltage detection circuit 40 input-output potential difference detection circuit 41 to 49 node 51 NPN transistor 20 is turned on and node 48 is about 0.2V Period 52 period during which the NPN transistor 21 is turned off and the power PNP transistor 2 can be driven by the error amplifier 37 53 period during which the current consumption of the load circuit 35 is reduced by the third output voltage detection circuit 36 D1 voltage output terminal D2 voltage Input terminal V1 No when the output of comparator 32 switches 42 voltage V2 voltage of node 42 when output of comparator 33 switches V3 voltage of node 42 when node 49 switches 71 initial reset circuit 72 short circuit detection circuit 73 flip-flop circuit 74 error amplifier 75-80 Current source 81 Constant voltage circuit 82, 83 Capacitor 84-91 Resistance 92-100 NPN transistor 101-103 PNP transistor 104 Power PNP transistor 105, 106 Diode VIN Voltage applied to primary side input terminal VO Secondary side output terminal Output voltage A, B, C signal

Claims (4)

  A transistor connected between the voltage input terminal and the voltage output terminal for controlling the output voltage output to the load circuit connected to the voltage output terminal and an error comparison between the output voltage and a predetermined reference voltage are performed. A power supply device including an error amplifying unit for controlling a control terminal of the transistor, wherein when detecting that the voltage of the voltage output terminal is equal to or lower than a first output voltage, an output logic state is switched, and the transistor A first output voltage detection circuit for changing a current drawn from the control terminal to a predetermined value or less, and a voltage at the voltage output terminal being less than or equal to the second output voltage smaller than the first output voltage. And a second output voltage detection circuit that switches an output logic state and stops the control of the transistor by the error amplifying unit when detected.   When the voltage at the voltage output terminal is detected, and when it is detected that the voltage is equal to or lower than the third output voltage that is greater than the second output voltage, the output logic state is switched, and the current consumption in the load circuit is reduced. The power supply apparatus according to claim 1, further comprising a third output voltage detection circuit that switches the operation state of the load circuit to be reduced.   According to the voltage relationship between the voltage input terminal and the voltage output terminal, the operation of pulling a predetermined current or less from the control terminal of the transistor by the first output voltage detection circuit is temporarily stopped, and secondarily The power supply device according to claim 1, further comprising means for stopping control of the transistor by the error amplifying unit.   The first output voltage detection circuit includes a switch element that switches the output logic state between the resistor connected to the control terminal of the transistor and the ground when the voltage output terminal becomes equal to or lower than the first output voltage. When it is detected that the voltage output terminal is equal to or lower than the first output voltage, the output logic state is switched by the switch element, and the transistor is controlled through a current path formed by the resistor and the switch element. 4. The power supply device according to claim 1, wherein the power supply device is configured to draw a predetermined current or less from a terminal.

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