JP2005209058A - Control method for read/write of flash memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a control method for read/write of a flash memory which is efficiently controlled, has reduced a size of a control chip, and writes fast. <P>SOLUTION: In the control method of read/write of a flash memory 10, a plurality of flash memory blocks are set in one area and, on the basis of a relationship between the area and a logical address 18 corresponding at the time of system operation, an address mapping table (14) in a FAT and a first area and a high-speed access address mapping table corresponding to a partial block in a second area are created. When the logical address retrieved from a host terminal is transmitted to the flash memory, a physical address is detected directly from the table if the logical address exists in the FAT area of the memory; if otherwise, the location is calculated. Then, if the logical address exists within the first area, the physical address is retrieved from the address mapping table; otherwise, high-speed address/address mapping table is retrieved. When the logical address does not exist, other high-speed access/address mapping table is created, it is decided whether or not an area address mapping table in still another area is created, and retrieval is performed until the physical address corresponding to the logical address is detected. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a flash memory read / write control method, and more particularly to a flash memory read / write control method that controls the flash memory read / write method to increase the read / write speed.

  In the memory operation principle, when the controller uses the memory as a data storage area, the calculation result and its data are stored in the area, and when the program accesses, the area is accessed. When data is written and stored, the controller determines an address necessary for data storage and transmits the address to the memory via the bus. Therefore, the controller can transmit the corresponding data to the correct address. Further, when reading data, the address is accessed by a command transmitted from the controller, the data is taken out, and after the memory has reacted, the data is transmitted until the controller surely receives the data. The time taken for this procedure is the memory read time.

  The flash memory forms a block with a plurality of bits, and is provided for writing and reading data in units of this. Each block provided for data storage has a physical address representative of the order of the internal space of the flash memory, and at the same time, each block records a logical address displayed by the operation system of the host terminal, and Each physical address has a corresponding logical address.

  However, as disclosed in FIG. 1, in the flash memory mechanism, the physical address and logical address required for the host terminal to access data have a non-linear correspondence as disclosed in FIG. Thus, the position of the logical address cannot be known directly from the physical address. Therefore, when data is accessed, it must be searched from the beginning. For this reason, an address mapping table for comparing logical / physical addresses is generally formed to find a corresponding physical address.

  The address mapping table is created when the system is operating. Such a table is a table in which the relative relationship between the logical address and the physical address is recorded, and the comparison table is stored by a 2K size SRAM. If there are two or more address mapping tables, or there is a relatively large address mapping, the number of SRAMs and the capacity must be increased and stored. Therefore, the size of the control chip of the flash memory is increased. However, if the flash memory itself exceeds one area and the SRAM is fixed, if the address of the host terminal does not exist in the mapping table, the physical address is searched again from the other area of the flash memory, The corresponding physical address must be written to the address mapping table so that the physical address corresponding to the logical address can be obtained quickly.

  For flash memory, the time required for writing the data is longer than the time required for reading. In addition, at the same time that data is written to the memory, it must be considered whether data already exists in the written address. If data already exists at the address, the data to be written by the host terminal is previously written in an empty block where no data exists, and the data originally written at the address of the block is moved to a new block, Make the address of the host terminal correspond to the physical address. For this reason, the flash memory write operation is very complicated, especially when searching for a completely empty block, which takes a considerable amount of time and may search for all the blocks to find a usable empty block for the first time. Therefore, in order to make the reading and writing method of the flash memory efficient, there is a demand for a solution of a method that can improve the drawbacks of the prior art.

  An object of the present invention is to provide a flash memory read / write control method capable of efficiently controlling a flash memory and reducing the size of a control chip of the flash memory.

  It is another object of the present invention to provide a flash memory read / write control method capable of increasing the write speed by reducing the number of times the flash memory searches for an empty block.

The present invention will be specifically described below.
The flash memory read / write control method according to claim 1 sets a plurality of blocks of the flash memory in one area, and is based on a relationship between the block address and a logical address corresponding to the block address during system operation. Three sets of logical / physical address mapping tables, a FAT address mapping table, an address mapping table in the first area, and a high-speed access address mapping table for partial blocks in the second area,
When a logical address to be searched is transmitted from the host terminal to the flash memory, if the logical address to be searched exists in the FAT area of the memory, the physical address is directly detected from the FAT address mapping table, and the search is performed. If the logical address to perform the search does not exist in the FAT area of the memory, calculate the block in which area the logical address to perform the search is located,
As a result of the calculation, when it is determined that the logical address to be searched exists in the first area, the physical address is searched from the address mapping table of the first area, and the logical address to be searched is in the first area. If not, search the high-speed access address mapping table,
If the logical address to be searched does not exist in the high-speed access address mapping table, another high-speed access address mapping table is separately created based on the calculation result, and another high-speed access address mapping table is additionally created based on the search result. Whether or not to create an area address mapping table for each area, and until the physical address corresponding to the logical address to be searched is detected, the address obtained by performing the search is used for reading or writing data. It is a method to provide.

  In the flash memory read / write control method according to claim 2, when creating the mapping table according to claim 1, three sets of corresponding empty blocks are created and FIFO data is inserted to correspond to the logical address to be searched. If the physical address to be created exists in the created address mapping table, a new empty block is searched from the corresponding FIFO data in the address mapping table, and the new data is written in the new block. The data in the physical address is erased by copying the data in the new block, and finally the address mapping table is created according to the logical / physical address mapping relationship of the new block. It is a way to increase data.

  The flash memory read / write control method according to claim 3 is a method of selecting an empty block existing earliest by the FIFO principle when a new empty block is selected from the FIFO data in claim 2.

  The flash memory read / write control method according to claim 4 is a method in which the area in claim 1 creates one high-speed access address mapping table in one area.

  The flash memory read / write control method according to claim 5 is a method of calculating by a divider when calculating in which block of which area the logical address to be searched in claim 1 is present. .

  According to a sixth aspect of the present invention, there is provided a read / write control method for a flash memory, wherein the calculation method according to the fifth aspect determines a first fixed number from the number of blocks in an area and divides the fixed number by a logical address. The logical address to be searched represents a memory area to be mapped, and the calculated remainder is a method to represent the value of the shift position in the area address mapping table to which the logical address to be searched is mapped.

  According to a seventh aspect of the present invention, there is provided a read / write control method for a flash memory, wherein the remainder calculated by the second fixed number determined by the number of blocks in the high-speed area in claim 6 is obtained by dividing the second fixed number by a logical address. This is a method of expressing the value of the shift position in the address mapping table to which the logical address to be mapped.

  The method for controlling read / write of the flash memory according to claim 8 is a method in which new data is restricted within the same area when data is written or updated in the flash memory according to claim 1.

  The read / write control method of the flash memory according to claim 9 is the area address mapping table, the high-speed access address mapping table, and the empty area FIFO data in claim 1 in the random access memory provided in the SD controller. This method is stored in (RAM).

  The flash memory read / write control method according to claim 10 is a method in which the FAT address mapping table according to claim 1 and FIFO data of empty blocks are stored in a random access memory (RAM) in the CPU.

According to the flash memory read / write control method according to claim 11, when a plurality of blocks in the flash memory are set as one area and the system is operated, two sets of logic are determined from the relationship between the block address and the corresponding logical address. / Create a physical address mapping table, create a FAT address mapping table and a first area address mapping table respectively, and when the host terminal sends the logical address to be searched to the flash memory, the logical address to be searched is the FAT area of the memory If there is a physical address in the FAT address mapping table, or calculate in which area the logical address to search exists,
When the logical address to be searched exists in the first area, the physical address is searched from the address mapping table of the first area. When the logical address does not exist in the first area, the area address mapping table of another area is calculated based on the calculation result. In this method, a physical address corresponding to a logical address to be created and searched is searched, and the obtained address is used for reading and writing data.

  In the flash memory read / write control method according to claim 12, when creating the mapping table according to claim 11, two sets of corresponding empty areas are created, and FIFO data is inserted into the empty areas, of which When a physical address corresponding to a logical address to be searched from one address mapping table is found, a new empty block is found from the corresponding FIFO data in the address mapping table, and the new data is written into the new empty block. Copy the past data of the address into a new empty block, delete the data in the physical address, and finally write the logical / physical address mapping relationship of the new empty block to the address mapping table and erase the physical address This is a method of inserting FIFO data into an empty block.

  In the flash memory read / write control method according to claim 13, the order in which a new empty block is selected from the FIFO data in claim 11 is determined based on the FIFO block that existed first based on the FIFO principle. How to choose.

  According to a fourteenth aspect of the present invention, there is provided a flash memory read / write control method in which the order of calculating in which area the logical address to be searched is located is calculated by a divider.

  The flash memory read / write control method according to claim 15 is a method in which new data is restricted within the same area when data is written or updated in the flash memory according to claim 11.

  The read / write control method of the flash memory according to claim 16 is a method in which the area address mapping table and the FIFO data of the empty block according to claim 11 are stored in a random access memory in the SD controller.

  The flash memory read / write control method according to claim 17 is a method in which the FAT address mapping table and the FIFO data of empty blocks in claim 1 are stored in a random access memory in the CPU.

  The flash memory read / write control method of the present invention has the effect of reducing the number of times the flash memory searches for empty blocks and increasing the data write speed.

  The SD card controller receives data of various electronic products such as a card reader and a digital camera from the host terminal and stores them in the flash memory. This is to increase the control efficiency of the flash memory and reduce the chip size when designing the controller. Therefore, by providing the SD card controller with a logical address and physical address mapping table calculation method, the flash memory can be controlled more efficiently and the purpose of reducing the chip size can be achieved.

  Basically, the internal structure of the flash memory is divided into three calculation units: a zone, a block, and a page. In the method according to the present invention, a plurality of blocks in the flash memory (10) are set as one area. When the system is operated, three sets of logical / physical address mapping tables are created according to the relationship between each block address and the corresponding logical address. That is, the FAT (File Alocation Table) address mapping table (12), the first area (Zone0) address mapping table (14), and the high-speed access addresses of the partial blocks of the second area (Zone1) disclosed in FIG. It is a mapping table | surface (16).

  The FAT address mapping table (12) is created directly in the random access memory (RAM) in the CPU, and can achieve a relatively high efficiency. In addition, FIFO empty block FIFO data is also created in a random access memory (RAM) in the CPU.

  The first area address mapping table (14), the high-speed access address mapping table (16), and the empty block FIFO data are formed in the SRAM inside the SD card controller.

  When the host terminal transmits the logical address (18) to be searched to the controller of the flash memory, it is first confirmed whether or not the logical address (18) to be searched is in the FAT of the flash memory. If the logical address (18) exists in the FAT, the corresponding physical address is directly retrieved from the FAT address mapping table (12). If the logical address (18) does not exist in the FAT, a divider is used first to calculate which block in which area the logical address (18) is. As a result of this calculation, if it is determined that the logical address (18) to be searched is in the first area (Zone 0), the physical address is searched from the first area address mapping table (14). If it does not exist in the first area, the high-speed access address mapping table (16) is continuously searched.

  If the logical address (18) to be searched is not found in the high-speed access address mapping table (16), another high-speed access address mapping table (16 ′) is separately obtained based on the result of the above calculation. create. Further, it is determined whether or not to construct an area address mapping table (14 ′) of another area based on a search result based on a separately created high-speed access address mapping table (16 ′), and the logical address ( Search is performed until a physical address corresponding to 18) is obtained, and the obtained address is used for reading and writing data. Only one high speed access / address mapping table is created in each area.

  That is, if the logical address to be searched by the host terminal is not located in Zone 0 and is not located in the Zone 1 high-speed access block, a new high-speed access address mapping table is constructed and switched to this. There must be. If it is confirmed that the address to be searched is not located in Zone 0 but located in Zone 1, the zone 1 address mapping table is newly constructed, and the host terminal searches for the corresponding physical address. Served to do.

  When the above three sets of address mapping tables (12), (14) and (16) are created, empty blocks corresponding to the three sets of address mapping tables (12), (14) and (16) are simultaneously created. Build FIFO data (not shown). When the physical address corresponding to the logical address (18) to be searched is retrieved from one of the address mapping tables (12), (14), (16), based on the FIFO principle, A new empty block formed first is searched from the corresponding FIFO data in the address mapping table. Next, new data is written in the new empty block, and the original data in the physical address is copied into the new empty block. Next, the data in the physical address is erased, and finally the mapping relationship between the logical address and the physical address of the new empty block is created in the address mapping table. Also, an empty block from which the physical address has been deleted is added to the corresponding FIFO data. Therefore, by using the mapping table of each address together with the FIFO data of the empty block, the efficiency of the flash memory can be improved and the average usage frequency of each block can be increased efficiently.

  The spirit of the present invention is as described above. Next, the structure and mechanism of each mapping table of the present invention will be described with reference to FIG. In the present invention, in order to reduce the number of times the flash memory searches for empty blocks, an empty block FIFO (Empty Block FIFO) mechanism is applied to concentrate unused blocks in the area. When data is written into the flash memory, it can be written directly to the physical address by calling an empty block directly from within the FIFO data, so that the number of times the flash memory is searched for an empty block can be reduced. In the process of writing, it is not necessary to search whether the page in each block is used, and the writing speed increases. Also, when each block is erased, the physical address is stored in the FIFO data. Accordingly, the physical address of each erased block is replenished in the FIFO buffer data, the number of times FIFO data is recreated can be reduced, and the frequency of use of all the blocks is uniform.

  Looking at the operating principle of the flash memory, each area basically comprises 1024 blocks. When the capacity of such flash memory exceeds 16 Mbytes, two or more areas always appear, providing a sufficient swirling space. Each area uses 1000 blocks, and the remaining blocks are regarded as reserved blocks and are used as a data turning space. Therefore, if the flash memory is 128 Mbytes, it is divided into eight areas in total. Therefore, a total of 8192 blocks can be used. However, in the present invention, 8000 blocks are averaged and distributed in 8 areas, so that 24 blocks are reserved blocks in each area. Therefore, the logical address of the host does not exceed 0-7999 addresses. For this reason, the logical address can be calculated by dividing 1000 (a fixed number determined by the number of blocks in the area), and what is the offset (Offset) of the corresponding address mapping table. Can know. That is, it can directly correspond to a physical address. However, since the random access memory (RAM) of the storage area address mapping table has only 2K, it is necessary to confirm whether the logical address of the current corresponding area is a corresponding address in the address mapping table. Also, if the current corresponding area is an area that should not correspond to a logical address, another address mapping table must be created. In addition, the address calculation is accelerated. In the present invention, a divider is designed to divide one 1000 and 128. Such a divider automatically calculates the quotient and remainder of 1000 and 128 when a logical address is input. That is, the actual address of the direct address mapping table is searched to increase the efficiency of the system.

  Furthermore, the FAT table is frequently changed. Therefore, a set of FAT address mapping table dedicated to FAT and empty block FIFO data are added. The FAT address mapping table and empty block FIFO data directly correspond to logical addresses 0 to 39. However, when the logical address of the host is located between 0 and 39, there is no need to consider which area the current area address mapping table corresponds to, and the corresponding address can be found directly from the FAT address mapping table. That's fine. For this reason, the number of times of creating the area address mapping table can be reduced.

  In order to reduce the number of times of creating the entire area address mapping table, a set of high-speed access address mapping table and rapid empty block FIFO data are increased. The size of the high-speed access / address mapping table is 256 bytes and can be stored in 128 blocks. If the host logical block does not exist in the area address mapping and FAT address mapping table, the corresponding address is retrieved from the fast access address mapping table. If the logical address does not exist, create a fast access address mapping table. Because this table is composed of only 128 blocks, the speed of creating the high-speed access address mapping table is faster than that of creating the 2K area address mapping table. Therefore, the number of times of creating the entire area address mapping table can be reduced.

  Another type of combination method that further improves the conventional construction method will be described. In this combination method, the FAT address mapping table (12) and the empty block FIFO data described above are reserved, and the fast access address mapping table (16) is partially erased. Further, the size of the original first area address mapping table (14) is corrected from 1024 blocks to 256 blocks, and the area address mapping table is directly searched. The search is continued until the physical address corresponding to the logical address to be searched is obtained, and the obtained address is used for data reading and writing. This method saves the time to create the address mapping table and reduces the size of the SRAM. Therefore, the original 2K can be reduced to 512 bytes, and the efficiency is quadrupled to reduce to 3/4 SRAM. This saves costs and increases efficiency.

That is, the above method uses the area address mapping table together with the empty block FIFO data and uses the concept of combining the area address mapping table and the empty block FIFO data with the logical address in the FAT table, so that the flash memory is read and written. In this case, it is not necessary to create a FAT address mapping table for the FAT area regardless of which area the area address mapping table corresponds to.
Also, increase the high-speed access address mapping table, if a logical address appears and does not exist in the area address mapping table and FAT address mapping table, to create a relatively small high-speed access address mapping table first, The speed of the system can be surely increased.

  The above is a preferred embodiment of the present invention and does not limit the scope of the present invention. Therefore, any modifications or changes that can be made by those skilled in the art, which are made within the spirit of the present invention and have an equivalent effect on the present invention, shall belong to the scope of the claims of the present invention. To do.

It is explanatory drawing which showed the relationship between the physical address and logical address in the conventional flash memory, and explanatory drawing which showed the address mapping table | surface created using this relationship. It is explanatory drawing which showed the structure of the logical address of this invention.

Explanation of symbols

10 Flash memory 12 FAT address mapping table 14, 14 'First area address mapping table 16, 16' High-speed access address mapping table 18 Logical address

Claims (17)

A plurality of blocks of the flash memory are set in one area, and based on the relationship between the block address and the logical address corresponding to the block address when the system operates, a FAT address mapping table, an address mapping table in the first area, Create three sets of logical / physical address mapping tables for fast access address mapping tables for partial blocks in the second region,
When a logical address to be searched is transmitted from the host terminal to the flash memory, if the logical address to be searched exists in the FAT area of the memory, the physical address is directly detected from the FAT address mapping table, and the search is performed. If the logical address to perform the search does not exist in the FAT area of the memory, calculate the block in which area the logical address to perform the search is located,
As a result of the calculation, when it is determined that the logical address to be searched exists in the first area, the physical address is searched from the address mapping table of the first area, and the logical address to be searched is in the first area. If not, search the high-speed access address mapping table,
If the logical address to be searched does not exist in the high-speed access address mapping table, another high-speed access address mapping table is separately created based on the calculation result, and another high-speed access address mapping table is additionally created based on the search result. Whether or not to create an area address mapping table for each area, and until the physical address corresponding to the logical address to be searched is detected, the address obtained by performing the search is used for reading or writing data. A flash memory read / write control method characterized by comprising:   When creating the mapping table, if three sets of corresponding empty blocks are created, FIFO data is inserted, and the physical address corresponding to the logical address to be searched exists in the created address mapping table, the address mapping table Finds a new empty block from the corresponding FIFO data in, writes the new data into the new block, and copies the original data at the physical address into the new block to erase the data at the physical address 2. The flash memory according to claim 1, wherein an address mapping table is finally created based on a logical / physical address mapping relationship of a new block, and FIFO data is increased to an empty block after the physical address is erased. Read / write control method.   3. The flash memory read / write control method according to claim 2, wherein when a new empty block is selected from the FIFO data, an empty block existing first is selected according to the FIFO principle.   2. The flash memory read / write control method according to claim 1, wherein one high-speed access address mapping table is created in one area.   2. The flash memory read / write control method according to claim 1, wherein when calculating which block in which area the logical address to be searched for is calculated by a divider.   The calculation method is such that a first fixed number is determined from the number of blocks in an area, and the quotient calculated by dividing the fixed number by a logical address represents a memory area to which a logical address to be searched is mapped. 6. The flash memory read / write control method according to claim 5, wherein the remainder represents a value of a shift position in an area address mapping table to which a logical address to be searched is mapped.   The remainder calculated by the second fixed number determined by the number of blocks in the high-speed area represents the value of the shift position in the address mapping table mapped by the logical address to be searched by dividing the second fixed number by the logical address. The flash memory read / write control method according to claim 6.   2. The method of controlling read / write of a flash memory according to claim 1, wherein when data is written or updated in the flash memory, new data is restricted within the same area.   2. The area address mapping table, the high-speed access address mapping table, and empty area FIFO data are stored in a random access memory (RAM) provided in an SD controller. Flash memory read / write control method.   2. The flash memory read / write control method according to claim 1, wherein the FAT address mapping table and FIFO data of empty blocks are stored in a random access memory (RAM) in a CPU. When multiple blocks in the flash memory are set as one area and the system is operated, two sets of logical / physical address mapping tables are created from the relationship between the block address and the corresponding logical address, and each FAT address mapping table When the host terminal sends the logical address to be searched to the flash memory, if the logical address to be searched exists in the FAT area of the memory, the physical address is selected from the FAT address mapping table. Calculate directly in which area the logical address to search is located,
When the logical address to be searched exists in the first area, the physical address is searched from the address mapping table of the first area. When the logical address does not exist in the first area, the area address mapping table of another area is calculated based on the calculation result. A flash memory read / write control method characterized in that a physical address corresponding to a logical address to be created and searched is searched for, and the obtained address is used for reading and writing data.   When creating the mapping table, two sets of corresponding empty areas were created, FIFO data was inserted into the empty area, and the physical address corresponding to the logical address to be searched from one of the address mapping tables was found. Find a new empty block from the corresponding FIFO data in the address mapping table, write the new data into the new empty block, copy the past data of the physical address into the new empty block, 12. Finally, the logical / physical address mapping relationship of the new empty block is written into the address mapping table, the physical address is erased, and the FIFO data is inserted into the empty block. The flash memory read / write control method to be described.   12. The read / write operation of the flash memory according to claim 11, wherein the order in selecting a new empty block from within the FIFO data is selected from the empty blocks that existed earliest based on the FIFO principle. Control method.   12. The flash memory read / write control method according to claim 11, wherein an order of calculating in which region the logical address to be searched is located is calculated by a divider.   12. The flash memory read / write control method according to claim 11, wherein when data is written to or updated in the flash memory, new data is restricted within the same area.   12. The flash memory read / write control method according to claim 11, wherein the area address mapping table and FIFO data of empty blocks are stored in a random access memory in an SD controller. 2. The flash memory read / write control method according to claim 1, wherein the FAT address mapping table and empty block FIFO data are stored in a random access memory in a CPU.

Images