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JP2005203544A - Nitride semiconductor device and its manufacturing method - Google Patents

Nitride semiconductor device and its manufacturing method Download PDF

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JP2005203544A
JP2005203544A JP2004007939A JP2004007939A JP2005203544A JP 2005203544 A JP2005203544 A JP 2005203544A JP 2004007939 A JP2004007939 A JP 2004007939A JP 2004007939 A JP2004007939 A JP 2004007939A JP 2005203544 A JP2005203544 A JP 2005203544A
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barrier layer
nitride semiconductor
gate electrode
semiconductor device
layer
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Toshiyuki Oishi
敏之 大石
Takuma Nanjo
拓真 南條
Muneyoshi Fukita
宗義 吹田
Katsuomi Shiozawa
勝臣 塩沢
Yuji Abe
雄次 阿部
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Mitsubishi Electric Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To obtain a nitride semiconductor device which maintains a threshold voltage to a negative voltage and enables a high power operation at high breakdown strength. <P>SOLUTION: This nitride semiconductor device comprises a substrate 1, a channel layer 2 formed on the substrate 1 and composed of a nitride semiconductor, a barrier layer 3 formed on the channel layer 2 and composed of the nitride semiconductor having larger band gap energy than the channel layer 2, a gate electrode 5 formed on the barrier layer 3, and a source electrode 4 and a drain electrode 6 formed at opposing positions via the gate electrode 5 on the barrier layer 3, respectively. The thickness of the layer of the region of at least a part of the barrier layer 3 between the drain electrode 6 and the gate electrode 5 is thinner than that of the barrier layer 3 immediately below the gate electrode 5. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、窒化物半導体装置とその製造方法に関し、特にしきい値電圧を負電圧に維持した状態でかつ破壊耐圧が高く高出力動作可能な窒化物半導体装置とその製造方法に関するものである。   The present invention relates to a nitride semiconductor device and a manufacturing method thereof, and more particularly to a nitride semiconductor device having a high breakdown voltage and a high output operation while maintaining a threshold voltage at a negative voltage and a manufacturing method thereof.

窒化物半導体系、特に窒化ガリウム系半導体は高い絶縁破壊電界強度、高い熱伝導率、高い電子飽和速度を有しており高周波の高出力高電子移動度トランジスタの構成材料として期待されている。特に、窒化アルミニウムガリウム(AlGaN)/窒化ガリウム(GaN)ヘテロ接合構造を有する高電子移動度トランジスタ(AlGaN/GaN High Electron Mobility Transistor (HEMT))は、AlGaNとGaNとのヘテロ接合界面付近に電子が高濃度で蓄積するいわゆる2次元電子ガスが形成されるが、かかる2次元電子ガスはAlGaNに添加されるドナー不純物とは空間的に分離されて存在する結果、高い電子移動度が実現できるので、高周波で動作可能である。さらに、AlGaN/GaN系へテロ構造における2次元電子は、現在HEMTとして普及しているAlGaAs/GaAs系の場合に比べて、高電界領域で2倍以上の電子速度を有し、高周波でスイッチング動作可能でかつ高出力のHEMTへの応用が期待されている。   Nitride semiconductors, especially gallium nitride semiconductors, have high dielectric breakdown field strength, high thermal conductivity, and high electron saturation speed, and are expected as constituent materials for high-frequency, high-power, high-electron mobility transistors. In particular, a high electron mobility transistor having an aluminum gallium nitride (AlGaN) / gallium nitride (GaN) heterojunction structure (AlGaN / GaN High Electron Mobility Transistor (HEMT)) has electrons near the heterojunction interface between AlGaN and GaN. A so-called two-dimensional electron gas that accumulates at a high concentration is formed, but since the two-dimensional electron gas exists spatially separated from donor impurities added to AlGaN, high electron mobility can be realized. It can operate at high frequency. Furthermore, the two-dimensional electrons in the AlGaN / GaN heterostructure have an electron velocity more than twice in the high electric field region compared with the AlGaAs / GaAs system that is currently popular as HEMT, and switching operation at high frequency. It is expected to be applied to a HEMT with a high output that is possible.

従来の窒化物半導体を用いた高電子移動度トランジスタ(AlGaN/GaN High Electron Mobility Transistor (HEMT))では、例えば非特許文献1の図1に示されるように、AlGaNバリア層の層厚はソース/ドレイン電極間で一定である。つまり、ゲート電極直下のAlGaNバリア層厚とゲート/ドレイン電極間のAlGaNバリア層の層厚は等しい。なお、後述の実施の形態1における図1(b)の素子断面図が従来技術による素子構造とほぼ同一である。   In a conventional high electron mobility transistor (AlGaN / GaN High Electron Mobility Transistor (HEMT)) using a nitride semiconductor, for example, as shown in FIG. Constant between drain electrodes. That is, the thickness of the AlGaN barrier layer immediately below the gate electrode is equal to the thickness of the AlGaN barrier layer between the gate / drain electrodes. Note that the element cross-sectional view of FIG. 1B in the first embodiment described later is almost the same as the element structure according to the prior art.

安藤 その他、”薄層化サファイア基板上の110W出力AlGaN/GaNヘテロFET”、電子情報通信学会技術研究報告 ED2001−185、7〜12ページAndo and others, “110W output AlGaN / GaN hetero FET on thin sapphire substrate”, IEICE technical report ED2001-185, pp. 7-12

AlGaN/GaN HEMTを電力増幅器として使用する場合、出力電流(ドレイン電流)はなるべく大きくできる方が望ましい。ドレイン電流を増加するには、入力電圧(ゲート電圧)を増大する必要がある。しかし、ゲート電圧を増加しすぎて負電圧(マイナス電圧)から正電圧(プラス電圧)に転じると、ゲート電極におけるショットキー障壁に正電圧が印加されてしまう。この場合、ゲート電流が急激に増加するのでトランジスタ動作としては望ましくない。ゲート電流の増大はショットキー障壁の劣化を引き起こし、素子特性、特に信頼性の劣化を招くからである。よって、AlGaN/GaN HEMTでは、しきい値電圧Vthはマイナス数V以下の負電圧であることが望まれる。 When using an AlGaN / GaN HEMT as a power amplifier, it is desirable that the output current (drain current) be as large as possible. In order to increase the drain current, it is necessary to increase the input voltage (gate voltage). However, if the gate voltage is increased too much to change from a negative voltage (minus voltage) to a positive voltage (plus voltage), a positive voltage is applied to the Schottky barrier in the gate electrode. In this case, the gate current increases rapidly, which is not desirable for transistor operation. This is because an increase in the gate current causes a deterioration of the Schottky barrier, leading to deterioration of device characteristics, particularly reliability. Therefore, in the AlGaN / GaN HEMT, the threshold voltage Vth is desired to be a negative voltage equal to or less than a minus number V.

しかしながら、従来のAlGaN/GaN HEMTにでは、しきい値電圧Vthをマイナス数V(例えば−5V以下)に保持した状態で、ゲート/ドレイン電極間破壊耐圧(以下、単に「破壊耐圧」と言う)を向上させることは難しい。破壊耐圧の向上を目的としてAlGaNバリア層厚を薄くすると、しきい値電圧Vthが正バイアス側にシフトしてしまう不具合が生じるからである。 However, in the conventional AlGaN / GaN HEMT, the breakdown voltage between the gate and drain electrodes (hereinafter, simply referred to as “breakdown breakdown voltage”) with the threshold voltage Vth held at a negative number V (for example, −5 V or less). ) Is difficult to improve. This is because if the thickness of the AlGaN barrier layer is reduced for the purpose of improving the breakdown voltage, the threshold voltage Vth is shifted to the positive bias side.

上述したように、従来の素子構造ではしきい値電圧Vthと破壊耐圧にトレードオフの関係が存在するため、しきい値電圧Vthをマイナス数V程度の負電圧に保持した状態で、かつ破壊耐圧を向上させるのは困難であるという問題があった。 As described above, in the conventional element structure, there is a trade-off relationship between the threshold voltage Vth and the breakdown voltage, so that the threshold voltage Vth is maintained at a negative voltage of about minus several V, and There is a problem that it is difficult to improve the breakdown voltage.

この発明は、上記のような問題を解決するためになされたものであり、しきい値電圧Vthをマイナス数V程度の負電圧に保持した状態でかつ破壊耐圧が高く高出力動作が可能な窒化物半導体装置を得ることを目的とし、さらにその製造方法を提供することを目的とする。 The present invention has been made in order to solve the above-described problems. The threshold voltage Vth is maintained at a negative voltage of about minus several V, and the breakdown voltage is high and high output operation is possible. It is an object to obtain a nitride semiconductor device and to provide a manufacturing method thereof.

本発明に係る窒化物半導体装置は、基板と、上記基板上に形成され窒化物半導体からなるチャネル層と、上記チャネル層上に形成され上記チャネル層よりバンドギャップエネルギーの大きい窒化物半導体からなるバリア層と、上記バリア層上に形成されたゲート電極と、上記バリア層上で上記ゲート電極を介して対向する位置にそれぞれ形成されたソース電極およびドレイン電極と、を備え、上記ドレイン電極と上記ゲート電極間の上記バリア層の少なくとも一部の領域の層厚が上記ゲート電極直下のバリア層の層厚より薄いこととした。   The nitride semiconductor device according to the present invention includes a substrate, a channel layer formed on the substrate and made of a nitride semiconductor, and a barrier made of a nitride semiconductor formed on the channel layer and having a larger band gap energy than the channel layer. A gate electrode formed on the barrier layer, and a source electrode and a drain electrode formed on the barrier layer at positions facing each other via the gate electrode, the drain electrode and the gate The layer thickness of at least a part of the barrier layer between the electrodes is smaller than the layer thickness of the barrier layer immediately below the gate electrode.

この発明に係る窒化物半導体装置は、上述の構成を適用したので、しきい値電圧Vthと破壊耐圧のトレードオフを緩和して、しきい値電圧Vthを負電圧に維持した状態でかつ破壊耐圧が高くて高出力動作が可能となる。 In the nitride semiconductor device according to the present invention, since the above-described configuration is applied, the trade-off between the threshold voltage Vth and the breakdown voltage is alleviated and the threshold voltage Vth is maintained at a negative voltage and High breakdown voltage enables high output operation.

実施の形態1.
本発明の実施の形態1による窒化物半導体装置、より具体的にはAlGaN/GaN HEMTの素子断面図を図1(a)に示す。基板1上に、GaNチャネル層2、AlGaNバリア層3が形成されている。なお、基板1は、サファイア(Al)、炭化珪素(SiC)、GaN、シリコン(Si)等の材料が使用できるが、炭化珪素基板が最も好適である。
Embodiment 1 FIG.
FIG. 1A shows an element cross-sectional view of a nitride semiconductor device according to Embodiment 1 of the present invention, more specifically, an AlGaN / GaN HEMT. A GaN channel layer 2 and an AlGaN barrier layer 3 are formed on the substrate 1. The substrate 1 may be made of a material such as sapphire (Al 2 O 3 ), silicon carbide (SiC), GaN, silicon (Si), etc., but a silicon carbide substrate is most preferable.

AlGaNバリア層3上には、ソース電極4、ゲート電極5、ドレイン電極6がそれぞれ形成されている。ソース電極4およびドレイン電極6はゲート電極5を介して互いに対向する位置に設けられている。   On the AlGaN barrier layer 3, a source electrode 4, a gate electrode 5, and a drain electrode 6 are formed. The source electrode 4 and the drain electrode 6 are provided at positions facing each other through the gate electrode 5.

従来の窒化物半導体装置に対する本実施の形態の窒化物半導体装置の特徴的な点は、ソース電極4とゲート電極5間、ゲート電極5とドレイン電極6間のAlGaNバリア層3の層厚がゲート電極5直下のAlGaNバリア層厚より薄くなっている点にある。つまり、ドレイン電極6とゲート電極5間およびソース電極4とゲート電極5間のAlGaNバリア層3の少なくとも一部の領域の層厚がゲート電極5直下のAlGaNバリア層3の層厚より薄くなっている。具体的には、かかる領域のAlGaNバリア層3中にエッチングによる溝7が形成されている。なお、比較として、かかる特徴の無い従来の均一な層厚を有するAlGaNバリア層を具備した窒化物半導体装置の素子断面図を図1(b)に示す。   A characteristic feature of the nitride semiconductor device of the present embodiment over the conventional nitride semiconductor device is that the thickness of the AlGaN barrier layer 3 between the source electrode 4 and the gate electrode 5 and between the gate electrode 5 and the drain electrode 6 is the gate. The thickness is smaller than the thickness of the AlGaN barrier layer directly under the electrode 5. That is, the layer thickness of at least a part of the AlGaN barrier layer 3 between the drain electrode 6 and the gate electrode 5 and between the source electrode 4 and the gate electrode 5 is smaller than the layer thickness of the AlGaN barrier layer 3 immediately below the gate electrode 5. Yes. Specifically, an etching groove 7 is formed in the AlGaN barrier layer 3 in such a region. For comparison, FIG. 1B shows an element cross-sectional view of a nitride semiconductor device having an AlGaN barrier layer having a conventional uniform layer thickness without such a feature.

以下、本実施の形態の窒化物半導体装置によって実現される素子特性上の特徴を説明する。しきい値電圧Vthとゲート電極5直下のAlGaNバリア層3の層厚との関係を図2(a)に示す。図2(a)からわかるように、しきい値電圧Vthはゲート電極5直下のAlGaNバリア層3の層厚が薄くなるにつれて正電圧側へ比例的に増加する。AlGaNバリア層3の層厚が薄くなるほど、ゲート電極5下部のGaNチャネル層2全体を空乏化するのに必要なゲート電圧がわずかで済むようになるからである。以下、しきい値電圧VthとAlGaNバリア層3の層厚の関係をさらに説明する。 Hereinafter, characteristics of element characteristics realized by the nitride semiconductor device of the present embodiment will be described. FIG. 2A shows the relationship between the threshold voltage Vth and the layer thickness of the AlGaN barrier layer 3 immediately below the gate electrode 5. As can be seen from FIG. 2A, the threshold voltage Vth increases in proportion to the positive voltage side as the thickness of the AlGaN barrier layer 3 immediately below the gate electrode 5 decreases. This is because as the layer thickness of the AlGaN barrier layer 3 is reduced, the gate voltage required to deplete the entire GaN channel layer 2 below the gate electrode 5 becomes smaller. Hereinafter, the relationship between the threshold voltage Vth and the layer thickness of the AlGaN barrier layer 3 will be further described.

AlGaN/GaN HEMTのしきい値電圧をVthとすると、

th=φ-ΔEc-qd2/(2ε)-qPd/ε (1)

となる。なお、(1)式中、φはショットキー障壁高さ、ΔEcは伝導帯側のバンド不連続、qは電荷量、NはAlGaNバリア層のドーピング濃度、dはAlGaNバリア層中のドーピング膜厚、εは誘電率、Pは分極率、dはAlGaNバリア層の層厚をそれぞれ表す。(1)式中、第3項がAlGaNバリア層のドーピングによる項、第4項が分極による項を表す。第3項はGaAs半導体系材料と共通の値となるが、第4項の分極による項がGaN等の窒化物半導体系材料特有の大きな値となっている。よって、AlGaN/GaN HEMTではしきい値電圧Vthに対する第3項の寄与は殆ど無い一方、第4項からの寄与が大半を占める。従って、AlGaN/GaN HEMTではしきい値電圧Vth制御のファクターとして、AlGaNバリア層の層厚dが非常に重要である。要するに、しきい値電圧VthはAlGaNバリア層の層厚dに強く依存している。
When the threshold voltage of AlGaN / GaN HEMT is Vth ,

V th = φ−ΔEc−qd 1 N 2 / (2ε) −qPd 2 / ε (1)

It becomes. In the equation (1), φ is the Schottky barrier height, ΔEc is the band discontinuity on the conduction band side, q is the charge amount, N is the doping concentration of the AlGaN barrier layer, and d 1 is the doping film in the AlGaN barrier layer. Thickness, ε is dielectric constant, P is polarizability, and d 2 is the thickness of the AlGaN barrier layer. In the formula (1), the third term represents a term due to doping of the AlGaN barrier layer, and the fourth term represents a term due to polarization. The third term is a value common to the GaAs semiconductor material, but the term due to the polarization of the fourth term is a large value peculiar to the nitride semiconductor material such as GaN. Therefore, in the AlGaN / GaN HEMT, the third term contributes little to the threshold voltage Vth, while the contribution from the fourth term occupies the majority. Accordingly, as a factor of AlGaN / GaN HEMT at the threshold voltage V th control, thickness d 2 of the AlGaN barrier layer is very important. In short, the threshold voltage V th strongly depends on the layer thickness d 2 of the AlGaN barrier layer.

一方、破壊耐圧に関しては、図2(b)の破壊耐圧とゲート/ドレイン電極5,6間のAlGaNバリア層3の層厚との関係から分かるように、ゲート/ドレイン電極5,6間のAlGaNバリア層3の層厚が薄くなるにつれて破壊耐圧は急激に増加、すなわち向上する。ゲート電極5からドレイン電極6方向への空乏層の伸長の度合いはAlGaNバリア層3の層厚減少に伴い大きくなるからである。   On the other hand, with respect to the breakdown voltage, as can be seen from the relationship between the breakdown voltage in FIG. 2B and the thickness of the AlGaN barrier layer 3 between the gate / drain electrodes 5, 6, the AlGaN between the gate / drain electrodes 5, 6. As the layer thickness of the barrier layer 3 decreases, the breakdown voltage increases rapidly, that is, improves. This is because the degree of extension of the depletion layer from the gate electrode 5 toward the drain electrode 6 increases as the thickness of the AlGaN barrier layer 3 decreases.

図2からAlGaNバリア層3の層厚が均一な従来構造(図1(b))では、しきい値電圧Vthが−5V以下でかつ破壊耐圧が150Vを越えるAlGaN/GaN HEMTの作製は困難であることがわかる。つまり、図2(a)からしきい値電圧Vthを−5V以下とするにはAlGaNバリア層3の層厚を25nm以上に設定する必要があるが、図2(b)によると破壊耐圧を150V以上にするには、AlGaNバリア層3の層厚を20nm以下に設定せねばならないからである。 From FIG. 2, it is difficult to fabricate an AlGaN / GaN HEMT having a threshold voltage Vth of −5 V or less and a breakdown voltage exceeding 150 V in the conventional structure (FIG. 1B) in which the thickness of the AlGaN barrier layer 3 is uniform. It can be seen that it is. That is, in order to make the threshold voltage Vth -5 V or less from FIG. 2A, it is necessary to set the layer thickness of the AlGaN barrier layer 3 to 25 nm or more, but according to FIG. This is because the layer thickness of the AlGaN barrier layer 3 must be set to 20 nm or less in order to set it to 150 V or more.

一方、本実施の形態に係るAlGaN/GaN HEMTのように、ゲート電極5下のAlGaNバリア層3の層厚を保持して例えばしきい値電圧Vthを−5Vに設定しながら、ゲート/ドレイン電極間5,6のAlGaNバリア層厚を20nm以下に薄層化すれば、破壊耐圧を150V以上に維持できる。要するに、しきい値電圧Vthと破壊耐圧を所定の範囲内において独立に制御できるようになる。 On the other hand, like the AlGaN / GaN HEMT according to the present embodiment, while maintaining the layer thickness of the AlGaN barrier layer 3 under the gate electrode 5 and setting the threshold voltage Vth to −5 V, for example, the gate / drain If the thickness of the AlGaN barrier layer between the electrodes 5 and 6 is reduced to 20 nm or less, the breakdown voltage can be maintained at 150 V or more. In short, the threshold voltage Vth and the breakdown voltage can be controlled independently within a predetermined range.

以上の説明から、本実施の形態に係るAlGaN/GaN HEMTでは、ソース/ゲート電極4、5間、ゲート/ドレイン電極5、6間のAlGaNバリア層3の層厚がゲート電極5直下のAlGaNバリア層厚に対して、どの程度薄くなっているかが、極めて重要であることがわかる。薄層化されたAlGaNバリア層3の層厚がゲート電極5直下のAlGaNバリア層厚に対して、20%以上80%以下の範囲が好適であり、35%以上65%以下の範囲がさらに好適である。なお、上記範囲の下限は、AlGaN/GaN界面においてピエゾ効果が充分発現する必要があるとの条件から決まっている。   From the above description, in the AlGaN / GaN HEMT according to the present embodiment, the thickness of the AlGaN barrier layer 3 between the source / gate electrodes 4 and 5 and between the gate / drain electrodes 5 and 6 is the AlGaN barrier immediately below the gate electrode 5. It can be seen that how thin the layer thickness is is extremely important. The thickness of the thinned AlGaN barrier layer 3 is preferably in the range of 20% or more and 80% or less, and more preferably in the range of 35% or more and 65% or less with respect to the thickness of the AlGaN barrier layer immediately below the gate electrode 5. It is. Note that the lower limit of the above range is determined from the condition that the piezoelectric effect needs to be sufficiently developed at the AlGaN / GaN interface.

本実施の形態に係るAlGaN/GaN HEMTでは、GaNチャネル層2、AlGaNバリア層3の層厚はそれぞれ、0.5〜3μm、5〜50nm程度が好適である。またAlGaNバリア層3のAl組成比は0.1〜0.5程度が好適である。   In the AlGaN / GaN HEMT according to the present embodiment, the thicknesses of the GaN channel layer 2 and the AlGaN barrier layer 3 are preferably about 0.5 to 3 μm and about 5 to 50 nm, respectively. The Al composition ratio of the AlGaN barrier layer 3 is preferably about 0.1 to 0.5.

なお、ピエゾ効果が発現する窒素化物半導体から構成され、かつ、バンドギャップエネルギーが互いに異なる材料であればチャネル層2とバリア層3は他の材料と容易に置換可能である。例えば、上述のGaNチャネル層2とAlGaNバリア層3を、それぞれInGaNとAlGaN、InGaAlNとAlGaN、AlGaNとAlN等の材料の組合せに置換可能である。   Note that the channel layer 2 and the barrier layer 3 can be easily replaced with other materials as long as they are made of a nitride semiconductor exhibiting a piezo effect and have different band gap energies. For example, the above-described GaN channel layer 2 and AlGaN barrier layer 3 can be replaced with a combination of materials such as InGaN and AlGaN, InGaAlN and AlGaN, and AlGaN and AlN, respectively.

以上、本実施の形態の窒化物半導体装置では、上述の素子構造を適用したので、しきい値電圧Vthを負電圧に維持した状態でかつ破壊耐圧が高くて高出力動作が可能な窒化物半導体装置を容易に提供できる。 As described above, in the nitride semiconductor device according to the present embodiment, since the above-described element structure is applied, a nitride capable of high output operation with a high breakdown voltage while maintaining threshold voltage Vth at a negative voltage. A semiconductor device can be easily provided.

次に、本実施の形態の窒化物半導体装置の製造方法について、図3に基づき説明する。
先ず、基板1上に、GaNチャネル層2、AlGaNバリア層3を順次エピタキシャル結晶成長する。かかる結晶成長法としては、有機金属を用いた化学的気相成長法(MOCVD: Metalorganic Chemical Vapor Deposition)、分子線エピタキシー法(MBE: Molecular Beam Epitaxy)が好適であるが、他の結晶成長法を用いても良い(図3(a))。
Next, a method for manufacturing the nitride semiconductor device of the present embodiment will be described with reference to FIG.
First, a GaN channel layer 2 and an AlGaN barrier layer 3 are epitaxially grown on the substrate 1 in order. As such a crystal growth method, a chemical vapor deposition method (MOCVD: Metalorganic Chemical Vapor Deposition) using an organic metal and a molecular beam epitaxy (MBE) method are suitable, but other crystal growth methods can be used. It may be used (FIG. 3A).

続いて、AlGaNバリア層3上にソースおよびドレイン電極4,6を形成する。各電極の形成方法は以下の通りである。ソースおよびドレイン電極4,6となる以外の部分をレジスト膜で被覆し、ソースおよびドレイン電極4,6を構成する金属、つまり、オーミック特性が得られる金属を真空蒸着やスパッタ法等により成膜する。かかる金属材料としては、例えばTi/Al、Ti/Al/Ti/Mo/Au、Ti/WSi等の組合せが挙げられる。レジスト膜のパターニングは公知のリソグラフィ技術によって行う。ソースおよびドレイン電極4,6の膜厚は材料にも依存するものの、それぞれの金属材料において2〜1000nmの範囲が好適である。公知のいわゆるリフトオフ法を用いれば、容易にソース/ドレイン領域に金属パターンが形成される。   Subsequently, source and drain electrodes 4 and 6 are formed on the AlGaN barrier layer 3. The formation method of each electrode is as follows. The portions other than the source and drain electrodes 4 and 6 are covered with a resist film, and the metal constituting the source and drain electrodes 4 and 6, that is, the metal capable of obtaining ohmic characteristics is formed by vacuum deposition or sputtering. . Examples of such metal materials include combinations of Ti / Al, Ti / Al / Ti / Mo / Au, Ti / WSi, and the like. The resist film is patterned by a known lithography technique. Although the film thickness of the source and drain electrodes 4 and 6 depends on the material, a range of 2 to 1000 nm is preferable for each metal material. If a known so-called lift-off method is used, a metal pattern is easily formed in the source / drain regions.

ソース/ドレイン電極4,6において良好なオーミック特性を得るために、通常、リフトオフ後に熱処理を行う。熱処理はランプによる加熱、炉による加熱等が用いられ、窒素やアルゴンの不活性ガス、または水素や酸素雰囲気中で500〜1000℃、10〜300秒程度で熱処理される。これにより、ソース電極4からAlGaNバリア層3直下のGaNチャネル層2、そしてドレイン電極6に達する電流の通路が確保される。   In order to obtain good ohmic characteristics in the source / drain electrodes 4 and 6, heat treatment is usually performed after lift-off. Heat treatment is performed using a lamp, a furnace, or the like, and is performed in an inert gas such as nitrogen or argon, or in a hydrogen or oxygen atmosphere at 500 to 1000 ° C. for about 10 to 300 seconds. This secures a current path from the source electrode 4 to the GaN channel layer 2 immediately below the AlGaN barrier layer 3 and to the drain electrode 6.

続いて、ソース/ドレイン電極4,6を形成した場合と同様のリフトオフ方法によって、AlGaNバリア層3上にゲート電極5形成用の金属膜を形成する。すなわち、レジスト膜でゲート領域以外にパターンを形成後、ゲート金属を蒸着し、レジスト膜を除去する。ゲート電極5としてはショットキー特性を示す金属、例えばNi、Pt、Ir、Pd、PtSi等を適用する。かかる金属を1〜500nm程度成膜する。また、ゲート金属上に、さらに金(Au)やアルミニウム(Al)を積層しても良い。ゲート電極5形成後の素子断面図を(図3(b))に示す。   Subsequently, a metal film for forming the gate electrode 5 is formed on the AlGaN barrier layer 3 by the lift-off method similar to the case where the source / drain electrodes 4 and 6 are formed. That is, after a pattern is formed in a region other than the gate region using a resist film, a gate metal is deposited and the resist film is removed. As the gate electrode 5, a metal exhibiting Schottky characteristics, for example, Ni, Pt, Ir, Pd, PtSi, or the like is applied. The metal is deposited to a thickness of about 1 to 500 nm. Further, gold (Au) or aluminum (Al) may be further stacked on the gate metal. A cross-sectional view of the device after the formation of the gate electrode 5 is shown in FIG.

さらに、上述の各電極が形成されたウエハ上にレジスト膜8を形成し、公知のリソグラフィ技術によってAlGaNバリア層3で溝7を形成する部位のみに開口を設ける(図3(c))。かかる開口を通して、AlGaNバリア層3を所望の深さまでエッチング除去する(図3(d))。エッチング方法としては、ドライエッチングの場合、例えば塩素ガスと不活性ガス(アルゴン、窒素)の混合ガスのプラズマがエッチングガスとして利用できる。また、ウエットエッチングであれば光照射しながら水酸化カリウム(KOH)溶液中でエッチングすることが可能である。   Further, a resist film 8 is formed on the wafer on which the above-described electrodes are formed, and an opening is provided only at a site where the groove 7 is formed in the AlGaN barrier layer 3 by a known lithography technique (FIG. 3C). Through this opening, the AlGaN barrier layer 3 is removed by etching to a desired depth (FIG. 3D). As an etching method, in the case of dry etching, for example, plasma of a mixed gas of chlorine gas and inert gas (argon, nitrogen) can be used as the etching gas. Further, in the case of wet etching, it is possible to perform etching in a potassium hydroxide (KOH) solution while irradiating light.

なお、上述の製造方法ではレジスト膜8をエッチングマスクとしてAlGaNバリア層3をエッチングする方法を挙げたが、他の製造方法、例えばソース電極4、ゲート電極5およびドレイン電極6の最表層を耐エッチング性を持つ金属(この場合はAu)で構成し、電極をエッチングマスクとして上述の溝7を形成する方法も可能である。   In the above manufacturing method, the AlGaN barrier layer 3 is etched using the resist film 8 as an etching mask. However, other manufacturing methods, for example, the outermost layer of the source electrode 4, the gate electrode 5 and the drain electrode 6 are resistant to etching. It is also possible to form the groove 7 by using a metal having a property (in this case, Au) and using the electrode as an etching mask.

かかる製造方法の適用により、しきい値電圧Vthを負電圧に維持した状態でかつ破壊耐圧が高くて高出力動作が可能な窒化物半導体装置が容易に得られる。 By applying such a manufacturing method, a nitride semiconductor device capable of high output operation with a high breakdown voltage while maintaining the threshold voltage Vth at a negative voltage can be easily obtained.

実施の形態2.
本発明の実施の形態2による窒化物半導体装置、具体的にはAlGaN/GaN HEMTの素子断面図を図4に示す。実施の形態1の窒化物半導体装置では、ソース/ゲート電極4、5間とゲート/ドレイン電極5、6間の双方のAlGaNバリア層3をエッチングして溝7を形成した。しかしながら、破壊耐圧はゲート/ドレイン電極5、6間のAlGaNバリア層3でほぼ決定される。ゲート電極5で生じた空乏層は主にドレイン電極6側に伸長するからである。そこで、図4に示すようにゲート電極5とドレイン電極6間のAlGaNバリア層3のみに溝7を形成しても良い。かかる素子構造は、実施の形態1におけるエッチング工程において、レジスト膜8の開口をゲート/ドレイン電極5、6間の所望の位置に設けるだけで実現できる。
Embodiment 2. FIG.
FIG. 4 shows an element cross-sectional view of the nitride semiconductor device according to the second embodiment of the present invention, specifically, an AlGaN / GaN HEMT. In the nitride semiconductor device of the first embodiment, the trench 7 is formed by etching the AlGaN barrier layer 3 between the source / gate electrodes 4 and 5 and between the gate / drain electrodes 5 and 6. However, the breakdown voltage is almost determined by the AlGaN barrier layer 3 between the gate / drain electrodes 5 and 6. This is because the depletion layer generated at the gate electrode 5 mainly extends to the drain electrode 6 side. Therefore, the groove 7 may be formed only in the AlGaN barrier layer 3 between the gate electrode 5 and the drain electrode 6 as shown in FIG. Such an element structure can be realized only by providing the opening of the resist film 8 at a desired position between the gate / drain electrodes 5 and 6 in the etching process in the first embodiment.

リセス幅、つまりゲート電極5から測定したゲート/ドレイン電極5,6間における溝7の幅と破壊耐圧の関係を図5に示す。エッチング量、すなわちエッチング深さとリセス幅を調整することで破壊耐圧の向上が可能となる。図5によれば、AlGaNバリア層3のエッチングによる溝形成前の層厚25nmに対して、エッチングによって深さ5nmの溝7を形成した場合、リセス幅を500nm以上とすることで、溝形成前の素子の破壊耐圧に対して20V以上の破壊耐圧向上が見込めることが分かる。また、さらにエッチング量を増加すると、リセス幅は少なくても所望の破壊耐圧を実現できることがわかる。なお、上述のリセス幅は、ゲート/ドレイン電極5,6間の距離が2000nmの場合、500nm以上2000nm以下の範囲内が好適である。さらに一般的には、ゲート/ドレイン電極5,6間の距離に対するリセス幅の比率は、25%以上100%以下が好適である。   FIG. 5 shows the relationship between the recess width, that is, the width of the groove 7 between the gate / drain electrodes 5 and 6 measured from the gate electrode 5 and the breakdown voltage. It is possible to improve the breakdown voltage by adjusting the etching amount, that is, the etching depth and the recess width. According to FIG. 5, when the groove 7 having a depth of 5 nm is formed by etching with respect to the layer thickness 25 nm before the groove formation by etching of the AlGaN barrier layer 3, the recess width is set to 500 nm or more before the groove formation. It can be seen that the breakdown voltage can be improved by 20 V or more with respect to the breakdown voltage of the element. It can also be seen that when the etching amount is further increased, a desired breakdown voltage can be realized even if the recess width is small. The recess width is preferably in the range of 500 nm to 2000 nm when the distance between the gate / drain electrodes 5 and 6 is 2000 nm. More generally, the ratio of the recess width to the distance between the gate / drain electrodes 5 and 6 is preferably 25% or more and 100% or less.

さらに、図6に示すようにゲート電極5およびドレイン電極6端部近傍のAlGaNバリア層3に接しないように溝7を形成しても良い。かかる素子構造は、レジスト膜の開口をゲート/ドレイン電極5、6間の所望の位置に設けるだけで実現できる。溝7形成時における各電極の端部の影響による溝深さの不均一性等が緩和されるからである。   Furthermore, as shown in FIG. 6, the groove 7 may be formed so as not to contact the AlGaN barrier layer 3 in the vicinity of the ends of the gate electrode 5 and the drain electrode 6. Such an element structure can be realized simply by providing an opening in the resist film at a desired position between the gate / drain electrodes 5 and 6. This is because non-uniformity of the groove depth due to the influence of the end portions of the respective electrodes when the groove 7 is formed is alleviated.

実施の形態2の窒化物半導体装置によると、ゲート/ドレイン電極間のAlGaNバリア層3のみに溝7を形成するので、しきい値電圧Vthを負電圧に維持した状態でかつ破壊耐圧が高くて高出力動作が可能な窒化物半導体装置を一層容易に製造できる。 According to the nitride semiconductor device of the second embodiment, since trench 7 is formed only in AlGaN barrier layer 3 between the gate / drain electrodes, the breakdown voltage is high while maintaining threshold voltage Vth at a negative voltage. Thus, a nitride semiconductor device capable of high output operation can be manufactured more easily.

(a)は実施の形態1の窒化物半導体装置の素子断面図、(b)は従来の窒化物半導体装置の素子断面図である。(A) is element sectional drawing of the nitride semiconductor device of Embodiment 1, (b) is element sectional drawing of the conventional nitride semiconductor device. (a)はしきい値電圧とゲート電極直下のAlGaNバリア層の層厚の関係を示す図、(b)は破壊耐圧とゲート/ドレイン電極間のAlGaNバリア層の層厚との関係を示す図である。(A) is a figure which shows the relationship between threshold voltage and the layer thickness of the AlGaN barrier layer right under a gate electrode, (b) is a figure which shows the relationship between a breakdown voltage and the layer thickness of the AlGaN barrier layer between gate / drain electrodes. It is. 実施の形態1の窒化物半導体装置の製造方法を示す図である。3 is a diagram showing a method for manufacturing the nitride semiconductor device of the first embodiment. FIG. 実施の形態2の窒化物半導体装置の素子断面図である。FIG. 6 is an element cross-sectional view of the nitride semiconductor device of the second embodiment. 破壊耐圧とリセス幅の関係を示す図である。It is a figure which shows the relationship between a breakdown voltage and a recess width. 実施の形態2の他の窒化物半導体装置の素子断面図である。FIG. 12 is an element cross-sectional view of another nitride semiconductor device in the second embodiment.

符号の説明Explanation of symbols

1 基板、 2 GaNチャネル層、 3 AlGaNバリア層、 4 ソース電極、 5 ゲート電極、 6 ドレイン電極、 7 溝、 8 レジスト膜。
1 substrate, 2 GaN channel layer, 3 AlGaN barrier layer, 4 source electrode, 5 gate electrode, 6 drain electrode, 7 groove, 8 resist film.

Claims (7)

基板と、
前記基板上に形成され窒化物半導体からなるチャネル層と、
前記チャネル層上に形成され前記チャネル層よりバンドギャップエネルギーの大きい窒化物半導体からなるバリア層と、
前記バリア層上に形成されたゲート電極と、
前記バリア層上で前記ゲート電極を介して対向する位置にそれぞれ形成されたソース電極およびドレイン電極と、を備え、
前記ドレイン電極と前記ゲート電極間の前記バリア層の少なくとも一部の領域の層厚が前記ゲート電極直下のバリア層の層厚より薄いことを特徴とする窒化物半導体装置。
A substrate,
A channel layer formed on the substrate and made of a nitride semiconductor;
A barrier layer made of a nitride semiconductor formed on the channel layer and having a larger band gap energy than the channel layer;
A gate electrode formed on the barrier layer;
A source electrode and a drain electrode respectively formed at positions facing each other through the gate electrode on the barrier layer,
The nitride semiconductor device, wherein a thickness of at least a part of the barrier layer between the drain electrode and the gate electrode is thinner than a thickness of the barrier layer immediately below the gate electrode.
前記ソース電極と前記ゲート電極間の前記バリア層の少なくとも一部の領域の層厚が前記ゲート電極直下のバリア層の層厚より薄いことを特徴とする請求項1記載の窒化物半導体装置。 2. The nitride semiconductor device according to claim 1, wherein a layer thickness of at least a part of the barrier layer between the source electrode and the gate electrode is smaller than a layer thickness of the barrier layer immediately below the gate electrode. 前記バリア層の層厚の薄い領域が、エッチングによって形成された溝であることを特徴とする請求項1または2記載の窒化物半導体装置。 3. The nitride semiconductor device according to claim 1, wherein the thin region of the barrier layer is a groove formed by etching. 前記チャネル層が、窒化ガリウム(GaN)からなり、前記バリア層が窒化アルミニウムガリウム(AlGaN)からなることを特徴とする請求項1記載の窒化物半導体装置。 The nitride semiconductor device according to claim 1, wherein the channel layer is made of gallium nitride (GaN), and the barrier layer is made of aluminum gallium nitride (AlGaN). 前記バリア層の薄い部分の層厚が、前記ゲート電極直下における前記バリア層の層厚の20%以上80%以下であることを特徴とする請求項1記載の窒化物半導体装置。 2. The nitride semiconductor device according to claim 1, wherein a thickness of a thin portion of the barrier layer is 20% to 80% of a thickness of the barrier layer immediately below the gate electrode. 前記ゲート電極とドレイン電極との距離に対する前記バリア層の薄い部分の領域の幅の比率が、25%以上であることを特徴とする請求項1記載の窒化物半導体装置。 2. The nitride semiconductor device according to claim 1, wherein a ratio of a width of a thin portion of the barrier layer to a distance between the gate electrode and the drain electrode is 25% or more. 請求項1記載の窒化物半導体装置の製造方法であって、
基板上に、チャネル層およびバリア層をエピタキシャル結晶成長する工程と、
前記バリア層上にゲート電極、ソース電極およびドレイン電極をそれぞれ形成する工程と、
前記ゲート電極を含むバリア層上に金属膜もしくはレジスト膜を成膜する工程と、
リソグラフィ技術によって前記バリア層を薄層化する部分に該当する領域上の前記金属膜もしくはレジスト膜に開口を設ける工程と、
前記開口から前記バリア層を所定の層厚までエッチング除去する工程と、
前記金属膜もしくはレジスト膜を除去する工程と、
を含んでなる窒化物半導体装置の製造方法。
A method for manufacturing a nitride semiconductor device according to claim 1,
Epitaxially growing a channel layer and a barrier layer on a substrate;
Forming a gate electrode, a source electrode and a drain electrode on the barrier layer,
Forming a metal film or a resist film on the barrier layer including the gate electrode;
A step of providing an opening in the metal film or resist film on a region corresponding to a portion where the barrier layer is thinned by a lithography technique;
Etching away the barrier layer from the opening to a predetermined layer thickness;
Removing the metal film or resist film;
A method for manufacturing a nitride semiconductor device comprising:
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