JP2005191534A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To stably obtain a desired capacitor capacity in a capacitor having a lower electrode having a concave cross section.
A semiconductor device includes an interlayer insulating film having a recess, a protective insulating film having an opening formed on the interlayer insulating film and exposing the recess, a bottom surface of the recess, and A lower electrode 11 having a concave cross section formed on a side surface, a capacitor insulating film 12 formed on the lower electrode 11, and an upper electrode 13 formed on the capacitor insulating film 12 are provided. The opening diameter of the recess 10 of the interlayer insulating film 9 is larger than the opening diameter of the opening 15 a of the protective insulating film 15, and the end of the protective insulating film 15 on the opening 15 a side is the side surface of the recess 10 of the interlayer insulating film 9. It is formed in a bowl shape protruding inward.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a semiconductor device such as a dynamic random access memory (DRAM) device having a stacked capacitor structure in which memory cell capacitors are stacked above a transistor, and the manufacturing thereof. Regarding the method.

  In recent years, in DRAM devices, attempts have been made to increase the storage capacity by increasing the storage capacity of the memory cell per unit occupied area, thereby reducing the occupied area of the memory cell and reducing the chip size of the DRAM. It is.

  As a stacked capacitor structure in a conventional DRAM device, a capacitor electrode structure has been proposed in which a groove is provided in an interlayer insulating film formed on a MIS transistor, and a lower electrode having a concave cross section is formed in the groove (for example, Patent Documents). 1).

  FIG. 5 shows a cross-sectional structure of a conventional semiconductor device having a stacked capacitor structure. As shown in FIG. 5, the conventional semiconductor device includes a plurality of MIS transistors 100 that are switch transistors respectively formed in active regions partitioned by a shallow trench isolation 102 on the main surface of a semiconductor substrate 101, and the MIS transistors 100. And a capacitor 122 formed with a first interlayer insulating film 107 interposed therebetween.

  Each MIS transistor 100 includes a gate insulating film 103 formed on an active region of a semiconductor substrate 101, a gate electrode 104 thereon, an insulating sidewall 105 formed on a side surface of the gate electrode 104, and an upper portion of the active region. The source region 106A and the drain region 106B are formed.

  The capacitor 122 is formed by sequentially laminating the groove 110 of the second interlayer insulating film 109 formed on the first interlayer insulating film 107 covering each MIS transistor 100, and the lower electrode 111 having a concave cross section. The capacitor insulating film 112 and the upper electrode 113 are included. The lower electrode 111 is electrically connected to the source region 106A of the MIS transistor 100 by a first plug 108A formed in the first interlayer insulating film 107.

  A third interlayer insulating film 114 is formed on the second interlayer insulating film 109 so as to cover the capacitor 122, and a bit wiring 119 is formed on the third interlayer insulating film 114. The bit wiring 119 includes a second plug 108B formed in the first interlayer insulating film 107, and a third plug 118 formed in the third interlayer insulating film 114 and the second interlayer insulating film 109. The drain region 106B of the MIS transistor 100 is electrically connected.

  Next, a method for manufacturing a semiconductor device having a conventional stacked capacitor structure is shown in FIGS. Here, only a method for manufacturing the capacitor 122 is shown.

  First, in the step shown in FIG. 6A, a source region 106A of a MIS transistor (not shown) is formed in the active region of the semiconductor substrate 101 by ion implantation, and then a first interlayer insulating film 107 covering the MIS transistor is formed. Form. Subsequently, a contact hole exposing the source region 106A is formed in the first interlayer insulating film 107, and a conductive film is buried in the formed contact hole to form a first plug 108A. Thereafter, a second interlayer insulating film 109 is formed on the first plug 108A and the first interlayer insulating film 107, and then the first plug 108A is formed in the capacitor formation region of the second interlayer insulating film 109. An exposed groove 110 is formed.

  Next, in the step shown in FIG. 6B, a polysilicon film 111A doped with impurities is formed on the second interlayer insulating film 109 including the trench 110. Thereafter, a resist film 120 is applied over the entire surface including the groove portion 110 on the second interlayer insulating film 109, and then the applied resist film 120 is etched back by anisotropic dry etching to form a capacitor region. The resist film 120 is left only inside the groove 110.

  Next, in the step shown in FIG. 6C, using the resist film 120 as a mask, the portion of the polysilicon film 111A over the second interlayer insulating film 109 is removed by anisotropic dry etching. As a result, a lower electrode 111 having a concave cross section is formed inside the groove 110 of the second interlayer insulating film 109.

  Next, in the step shown in FIG. 6D, after removing the resist film 120, a capacitor insulating film 112 and an upper electrode conductive film are formed on the second interlayer insulating film 109 and the lower electrode 111. . Thereafter, the capacitor insulating film and the upper electrode conductive film are patterned to form the capacitor insulating film 112 and the upper electrode 113. Thus, a capacitor 122 composed of the lower electrode 111, the capacitor insulating film 112, and the upper electrode 113 is formed.

Thus, according to the conventional method for manufacturing the capacitor 122, the lower electrode 111 has a concave cross section, so that the surface area at the side portion is increased and the storage capacity per unit occupied area can be increased.
JP-A-10-79478

  However, the conventional method for manufacturing a capacitor, that is, a semiconductor device has the following problems. In the conventional manufacturing method, as shown in FIG. 6C, the portion of the polysilicon film 111A located on the second interlayer insulating film 109 is removed by anisotropic dry etching using the resist film 120 as a mask. Thus, the lower electrode 111 having a concave cross section is formed inside the groove 110. At this time, it is necessary to perform over-etching so that the polysilicon film 111 A does not remain on the second interlayer insulating film 109. By this over-etching, the upper end of the side portion of the lower electrode 111 is removed, and an unexpected recess 123 is formed. As a result, the height of the upper end portion of the lower electrode 111 having a concave cross section is reduced, and the surface area of the lower electrode 111 is reduced. For example, when the thickness of the polysilicon film 111A is 50 nm, the depth of the recess 123 is about 150 nm. Further, when the roughened polysilicon is formed to increase the surface area of the lower electrode 111, the roughened polysilicon is less likely to be etched than the doped polysilicon constituting the lower electrode 111. The recess 123 is formed deeper. In addition, the depth of the recess 123 generated by overetching the polysilicon film 111A is not necessarily uniform in the plane of the semiconductor substrate 101. Therefore, the surface area of the plurality of lower electrodes 111 formed on the semiconductor substrate 101 is not limited. As a result, the desired capacitor capacity cannot be stably obtained.

  An object of the present invention is to make it possible to stably obtain a desired capacitor capacity in a capacitor having a lower electrode having a concave cross section.

  In order to achieve the above object, the present invention provides a semiconductor device in which a protective insulating film is formed on an insulating film forming a lower electrode having a concave cross section, and a bowl-like shape is formed around the concave portion of the insulating film in the formed protective insulating film. It is set as the structure which provides the opening part which protrudes in this.

  Specifically, a semiconductor device according to the present invention includes a first insulating film having a recess, a second insulating film formed on the first insulating film and having an opening exposing the recess, and the recess A concave portion of the first insulating film, comprising: a lower electrode having a concave section formed on the bottom surface and the side surface; a capacitor insulating film formed on the lower electrode; and an upper electrode formed on the capacitor insulating film. The opening diameter of the second insulating film is larger than the opening diameter of the opening portion of the second insulating film, and the end portion on the opening portion side of the second insulating film is formed in a bowl shape protruding inward from the side surface of the concave portion of the first insulating film. It is characterized by being.

  According to the semiconductor device of the present invention, the opening diameter of the concave portion of the first insulating film is larger than the opening diameter of the opening portion of the second insulating film, which is the protective insulating film, and on the opening side of the second insulating film. Since the end portion is formed in a bowl shape protruding inward from the side surface of the concave portion of the first insulating film, the side portion of the lower electrode having a concave cross section formed on the bottom surface and the side surface of the concave portion is the second insulating film. It will be located below the bowl-shaped part. Therefore, even if the lower electrode forming film is overetched when the lower electrode is formed, the upper end of the side of the lower electrode having a concave cross section is not etched, so the surface area of the lower electrode is a predetermined value. It becomes. In addition, since the surface area of the lower electrode does not vary on the semiconductor substrate, a desired capacitor capacity can be stably obtained.

  In the semiconductor device of the present invention, it is preferable that the protruding width of the hook-shaped portion in the second insulating film is equal to or larger than the film thickness of the lower electrode.

  In the semiconductor device of the present invention, the thickness of the second insulating film is preferably smaller than the thickness of the first insulating film.

  In the semiconductor device of the present invention, it is preferable that the first insulating film is a BPSG film and the second insulating film is a silicon oxide film or a silicon nitride film containing no impurities. In this way, when wet etching is used to form the ridge-shaped portion around the opening of the second insulating film, the etching rate of the silicon oxide film or silicon nitride film not containing impurities is set to be boron and phosphorus. Since the etching rate is lower (slower) than the etching rate of the added BPSG film, it is possible to reliably form the hook-shaped portion in the second insulating film.

  In the semiconductor device of the present invention, the lower electrode is preferably made of a doped polysilicon film, and roughened polysilicon is preferably formed on the surface of the lower electrode. In this case, since the surface area of the lower electrode is increased by the roughened polysilicon, the capacitance of the capacitor can be increased.

  In the semiconductor device of the present invention, it is preferable that the upper portion of the side surface of the concave portion of the first insulating film in the roughened polysilicon is located inside the flange-shaped portion of the second insulating film. In this way, the recess during over-etching does not occur even with the roughened polysilicon formed on the surface of the lower electrode.

  The method for manufacturing a semiconductor device according to the present invention includes a step (a) of forming a first insulating film on a semiconductor substrate and a step (b) of forming a second insulating film on the first insulating film. And (c) forming an opening in the second insulating film and forming a recess through the opening in the first insulating film, and opening the second insulating film as a mask after the step (c). Etching is performed on the concave portion of the first insulating film exposed from the portion so that the opening diameter of the concave portion is larger than the opening diameter of the opening portion of the second insulating film, thereby opening the second insulating film. A step (d) in which a side end protrudes inward from the side surface of the concave portion of the first insulating film, and a bottom surface and a side surface of the concave portion are included on the second insulating film after the step (d). Step (e) for forming the conductive film for the lower electrode, and a recess formed with the conductive film for the lower electrode after the step (e). And filling the resist with a resist (f) and etching the upper part of the second electrode conductive film on the second electrode conductive film using the resist as a mask, thereby forming a recess-shaped lower electrode made of the lower electrode conductive film in the recess. A step (g) of forming, a step (h) of forming a capacitive insulating film on the lower electrode, and a step (i) of forming an upper electrode on the capacitive insulating film.

  According to the method for manufacturing a semiconductor device of the present invention, an opening is formed in the second insulating film and a recess is formed through the opening in the first insulating film, and then exposed from the opening using the second insulating film as a mask. Etching the recess of the first insulating film to make the opening diameter of the recess larger than the opening diameter of the opening of the second insulating film, so that the end of the second insulating film on the opening side It is assumed that the portion protrudes inward from the side surface of the concave portion of the first insulating film. Thus, in order to form the hook-shaped portion in the opening of the second insulating film formed on the first insulating film, in the subsequent step (g), the conductive for the lower electrode when the lower electrode is formed. Even when overetching the film, the upper end of the side of the lower electrode having a concave cross section is not etched, so that the surface area of the lower electrode has a predetermined value. In addition, since the surface area of the lower electrode does not vary on the semiconductor substrate, a desired capacitor capacity can be stably obtained.

  In the method for manufacturing a semiconductor device of the present invention, the etching rate of the second insulating film is preferably smaller (slower) than the etching rate of the first insulating film.

  In the method for manufacturing a semiconductor device of the present invention, in the step (d), the protruding width of the hook-like portion of the second insulating film is formed to be equal to or larger than the film thickness of the lower electrode conductive film. It is preferable to do.

  In the method for manufacturing a semiconductor device of the present invention, it is preferable that the first insulating film is a BPSG film, and the second insulating film is a silicon oxide film or a silicon nitride film not containing impurities.

  In the semiconductor device manufacturing method of the present invention, the lower electrode conductive film is a doped polysilicon film, and the semiconductor device manufacturing method of the present invention is performed after the step (e) and before the step (f). Preferably, the method further includes a step of forming roughened polysilicon on the surface of the doped polysilicon film.

  In the method of manufacturing a semiconductor device according to the present invention, in the step (d), the upper side surface portion of the concave portion of the first insulating film in the roughened polysilicon is positioned inside the hook-shaped portion of the second insulating film. It is preferable to form a recess in the first insulating film.

  According to the semiconductor device and the manufacturing method thereof according to the present invention, the upper end portion of the side portion of the lower electrode having a concave cross section is not etched even in the over-etching of the lower electrode formation film when forming the lower electrode. The surface area of the lower electrode is a predetermined value. In addition, since the surface area of the lower electrode does not vary on the semiconductor substrate, a desired capacitor capacity can be stably obtained.

  An embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 shows a cross-sectional configuration of a semiconductor device according to an embodiment of the present invention. As shown in FIG. 1, the semiconductor device according to this embodiment is formed in a shallow trench isolation 2 selectively formed on the main surface of a semiconductor substrate 1 and an active region partitioned by the shallow trench isolation 2. A plurality of MIS transistors 20 as switch transistors, and a capacitor 30 formed above the MIS transistor 20 with a first interlayer insulating film 7 interposed therebetween.

  Each MIS transistor 20 includes a gate insulating film 3 formed on the active region of the semiconductor substrate 1, a gate electrode 4 formed on the gate insulating film 3, and insulating properties formed on both side surfaces of the gate electrode 4. The sidewall 5 and the source region 6A and the drain region 6B made of an impurity diffusion layer formed by ion implantation above the active region are formed.

  The capacitor 30 is formed on the bottom surface and the side surface of the recess 10 of the second interlayer insulating film 9 formed on the first interlayer insulating film 7 covering each MIS transistor 20, and has a concave cross section, for example, a bottomed cylindrical shape. The lower electrode 11, the capacitor insulating film 12 and the upper electrode 13 sequentially formed on the lower electrode 11. On the inner surface of the lower electrode 11, roughened polysilicon 16 made of hemispherical grains (HSG) grains is formed to further increase the surface area of the lower electrode 11. The lower electrode 11 is electrically connected to the source region 6A of the MIS transistor 20 through a first plug 8A formed in the first interlayer insulating film 7.

Here, doped polysilicon doped with phosphorus (P) or arsenic (As) is used for the lower electrode 11 and the upper electrode 13, and a silicon nitride film is sandwiched between silicon oxide films for the capacitor insulating film 12. A so-called ONO film is used. However, the configurations of the lower electrode 11, the upper electrode 13, and the capacitor insulating film 12 are not limited to these. That is, tantalum oxide (Ta ₂ O ₅ ), which is a high dielectric, may be used for the capacitor insulating film 12, and titanium nitride (TiN) can be used for the upper electrode 13 in this case. Furthermore, when a metal oxide such as tantalum oxide (Ta ₂ O ₅ ), aluminum oxide (Al ₂ O ₃ ), or hafnium oxide (HfO ₂ ) is used for the capacitor insulating film 12, the lower electrode 11 and the upper electrode 13 are used. Titanium nitride may be used for each of these. Note that a metal oxide containing at least two of tantalum, aluminum, and hafnium can be used for the capacitor insulating film 12.

  As a feature of the present embodiment, a protective insulating film 15 having an opening 15 a that exposes the recess 10 of the second interlayer insulating film 9 between the second interlayer insulating film 9 and the third interlayer insulating film 14. Is formed. The end of the protective insulating film 15 on the opening 15 a side is formed in a bowl shape protruding inward from the side surface of the recess 10 of the second interlayer insulating film 9.

  A third interlayer insulating film 14 is formed on the protective insulating film 15 so as to cover the capacitor 30, and a bit wiring 19 is formed on the third interlayer insulating film 14. The bit wiring 19 includes a second plug 8B that penetrates the first interlayer insulating film 7, and a third plug 118 that penetrates the third interlayer insulating film 14, the protective insulating film 15, and the second interlayer insulating film 9. Are electrically connected to the drain region 6B of the MIS transistor 20.

  According to the present embodiment, the end on the opening 15a side of the protective insulating film 15 formed on the second interlayer insulating film 9 protrudes in a bowl shape inside the concave portion 10, so that the side surface of the concave portion 10 is The lower electrode 11 formed thereon is prevented from being etched by overetching when the lower electrode 11 is formed. As a result, the height of the upper end of the side portion of the lower electrode 11 having a concave cross section does not change depending on the over-etching processing time, so that both the reduction and variation in the surface area of the lower electrode 11 can be prevented. The capacity can be obtained stably.

  Hereinafter, a method of manufacturing the semiconductor device configured as described above will be described with reference to the drawings.

  2 (a) to 2 (c), 3 (a) to 3 (c), 4 (a), and 4 (b) illustrate a method of manufacturing a semiconductor device according to an embodiment of the present invention. The cross-sectional structure in the order of processes is shown.

  First, in the step shown in FIG. 2A, for example, a shallow trench isolation 2 made of silicon oxide is formed on an upper portion of a semiconductor substrate 1 made of P-type silicon, and then the semiconductor substrate 1 surrounded by the shallow trench isolation 2 is formed. A gate insulating film 3 made of silicon oxide and a gate electrode 4 made of polysilicon doped with phosphorus (P) are sequentially formed on the active region made of. Thereafter, insulating sidewalls 5 are formed on both side surfaces of the gate electrode 4, and then the N-type source region 6A and the N-type source regions 6A and N-type drain region 6B is formed. Thereby, the MIS transistor 20 which is a switch transistor of the memory cell is formed. Subsequently, a first interlayer insulating film 7 is formed on the semiconductor substrate 1 so as to cover each MIS transistor 20, and the upper surface thereof is planarized. Thereafter, contact holes for exposing the source region 6A and the drain region 6B of the MIS transistor 20 are formed in the first interlayer insulating film 7. Subsequently, a conductive material made of N-type polysilicon is embedded in each contact hole, and a first plug 8A connected to the source region 6A and a second plug 8B connected to the drain region 6B are formed. Form. Subsequently, a second interlayer insulating film made of BPSG (Boro-Phospho-Silicate Glass) and having a thickness of about 600 nm is formed on the first interlayer insulating film 7 by, for example, chemical vapor deposition (CVD). 9 and, for example, by high-density plasma deposition method, it is made of silicon oxide (HDP-NSG: High-Density-Plasma Non-Silicate Glass) that does not contain impurities. A protective insulating film 15 having a low etching rate is sequentially formed. Here, the protective insulating film 15 is not limited to HDP-NSG, and an insulating film having a lower etching rate by wet etching than the material forming the second interlayer insulating film 9, for example, an insulating film such as silicon nitride may be used. Good.

  Next, in the step shown in FIG. 2B, the upper portion of the source region 6A of the MIS transistor in the second interlayer insulating film 9 and the protective insulating film 15 is anisotropically dried with an etching gas mainly composed of fluorocarbon. Etching is performed. As a result, openings 9a and 15a are formed through the second interlayer insulating film 9 and the protective insulating film 15 to expose the first plug 8A.

  Next, in the step shown in FIG. 2C, for example, by wet etching using a hydrofluoric acid-based solution or the like on the second interlayer insulating film 9 exposed from the opening 19a using the protective insulating film 15 as a mask. By performing isotropic etching, the side surface of the opening 9a in the second interlayer insulating film 9 is set back by a predetermined distance, for example, 75 nm from the end of the opening 15a of the protective insulating film 15. As a result, the recess 10 having an opening width larger than the opening width of the opening 15 a of the protective insulating film 15 is formed in the second interlayer insulating film 9. As a result, the end of the opening 15a of the protective insulating film 15 protrudes in a bowl shape from the side surface of the recess 10 of the second interlayer insulating film 9. By this wet etching, the natural oxide film formed on the surface of the first plug 8A exposed from the recess 10 can be removed at the same time.

  The amount of recess 10 recessed in the second interlayer insulating film 9, that is, the protruding width of the hook-shaped portion protruding to the opening 15a side of the protective insulating film 15, is the film thickness of the lower electrode conductive film formed in a later step. It is desirable to set equal or higher.

In the present embodiment, wet etching is used for etching to form the ridge-shaped portion in the protective insulating film 15, but it can also be formed by dry etching. For example, a mixed gas of carbon tetrafluoride (CF ₄ ) and oxygen (oxygen O ₂ ) can be used as the etching gas.

  Next, in the step shown in FIG. 3A, doped polycrystal doped with, for example, phosphorus over the entire surface including the concave portion 10 of the second interlayer insulating film 9 on the protective insulating film 15 by low pressure CVD. A lower electrode conductive film 11A made of silicon and having a thickness of about 25 nm is formed. At this time, the lower electrode conductive film 11A is formed by the low pressure CVD method, so that the lower portion of the protective insulating film 15 and the side surface of the recess 10 in the second interlayer insulating film 9 are also well covered. An electrode conductive film 11A can be formed. Thereafter, an amorphous silicon film having a film thickness of about 25 nm is deposited on the lower electrode conductive film 11A by a low pressure CVD method. Subsequently, the deposited amorphous silicon film is subjected to a heat treatment to form an HSG of the amorphous silicon film. By performing the roughening (roughening) treatment, a large number of HSG grains (roughened polysilicon) 16 are formed on the lower electrode conductive film 11A. At this time, in order to prevent depletion of the lower electrode conductive film 11A, the amorphous silicon film may be doped with phosphorus or the like when the amorphous silicon film is formed.

  Next, in the step shown in FIG. 3B, a resist film 40 is applied on the HSG grains 16 including the recesses 10 and then etched back by anisotropic dry etching mainly containing oxygen gas. Thus, the resist film 40 is left only in the recess 10 of the second interlayer insulating film 9.

Next, in the step shown in FIG. 3C, the portion of the HSG grains 16 and the lower electrode conductive film 11A on the second interlayer insulating film 9 is made chlorine by using the resist film 40 remaining in the recess 10 as a mask. An etching gas composed of (Cl ₂ ) or hydrogen bromide (HBr), or a halogen-based gas containing at least one of Cl ₂ and HBr and having oxygen (O ₂ ) added thereto, such as Cl ₂ / O ₂ , Cl _It is removed by anisotropic dry etching using an etching gas composed of ₂ / HBr / O ₂ or HBr / O ₂ . As a result, the lower electrode 11 having a concave cross section having the HSG grains 16 is formed on the bottom and side surfaces of the recess 10 of the second interlayer insulating film 9. At this time, as a feature of the present embodiment, even if overetching is performed on the lower electrode conductive film 11A, the recess amount 22 of the lower electrode 11 can be set to a constant value. This is because the entrance of etching ions is prevented by at least the lower electrode conductive film 11 </ b> A formed on the lower side of the upper portion by the hook-shaped portion at the end of the opening 15 a of the protective insulating film 15. is there. Accordingly, in the lower electrode 11, a recess amount 22 corresponding to the film thickness of the protective insulating film 15 is generated from the upper surface of the protective insulating film 15, but a recess amount from the upper surface of the second interlayer insulating film 9 is hardly generated.

  In the present embodiment, the side portion of the HSG grain (roughened polysilicon) 16 is not included inside the bowl-shaped portion of the protective insulating film 15, but the concave portion 10 of the second interlayer insulating film 9. The opening width of the HSG grains 16 is increased so that the side portions of the HSG grains 16 are covered with the bowl-shaped portions of the protective insulating film 15, so that the HSG grains 16 also enter the inside of the bowl-shaped portions of the protective insulating film 15. Is preferred.

  Next, in the step shown in FIG. 4A, after removing the resist film 40, a capacitor made of, for example, an ONO film is formed on the entire surface including the lower electrode 11 and the HSG grains 16 on the protective insulating film 15 by the CVD method. An upper electrode conductive film made of doped polysilicon and phosphorus-doped doped polysilicon is deposited. After that, the capacitor insulating film 12 and the upper electrode 13 are formed by patterning the deposited capacitor insulating film and the upper electrode conductive film into a predetermined shape so as to remain in the recess 10 and the vicinity thereof by lithography and etching. . As a result, the capacitor 30 including the lower electrode 11 having the HSG grains 16 in the groove 10 of the second interlayer insulating film 9, the capacitive insulating film 16, and the upper electrode 13 is formed.

  Next, in the step shown in FIG. 4B, the third interlayer insulating film 14 is deposited on the protective insulating film 15 including the capacitor 30, and then the surface of the deposited third interlayer insulating film 14 is flattened. Turn into. Subsequently, a third plug 18 that penetrates the third interlayer insulating film 14, the protective insulating film 15, and the second interlayer insulating film 9 and is connected to the second plug 8 B on the drain region 6 B of the MIS transistor 20. Form. Thereafter, a bit wiring 19 made of a metal wiring connected to the third plug 18 is selectively formed on the third interlayer insulating film 14.

  Thus, according to the method for manufacturing the semiconductor device according to the present embodiment, as shown in FIG. 3C, the second interlayer insulating film 9 having the recess 10 for forming the lower electrode 11 having a concave cross section is formed. Since a protective insulating film 15 having an opening 15a covering the upper portion of the concave portion 10 in a bowl shape is provided on the side surface of the concave portion 10 of the second interlayer insulating film 9 by the hook-like portion of the protective insulating film 15 It is possible to prevent the lower electrode 11 formed in step 1 from being etched by overetching when the lower electrode 11 is formed. Thereby, since the height of the upper end portion of the side portion of the lower electrode 11 having a concave cross section does not change depending on the etching time of over-etching, the surface area of the lower electrode 11 is not reduced and variation in the surface area is also suppressed. A desired capacitor capacity can be obtained stably.

  In the present embodiment, the HSG grains (roughened polysilicon) 16 are formed on the surface of the lower electrode 11, but the HSG grains 16 are not necessarily formed.

  In the present embodiment, the lower electrode 11 of the capacitor 30 is connected via the first plug 8A penetrating the first interlayer insulating film 7 covering the MIS transistor 20, but the first interlayer insulating film 7 is The lower electrode 11 may be formed so as to be directly connected to the source region 6A without being provided.

  According to the semiconductor device and the manufacturing method thereof according to the present invention, a predetermined value can be obtained for the surface area of the lower electrode having a concave cross section, and the surface area does not vary, so that a desired capacitor capacity can be stably obtained. The effect is obtained, and it is useful for a DRAM device having a stacked capacitor structure.

1 is a structural cross-sectional view showing a main part of a semiconductor device according to an embodiment of the present invention. (A)-(c) is the structure sectional drawing of the order of a process which shows the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention. (A)-(c) is the structure sectional drawing of the order of a process which shows the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention. (A) And (b) is the structure sectional drawing of the order of a process which shows the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention. It is a structure sectional view showing the important section of the conventional semiconductor device. (A)-(d) is the structure sectional drawing of the order of a process which shows the manufacturing method of the conventional semiconductor device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Element isolation isolation 3 Gate insulating film 4 Gate electrode 5 Insulating sidewall 6A Source region 6B Drain region 7 1st interlayer insulating film 8A 1st plug 8B 2nd plug 9 2nd interlayer insulating film 9a Opening 10 Recess 11 Lower electrode 11A Lower electrode conductive film 12 Capacitor insulating film 13 Upper electrode 14 Third interlayer insulating film 15 Protective insulating film 15a Opening 16 HSG grains (roughened polysilicon)
18 Third plug 19 Bit wiring 20 MIS transistor 22 Recess amount 30 Capacitor 40 Resist film

Claims (12)

A first insulating film having a recess;
A second insulating film formed on the first insulating film and having an opening exposing the recess;
A lower electrode having a concave cross section formed on the bottom and side surfaces of the recess;
A capacitive insulating film formed on the lower electrode;
An upper electrode formed on the capacitive insulating film,
The opening diameter of the recess of the first insulating film is larger than the opening diameter of the opening of the second insulating film, and the end of the second insulating film on the opening side is the first insulating film A semiconductor device characterized by being formed in a bowl shape protruding inward from the side surface of the recess. The semiconductor device according to claim 1,
The protrusion width of the hook-shaped portion in the second insulating film is equal to or larger than the film thickness of the lower electrode. The semiconductor device according to claim 1 or 2,
The semiconductor device is characterized in that the thickness of the second insulating film is smaller than the thickness of the first insulating film. The semiconductor device according to any one of claims 1 to 3,
The semiconductor device according to claim 1, wherein the first insulating film is a BPSG film, and the second insulating film is a silicon oxide film or a silicon nitride film containing no impurities. The semiconductor device of any one of Claims 1-4 WHEREIN:
The lower electrode is made of a doped polysilicon film, and roughened polysilicon is formed on the surface of the lower electrode. The semiconductor device according to claim 5,
The semiconductor device according to claim 1, wherein an upper portion of the side surface of the concave portion of the first insulating film in the roughened polysilicon is located inside a flange-shaped portion of the second insulating film. Forming a first insulating film on the semiconductor substrate (a);
Forming a second insulating film on the first insulating film (b);
Forming an opening in the second insulating film, and forming a recess through the opening in the first insulating film (c);
After the step (c), the concave portion of the first insulating film exposed from the opening is etched using the second insulating film as a mask so that the opening diameter of the concave portion is the second insulating film. A step (d) in which the end of the second insulating film on the opening side is protruded inward from the side surface of the concave portion of the first insulating film by making it larger than the opening diameter of the opening of the film When,
After the step (d), a step (e) of forming a lower electrode conductive film on the second insulating film so as to include a bottom surface and a side surface of the recess;
After the step (e), a step (f) of filling a resist in the concave portion in which the conductive film for the lower electrode is formed;
Etching the upper portion of the conductive film for the lower electrode with the resist as a mask to form a lower electrode having a concave cross section made of the conductive film for the lower electrode in the concave portion (g) When,
Forming a capacitive insulating film on the lower electrode (h);
And a step (i) of forming an upper electrode on the capacitive insulating film. In the manufacturing method of the semiconductor device according to claim 7,
A method of manufacturing a semiconductor device, wherein an etching rate of the second insulating film is smaller than an etching rate of the first insulating film. In the manufacturing method of the semiconductor device according to claim 7 or 8,
In the step (d), the protruding width of the flange-shaped portion of the second insulating film is formed to be equal to or greater than the film thickness of the lower electrode conductive film. Device manufacturing method. In the manufacturing method of the semiconductor device of any one of Claims 7-9,
The method of manufacturing a semiconductor device, wherein the first insulating film is a BPSG film, and the second insulating film is a silicon oxide film or a silicon nitride film containing no impurities. In the manufacturing method of the semiconductor device of any one of Claims 7-10,
The lower electrode conductive film is a doped polysilicon film,
A step of forming a roughened polysilicon on the surface of the doped polysilicon film after the step (e) and before the step (f) is further provided. Production method. In the manufacturing method of the semiconductor device according to claim 11,
In the step (d), the first insulating layer is formed so that the upper side surface portion of the concave portion of the first insulating film in the roughened polysilicon is located inside the bowl-shaped portion of the second insulating film. A method of manufacturing a semiconductor device, comprising forming a concave portion of a film.

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