JP2005175572A - Despread demodulator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform despread demodulation using a spread code generation circuit which does not require external parts and does not require synchronization control.
A first spreading code generating circuit for generating spreading codes, a second spreading code generating circuit for generating spreading codes rearranged in the reverse direction, and an abbreviation corresponding to a newer or older one of the spreading signals. A polarity conversion circuit 101 that converts half of the spread codes to be inverted and non-inverted during one cycle of the clock f2, and a hold circuit 108 that holds the adder output when approximately half of the spread codes are reversed; A second peak detector 109 that detects the peak by calculating the sum of absolute values of the output of the adder and the output of the hold circuit when approximately half of the spreading codes are non-inverted; A spreading code control circuit that alternately switches a spreading code input from the spreading code generation circuit to the polarity conversion circuit and a spreading code input from the second spreading code generation circuit to the polarity conversion circuit;
[Selection] Figure 1

Description

  The present invention receives a spread signal transmitted by frequency spreading a desired signal by an operation using a spread code, and despreads the received spread signal by an operation using a spread code to extract the desired signal. The present invention relates to a despreading demodulator in wireless communication.

  FIG. 24 shows the configuration of a despreading demodulator as the first prior art. In this configuration, the received spread signal is multiplied by the spread code generated by the spread code generation circuit 1002 in the multiplier 1001 and passed through a low-pass filter (LPF) 1003 to remove harmonic components, and the received signal (baseband) Signal). Reference numeral 1004 denotes a synchronization control circuit for matching the phases of the spread code and the spread signal.

  FIG. 25 shows the configuration of a despreading demodulator according to the second prior art. FIG. 26 shows the characteristics of the signal at point A on the input side and point B on the output side of the peak detector 1114 in the despreading demodulator of FIG. Shows a typical waveform. In this configuration, the received spread signal is converted into a correlation signal by the matched filter 1111 corresponding to the spread code, delayed by the reciprocal of the data clock by the delay line 1112, and the delayed signal and the correlation signal are multiplied by the multiplier 1113. The received signal is obtained by multiplying and then performing peak detection with the peak detector 1114.

The despreading demodulator having the synchronization control circuit of FIG. 24 and the despreading demodulator having the matched filter of FIG. 25 are described in Non-Patent Document 1, for example. The applicant has not yet found prior art documents related to the present invention by the time of filing other than the prior art documents specified by the prior art document information described in this specification.
Marubayashi Gen, Nakagawa Masao, Kawano Ryuji, "Spread Spectrum Communication and its Applications", IEICE, 1998, 94-145, ISBN 4-88562-163-X

  In the despreading demodulator which is the first prior art shown in FIG. 24, it is necessary to match the phase of the spreading code and the spread signal with high accuracy. For this reason, there has been a problem that the configuration of the synchronization control circuit 1004 becomes complicated, and the circuit scale and power consumption increase.

  In the despreading demodulator that is the second prior art shown in FIG. 25, a normal SAW (Surface Acoustic Wave) filter is used as the matched filter 1111. For this reason, there was a problem that the mounting area and the mounting cost increased. In addition, since a matched filter 1111 specialized for a specific spreading code is used, there is a problem that a spreading signal with a different spreading code cannot be demodulated. In addition, when the matched filter 1111 is configured by an on-chip circuit, there is a problem that an area size and power consumption increase.

  The present invention has been made in view of the above points, and an object of the present invention is to provide a low-power despreading demodulator that eliminates the need for external components and does not require synchronization control, thereby enabling portable wireless communication. This contributes to low power and low cost.

The despreading demodulator according to the present invention includes N (N is an integer of 2 or more) sample-and-hold circuits that sample and hold a received spread signal, and a first clock having the same frequency as the clock used for spreading the spread signal. And a sample hold control circuit for controlling the N sample hold circuits to sequentially perform a sample hold operation in synchronization with the first clock, and the N first hold circuits in synchronization with the second clock. A first spreading code generating circuit for generating a spreading code, and a second spreading code for generating N second spreading codes in which the first spreading codes are rearranged in the reverse direction in synchronization with the second clock. Of the N spreading codes output from the spreading code generating circuit and the first spreading code generating circuit or the second spreading code generating circuit, the spreading signal having the newest received order or the spreading signal having the oldest spreading code is received. Signal Polarity is converted and output so that approximately half corresponding to the deviation exhibits two polarity states of inversion and non-inversion during one cycle of the second clock, and the remaining approximately half of the sign is output as it is. A conversion circuit, N multipliers for multiplying the signal output from the sample hold circuit and the spreading code output from the polarity conversion circuit for each corresponding signal, and adding the outputs of the N multipliers A first peak detector that detects a peak of the output of the adder and demodulates a received signal based on the detected peak, and the approximately half of the spreading codes are in an inverted state or a non-inverted state A hold circuit that holds the output of the adder when in either one of the first states, and a second state in which the substantially half of the spreading codes are different from the first state in an inverted state or a non-inverted state When A second peak detector for calculating a sum of absolute values of the output of the adder and the output of the hold circuit and detecting a peak of the sum of absolute values, and a peak detected by the second peak detector. Each time, the input of the first spreading code from the first spreading code generation circuit to the polarity conversion circuit and the input of the second spreading code from the second spreading code generation circuit to the polarity conversion circuit. And a spreading code control circuit for alternately switching between and.
The first spreading code generation circuit includes N first flip-flop circuit groups for shifting the first spreading code in synchronization with the second clock, and among the first flip-flop circuit groups. A first exclusive OR circuit for inputting outputs of the plurality of flip-flop circuits, and a flip-flop circuit of the first flip-flop circuit group connected in a cascaded manner, and the first exclusive OR circuit Of the first flip-flop circuit group to the input of the first flip-flop circuit of the first flip-flop circuit group so as to be openable and closable. N second flip-flop circuit groups for shifting the second spreading code in the opposite direction to the first spreading code in synchronization with the first clock, and the second flip-flop circuit group. A second exclusive OR circuit for inputting the output of the flip-flop circuit and a flip-flop circuit of the second flip-flop circuit group connected in a cascaded manner, and the output of the second exclusive OR circuit And a second switch group that is openably and closably connected to the input of the first flip-flop circuit in the second flip-flop circuit group, and the spreading code control circuit has the peak detected by the peak detector. Each time it is detected, the control to turn on the first switch group and the control to turn on the second switch group are alternately switched.

  The despreading demodulator of the present invention includes a sample hold circuit, a sample hold control circuit, a first spread code generation circuit, a second spread code generation circuit, and a signal output from the sample hold circuit. N multipliers for multiplying the corresponding spreading codes output from the first spreading code generating circuit or the second spreading code generating circuit for each corresponding signal, and multiplier output signals of the N multipliers Of these, approximately half corresponding to either the newer spread signal or the older spread signal received in order has two polarity states, inverted and non-inverted, during one period of the second clock. Polarity conversion circuit that outputs the signal after the polarity conversion, and outputs the remaining half of the multiplier output signal as it is, an adder that adds the output of this polarity conversion circuit, and a peak of the output of this adder are detected. , A first peak detector for demodulating the received signal based on the output peak, and the adder output when the substantially half of the spreading codes are in the first state of either the inversion state or the non-inversion state A hold circuit that holds the output of the adder and the output of the hold circuit when the substantially half of the spreading codes are in a second state different from the first state in an inverted state or a non-inverted state. A second peak detector that calculates the sum of absolute values and detects the peak of the sum of absolute values, and each time a peak is detected by the second peak detector, the first spread code generator circuit A spread code control circuit for alternately switching the input of the first spread code to the multiplier and the input of the second spread code from the second spread code generation circuit to the multiplier; is there.

  The despreading demodulator of the present invention includes a sample hold circuit, a sample hold control circuit, a first spread code generation circuit, a second spread code generation circuit, and sample hold circuits of the N sample hold circuits. Of the output signals, approximately half corresponding to either the newer spread signal or the older spread signal received in order has two polarity states, inverted and non-inverted, during one period of the second clock. The polarity conversion circuit that converts the polarity so as to exhibit the same and outputs the remaining half of the sample-and-hold output signals as they are, and the signal output from the polarity conversion circuit and the first spreading code generation circuit or the first N multipliers that multiply the spreading codes output from the two spreading code generation circuits for each corresponding signal, an adder that adds the outputs of the N multipliers, and the addition A first peak detector that detects a peak of the output signal and demodulates the received signal based on the detected peak, and a first state in which approximately half of the spreading codes are in an inversion state or a non-inversion state And a hold circuit for holding the output of the adder when in the state, and the output of the adder when the substantially half of the spreading codes are in a second state different from the first state in an inverted state or a non-inverted state And a second peak detector for detecting the peak of the absolute value sum, and each time a peak is detected by the second peak detector, Spreading that alternately switches the input of the first spreading code from the first spreading code generation circuit to the multiplier and the input of the second spreading code from the second spreading code generation circuit to the multiplier Having a sign control circuit It is.

  The despreading demodulator of the present invention samples and holds the received spread signal in synchronization with the first clock having the same frequency as the clock used for spreading the spread signal (N is an integer of 2 or more). Among the N sampled and held circuits, the spread code generating circuit for generating N spread codes in synchronization with the second clock, and the N spread codes output from the spread code generating circuit, the received order is Polarity conversion is performed so that approximately half corresponding to either the new spread signal or the old spread signal exhibits two polarity states of inversion and non-inversion during one period of the second clock. The remaining half of the codes are multiplied by the polarity conversion circuit that outputs the signals as they are, the signal output from the sample hold circuit and the spreading code output from the polarity conversion circuit for each corresponding signal N A multiplier for adding the outputs of the N multipliers, a first peak detector for detecting a peak of the output of the adder and demodulating a received signal based on the detected peak, A hold circuit that holds the adder output when the approximately half of the spreading codes are in the first state of either the inversion state or the non-inversion state; and the substantially half of the spreading codes are in the inversion state or non-inversion Calculating a sum of absolute values of the adder output and the output of the hold circuit in a second state different from the first state, and detecting a peak of the absolute value sum; And a clock control circuit for controlling the input of the second clock to the spreading code generation circuit in accordance with detection of a peak by the second peak detector.

  The despreading demodulator of the present invention includes a sample hold circuit, a spread code generation circuit, a signal output from the sample hold circuit, and a spread code output from the spread code generation circuit for each corresponding signal. Of the N multipliers to be multiplied and the multiplier output signals of the N multipliers, approximately half corresponding to either the newer spread signal or the older spread signal received in order. A polarity conversion circuit that converts the polarity so as to exhibit two polarity states of inversion and non-inversion during one cycle of the second clock and outputs the remaining substantially half of the multiplier output signals as they are, and this polarity An adder for adding the outputs of the conversion circuit; a first peak detector for detecting a peak of the output of the adder; and demodulating the received signal based on the detected peak; and approximately half of the spreading codes are in an inverted state Also A hold circuit that holds the output of the adder when in one of the non-inverted states and the first state of the approximately half of the spread codes in the inverted state or non-inverted state A second peak detector for calculating a sum of absolute values of the output of the adder and the output of the hold circuit in different second states and detecting a peak of the sum of the absolute values; A clock control circuit for controlling the input of the second clock to the spreading code generation circuit in accordance with detection of a peak by a peak detector.

  The despreading demodulator according to the present invention includes a sample hold circuit, a spread code generation circuit, and a sample hold output signal of the N sample hold circuits, the spread signal having the newest received order or the old one. The half of the sampled signal is converted in polarity so that approximately half corresponding to one of the spread signals exhibits two polarity states of inversion and non-inversion during one cycle of the second clock, and the remaining half of the sample hold A polarity conversion circuit that outputs the output signal as it is, N multipliers that multiply the signal output from the polarity conversion circuit and the spread code output from the spread code generation circuit for each corresponding signal, and An adder for adding the outputs of the N multipliers, a peak detector for detecting the peak of the output of the adder, a peak of the output of the adder, and detecting the detected peak A first peak detector that demodulates a received signal; and a hold circuit that holds the output of the adder when the substantially half of the spreading codes are in a first state of either an inversion state or a non-inversion state; Calculating the sum of absolute values of the adder output and the output of the hold circuit when approximately half of the spreading codes are in the second state different from the first state in the inverted state or the non-inverted state. A second peak detector for detecting the peak of the sum of absolute values, and controlling the input of the second clock to the spread code generating circuit in accordance with the detection of the peak by the second peak detector. And a clock control circuit.

  The despreading demodulator according to the present invention also includes N (N is an integer of 2 or more) sample-and-hold circuits that sample-hold the received spread signal, and a first frequency having the same frequency as the clock used for spreading the spread signal. The sample and hold control circuit controls the N sample and hold circuits to sequentially perform the sample holding operation in synchronism with the first clock, and the N sample and hold circuits in synchronization with the second clock. A first spreading code generating circuit for generating one spreading code, and a second spreading code for generating N second spreading codes in which the first spreading codes are rearranged in the reverse direction in synchronization with the second clock. Out of N spreading codes output from the two spreading code generation circuits and the first spreading code generation circuit or the second spreading code generation circuit, the spreading signal having the newest received order or the older spreading code The diffusion N half inverters corresponding to any of the signals are inverted in polarity and output, and the remaining half of the codes are output as they are, the signal output from the sample hold circuit and the first diffusion N number of first multipliers that multiply the spread code output from the code generation circuit or the second spread code generation circuit for each corresponding signal, the signal output from the sample hold circuit, and the inverter N number of second multipliers that multiply the output spreading code for each corresponding signal, a first adder that adds outputs of the N number of first multipliers, and N number of second multipliers A second adder for adding the outputs of the multiplier, a peak of the output of the first adder and a peak of the output of the second adder are detected, and the received signal is demodulated based on the detected peak A first peak detector and an output of the first adder The second peak detector for calculating the sum of absolute values with the output of the second adder and detecting the peak of the sum of absolute values, and each time a peak is detected by the second peak detector , Input of the first spreading code from the first spreading code generation circuit to the first multiplier and inverter, and from the second spreading code generation circuit to the first multiplier and inverter. A spreading code control circuit that alternately switches the input of the second spreading code.

  The despreading demodulator of the present invention includes a sample hold circuit, a sample hold control circuit, a first spread code generation circuit, a second spread code generation circuit, and a signal output from the sample hold circuit. N multipliers for multiplying the corresponding spreading codes output from the first spreading code generating circuit or the second spreading code generating circuit for each corresponding signal, and multiplier output signals of the N multipliers Of these, approximately half corresponding to either the newer spread signal or the older spread signal received in reverse order is output with the polarity inverted, and the remaining approximately half multiplier output signals are output as they are. A first adder for adding the outputs of the N multipliers, a second adder for adding the outputs of the N inverters, and a peak of the output of the first adder And the output pin of the second adder. And calculating a sum of absolute values of the first peak detector that demodulates the received signal based on the detected peak, and the output of the first adder and the output of the second adder. A second peak detector for detecting the peak of the sum of absolute values, and each time a peak is detected by the second peak detector, the first spreading code generation circuit to the multiplier A spreading code control circuit that alternately switches between an input of the first spreading code and an input of the second spreading code from the second spreading code generation circuit to the multiplier;

  The despreading demodulator of the present invention includes a sample hold circuit, a sample hold control circuit, a first spread code generation circuit, a second spread code generation circuit, and sample hold circuits of the N sample hold circuits. Of the output signals, approximately half of the received signals that are received in the newest order or the older spread signal are inverted in polarity and output, and the remaining approximately half of the sample-and-hold output signals remain as they are. The N inverters to be output, the signal output from the sample and hold circuit, and the spreading code output from the first spreading code generating circuit or the second spreading code generating circuit are multiplied for each corresponding signal. N first multipliers, a signal output from the inverter, and a spreading code output from the first spreading code generation circuit or the second spreading code generation circuit N for each corresponding signal, first adder for adding the outputs of the N first multipliers, and adding the outputs of the N second multipliers And a first peak detector that detects a peak of the output of the first adder and a peak of the output of the second adder and demodulates the received signal based on the detected peak And a second peak detector for calculating a sum of absolute values of the output of the first adder and the output of the second adder and detecting a peak of the sum of the absolute values, and the peak detection Each time the peak is detected by the generator, the first spreading code is input from the first spreading code generation circuit to the first multiplier and the second multiplier and the second spreading code is generated. An extension for alternately switching the input of the second spreading code from the circuit to the first multiplier and the second multiplier. Those having a sign control circuit.

  The despreading demodulator of the present invention samples and holds the received spread signal in synchronization with the first clock having the same frequency as the clock used for spreading the spread signal (N is an integer of 2 or more). Among the N sample and hold circuits, the spread code generation circuit that generates N spread codes in synchronization with the second clock, and the N spread codes that are output from the spread code generation circuit, the received order is N inverters that output the inverted half of the signal corresponding to either the new spread signal or the old spread signal with the polarity reversed, and output the remaining half of the code as they are; and the sample hold N first multipliers that multiply the signal output from the circuit and the spreading code output from the spreading code generation circuit for each corresponding signal, the signal output from the sample and hold circuit, and the previous N second multipliers that multiply the spreading code output from the inverter for each corresponding signal, a first adder that adds the outputs of the N first multipliers, and N A second adder for adding the outputs of the second multiplier, a peak of the output of the first adder and a peak of the output of the second adder, and receiving based on the detected peak A first peak detector for demodulating the signal, a second sum for calculating a sum of absolute values of the output of the first adder and the output of the second adder, and detecting a peak of the sum of the absolute values. And a clock control circuit for controlling the input of the second clock to the spreading code generation circuit in accordance with detection of a peak by the second peak detector.

  The despreading demodulator of the present invention includes a sample hold circuit, a spread code generation circuit, a signal output from the sample hold circuit, and a spread code output from the spread code generation circuit for each corresponding signal. Of the N multipliers to be multiplied, and the multiplier output signals of the N multipliers, the polarity corresponding to either the spread signal with the newer received order or the spread signal with the older one is polar N inverters that output the inverted signals of the remaining half of the multiplier output signals, a first adder that adds the outputs of the N multipliers, and N inverters. A second adder for adding outputs, a first output peak from the first adder and a second output peak from the second adder, and a received signal demodulated based on the detected peak Of the peak detector and the first adder A second peak detector for calculating a sum of absolute values of the force and the output of the second adder and detecting a peak of the sum of absolute values, and detecting a peak by the second peak detector. And a clock control circuit for controlling the input of the second clock to the spreading code generation circuit.

  The despreading demodulator according to the present invention includes a sample hold circuit, a spread code generation circuit, and a sample hold output signal of the N sample hold circuits, the spread signal having the newest received order or the old one. N half inverters corresponding to any one of the spread signals are inverted and output, and the remaining half of the sample hold output signals are output as they are, and the signal output from the sample hold circuit And N spreading multipliers outputted from the spreading code generating circuit for each corresponding signal, the signals outputted from the inverter and the spreading outputted from the spreading code generating circuit N second multipliers for multiplying the code for each corresponding signal, first adders for adding the outputs of the N first multipliers, and outputs of the N second multipliers Add And a first peak detector that detects a peak of the output of the first adder and a peak of the output of the second adder and demodulates the received signal based on the detected peak And a second peak detector for calculating a sum of absolute values of the output of the first adder and the output of the second adder and detecting a peak of the sum of the absolute values, And a clock control circuit for controlling the input of the second clock to the spreading code generation circuit in accordance with detection of a peak by the peak detector.

Further, in one configuration example of the despreading demodulator of the present invention, the clock control circuit detects the second clock to the spreading code generation circuit every time a peak is detected by the second peak detector. The input is stopped and restarted alternately.
In the configuration example of the despreading demodulator of the present invention, the clock control circuit may detect the second clock to the spreading code generation circuit when a peak is detected by the second peak detector. The input is stopped for a certain time.
Also, in one configuration example of the despreading demodulator of the present invention, the spreading code generating circuit is configured by a flip-flop circuit, an exclusive OR circuit, and a switch for controlling the output path of the flip-flop circuit. is there.

  According to the present invention, the spread signal is despread and demodulated using the first spread code generation circuit and the second spread code generation circuit that do not require external components and do not require synchronization control between the spread signal and the spread code. Thus, a low-power despreading demodulator can be realized, and a low-power and low-cost portable radio equipped with the despreading demodulator can be realized. Also, by providing the first spreading code generation circuit, the second spreading code generation circuit, and the spreading code control circuit, the correlation peak signal from the adder is the first clock, the second clock, and the spreading code. Therefore, the correlation peak signal can be obtained frequently, so that despread demodulation can be performed even when the data clock frequency of the data to be transmitted is high, and the data clock frequency can be increased. Further, by providing a polarity conversion circuit, the output of the adder is always output even when the received signal, which is the output of the first peak detector, changes from “1” to “0” or “0” to “1”. Since the peak appears, the jitter of the received signal can be greatly reduced. Further, by providing the hold circuit and the second peak detector, even when the received signal changes from “1” to “0” or “0” to “1”, it is always constant by the second peak detector. Since a peak above the level is detected, the possibility that the peak detection becomes impossible can be further reduced.

  Also, the spread signal is despread demodulated using a spread code generation circuit that does not require external components and does not require synchronization control between the spread signal and the spread code, thus realizing a low-power despread demodulator. Therefore, it is possible to realize low power and low cost of a portable radio device equipped with a despreading demodulator. Further, by providing the clock control circuit, the correlation peak signal from the adder does not depend on the first clock, the second clock, and the spread code, and the correlation peak signal can be frequently obtained. Even when the data clock frequency is high, despread demodulation can be performed, and the data clock frequency can be increased. Further, by providing a polarity conversion circuit, the output of the adder is always output even when the received signal, which is the output of the first peak detector, changes from “1” to “0” or “0” to “1”. Since the peak appears, the jitter of the received signal can be greatly reduced. Further, by providing the hold circuit and the second peak detector, even when the received signal changes from “1” to “0” or “0” to “1”, it is always constant by the second peak detector. Since a peak above the level is detected, the possibility that the peak detection becomes impossible can be further reduced.

  In addition, the spread signal is despread and demodulated using the first spread code generation circuit and the second spread code generation circuit that do not require external parts and do not require synchronization control between the spread signal and the spread code. Therefore, a low power despreading demodulator can be realized, and low power and low cost of a portable radio device equipped with the despreading demodulator can be realized. Further, by providing the first spreading code generation circuit, the second spreading code generation circuit, and the spreading code control circuit, the correlation peak signals from the first adder and the second adder are the first Since the correlation peak signal can be frequently obtained without depending on the clock, the second clock, and the spreading code, despread demodulation can be performed even when the data clock frequency of the data to be transmitted is high. Can be speeded up. Further, an inverter, a first multiplier, a second multiplier, a first adder, a second adder, and a first peak detector are provided, or the inverter, the multiplier, and the first By providing the second adder, the second adder and the first peak detector, the received signal which is the output of the first peak detector is changed from “1” to “0” or “0” to “1”. Even when it changes to, a peak always appears in the outputs of the first adder and the second adder, so that the jitter of the received signal can be greatly reduced. In addition, by providing the second peak detector, even when the received signal changes from “1” to “0” or “0” to “1”, the second peak detector always provides a peak above a certain level. Therefore, the possibility that peak detection becomes impossible can be further reduced.

  Also, the spread signal is despread demodulated using a spread code generation circuit that does not require external components and does not require synchronization control between the spread signal and the spread code, thus realizing a low-power despread demodulator. Therefore, it is possible to realize low power and low cost of a portable radio device equipped with a despreading demodulator. Also, by providing the clock control circuit, the correlation peak signal from the first adder and the second adder does not depend on the first clock, the second clock and the spread code, and the correlation peak signal is frequently used. Therefore, despread demodulation can be performed even when the data clock frequency of data to be transmitted is high, and the data clock frequency can be increased. Further, an inverter, a first multiplier, a second multiplier, a first adder, a second adder, and a first peak detector are provided, or the inverter, the multiplier, and the first By providing the second adder, the second adder and the first peak detector, the received signal which is the output of the first peak detector is changed from “1” to “0” or “0” to “1”. Even when it changes to, a peak always appears in the outputs of the first adder and the second adder, so that the jitter of the received signal can be greatly reduced. In addition, by providing the second peak detector, even when the received signal changes from “1” to “0” or “0” to “1”, the second peak detector always provides a peak above a certain level. Therefore, the possibility that peak detection becomes impossible can be further reduced.

[First Embodiment]
FIG. 1 is a block diagram showing a configuration of a despreading demodulator according to a first embodiment of the present invention. The despread demodulator according to the present embodiment includes N sample hold circuits 1a to 1g (N is an integer equal to or larger than 2 and 7 in the present embodiment) for holding an input spread signal as a sample, A sample hold control circuit 2 that controls the sample hold circuits 1a to 1g to sequentially perform the sample hold operation with the clock f1 as an input and a shift register that shifts the output signal from the sample hold control circuit 2 in synchronization with the clock f1 are configured. Flip-flop circuits 3a to 3f, a spread code generating circuit 4 for generating N spread codes in synchronization with the second clock f2, and among the N spread codes output from the spread code generating circuit 4, Almost half corresponding to either the newer spread signal or the older spread signal received by the despreading demodulator is inverted or not in one cycle of the clock f2. The polarity conversion circuit 101 outputs the signal after converting the polarity so as to exhibit two polarity states, and outputs the remaining half of the code as it is, and the diffusion signal and the polarity conversion circuit output from the sample hold circuits 1a to 1g. N multipliers 5 a to 5 g that multiply the spread code output from 101 for each corresponding signal, an adder 6 that adds the output signals of the multipliers 5 a to 5 g, and an output signal of the adder 6 A first peak detector 7 for detecting a peak and demodulating a received signal (baseband signal) based on the detected peak; an output of the adder when approximately half of the spreading codes are in an inverted state; A distributor 107 that distributes and outputs the output of the adder at the time, a hold circuit 108 that holds the output of the adder when the substantially half of the spreading codes output from the distributor 107 are in an inverted state, and a distributor 1 7 calculates a sum of absolute values of the output of the adder and the output of the hold circuit 108 when the substantially half of the spreading codes are in a non-inverted state, and detects a peak of the sum of the absolute values. And a peak detector 109.

The first clock f1 is a clock having the same frequency as the clock used for spreading the spread signal on the transmission side. The second clock f2 is a clock having the same frequency as the clock used for generating the spread code on the transmission side.
In the present embodiment, N = 7, N = 7 sample hold circuits 1a-1g and 5a-5g multipliers, and (N-1) = 6 flip-flop circuits 3a-3f. As shown, N may be an integer of 2 or more.

  FIG. 2 shows an example of the configuration of the multiplier 5 (5a to 5g). Each multiplier 5 includes NMOS transistors MN1 to MN7, and is configured by a two-stage vertically stacked differential circuit. The spread code output from the polarity conversion circuit 101 and the spread signal output from the sample hold circuit 1 (1a to 1g) are differential signals. The spreading code output from the polarity conversion circuit 101 is input to the differential circuit including the transistors MN1 and MN2 and the differential circuit including the transistors MN3 and MN4 in opposite phases, and is output from the sample hold circuit 1 (1a to 1g). The spread signal is input to a differential circuit composed of transistors MN5 and MN6. Thereby, the spread code and the spread signal are multiplied, and the multiplication result is output in the current mode.

  FIG. 3 shows an example of the configuration of the adder 6. The adder 6 includes load resistors 31 and 32 to which a power supply voltage is applied at one end and a differential output of the multipliers 5a to 5g is input to the other end. The differential outputs of the multipliers 5a to 5g output in the current mode are converted into voltages by the load resistors 31 and 32 in the adder 6 and added to be output in the voltage mode. The output signal of the adder 6 is peak detected by the first peak detector 7 and output as a received signal (baseband signal).

  FIG. 4 shows an example of the configuration of the spread code generating circuit 4. The spread code generation circuit 4 includes exclusive OR circuits 41 and 42, flip-flop circuits 43a to 43n constituting shift registers that shift in synchronization with the clock f2, exclusive OR circuits 41 and 42, and flip-flop circuits. The switches 44a to 44p for turning on / off the output paths 43a to 43n and the spread code control circuit 45 for controlling the switches 44a to 44p are configured.

  In the present embodiment, the outputs of the flip-flop circuits 43a and 43c are taken into the exclusive OR circuit 41, and the operation result of the exclusive OR circuit 41 is returned to the input of the flip-flop 43a, whereby the first spreading code is obtained. Occur. On the other hand, the outputs of the flip-flop circuits 43j and 43i are taken into the exclusive OR circuit 42, and the operation result of the exclusive OR circuit 42 is returned to the input of the flip-flop 43h, thereby rearranging the first spreading codes in reverse order. A second spreading code is generated.

  That is, the first flip-flop circuit group including the first exclusive OR circuit 41 and the flip-flop circuits 43a to 43g and the first switch group including the switches 44a to 44g and 44o are configured to transmit the first spreading code. A first spreading code generating circuit 40-1 is generated. The second exclusive-OR circuit 42, the second flip-flop circuit group including the flip-flop circuits 43h to 43n, and the second switch group including the switches 44h to 44n and 44p are the first spreading code and A second spreading code generating circuit 40-2 for generating a second spreading code in which the signal is shifted in the reverse direction is configured. By simply changing the combination of inputs to the exclusive OR circuits 41 and 42, it is possible to form spreading code generation circuits corresponding to various spreading codes.

  In this embodiment, since the spread signal is sampled and held in the order of the sample hold circuits 1a, 1b, 1c, 1d, 1e, 1f, and 1g, the signals sampled and held by the sample hold circuits 1a to 1g are inputted. The arrangement order is reverse to that of the spread signal. Therefore, in order to obtain the correlation between the spread signal input to the despread demodulator and the spread code, the order of the spread codes is reversed in accordance with the order of the spread signals sampled and held by the sample hold circuits 1a to 1g. That's fine. That is, the first spreading code output from the first spreading code generation circuit 40-1 may be arranged in the reverse order of the spreading codes used for spreading the spread signal on the transmission side.

  The spreading code control circuit 45 controls the switches 44a to 44p according to peak detection by a second peak detector 109 described later. When the switches 44a to 44g and 44o are on, the switches 44h to 44n and 44p are off, and the first spreading code generated by the first spreading code generation circuit 40-1 is shifted from left to right in FIG. I will do it. Conversely, when the switches 44a to 44g and 44o are off, the switches 44h to 44n and 44p are on, and the second spreading code generated by the second spreading code generation circuit 40-2 is from right to left in FIG. Shift to.

  The spread code control circuit 45 alternates between the first switch group (44a to 44g, 44o) and the second switch group (44h to 44n, 44p) each time a peak is detected by the second peak detector 109. To switch the direction of spreading code shift. Of the first spreading code generation circuit 40-1 or the second spreading code generation circuit 40-2, the corresponding multipliers 5a to 5g from the flip-flop circuit group of one spreading code generation circuit whose switch group is on. A spreading code is input to the. In addition, since the output of this flip-flop circuit group is simultaneously input to the flip-flop circuit group of the other spreading code generation circuit whose switch group is off, when switching the switch group, it is output at that time. The spreading code starts to shift in the reverse direction while retaining the spreading code.

  FIG. 5 shows waveforms during the operation of the spreading code generation circuit of FIG. 4 (in this example, the spreading code of PN7 {1-1111-1-1}). FIG. 5A shows a first spreading code generated when the first spreading code generation circuit 40-1 is in an ON state, and FIG. 5B shows a second spreading code generation circuit 40-2 in an ON state. The second spreading code generated at the time is shown.

Hereinafter, the operation of the despreading demodulator of this embodiment will be described in detail.
The sample and hold control circuit 2 receives the first clock f1 and samples the spread signal for one clock every clocks equal to the number of the multipliers 5a to 5g (in this embodiment, every N = 7 clocks). A sample hold control signal to be held is generated.
The flip-flop circuits 3a to 3f constituting the shift register shift the sample hold control signal output from the sample hold control circuit 2 to the respective sample hold circuits 1b to 1g while shifting the sample hold control signal to the right in FIG. 1 in synchronization with the clock f1. Output.

  Assuming that the sample hold circuit 1a holds the spread signal in response to the sample hold control signal, the sample hold circuit 1b samples and holds the spread signal with a delay of one cycle of the clock f1, and further only one cycle of the clock f1. The sample hold circuit 1c samples and holds the spread signal with a delay. As described above, the sample hold circuits 1a to 1g sequentially perform the sample hold operation in synchronization with the clock f1.

Therefore, the new spread signal received is updated and held by the sample hold control circuit 2 and the flip-flop circuits 3a to 3f at the same number of clocks as the number of multipliers at the inputs of the multipliers 5a to 5g. . On the other hand, a spread code is generated from the spread code generation circuit 4 in synchronization with the clock f 2 and input to the polarity conversion circuit 101.
The spread signal output from the sample hold circuits 1a to 1g and the spread code output from the spread code generation circuit 4 via the polarity conversion circuit 101 are multiplied for each corresponding signal by the multipliers 5a to 5g. The multiplication results of the devices 5a to 5g are added by the adder 6 and output.

  Here, the operation when the polarity conversion circuit 101 is omitted and the spread code generation circuit 4 and the multipliers 5a to 5g are directly connected will be described. Due to the spread code from the spread code generation circuit 4, the phase of the spread signal and the spread code coincide with each other at least once in the time interval of the spread code length, and a correlation peak signal is obtained from the adder 6. When the second peak detector 109 detects this peak as will be described later, the signal path between the flip-flops in the spread code generation circuit 4 is switched by the spread code control circuit 45, and the shift direction of the spread code is switched. .

  When the spreading code shifts in one direction, the next correlation peak signal appears when the spreading code shifts and the same spreading code pattern is input to the multipliers 5a to 5g, and the spreading code length Once every time interval. In the present embodiment, every time a peak is detected by the second peak detector 109, the direction in which the spreading code is shifted is switched. For this reason, when a correlation peak signal is obtained, the spreading code control circuit 45 switches the shifting direction of the spreading code, and the spreading code shifted in the reverse direction is input to the multipliers 5a to 5g.

  During the delay time from when the spread code control circuit 45 detects the correlation peak signal to when the spread code starts to shift in the reverse direction, the spread code being input to the multipliers 5a to 5g is shifted in the shift direction before switching. I keep doing it. For this reason, when the spread code pattern when the correlation peak signal is detected and the shift direction are switched, the phase of the spread code input to the multipliers 5a to 5g is shifted, but is input to the multipliers 5a to 5g. Since the spreading code starts to shift in the reverse direction, the phase of the spreading signal and the spreading code again coincide with each other shortly after the shift direction is switched, and the next correlation peak signal is obtained from the adder 6. When the second correlation detector 109 detects the next correlation peak signal, the spreading code control circuit 45 switches the spreading code shift direction to the reverse direction.

Thereafter, by repeating the same control, a correlation peak signal can be frequently obtained regardless of the spreading code length to be used.
In this configuration, a positive / negative correlation value output is obtained from the adder 6 corresponding to “1” and “0” of the digital data sent from the transmission side. The first peak detector 7 detects a peak of the output signal of the adder 6 and outputs a digital reception signal (baseband signal).

  Thus, in this embodiment, despread demodulation can be performed without performing synchronization control between the spread signal and the spread code. Further, in the present embodiment, the correlation peak signal from the adder 6 is changed to the clock f1, by switching the shift direction of the spread code in the spread code generation circuit 4 in accordance with the detection of the peak by the second peak detector 109. Since the configuration does not depend on f2 or the spreading code to be used, the data rate of the signal to be transmitted can be increased.

  However, in a configuration where no polarity conversion is performed by the polarity conversion circuit 101, for example, a despreading demodulator having a configuration proposed in Japanese Patent Application No. 2002-352019, peak detection becomes impossible during transition of transmission data, and a detection impossible period occurs. In the configuration in which polarity conversion by the polarity conversion circuit 101 is not performed, for example, as shown in FIG. 6, the received signal that is the output of the first peak detector 7 (point B in FIG. 1) transitions from “1” to “0”. The positive peak P1 corresponding to the received signal “1” appearing at the output of the adder 6 (point A in FIG. 1) is interrupted, and the negative peak P0 corresponding to the received signal “0” appears. It takes time. As a result, there is a problem that large jitter occurs in the received signal after demodulation. Further, there is a problem that the transmission capacity cannot be increased.

  On the other hand, in this embodiment, a polarity conversion circuit 101 is provided between the spread code generation circuit 4 and the multipliers 5a to 5g. The polarity conversion circuit 101 has the second half of the N spreading codes output from the spreading code generation circuit 4 corresponding to either the newer spreading signal or the older spreading signal received in the second order. About half of the codes are converted and output so as to exhibit two polarity states of inversion and non-inversion during one period of the clock f2, and the remaining codes excluding the almost half of the N spreading codes are output. Output as is.

  The polarity conversion circuit 101 operates based on the second clock f2. FIG. 7 shows the relationship between the second clock f2 and the operating state of the polarity conversion circuit 101. The states of the N spread codes output from the spread code generation circuit 4 change in synchronization with the clock f2. In the example of FIG. 7B, “A”, “B”, “C”, “D”, “E”, “F”, “G”, “H”,... In synchronization with the clock f2. Thus, the state of the spreading code has changed.

When the clock f2 is “1”, the polarity conversion circuit 101 inverts the polarity state of the approximately half of the spread codes (“−” in FIG. 7C), and when the clock f2 is “0”, The polarity state of the half of the spreading codes is assumed to be non-inverted (“+” in FIG. 7C). That is, approximately half of the spreading codes exhibit two polarity states of inversion and non-inversion during one period of the clock f2.
The approximate half may be an integer obtained by dividing N by 2 when N is an even number, but when N is an odd number, a value obtained by adding 1 to an integer obtained by dividing N by 2 or an integer from 1 Any of the values obtained by subtracting. For example, approximately half of N = 7 is either 3 or 4.

  Further, when the latest spread signal is held in the sample hold circuit 1d, if the spread signal is arranged in the newest order, the sample hold circuits are in the order of 1d, 1c, 1b, 1a, 1g, 1f, 1e. The half of the spreading codes corresponding to the newer one is a spreading code corresponding to the multipliers 5d, 5c, 5b, 5a (when the half is about 4) or a spreading code corresponding to the multipliers 5d, 5c, 5b ( About half is 3). At the time when the latest spread signal is held in the sample and hold circuit 1a, the spread code corresponding to the multipliers 5a, 5g, 5f, and 5e (when approximately half is 4) or the multipliers 5a, 5g, and 5f is supported. Spreading code (when approximately half is 3).

  On the other hand, when the latest spread signal is held in the sample-and-hold circuit 1d, if the sample-and-hold circuits are arranged in order from the oldest spread signal, the order becomes 1e, 1f, 1g, 1a, 1b, 1c, and 1d. The half of the spreading codes corresponding to the older one is the spreading code corresponding to the multipliers 5e, 5f, 5g, 5a (when the half is approximately 4) or the spreading code corresponding to the multipliers 5e, 5f, 5g ( About half is 3). At the time when the latest spread signal is held in the sample hold circuit 1a, the spread code corresponding to the multipliers 5b, 5c, 5d, and 5e (when approximately half is 4) or the multipliers 5b, 5c, and 5d is supported. Spreading code (when approximately half is 3).

  As described above, approximately half of the spreading codes to be subjected to polarity conversion by the polarity conversion circuit 101 are determined by the position of the sample hold circuit in which the latest spread signal is held. For this reason, the polarity conversion circuit 101 checks the position of the sample and hold circuit in which the latest spread signal is held based on the sample and hold control signals output from the sample and hold control circuit 2 and the flip-flop circuits 3a to 3f. Based on the position, approximately half of the spreading codes corresponding to the newer or older spread signal are determined.

  8 (a) and 8 (b) show characteristic signal waveforms at points A and B in FIG. FIG. 8 shows a case where approximately half of the spreading codes whose polarity is converted by the polarity converting circuit 101 correspond to approximately half of the older spread signal. As can be seen from FIG. 8, when the received signal, which is the output of the first peak detector 7 (point B in FIG. 1), transitions from “1” to “0”, the polarity conversion circuit 101 does not perform polarity conversion. Compared with the case of 6, the negative peak P0 ′ corresponding to the received signal “0” appears earlier in the output of the adder 6 (point A in FIG. 1). The reason is that in the middle of the transition of the received signal from “1” to “0”, approximately half of the new spread signal has already changed to “0”, while approximately half of the old spread signal is Although still “1”, the polarity of the spreading code corresponding to approximately half of the older spread signal is inverted so that the older half of the spread signal is substantially changed to “0”. Because it becomes. For the same reason, when the received signal transitions from “0” to “1”, the positive peak corresponding to the received signal “1” is higher in the adder 6 than when the polarity conversion by the polarity conversion circuit 101 is not performed. Appears early in the output.

  FIG. 9 shows a signal waveform when approximately half of the spreading codes whose polarity is converted by the polarity converting circuit 101 correspond to approximately half of the new spread signal. As can be seen from FIG. 9, when the received signal, which is the output (point B) of the first peak detector 7, transitions from “1” to “0”, compared to the case where the polarity conversion by the polarity conversion circuit 101 is not performed. A new positive peak P1 ′ corresponding to the received signal “1” appears at the output (point A) of the adder 6. The reason is that by inverting the polarity of the spreading code corresponding to approximately half of the new spread signal, approximately half of the new spread signal is substantially changed to “1”. For the same reason, when the received signal transitions from “0” to “1”, a new negative peak corresponding to the received signal “0” is added to the adder compared to the case where the polarity conversion by the polarity conversion circuit 101 is not performed. Appears at output 6.

  Thus, in this embodiment, by providing the polarity conversion circuit 101, the output of the adder 6 is always output even when the received signal changes from “1” to “0” or “0” to “1”. Since the peak appears, the possibility that the peak detection becomes impossible can be greatly reduced, and the jitter of the received signal can be greatly reduced.

  However, even when the polarity conversion circuit 101 is provided as in the present embodiment, peak detection may not be possible. The first peak detector 7 regards an adder output equal to or greater than a predetermined threshold value as a correlation peak signal in which the phase of the spread signal and the spread code match, but if the threshold is set too low, the correlation peak signal Noise components that should not be regarded as peaks are detected as peaks. Therefore, there is a limit to setting the peak detection threshold low. On the other hand, as can be seen from FIG. 8A and FIG. 9A, the peak value input from the adder 6 to the first peak detector 7 is that the received signal is “1” to “0” or “0”. The level drops when changing from "" to "1". Due to this level decrease, there is a possibility that a signal that should be regarded as a correlation peak signal may be missed without being detected, and peak detection may become impossible.

  Therefore, in the present embodiment, a distributor 107, a hold circuit 108, and a second peak detector 109 are provided, and the spread code generation circuit 4 is controlled by the output of the second peak detector 109, and the first peak is detected. The detector 7 is used only for demodulating the received signal.

  The distributor 107 distributes and outputs the adder output when the substantially half of the spreading codes are in the inversion state and the adder output when the spread code is in the non-inversion state. As described above, the polarity conversion circuit 101 inverts the polarity state of the approximately half of the spreading codes when the second clock f2 is “1”, and the approximately half of the spreading codes when the clock f2 is “0”. The polarity state of is non-inverted. Based on the clock f2, the distributor 107 outputs the output of the adder 6 when the substantially half of the spread codes are in an inverted state to the hold circuit 108, and the adder when the substantially half of the spread codes are in a non-inverted state. 6 is output to the second peak detector 109.

The hold circuit 108 holds the output of the distributor 107 for one clock in synchronization with the second clock f2. The reason why the hold circuit 108 is necessary is that the peak of the adder output when approximately half of the spreading codes are in the non-inverted state and the peak of the adder output when in the inverted state are output with a time lag. is there.
The second peak detector 109 calculates the sum of absolute values of the output of the distributor 107 and the output of the hold circuit 108, and detects the peak of this absolute value sum.

  As described above, by calculating the sum of absolute values of the adder output when approximately half of the spreading codes are in the non-inverted state and the adder output when in the inverted state, FIG. 8 (c) and FIG. 9 (c) The output (second point C in FIG. 1) of the second peak detector 109 can be obtained. Thus, according to the present embodiment, the possibility that peak detection becomes impossible can be further reduced.

[Second Embodiment]
Next, a second embodiment of the present invention will be described. FIG. 10 is a block diagram showing the configuration of the despreading demodulator according to the second embodiment of the present invention. The same components as those in FIG. 1 are denoted by the same reference numerals. The present embodiment has a configuration in which the installation location of the polarity conversion circuit is changed with respect to the despread demodulator of the first embodiment. In other words, the polarity conversion circuit 102 according to the present embodiment is provided between the multipliers 5 a to 5 g and the adder 6.

Of the N multiplier output signals of the multipliers 5a to 5g, the polarity conversion circuit 102 is approximately half corresponding to either the newer spread signal or the older spread signal received by the despread demodulator. Substantially half of the multiplier output signals are converted and output so as to exhibit two inverted and non-inverted polarity states in one cycle of the second clock f2, and among the N multiplier output signals, The remaining signals excluding approximately half are output as they are. The polarity conversion circuit 102 operates based on the second clock f2, and the latest spread signal is held based on the sample hold control signal output from the sample hold control circuit 2 and the flip-flop circuits 3a to 3f. As in the first embodiment, the position of the sample and hold circuit is checked, and approximately half of the multiplier output signals corresponding to the newer or older one of the spread signals are determined based on this position.
Thus, also in this embodiment, the same effect as that of the first embodiment can be obtained.

[Third Embodiment]
Next, a third embodiment of the present invention will be described. FIG. 11 is a block diagram showing the configuration of the despreading demodulator according to the third embodiment of the present invention. The same components as those in FIG. 1 are denoted by the same reference numerals. The present embodiment has a configuration in which the installation location of the polarity conversion circuit is changed with respect to the despread demodulator of the first embodiment. That is, the polarity conversion circuit 103 according to the present embodiment is provided between the sample hold circuits 1a to 1g and the multipliers 5a to 5g.

  The polarity conversion circuit 103 is an abbreviation corresponding to either the newer spread signal or the older spread signal in the order received by the despread demodulator among the N sample hold output signals of the sample hold circuits 1a to 1g. The half of the sample and hold output signals are converted in polarity so that half of them exhibit two polarity states of inversion and non-inversion during one period of the second clock f2, and the N sample and hold output signals are output. The remaining signals excluding the approximately half are output as they are. The polarity conversion circuit 103 operates based on the second clock f2, and based on the sample hold control signal, the position of the sample hold circuit where the latest spread signal is held is checked. Determining approximately half of the sample and hold output signals corresponding to the newer or older one is the same as in the first embodiment. Thus, also in this embodiment, the same effect as that of the first embodiment can be obtained.

  In the first to third embodiments, in order to obtain the correlation between the spread signal and the spread code, the spread order of the spread codes is reversed in accordance with the spread order of the spread signals sampled and held by the sample hold circuits 1a to 1g. However, the signals sampled and held by the sample hold circuits 1a to 1g may be arranged in the same order as the input spread signals. In order to arrange them in the same order as the input spread signals, the output of the sample hold control circuit 2 shown in FIGS. 1, 10, and 11 is the flip-flop circuit 3f, and the output of the flip-flop circuit 3f is the flip-flop circuit 3e. The output of the flip-flop circuit 3e is the flip-flop circuit 3d, the output of the flip-flop circuit 3d is the flip-flop circuit 3c, the output of the flip-flop circuit 3c is the flip-flop circuit 3b, and the output of the flip-flop circuit 3b is the flip-flop. What is necessary is just to connect so that each may be input into the circuit 3a. In this case, it is not necessary to reverse the arrangement order of the spread codes, and the first spread code output from the first spread code generation circuit 40-1 was used for spreading the spread signal on the transmission side. The same order as the spreading codes may be used.

[Fourth Embodiment]
Next, a fourth embodiment of the present invention will be described. FIG. 12 is a block diagram showing a configuration of a despreading demodulator according to the fourth embodiment of the present invention. The despread demodulator of the present embodiment includes N (N = 7 in the present embodiment) sample and hold circuits 8a to 8g that hold the input spread signal in synchronization with the first clock f1, Of the N spreading codes generated from the N spreading codes in synchronization with the second clock f2, and the N spreading codes output from the spreading code generating circuit 9, the order received by the despreading demodulator is Polarity conversion is performed so that approximately half corresponding to either the new spread signal or the old spread signal exhibits two polarity states of inversion and non-inversion during one period of the clock f2, and the remaining approximately The polarity conversion circuit 104 that outputs half of the codes as they are, and N multipliers that multiply the signals output from the sample hold circuits 8a to 8g and the spreading codes output from the polarity conversion circuit 104 for each corresponding signal. 0a to 10g, an adder 11 for adding the output signals of the multipliers 10a to 10g, a peak of the output signal of the adder 11 is detected, and a received signal (baseband signal) is demodulated based on the detected peak. From the first peak detector 12, a distributor 110 that distributes and outputs an adder output when the substantially half of the spreading codes are in an inverted state and an adder output when the spread code is in a non-inverted state, A hold circuit 111 that holds the output of the adder when the approximately half of the spreading codes are in an inverted state, and an adder that is output from the distributor 111 when the approximately half of the spreading codes are in a non-inverted state The second peak detector 112 is configured to calculate the sum of absolute values of the output and the output of the hold circuit 111 and detect the peak of the sum of absolute values. In the present embodiment, N = 7 and seven sample-hold circuits and seven multipliers are shown, but N may be an integer of 2 or more.

  FIG. 13 shows an example of the configuration of the spread code generating circuit 9 of the present embodiment. The spread code generation circuit 9 includes an exclusive OR circuit 91, flip-flop circuits 92a to 92g that constitute a shift register that shifts the output of the exclusive OR circuit 91 in synchronization with the clock f2, and a second circuit that will be described later. And a clock control circuit 93 for controlling the input of the second clock f2 to the flip-flop circuits 92a to 92g in accordance with the detection of the peak by the peak detector 112. In the present embodiment, the outputs of the flip-flop circuits 92a and 92c are taken into the exclusive OR circuit 91, and the operation result of the exclusive OR circuit 91 is returned to the input of the flip-flop circuit 92a, thereby spreading code (this embodiment). In this form, PN7) is generated.

  Various spreading codes can be generated simply by changing the combination of inputs to the exclusive OR circuit 91. When the number of sample and hold circuits 8a to 8g and multipliers 10a to 10g is increased, the number of flip-flop circuits 92 of the spread code generation circuit 9 may be increased accordingly. In the present embodiment, unlike the first to third embodiments, the signals sampled and held by the sample hold circuits 8a to 8g are arranged in the same order as the input spread signals. Therefore, it is not necessary to reverse the arrangement order of the spreading codes, and the spreading code output from the spreading code generation circuit 9 may be the same as the spreading code used for spreading the spread signal on the transmission side.

  Hereinafter, the operation of the despreading demodulator of this embodiment will be described in detail. The spread signal is sampled and held by the sample and hold circuits 8a to 8g and inputted to the multipliers 10a to 10g. At this time, the spread signals received and held by the sample hold circuits 8a to 8g are input to the multipliers 10a to 10g, and are also input to the next stage sample hold circuit and held at the cycle of the clock f1 synchronized with the spread signals. The spread signal thus shifted is shifted in the cycle of the clock f1. With the above operation, the spread signal is supplied to the multipliers 10a to 10g by the sample and hold circuits 8a to 8g with a delay of one cycle of the clock f1. In the present embodiment, the spread signals corresponding to the 7-chip rate are always input to the multipliers 10a to 10 by the sample and hold circuits 8a to 8g. The 7-chip rate spread signal is updated in synchronization with the clock f1.

  On the other hand, the spread code generation circuit 9 outputs the spread code in synchronization with the clock f2. The spread codes output from the flip-flop circuits 92 a to 92 g of the spread code generation circuit 9 are output to the polarity conversion circuit 104. The flip-flop circuits 92a to 92g are connected in cascade and constitute a shift register. Therefore, the spread code is output to the polarity conversion circuit 104 while shifting in the right direction in FIG. 13 in synchronization with the clock f2.

  The polarity conversion circuit 104 is an abbreviation corresponding to either the newer spread signal or the older spread signal in the order received by the despreading demodulator among the N spread codes output from the spread code generation circuit 9. The substantially half of the codes are polarity-converted and output so that the half exhibits two polarity states of inversion and non-inversion during one cycle of the second clock f2, and the approximately half of the N spreading codes are excluded. The remaining codes are output as they are.

  In the present embodiment, the latest spread signal is always held in the sample hold circuit 8a, and the oldest spread signal is always held in the sample hold circuit 8g. Therefore, the approximately half of the spreading codes corresponding to the newer one of the spread signals corresponds to the spreading code corresponding to the multipliers 10a, 10b, 10c and 10d (when approximately half is 4) or the multipliers 10a, 10b and 10c. Spreading codes (when approximately half is 3), and approximately half of the spreading codes corresponding to the older spread signal are the spreading codes corresponding to the multipliers 10g, 10f, 10e, 10d (approximately half are 4). Or a spreading code corresponding to the multipliers 10g, 10f, 10e (when approximately half is 3). The polarity conversion circuit 104 operates based on the second clock f2 as in the first embodiment.

The spread signals output from the sample hold circuits 8a to 8g and the spread code output from the polarity conversion circuit 104 are multiplied for each corresponding signal by the multipliers 10a to 10g, and the multiplication results of the multipliers 10a to 10g are obtained. The signals are added by the adder 11 and output.
The first peak detector 12 outputs a digital reception signal (baseband signal) by detecting the peak of the output signal of the adder 11.

  In this embodiment, by providing the polarity conversion circuit 104, it is possible to greatly reduce the possibility of peak detection being impossible. However, as described in the first embodiment, the polarity conversion circuit 104 is provided. In some cases, peak detection may become impossible.

Therefore, in the present embodiment, a distributor 110, a hold circuit 111, and a second peak detector 112 are provided, and the spread code generation circuit 9 is controlled by the output of the second peak detector 112, and the first peak is detected. The detector 12 is used only for demodulating the received signal.
Based on the clock f2, the distributor 110 outputs the output of the adder 11 when the substantially half of the spread codes are in an inverted state to the hold circuit 111, and the adder when the substantially half of the spread codes are in a non-inverted state. 11 is output to the second peak detector 112.

The hold circuit 111 holds the output of the distributor 110 for one clock in synchronization with the second clock f2.
The second peak detector 112 calculates the sum of absolute values of the output of the distributor 110 and the output of the hold circuit 111 and detects the peak of this sum of absolute values.

  As described in the first embodiment, a correlation peak signal (referred to as a first correlation peak signal) is obtained from the adder 11 at the moment when the phases of the spread signal and the spread code coincide. When the first correlation peak signal is detected by the second peak detector 112, the clock control circuit 93 stops the input of the clock f2 to the flip-flop circuits 92a to 92g of the spread code generation circuit 9. Thus, the spread code is held in the flip-flop circuits 92a to 92g without shifting.

  During the delay time from when the second peak detector 112 detects the first correlation peak signal until the spread code shift actually stops, the phase of the spread signal and the spread code is the difference between the clock f1 and the clock f2. It keeps changing at the frequency of. For this reason, when the shift of the spread code is stopped, the phase of the spread signal and the spread code is shifted as compared with the case where the first correlation peak signal is detected. Slightly advanced phase.

  Even after the spread code shift is stopped, the spread signal is shifted in synchronism with the clock f1, so that the phase of the spread signal and the spread code changes at the speed of f1, and is delayed from the spread code. The phase of the spread signal changes in the direction of the lead phase. When the spread code shift is stopped, the spread code phase is only slightly advanced with respect to the spread signal, so the spread code and the spread code are again in phase soon after the spread code shift stop. , A correlation peak signal (referred to as a second correlation peak signal) is obtained from the adder 11.

  When the clock control circuit 93 stops the input of the clock f2 to the spread code generation circuit 9 according to the first correlation peak signal, the second peak detector 112 detects the second correlation peak signal. Then, the input of the clock f2 to the flip-flop circuits 92a to 92g of the spread code generating circuit 9 is resumed. During the delay time from when the second peak detector 112 detects the second correlation peak signal until the spread code shift is actually resumed, the phases of the spread signal and the spread code are the same as those of the clock f1 and the clock f2. It keeps changing at the difference frequency. For this reason, when the shift of the spread code is resumed, there is a shift in the phase of the spread signal and the spread code compared to when the second correlation peak signal is detected. Slightly advanced phase.

  After resuming the shift of the spread code, the phase of the spread signal and the spread code starts to change again so that the spread code phase is advanced with respect to the spread signal by the frequency difference between f1 and f2. When the spread code shift is resumed, the phase of the spread signal is only slightly advanced with respect to the spread code, so that the spread signal and the spread code are again in phase soon after the spread code shift resumes. , A correlation peak signal (referred to as a third correlation peak signal) is obtained from the adder 11.

When the clock control circuit 93 restarts the input of the clock f2 to the spread code generation circuit 9 in response to the second correlation peak signal, the second peak detector 112 detects the third correlation peak signal. Then, the input of the clock f2 to the spread code generating circuit 9 is stopped.
Thereafter, the correlation peak signal can be frequently obtained by repeating the same control.

  In the configuration in which the clock control circuit is omitted in the despreading demodulator of FIG. 12, the period at which the correlation peak signal is obtained depends on the sum frequency or difference frequency of the clock f1 and the clock f2 and the code length of the spreading code to be used. However, in this embodiment, a correlation peak signal can be obtained without depending on the clocks f1 and f2 and the spreading code to be used. Characteristic in the output of the adder 11 (point A in FIG. 12), the output of the first peak detector 12 (point B in FIG. 12), and the output of the second peak detector 112 (point C in FIG. 12). The signal waveform is the same as in FIGS.

According to the present embodiment, as in the first embodiment, despread demodulation can be performed without performing synchronization control between the spread signal and the spread code. In this embodiment, since the correlation peak signal from the adder 11 does not depend on the clocks f1 and f2 and the spreading code to be used, the data rate of the signal to be transmitted can be increased.
Furthermore, in this embodiment, even when the received signal changes from “1” to “0” or from “0” to “1”, a peak always appears at the output of the adder 11, so that detection becomes impossible. There is no. As a result, in this embodiment, the jitter of the received signal can be greatly reduced.

  In this embodiment, every time a correlation peak signal from the adder 11 is detected, the input of the clock f2 to the spread code generation circuit 9 is stopped / restarted. However, the correlation peak signal is detected and spread. The same effect can be obtained even if the input of the clock f2 is resumed after waiting for a certain time without detecting the next correlation peak signal after the input of the clock f2 to the code generation circuit 9 is stopped.

[Fifth Embodiment]
Next, a fifth embodiment of the present invention will be described. FIG. 14 is a block diagram showing a configuration of a despreading demodulator according to the fifth embodiment of the present invention. The same components as those in FIG. 12 are denoted by the same reference numerals. This embodiment has a configuration in which the installation location of the polarity conversion circuit is changed with respect to the despreading demodulator of the fourth embodiment. That is, the polarity conversion circuit 105 of the present embodiment is provided between the multipliers 10 a to 10 g and the adder 11.

Of the N multiplier output signals of the multipliers 10a to 10g, the polarity conversion circuit 105 has approximately half of the N spread signals corresponding to either the new spread signal or the old spread signal received by the despread demodulator. Substantially half of the multiplier output signals are converted and output so as to exhibit two inverted and non-inverted polarity states in one cycle of the second clock f2, and among the N multiplier output signals, The remaining signals excluding approximately half are output as they are. The polarity conversion circuit 105 operates based on the second clock f2 as in the fourth embodiment. Of the N multiplier output signals of the multipliers 10a to 10g, approximately half of the multiplier output signals corresponding to the newer one of the spread signals are output signals of the multipliers 10a, 10b, 10c, and 10d (approximately half of them). 4) or output signals of the multipliers 10a, 10b, and 10c (when approximately half is 3), and approximately half of the multiplier output signals corresponding to the older spread signal are the multipliers 10g, 10f, 10e, 10d output signals (when approximately half is 4) or multipliers 10g, 10f, 10e (when approximately half is 3).
Thus, also in this embodiment, the same effect as that of the fourth embodiment can be obtained.

[Sixth Embodiment]
Next, a sixth embodiment of the present invention will be described. FIG. 15 is a block diagram showing the configuration of the despreading demodulator according to the sixth embodiment of the present invention. The same components as those in FIG. 12 are denoted by the same reference numerals. This embodiment has a configuration in which the installation location of the polarity conversion circuit is changed with respect to the despreading demodulator of the fourth embodiment. That is, the polarity conversion circuit 106 of the present embodiment is provided between the sample hold circuits 8a to 8g and the multipliers 10a to 10g.

The polarity conversion circuit 106 is an abbreviation corresponding to either the newer spread signal or the older spread signal received in the despreading demodulator among the N sample hold output signals of the sample hold circuits 8a to 8g. The half of the sample and hold output signals are converted in polarity so that half of them exhibit two polarity states of inversion and non-inversion during one period of the second clock f2, and the N sample and hold output signals are output. The remaining signals excluding the approximately half are output as they are. The polarity conversion circuit 106 operates based on the second clock f2 as in the fourth embodiment. Of the N sample and hold output signals of the sample and hold circuits 8a to 8g, approximately half of the output signals corresponding to the newer one of the spread signals are the output signals of the sample and hold circuits 8a, 8b, 8c, and 8d (approximately half of the output signals). 4) or the output signals of the sample-and-hold circuits 8a, 8b, and 8c (when approximately half is 3), and the approximately half of the output signals corresponding to the older spread signal are the sample-and-hold circuits 8g, 8f, 8e and 8d output signals (when approximately half is 4) or sample and hold circuits 8g, 8f and 8e (when approximately half is 3).
Thus, also in this embodiment, the same effect as that of the fourth embodiment can be obtained.

  In the first to sixth embodiments, the distributors 107 and 110 include approximately half of the spreading codes (first and fourth embodiments) and approximately half of the multiplier output signals (second and fifth). Embodiment) or the output of the adder when approximately half of the sample and hold output signals (third and sixth embodiments) are in an inverted state are output to the hold circuits 108 and 111, and the addition is performed when the sample is in a non-inverted state. Is output to the second peak detectors 109 and 112. In contrast, approximately half of the spread codes, approximately half of the multiplier output signals or approximately half of the sample and hold output signals are output to the second peak detectors 109 and 112 when the approximately half of the sample and hold output signals are inverted. You may make it output to the hold circuits 108 and 111 the adder output when a half spreading code, a substantially half multiplier output signal, or a substantially half sample hold output signal is a non-inversion state. In this case, when the clock f2 is “1”, the polarity conversion circuits 101 to 106 set the polarity states of approximately half of the spread codes, approximately half of the multiplier output signals, or approximately half of the sample hold output signals to be non-inverted. When f2 is “0”, the polarity state of approximately half of the spread codes, approximately half of the multiplier output signals, or approximately half of the sample and hold output signals is inverted.

[Seventh Embodiment]
Next, a seventh embodiment of the present invention will be described. FIG. 16 is a block diagram showing the configuration of the despreading demodulator according to the seventh embodiment of the present invention. The same components as those in FIG. 1 are denoted by the same reference numerals. In the first embodiment, the polarity conversion is performed so that approximately half of the spreading codes exhibit two polarity states of inversion and non-inversion in one cycle of the second clock f2, and approximately half of the spreading codes are obtained. Since the peak of the adder output in the non-inverted state and the peak of the adder output in the inverted state are output with a time offset, the adder output when approximately half of the spreading codes are in the inverted state is held. The sum of absolute values of these peaks is calculated after being held in the circuit 108. On the other hand, in the present embodiment, the peak of the adder output when approximately half of the spreading codes are in the non-inverted state and the peak of the adder output when in the inverted state are obtained simultaneously. .

  The despreading demodulator of this embodiment is output from the sample hold circuits 1a to 1g, the sample hold control circuit 2, the flip-flop circuits 3a to 3f, the spread code generation circuit 4, and the spread code generation circuit 4. Of the N spreading codes, approximately half of the N spreading codes corresponding to either the newer spreading signal or the older spreading signal in the order received by the despreading demodulator are output with the polarity reversed, and the remaining half of the codes , N inverters 113a to 113g that output as they are, and N that multiply the spread signal output from the sample hold circuits 1a to 1g and the spread code output from the spread code generation circuit 4 for each corresponding signal. The first multipliers 5a-1 to 5g-1, the spread signals output from the sample hold circuits 1a to 1g and the spread codes output from the inverters 113a to 113g. N number of second multipliers 5a-2 to 5g-2 to be multiplied for each corresponding signal, and a first adder 6 to which the output signals of the first multipliers 5a-1 to 5g-1 are added. 1, a second adder 6-2 that adds the output signals of the second multipliers 5 a-2 to 5 g-2, a peak of the output of the first adder 6-1, and a second adder The first peak detector 114 that detects the peak of the output 6-2 and demodulates the received signal (baseband signal) based on the detected peak, and the output of the first adder 6-1 and the second peak And a second peak detector 115 for calculating the sum of absolute values with the output of the adder 6-2 and detecting the peak of the sum of absolute values.

Hereinafter, the operation of the despreading demodulator of this embodiment will be described in detail. The operations of the sample and hold circuits 1a to 1g, the sample and hold control circuit 2, the flip-flop circuits 3a to 3f, and the spread code generating circuit 4 are the same as those in the first embodiment.
The inverters 113a to 113g invert the polarity of approximately half of the N spread codes output from the spread code generation circuit 4 corresponding to either the new spread signal or the old spread signal received. The remaining codes excluding the approximately half of the N spread codes are output as they are.

  As in the first embodiment, approximately half of the spreading codes that are the targets of polarity inversion by the inverters 113a to 113g are determined by the position of the sample-and-hold circuit that holds the latest spread signal. For this reason, the inverters 113a to 113g check the positions of the sample and hold circuits in which the latest spread signals are held based on the sample and hold control signals output from the sample and hold control circuit 2 and the flip-flop circuits 3a to 3f. Based on this position, approximately half of the spreading codes corresponding to the newer or older spread signal are determined.

The spread signal output from the sample hold circuits 1a to 1g and the spread code output from the spread code generation circuit 4 are multiplied for each corresponding signal by the first multipliers 5a-1 to 5g-1. Similarly, the spread signals output from the sample hold circuits 1a to 1g and the spread codes output from the inverters 113a to 113g are multiplied for each corresponding signal by the second multipliers 5a-2 to 5g-2. The
The first adder 6-1 adds the output signals of the first multipliers 5a-1 to 5g-1, and the second adder 6-2 is a second multiplier 5a-2 to 5g. -2 output signals are added.

  17 (a), 17 (b), 17 (c), and 17 (d) show characteristic signal waveforms at points D, E, F, and G in FIG. FIG. 17 shows a case where approximately half of the spreading codes whose polarities are inverted by the inverters 113a to 113g correspond to the older half of the spread signal. The output (point D in FIG. 16) of the first adder 6-1 shown in FIG. 17 (a) is the same as the output of the adder shown in FIG. 6 (a). When transitioning to “0”, the peak changes from the positive peak P1 corresponding to the received signal “1” to the negative peak P0 corresponding to the received signal “0”.

On the other hand, at the output of the second adder 6-2 shown in FIG. 17B (point E in FIG. 16), the spreading codes corresponding to approximately half of the older spread signal are polarized by the inverters 113a to 113g. Due to the inversion, a negative peak P0 ′ corresponding to the received signal “0” appears. The reason why the negative peak P0 ′ appears is as described in FIG.
The first peak detector 114 has a peak output from the first adder 6-1 shown in FIG. 17A and a peak output from the second adder 6-2 shown in FIG. And the received signal is demodulated based on the detected peak as shown in FIG.
The second peak detector 115 calculates the sum of absolute values of the output of the first adder 6-1 and the output of the second adder 6-2, and as shown in FIG. Detect peak of sum of values.

FIG. 18 shows a signal waveform when approximately half of the spreading codes whose polarity is inverted by the inverters 113a to 113g correspond to approximately half of the newer one of the spread signals. The output of the first adder 6-1 shown in FIG. 18A is the same as that in FIG.
The output of the second adder 6-2 shown in FIG. 18B is obtained by inverting the polarity of the spread code corresponding to approximately half of the new spread signal by the inverters 113a to 113g. A positive peak P1 ′ corresponding to “1” appears. The reason why the positive peak P1 ′ appears is as described in FIG.

The first peak detector 114 has a peak output from the first adder 6-1 shown in FIG. 18A and a peak output from the second adder 6-2 shown in FIG. And the received signal is demodulated based on the detected peak as shown in FIG.
The second peak detector 115 calculates the sum of absolute values of the output of the first adder 6-1 and the output of the second adder 6-2, and as shown in FIG. Detect peak of sum of values.

In this way, the second peak detector 115 detects the same peak as in FIG. 8C and FIG. 9C, and the spread code control circuit 45 of the spread code generation circuit 4 is the same as in the first embodiment. Every time a peak is detected by the second peak detector 115, the first switch groups 44a to 44g, 44o and the second switch groups 44h to 44n, 44p are alternately switched to shift the spread code. Switch direction.
As described above, according to the present embodiment, the same effects as those of the first embodiment can be obtained.

[Eighth Embodiment]
Next, an eighth embodiment of the present invention will be described. FIG. 19 is a block diagram showing the configuration of the despreading demodulator according to the eighth embodiment of the present invention. The same components as those in FIGS. 1 and 16 are given the same reference numerals. This embodiment uses the same sample and hold circuits 1a to 1g, sample and hold control circuit 2, flip-flop circuits 3a to 3f, spread code generation circuit 4 and multipliers 5a to 5g as in the first embodiment. The first adder 6-1, the second adder 6-2, the first peak detector 114, and the second peak detector 115 similar to those in the seventh embodiment are used, and the multiplier 5a. Inverters 116a to 116g are provided between ˜5g and the second adder 6-2. The first adder 6-1 of the present embodiment adds the output signals of the multipliers 5a to 5g.

  The inverters 116a to 116g correspond to either the newer spread signal or the older spread signal in the order received by the despreading demodulator among the N multiplier output signals of the multipliers 5a to 5g. Half of the signals are output with the polarity inverted, and the remaining signals other than the approximately half of the N multiplier output signals are output as they are. Based on the sample and hold control signals output from the sample and hold control circuit 2 and the flip-flop circuits 3a to 3f, the inverters 116a to 116g check the position of the sample and hold circuit where the latest spread signal is held, and based on this position. Thus, it is the same as in the seventh embodiment that approximately half of the multiplier output signals corresponding to the newer or older spread signal are determined.

The second adder 6-2 adds the output signals of the inverters 116a to 116g. The operations of the first peak detector 114, the second peak detector 115, and the spreading code control circuit 45 of the spreading code generation circuit 4 are the same as those in the seventh embodiment.
Thus, also in this embodiment, the same effect as that of the seventh embodiment can be obtained.

[Ninth Embodiment]
Next, a ninth embodiment of the present invention will be described. FIG. 20 is a block diagram showing the configuration of the despreading demodulator according to the ninth embodiment of the present invention. The same components as those in FIGS. 1 and 16 are given the same reference numerals. This embodiment uses the same sample and hold circuits 1a to 1g, sample and hold control circuit 2, flip-flop circuits 3a to 3f, and spread code generation circuit 4 as the first embodiment, and the seventh embodiment. The first multipliers 5a-1 to 5g-1, the second multipliers 5a-2 to 5g-2, the first adder 6-1, the second adder 6-2, and the first The peak detector 114 and the second peak detector 115 are used, and inverters 117a to 117g are provided between the sample hold circuits 1a to 1g and the multipliers 5a-2 to 5g-2.

  The inverters 117a to 117g correspond to either the spread signal having the newest order or the oldest spread signal in the order received by the despreading demodulator among the N sample and hold output signals of the sample and hold circuits 1a to 1g. Approximately half of the signals are output with the polarity inverted, and the remaining signals other than the approximately half of the N sample hold output signals are output as they are. Based on the sample and hold control signal, the inverters 117a to 117g check the position of the sample and hold circuit where the latest spread signal is held, and based on this position, approximately half of the samples corresponding to the newer or older one of the spread signal The determination of the hold output signal is the same as in the seventh embodiment.

The first multipliers 5a-1 to 5g-1 of the present embodiment use the spread signal output from the sample hold circuits 1a to 1g and the spread code output from the spread code generation circuit 4 for each corresponding signal. The second multipliers 5 a-2 to 5 g-2 multiply the signals output from the inverters 117 a to 117 g and the spread code output from the spread code generation circuit 4 for each corresponding signal.
The operations of the first adder 6-1, the second adder 6-2, the first peak detector 114, the second peak detector 115, and the spreading code control circuit 45 of the spreading code generating circuit 4 are as follows. This is the same as the seventh embodiment.
Thus, also in this embodiment, the same effect as that of the seventh embodiment can be obtained.

  In the seventh to ninth embodiments, in order to obtain the correlation between the spread signal and the spread code, the arrangement order of the spread codes is reversed in accordance with the arrangement order of the spread signals sampled and held by the sample hold circuits 1a to 1g. However, the signals sampled and held by the sample hold circuits 1a to 1g may be arranged in the same order as the input spread signals. In order to arrange them in the same order as the input spread signals, the output of the sample hold control circuit 2 shown in FIGS. 16, 19, and 20 is the flip-flop circuit 3f, and the output of the flip-flop circuit 3f is the flip-flop circuit 3e. The output of the flip-flop circuit 3e is the flip-flop circuit 3d, the output of the flip-flop circuit 3d is the flip-flop circuit 3c, the output of the flip-flop circuit 3c is the flip-flop circuit 3b, and the output of the flip-flop circuit 3b is the flip-flop. What is necessary is just to connect so that each may be input into the circuit 3a. In this case, it is not necessary to reverse the arrangement order of the spread codes, and the first spread code output from the first spread code generation circuit 40-1 was used for spreading the spread signal on the transmission side. The same order as the spreading codes may be used.

[Tenth embodiment]
Next, a tenth embodiment of the present invention will be described. FIG. 21 is a block diagram showing the configuration of the despreading demodulator according to the tenth embodiment of the present invention. The same components as those in FIG. 12 are denoted by the same reference numerals. In the fourth embodiment, the polarity conversion is performed so that approximately half of the spreading codes exhibit two polarity states, inverted and non-inverted, in one cycle of the second clock f2. Since the peak of the adder output in the non-inverted state and the peak of the adder output in the inverted state are output with a time offset, the adder output when approximately half of the spreading codes are in the inverted state is held. The absolute value sum of these peaks is calculated after being held in the circuit 111. On the other hand, in the present embodiment, the peak of the adder output when approximately half of the spreading codes are in the non-inverted state and the peak of the adder output when in the inverted state are obtained simultaneously. .

  The despreading demodulator according to the present embodiment is received by the despreading demodulator among the N hold codes output from the sample and hold circuits 8a to 8g, the spread code generating circuit 9, and the spread code generating circuit 9. Inverters 118a to 118g for outputting approximately half corresponding to either the newer spread signal or the older spread signal with the polarity reversed, and outputting the remaining substantially half of the codes as they are, and a sample hold circuit N first multipliers 10a-1 to 10g-1 for multiplying the spread signals output from 8a to 8g and the spread codes output from the spread code generation circuit 9 for each corresponding signal, and sample and hold circuits N second multipliers 10a-2 to 10g-2 for multiplying the spread signals output from 8a to 8g and the spread codes output from the inverters 118a to 118g for each corresponding signal, A first adder 11-1 that adds the output signals of the first multipliers 10a-1 to 10g-1 and a second adder that outputs the output signals of the second multipliers 10a-2 to 10g-2. And the peak of the output of the first adder 11-1 and the peak of the output of the second adder 11-2 are detected, and the received signal (baseband signal) is detected based on the detected peak. ), The sum of absolute values of the output of the first adder 11-1 and the output of the second adder 11-2 is calculated, and the peak of this sum of absolute values is calculated. And a second peak detector 120 for detecting.

Hereinafter, the operation of the despreading demodulator of this embodiment will be described in detail. The operations of the sample hold circuits 8a to 8g and the spread code generation circuit 9 are the same as those in the fourth embodiment.
The inverters 118a to 118g invert the polarity of approximately half of the N spread codes output from the spread code generation circuit 9 corresponding to either the new spread signal or the old spread signal received. The remaining codes excluding the approximately half of the N spread codes are output as they are.

  In the present embodiment, the latest spread signal is always held in the sample hold circuit 8a, and the oldest spread signal is always held in the sample hold circuit 8g. Therefore, the approximately half of the spreading codes corresponding to the newer one of the spread signals corresponds to the spreading code corresponding to the multipliers 10a, 10b, 10c and 10d (when approximately half is 4) or the multipliers 10a, 10b and 10c. Spreading codes (when approximately half is 3), and approximately half of the spreading codes corresponding to the older spread signal are the spreading codes corresponding to the multipliers 10g, 10f, 10e, 10d (approximately half are 4). Or a spreading code corresponding to the multipliers 10g, 10f, 10e (when approximately half is 3). Therefore, for example, when approximately half of the spreading codes corresponding to the newer one of the spread signals are inverted and output, approximately half of the spreading codes corresponding to the older one of the spread signals are not always inverted. If the corresponding second inverter and second multiplier are omitted, and the output of the first multiplier is directly input to the second adder instead, the circuit scale can be reduced. become.

The spread signal output from the sample hold circuits 8a to 8g and the spread code output from the spread code generation circuit 9 are multiplied for each corresponding signal by the first multipliers 10a-1 to 10g-1, and the sample hold The spread signals output from the circuits 8a to 8g and the spread codes output from the inverters 118a to 118g are multiplied for each corresponding signal by the second multipliers 10a-2 to 10g-2.
The first adder 11-1 adds the output signals of the first multipliers 10a-1 to 10g-1, and the second adder 11-2 includes the second multipliers 10a-2 to 10g. -2 output signals are added.

The first peak detector 119 detects the output peak of the first adder 11-1 and the output peak of the second adder 11-2, and demodulates the received signal based on the detected peak. .
The second peak detector 120 calculates the sum of absolute values of the output of the first adder 11-1 and the output of the second adder 11-2, and detects the peak of the absolute value sum.

  The output of the first adder 11-1 (point D in FIG. 21), the output of the second adder 11-2 (point E in FIG. 21), the output of the first peak detector 119 (F in FIG. 21). Point) and the characteristic signal waveforms at the output of the second peak detector 120 (point G in FIG. 21) are the same as those in FIGS.

Similarly to the fourth embodiment, the clock control circuit 93 of the spread code generation circuit 9 is provided with flip-flop circuits 92a to 92g of the spread code generation circuit 9 each time a peak is detected by the second peak detector 120. The input and output of the clock f2 are alternately stopped and restarted. Alternatively, the clock control circuit 93 may restart the input of the clock f2 after waiting for a certain time after stopping the input of the clock f2 to the spread code generating circuit 9.
Thus, also in this embodiment, the same effect as that of the fourth embodiment can be obtained.

[Eleventh embodiment]
Next, an eleventh embodiment of the present invention will be described. FIG. 22 is a block diagram showing the configuration of the despreading demodulator according to the eleventh embodiment of the present invention. The same components as those in FIGS. 12 and 21 are given the same reference numerals. The present embodiment uses the same sample and hold circuits 8a to 8g, the spread code generation circuit 9 and the multipliers 10a to 10g as the fourth embodiment, and the same first embodiment as the tenth embodiment. Using the adder 11-1, the second adder 11-2, the first peak detector 119, and the second peak detector 120, the multipliers 10a to 10g and the second adder 11-2 Inverters 121a to 121g are provided between them. The first adder 11-1 of the present embodiment adds the output signals of the multipliers 10a to 10g.

  The inverters 121a to 121g are the abbreviations corresponding to either the newer spread signal or the older spread signal in the order received by the despread demodulator among the N multiplier output signals of the multipliers 10a to 10g. Half of the signals are output with the polarity inverted, and the remaining signals other than the approximately half of the N multiplier output signals are output as they are. Of the N multiplier output signals of the multipliers 10a to 10g, approximately half of the multiplier output signals corresponding to the newer one of the spread signals are output signals of the multipliers 10a, 10b, 10c, and 10d (approximately half of them). 4) or output signals of the multipliers 10a, 10b, and 10c (when approximately half is 3), and approximately half of the multiplier output signals corresponding to the older spread signal are the multipliers 10g, 10f, 10e, 10d output signals (when approximately half is 4) or multipliers 10g, 10f, 10e (when approximately half is 3).

The second adder 11-2 adds the output signals of the inverters 121a to 121g. The operations of the first peak detector 119, the second peak detector 120, and the clock control circuit 93 of the spreading code generation circuit 9 are the same as those in the tenth embodiment.
Thus, also in this embodiment, the same effect as that of the tenth embodiment can be obtained.

[Twelfth embodiment]
Next, a twelfth embodiment of the present invention will be described. FIG. 23 is a block diagram showing the configuration of the despreading demodulator according to the twelfth embodiment of the present invention. The same components as those in FIGS. 12 and 21 are given the same reference numerals. The present embodiment uses the same sample and hold circuits 8a to 8g and the spread code generating circuit 9 as those of the fourth embodiment, and the first multipliers 10a-1 to 10a-1 similar to those of the tenth embodiment. 10g-1, the second multipliers 10a-2 to 10g-2, the first adder 11-1, the second adder 11-2, the first peak detector 119, and the second peak detector 120. And inverters 122a to 122g are provided between the sample and hold circuits 8a to 8g and the multipliers 10a-2 to 10g-2.

  The inverters 122a to 122g correspond to either the newer spread signal or the older spread signal in the order received by the despreading demodulator among the N sample hold output signals of the sample hold circuits 8a to 8g. Approximately half of the signals are output with the polarity inverted, and the remaining signals other than the approximately half of the N sample hold output signals are output as they are. Of the N sample and hold output signals of the sample and hold circuits 8a to 8g, approximately half of the output signals corresponding to the newer one of the spread signals are the output signals of the sample and hold circuits 8a, 8b, 8c, and 8d (approximately half of the output signals). 4) or the output signals of the sample-and-hold circuits 8a, 8b, and 8c (when approximately half is 3), and the approximately half of the output signals corresponding to the older spread signal are the sample-and-hold circuits 8g, 8f, 8e and 8d output signals (when approximately half is 4) or sample and hold circuits 8g, 8f and 8e (when approximately half is 3).

  The first multipliers 10a-1 to 10g-1 according to the present embodiment use the spread signal output from the sample hold circuits 8a to 8g and the spread code output from the spread code generation circuit 9 for each corresponding signal. The second multipliers 10 a-2 to 10 g-2 multiply the signals output from the inverters 122 a to 122 g and the spread code output from the spread code generation circuit 9 for each corresponding signal.

The operations of the first adder 11-1, the second adder 11-2, the first peak detector 119, the second peak detector 120, and the clock control circuit 93 of the spreading code generation circuit 9 are This is the same as the embodiment.
Thus, also in this embodiment, the same effect as that of the tenth embodiment can be obtained.

  The sample hold control circuit 2, the spread code generation circuit 4, and the spread code control circuit 45 of the first to third embodiments and the seventh to ninth embodiments are connected to the DSP. (Digital Signal Processor) and the spread code generation circuit 9 and the clock according to the fourth to sixth embodiments and the tenth to twelfth embodiments. It is also possible to configure the control circuit 93 with a DSP.

  The present invention receives a spread signal transmitted by frequency spreading a desired signal by an operation using a spread code, and despreads the received spread signal by an operation using a spread code to extract the desired signal. Applicable to wireless communication.

FIG. 1 is a block diagram showing a configuration of a despreading demodulator according to a first embodiment of the present invention. It is a circuit diagram which shows one structural example of the multiplier used for the de-spreading demodulator of the 1st Embodiment of this invention. It is a circuit diagram which shows one structural example of the adder used for the de-spreading demodulator of the 1st Embodiment of this invention. It is a block diagram which shows one structural example of the spreading code generation circuit used for the de-spreading demodulator of the 1st Embodiment of this invention. It is a figure explaining the operation | movement of the spreading code generation circuit used for the despreading demodulator of the 1st Embodiment of this invention. It is a figure for demonstrating a problem at the time of omitting a polarity conversion circuit in the 1st Embodiment of this invention. It is a figure which shows the relationship between the 2nd clock used for the de-spreading demodulator of the 1st Embodiment of this invention, and the operation state of a polarity conversion circuit. It is a figure which shows an example of the signal waveform of the addition signal obtained by the despreading demodulator of the 1st Embodiment of this invention, a baseband signal, and the output signal of a 2nd peak detector. It is a figure which shows the other example of the signal waveform of the addition signal obtained by the de-spreading demodulator of the 1st Embodiment of this invention, a baseband signal, and the output signal of a 2nd peak detector. It is a block diagram which shows the structure of the de-spreading demodulator used as the 2nd Embodiment of this invention. It is a block diagram which shows the structure of the de-spreading demodulator used as the 3rd Embodiment of this invention. It is a block diagram which shows the structure of the de-spreading demodulator used as the 4th Embodiment of this invention. It is a block diagram which shows one structural example of the spreading code generation circuit used for the de-spreading demodulator of the 4th Embodiment of this invention. It is a block diagram which shows the structure of the de-spreading demodulator used as the 5th Embodiment of this invention. It is a block diagram which shows the structure of the de-spreading demodulator used as the 6th Embodiment of this invention. It is a block diagram which shows the structure of the de-spreading demodulator used as the 7th Embodiment of this invention. The output signal of the first adder, the output signal of the second adder, the baseband signal, and the output signal of the second peak detector obtained by the despreading demodulator of the seventh embodiment of the present invention It is a figure which shows one example of a waveform. The output signal of the first adder, the output signal of the second adder, the baseband signal, and the output signal of the second peak detector obtained by the despreading demodulator of the seventh embodiment of the present invention It is a figure which shows the other example of a waveform. It is a block diagram which shows the structure of the de-spreading demodulator used as the 8th Embodiment of this invention. It is a block diagram which shows the structure of the de-spreading demodulator used as the 9th Embodiment of this invention. It is a block diagram which shows the structure of the de-spreading demodulator used as the 10th Embodiment of this invention. It is a block diagram which shows the structure of the de-spreading demodulator used as the 11th Embodiment of this invention. It is a block diagram which shows the structure of the de-spreading demodulator which becomes the 12th Embodiment of this invention. It is a block diagram which shows the structure of the despreading demodulator which is a 1st prior art. It is a block diagram which shows the structure of the despreading demodulator which is a 2nd prior art. It is a signal waveform diagram of an addition signal and a baseband signal obtained by a despreading demodulator that is the second prior art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1a-1g, 8a-8g ... Sample hold circuit, 2 ... Sample hold control circuit, 3a-3f ... Flip-flop circuit, 4, 9 ... Spreading code generator circuit, 5a-5g, 5a-1-5g-1, 5a- 2-5g-2, 10a-10g, 10a-1-10g-1, 10a-2-10g-2 ... multiplier, 6, 6-1, 6-2, 11, 11-1, 11-2 ... addition 7, 12, 114, 119 ... first peak detector, 101-106 ... polarity conversion circuit, 107, 110 ... distributor, 108, 111 ... hold circuit, 109, 112, 115, 120 ... second Peak detectors 113a to 113g, 116a to 116g, 117a to 117g, 118a to 118g, 121a to 121g, 122a to 122g ... inverters, 40-1 ... first spreading code generation circuit, 40-2 Second spreading code generation circuit, 41, 42 ... exclusive OR circuit, 43a to 43n ... flip-flop circuit, 44a to 44p ... switch, 45 ... spreading code control circuit, 91 ... exclusive OR circuit, 92a to 92g ... Flip-flop circuit, 93 ... Clock control circuit.

Claims (15)

N (N is an integer of 2 or more) sample and hold circuits for holding and holding the received spread signal;
Sample hold control for controlling the N sample and hold circuits to sequentially perform a sample holding operation in synchronization with the first clock, with a first clock having the same frequency as the clock used for spreading the spread signal being input. Circuit,
A first spreading code generation circuit for generating N first spreading codes in synchronization with a second clock;
A second spreading code generation circuit for generating N second spreading codes obtained by rearranging the first spreading codes in reverse direction in synchronization with the second clock;
Of the N spreading codes output from the first spreading code generating circuit or the second spreading code generating circuit, the received order corresponds to either the newer spreading signal or the older spreading signal. A polarity conversion circuit that performs polarity conversion so that approximately half of the second clock exhibits two polarity states of inversion and non-inversion during one cycle of the second clock, and outputs the remaining approximately half of the codes as they are;
N multipliers that multiply the signal output from the sample hold circuit and the spreading code output from the polarity conversion circuit for each corresponding signal;
An adder for adding the outputs of the N multipliers;
A first peak detector that detects a peak of the output of the adder and demodulates a received signal based on the detected peak;
A hold circuit that holds the adder output when the substantially half of the spreading codes are in the first state of either the inversion state or the non-inversion state;
Calculating the sum of absolute values of the output of the adder and the output of the hold circuit when approximately half of the spreading codes are in the second state different from the first state in the inverted state or the non-inverted state. A second peak detector for detecting the peak of this sum of absolute values;
Each time a peak is detected by the second peak detector, the input of the first spreading code from the first spreading code generation circuit to the polarity conversion circuit and the second spreading code generation circuit from the second spreading code generation circuit A despreading demodulator comprising: a spreading code control circuit that alternately switches the input of the second spreading code to the polarity conversion circuit. N (N is an integer of 2 or more) sample and hold circuits for holding and holding the received spread signal;
Sample hold control for controlling the N sample and hold circuits to sequentially perform a sample holding operation in synchronization with the first clock, with a first clock having the same frequency as the clock used for spreading the spread signal being input. Circuit,
A first spreading code generation circuit for generating N first spreading codes in synchronization with a second clock;
A second spreading code generation circuit for generating N second spreading codes obtained by rearranging the first spreading codes in reverse direction in synchronization with the second clock;
N multipliers that multiply the signal output from the sample and hold circuit and the spreading code output from the first spreading code generation circuit or the second spreading code generation circuit for each corresponding signal;
Of the multiplier output signals of the N multipliers, approximately half corresponding to either the newest spread signal or the oldest spread signal received in one cycle of the second clock. A polarity conversion circuit that performs polarity conversion so as to exhibit two polarity states of inversion and non-inversion, and outputs the remaining substantially half of the multiplier output signals as they are;
An adder for adding the outputs of the polarity conversion circuit;
A first peak detector that detects a peak of the output of the adder and demodulates a received signal based on the detected peak;
A hold circuit that holds the adder output when the substantially half of the spreading codes are in the first state of either the inversion state or the non-inversion state;
Calculating the sum of absolute values of the output of the adder and the output of the hold circuit when approximately half of the spreading codes are in the second state different from the first state in the inverted state or the non-inverted state. A second peak detector for detecting the peak of this sum of absolute values;
Each time a peak is detected by the second peak detector, the input of the first spreading code from the first spreading code generation circuit to the multiplier and the multiplication from the second spreading code generation circuit. A despreading demodulator comprising: a spreading code control circuit that alternately switches the input of the second spreading code to the amplifier. N (N is an integer of 2 or more) sample and hold circuits for holding and holding the received spread signal;
Sample hold control for controlling the N sample and hold circuits to sequentially perform a sample holding operation in synchronization with the first clock, with a first clock having the same frequency as the clock used for spreading the spread signal being input. Circuit,
A first spreading code generation circuit for generating N first spreading codes in synchronization with a second clock;
A second spreading code generation circuit for generating N second spreading codes obtained by rearranging the first spreading codes in reverse direction in synchronization with the second clock;
Of the sample-and-hold output signals of the N sample-and-hold circuits, approximately half corresponding to either the newest spread signal or the oldest spread signal received during one cycle of the second clock A polarity conversion circuit that converts the polarity so as to exhibit two polarity states of inversion and non-inversion, and outputs the remaining half of the sample and hold output signals as they are.
N multipliers that multiply the signal output from the polarity conversion circuit and the spreading code output from the first spreading code generation circuit or the second spreading code generation circuit for each corresponding signal;
An adder for adding the outputs of the N multipliers;
A first peak detector that detects a peak of the output of the adder and demodulates a received signal based on the detected peak;
A hold circuit that holds the adder output when the substantially half of the spreading codes are in the first state of either the inversion state or the non-inversion state;
Calculating the sum of absolute values of the output of the adder and the output of the hold circuit when approximately half of the spreading codes are in the second state different from the first state in the inverted state or the non-inverted state. A second peak detector for detecting the peak of this sum of absolute values;
Each time a peak is detected by the second peak detector, the input of the first spreading code from the first spreading code generation circuit to the multiplier and the multiplication from the second spreading code generation circuit. A despreading demodulator comprising: a spreading code control circuit that alternately switches the input of the second spreading code to the amplifier. N (N is an integer of 2 or more) sample and hold circuits that sample and hold the received spread signal in synchronization with a first clock having the same frequency as the clock used for spreading the spread signal;
A spreading code generating circuit for generating N spreading codes in synchronization with the second clock;
Of the N spreading codes output from the spreading code generating circuit, approximately half corresponding to either the newer spreading signal or the older spreading signal in the received order is 1 of the second clock. A polarity conversion circuit that converts the polarity so as to exhibit two polarity states of inversion and non-inversion during the period, and outputs the remaining half of the codes as they are;
N multipliers that multiply the signal output from the sample hold circuit and the spreading code output from the polarity conversion circuit for each corresponding signal;
An adder for adding the outputs of the N multipliers;
A first peak detector that detects a peak of the output of the adder and demodulates a received signal based on the detected peak;
A hold circuit that holds the adder output when the substantially half of the spreading codes are in the first state of either the inversion state or the non-inversion state;
Calculating the sum of absolute values of the output of the adder and the output of the hold circuit when approximately half of the spreading codes are in the second state different from the first state in the inverted state or the non-inverted state. A second peak detector for detecting the peak of this sum of absolute values;
A despreading demodulator comprising: a clock control circuit that controls input of the second clock to the spreading code generation circuit in accordance with detection of a peak by the second peak detector. N (N is an integer of 2 or more) sample and hold circuits that sample and hold the received spread signal in synchronization with a first clock having the same frequency as the clock used for spreading the spread signal;
A spreading code generating circuit for generating N spreading codes in synchronization with the second clock;
N multipliers that multiply the signal output from the sample and hold circuit and the spreading code output from the spreading code generation circuit for each corresponding signal;
Of the multiplier output signals of the N multipliers, approximately half corresponding to either the newest spread signal or the oldest spread signal received in one cycle of the second clock. A polarity conversion circuit that performs polarity conversion so as to exhibit two polarity states of inversion and non-inversion, and outputs the remaining substantially half of the multiplier output signals as they are;
An adder for adding the outputs of the polarity conversion circuit;
A first peak detector that detects a peak of the output of the adder and demodulates a received signal based on the detected peak;
A hold circuit that holds the adder output when the substantially half of the spreading codes are in the first state of either the inversion state or the non-inversion state;
Calculating the sum of absolute values of the output of the adder and the output of the hold circuit when approximately half of the spreading codes are in the second state different from the first state in the inverted state or the non-inverted state. A second peak detector for detecting the peak of this sum of absolute values;
A despreading demodulator comprising: a clock control circuit that controls input of the second clock to the spreading code generation circuit in accordance with detection of a peak by the second peak detector. N (N is an integer of 2 or more) sample and hold circuits that sample and hold the received spread signal in synchronization with a first clock having the same frequency as the clock used for spreading the spread signal;
A spreading code generating circuit for generating N spreading codes in synchronization with the second clock;
Of the sample-and-hold output signals of the N sample-and-hold circuits, approximately half corresponding to either the newest spread signal or the oldest spread signal received during one cycle of the second clock A polarity conversion circuit that converts the polarity so as to exhibit two polarity states of inversion and non-inversion, and outputs the remaining half of the sample and hold output signals as they are.
N multipliers that multiply the signal output from the polarity conversion circuit and the spreading code output from the spreading code generation circuit for each corresponding signal;
An adder for adding the outputs of the N multipliers;
A peak detector for detecting the peak of the output of the adder;
A first peak detector that detects a peak of the output of the adder and demodulates a received signal based on the detected peak;
A hold circuit that holds the adder output when the substantially half of the spreading codes are in the first state of either the inversion state or the non-inversion state;
Calculating the sum of absolute values of the output of the adder and the output of the hold circuit when approximately half of the spreading codes are in the second state different from the first state in the inverted state or the non-inverted state. A second peak detector for detecting the peak of this sum of absolute values;
A despreading demodulator comprising: a clock control circuit that controls input of the second clock to the spreading code generation circuit in accordance with detection of a peak by the second peak detector. N (N is an integer of 2 or more) sample and hold circuits for holding and holding the received spread signal;
Sample hold control for controlling the N sample and hold circuits to sequentially perform a sample holding operation in synchronization with the first clock, with a first clock having the same frequency as the clock used for spreading the spread signal being input. Circuit,
A first spreading code generation circuit for generating N first spreading codes in synchronization with a second clock;
A second spreading code generation circuit for generating N second spreading codes obtained by rearranging the first spreading codes in reverse direction in synchronization with the second clock;
Of the N spreading codes output from the first spreading code generating circuit or the second spreading code generating circuit, the received order corresponds to either the newer spreading signal or the older spreading signal. N inverters that output the inverted half of the sign, and output the remaining half of the codes as they are,
N first multipliers that multiply the signal output from the sample and hold circuit and the spreading code output from the first spreading code generating circuit or the second spreading code generating circuit for each corresponding signal; ,
N second multipliers that multiply the signal output from the sample and hold circuit and the spreading code output from the inverter for each corresponding signal;
A first adder for adding the outputs of the N first multipliers;
A second adder for adding the outputs of the N second multipliers;
A first peak detector for detecting a peak of the output of the first adder and a peak of the output of the second adder, and demodulating a received signal based on the detected peak;
A second peak detector for calculating a sum of absolute values of the output of the first adder and the output of the second adder and detecting a peak of the sum of the absolute values;
Each time a peak is detected by the second peak detector, the input of the first spreading code and the second spreading from the first spreading code generation circuit to the first multiplier and inverter A despreading demodulator comprising a spreading code control circuit for alternately switching input of the second spreading code from a code generating circuit to the first multiplier and inverter. N (N is an integer of 2 or more) sample and hold circuits for holding and holding the received spread signal;
Sample hold control for controlling the N sample and hold circuits to sequentially perform a sample holding operation in synchronization with the first clock, with a first clock having the same frequency as the clock used for spreading the spread signal being input. Circuit,
A first spreading code generation circuit for generating N first spreading codes in synchronization with a second clock;
A second spreading code generation circuit for generating N second spreading codes obtained by rearranging the first spreading codes in reverse direction in synchronization with the second clock;
N multipliers that multiply the signal output from the sample and hold circuit and the spreading code output from the first spreading code generation circuit or the second spreading code generation circuit for each corresponding signal;
Of the multiplier output signals of the N multipliers, approximately half corresponding to either the newer spread signal or the older spread signal received in order is output with the polarity inverted, and the remaining short N inverters that output half of the multiplier output signals as they are,
A first adder for adding the outputs of the N multipliers;
A second adder for adding the outputs of the N inverters;
A first peak detector for detecting a peak of the output of the first adder and a peak of the output of the second adder, and demodulating a received signal based on the detected peak;
A second peak detector for calculating a sum of absolute values of the output of the first adder and the output of the second adder and detecting a peak of the sum of the absolute values;
Each time a peak is detected by the second peak detector, the input of the first spreading code from the first spreading code generation circuit to the multiplier and the multiplication from the second spreading code generation circuit. A despreading demodulator comprising: a spreading code control circuit that alternately switches the input of the second spreading code to the amplifier. N (N is an integer of 2 or more) sample and hold circuits for holding and holding the received spread signal;
Sample hold control for controlling the N sample and hold circuits to sequentially perform a sample holding operation in synchronization with the first clock, with a first clock having the same frequency as the clock used for spreading the spread signal being input. Circuit,
A first spreading code generation circuit for generating N first spreading codes in synchronization with a second clock;
A second spreading code generation circuit for generating N second spreading codes obtained by rearranging the first spreading codes in reverse direction in synchronization with the second clock;
Of the sample-and-hold output signals of the N sample-and-hold circuits, approximately half corresponding to either the newer spread signal or the older spread signal received is output with the polarity reversed, and the rest About half of the sample and hold output signals, N inverters that output as they are,
N first multipliers that multiply the signal output from the sample and hold circuit and the spreading code output from the first spreading code generating circuit or the second spreading code generating circuit for each corresponding signal; ,
N second multipliers that multiply the signal output from the inverter and the spreading code output from the first spreading code generation circuit or the second spreading code generation circuit for each corresponding signal;
A first adder for adding the outputs of the N first multipliers;
A second adder for adding the outputs of the N second multipliers;
A first peak detector for detecting a peak of the output of the first adder and a peak of the output of the second adder, and demodulating a received signal based on the detected peak;
A second peak detector for calculating a sum of absolute values of the output of the first adder and the output of the second adder and detecting a peak of the sum of the absolute values;
Each time the peak is detected by the peak detector, the input of the first spreading code from the first spreading code generation circuit to the first multiplier and the second multiplier and the second A despreading demodulator comprising a spreading code control circuit for alternately switching input of the second spreading code from the spreading code generation circuit to the first multiplier and the second multiplier. N (N is an integer of 2 or more) sample and hold circuits that sample and hold the received spread signal in synchronization with a first clock having the same frequency as the clock used for spreading the spread signal;
A spreading code generating circuit for generating N spreading codes in synchronization with the second clock;
Of the N spreading codes output from this spreading code generating circuit, the half of the signals received in the newer order or the older spreading signal corresponding to either the newer spreading signal or the older spreading signal is output with the polarity reversed, N inverters that output the remaining half of the codes as they are;
N first multipliers that multiply the signal output from the sample and hold circuit and the spreading code output from the spreading code generation circuit for each corresponding signal;
N second multipliers that multiply the signal output from the sample and hold circuit and the spreading code output from the inverter for each corresponding signal;
A first adder for adding the outputs of the N first multipliers;
A second adder for adding the outputs of the N second multipliers;
A first peak detector for detecting a peak of the output of the first adder and a peak of the output of the second adder, and demodulating a received signal based on the detected peak;
A second peak detector for calculating a sum of absolute values of the output of the first adder and the output of the second adder and detecting a peak of the sum of the absolute values;
A despreading demodulator comprising: a clock control circuit that controls input of the second clock to the spreading code generation circuit in accordance with detection of a peak by the second peak detector. N (N is an integer of 2 or more) sample and hold circuits that sample and hold the received spread signal in synchronization with a first clock having the same frequency as the clock used for spreading the spread signal;
A spreading code generating circuit for generating N spreading codes in synchronization with the second clock;
N multipliers that multiply the signal output from the sample and hold circuit and the spreading code output from the spreading code generation circuit for each corresponding signal;
Of the multiplier output signals of the N multipliers, approximately half corresponding to either the newer spread signal or the older spread signal received in order is output with the polarity inverted, and the remaining short N inverters that output half of the multiplier output signals as they are,
A first adder for adding the outputs of the N multipliers;
A second adder for adding the outputs of the N inverters;
A first peak detector for detecting a peak of the output of the first adder and a peak of the output of the second adder, and demodulating a received signal based on the detected peak;
A second peak detector for calculating a sum of absolute values of the output of the first adder and the output of the second adder and detecting a peak of the sum of the absolute values;
A despreading demodulator comprising: a clock control circuit that controls input of the second clock to the spreading code generation circuit in accordance with detection of a peak by the second peak detector. N (N is an integer of 2 or more) sample and hold circuits that sample and hold the received spread signal in synchronization with a first clock having the same frequency as the clock used for spreading the spread signal;
A spreading code generating circuit for generating N spreading codes in synchronization with the second clock;
Of the sample-and-hold output signals of the N sample-and-hold circuits, approximately half corresponding to either the newer spread signal or the older spread signal received is output with the polarity reversed, and the rest About half of the sample and hold output signals, N inverters that output as they are,
N first multipliers that multiply the signal output from the sample and hold circuit and the spreading code output from the spreading code generation circuit for each corresponding signal;
N second multipliers that multiply the signal output from the inverter and the spreading code output from the spreading code generation circuit for each corresponding signal;
A first adder for adding the outputs of the N first multipliers;
A second adder for adding the outputs of the N second multipliers;
A first peak detector for detecting a peak of the output of the first adder and a peak of the output of the second adder, and demodulating a received signal based on the detected peak;
A second peak detector for calculating a sum of absolute values of the output of the first adder and the output of the second adder and detecting a peak of the sum of the absolute values;
A despreading demodulator comprising: a clock control circuit that controls input of the second clock to the spreading code generation circuit in accordance with detection of a peak by the second peak detector. The despread demodulator according to any one of claims 4, 5, 6, 10, 11, and 12,
The clock control circuit alternately switches between stopping and restarting input of the second clock to the spreading code generation circuit each time a peak is detected by the second peak detector. Despread demodulator. The despread demodulator according to any one of claims 4, 5, 6, 10, 11, and 12,
The clock control circuit stops the input of the second clock to the spreading code generation circuit for a fixed time when a peak is detected by the second peak detector, vessel. The despread demodulator according to any one of claims 1 to 12,
A despread demodulator comprising the spread code generating circuit comprising a flip-flop circuit, an exclusive OR circuit, and a switch for controlling an output path of the flip-flop circuit.

Images