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JP2005159199A - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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JP2005159199A
JP2005159199A JP2003398540A JP2003398540A JP2005159199A JP 2005159199 A JP2005159199 A JP 2005159199A JP 2003398540 A JP2003398540 A JP 2003398540A JP 2003398540 A JP2003398540 A JP 2003398540A JP 2005159199 A JP2005159199 A JP 2005159199A
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wiring
semiconductor
wiring board
semiconductor device
semiconductor structure
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JP4324732B2 (en
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Ichiro Mihara
一郎 三原
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Casio Computer Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

【課題】 上層配線を有する半導体装置において、それが搭載される回路基板を含む全体としての小型化を図る。
【解決手段】 ベース板１の上面にはＣＳＰと呼ばれる半導体構成体２が設けられ、その周囲には配線板１３が設けられ、それらの上面には第１、第２の上層配線２８、３２が設けられ、第２の上層配線３２の接続パッド部上には半田ボール３５が設けられている。ベース板１の下面には第１、第２の下層配線３８、４２が配線板１３に接続されて設けられている。そして、最下層絶縁膜４３の下面に電子部品を第２の下層配線４２に接続させて搭載するようにして、電子機器のより一層の小型化が可能で、且つ、配線長を最短として回路特性劣化を抑制することができる。
【選択図】 図１PROBLEM TO BE SOLVED: To reduce the size of a semiconductor device having an upper layer wiring as a whole including a circuit board on which it is mounted.
A semiconductor structure 2 called CSP is provided on the upper surface of a base plate 1, a wiring board 13 is provided around the semiconductor structure 2, and first and second upper-layer wirings 28 and 32 are provided on the upper surface thereof. A solder ball 35 is provided on the connection pad portion of the second upper layer wiring 32. First and second lower layer wirings 38 and 42 are connected to the wiring board 13 on the lower surface of the base plate 1. The electronic component can be mounted on the lower surface of the lowermost insulating film 43 while being connected to the second lower layer wiring 42, so that the electronic device can be further miniaturized and the circuit length can be minimized. Deterioration can be suppressed.
[Selection] Figure 1

Description

この発明は半導体装置およびその製造方法に関する。   The present invention relates to a semiconductor device and a manufacturing method thereof.

近年、携帯電話に代表されるような携帯型電子機器の小型化に相俟ってＣＳＰ(chip size package)と呼ばれる半導体装置が開発されている。このＣＳＰは、複数の外部接続用の接続パッドが形成されたベアーの半導体装置の上面にパッシベーション膜（中間絶縁膜）を設け、このパッシベーション膜の各接続パッドの対応部に開口部を形成し、該開口部を介して各接続パッドに接続される配線を形成し、各配線の他端部側に柱状の外部接続用電極を形成するとともに、各外部接続用電極間に封止材を充填したものである。   In recent years, a semiconductor device called a CSP (chip size package) has been developed in conjunction with downsizing of a portable electronic device represented by a mobile phone. This CSP is provided with a passivation film (intermediate insulating film) on the upper surface of a bare semiconductor device in which a plurality of connection pads for external connection are formed, and an opening is formed in a corresponding portion of each connection pad of the passivation film. A wiring connected to each connection pad is formed through the opening, a columnar external connection electrode is formed on the other end side of each wiring, and a sealing material is filled between each external connection electrode Is.

このような、ＣＳＰによれば、各柱状の外部接続用電極上に半田ボールを形成しておくことにより、接続端子を有する回路基板にフェースダウン方式でボンディングすることができ、実装面積をほぼベアーの半導体装置と同一のサイズとすることが可能となるので、従来のワイヤーボンディング等を用いたフェースアップ方式のボンディング方法に比し、電子機器を大幅に小型化することが可能である。   According to such CSP, by forming solder balls on each columnar external connection electrode, it is possible to bond to a circuit board having connection terminals by a face-down method, and the mounting area is almost bare. Therefore, the electronic device can be significantly reduced in size as compared with a conventional face-up bonding method using wire bonding or the like.

このような、ＣＳＰにおいて、生産性を高めるために、ウエハ状態の半導体基板にパッシベーション膜、配線、外部接続用電極、および封止材を形成し、さらに、封止材で覆われずに露出された外部接続用電極の上面に半田ボールを設けた後、ダイシングラインで切断するようにしたものがある（例えば、特許文献１参照）。   In such a CSP, in order to increase productivity, a passivation film, wiring, external connection electrodes, and a sealing material are formed on a semiconductor substrate in a wafer state, and further exposed without being covered with the sealing material. In some cases, a solder ball is provided on the upper surface of the external connection electrode and then cut by a dicing line (see, for example, Patent Document 1).

特開２００１−１６８１２８号公報JP 2001-168128 A

ところで、上記従来の半導体装置では、集積化が進むに従って、外部接続用電極の数が増加すると、次のような問題があった。すなわち、上述した如く、ＣＳＰは、ベアーの半導体装置の上面に外部接続用電極を配列するので、通常は、マトリクス状に配列するのであるが、そのために、外部接続用電極数の多い半導体装置の場合には、外部接続用電極のサイズおよびピッチが極端に小さくなってしまう欠点を有しており、このため、ベアーの半導体装置のサイズの割に外部接続用電極が多いものには適用できないものであった。   By the way, the conventional semiconductor device has the following problems when the number of external connection electrodes increases as integration increases. That is, as described above, the CSP arranges the external connection electrodes on the upper surface of the bare semiconductor device. Therefore, the CSP is usually arranged in a matrix. For this reason, the CSP has a large number of external connection electrodes. In some cases, the size and pitch of the external connection electrodes become extremely small, and therefore, this is not applicable to the case where the number of external connection electrodes is large for the size of the bare semiconductor device. Met.

すなわち、外部接続用電極のサイズおよびピッチが極端に小さくなれば、回路基板との位置合わせが困難であるばかりでなく、接合強度が不足する、ボンディング時に電極間の短絡が発生する、通常はシリコン基板からなる半導体基板と回路基板の線膨張係数の差に起因して発生する応力により外部接続用電極が破壊される等の致命的な問題が発生するのである。   That is, if the size and pitch of the electrodes for external connection become extremely small, not only alignment with the circuit board is difficult, but also the bonding strength is insufficient, and a short circuit between the electrodes occurs during bonding, usually silicon A fatal problem such as destruction of the external connection electrode occurs due to the stress generated due to the difference between the linear expansion coefficients of the semiconductor substrate and the circuit board.

また、上記従来の半導体装置では、上述の如く、回路基板にフェースダウン方式でボンディングすることができ、実装面積をほぼベアーの半導体装置と同一のサイズとすることが可能となるので、従来のワイヤーボンディング等を用いたフェースアップ方式のボンディング方法に比し、電子機器を大幅に小型化することが可能であるが、それでも小型化に限界があった。   Further, in the conventional semiconductor device, as described above, it can be bonded to the circuit board in a face-down manner, and the mounting area can be made almost the same size as the bare semiconductor device. Compared to the face-up type bonding method using bonding or the like, the electronic device can be greatly downsized, but there is still a limit to downsizing.

すなわち、回路基板に他の必要な電子部品、例えば、他の半導体装置、コンデンサや抵抗等のチップ部品を搭載し、これらの電子部品に上記従来の半導体装置を接続すると、これらが平面的に配置されるため、小型化に限界があった。また、平面的に配置される関係から、配線長が増大し、インピーダンス（浮遊容量等）の増加等の問題が生じ、回路特性が劣化することがあった。   That is, when other necessary electronic components such as other semiconductor devices, chip components such as capacitors and resistors are mounted on the circuit board, and the conventional semiconductor device is connected to these electronic components, these are arranged in a plane. Therefore, there was a limit to miniaturization. In addition, due to the planar arrangement, the wiring length increases, causing problems such as an increase in impedance (such as stray capacitance), and circuit characteristics may deteriorate.

そこで、この発明は、外部接続用電極の数が増加しても、そのサイズおよびピッチを必要な大きさにすることが可能となり、且つ、電子機器のより一層の小型化が可能で、配線長を最短として回路特性劣化を抑制することが可能となる新規な半導体装置およびその製造方法を提供することを目的とする。   Therefore, even if the number of external connection electrodes increases, the present invention makes it possible to make the size and pitch necessary, and to further reduce the size of the electronic device, and to increase the wiring length. It is an object of the present invention to provide a novel semiconductor device and a method of manufacturing the same that can suppress deterioration of circuit characteristics.

請求項１に記載の発明は、ベース部材と、前記ベース部材上に設けられ、且つ、半導体基板および該半導体基板上に設けられた複数の外部接続用電極を有する少なくとも１つの半導体構成体と、前記半導体構成体に対応する部分に開口部を有し、該開口部内に前記半導体構成体を収納して前記半導体構成体の周囲に配置された配線板と、前記半導体構成体および前記配線板上に前記半導体構成体の外部接続用電極および前記配線板に電気的に接続されて設けられ、接続パッド部を有する少なくとも１層の上層配線とを備えていることを特徴とするものである。
請求項２に記載の発明は、請求項１に記載の発明において、前記配線板の開口部と前記半導体構成体との間には隙間が設けられ、該隙間に充填材が充填されていることを特徴とするものである。
請求項３に記載の発明は、請求項１に記載の発明において、前記最上層の上層配線の接続パッド部の少なくとも一部は前記配線板上に配置されていることを特徴とするものである。
請求項４に記載の発明は、請求項１に記載の発明において、前記ベース部材はプリプレグ材からなることを特徴とするものである。
請求項５に記載の発明は、請求項１に記載の発明において、前記配線板は多層配線板からなることを特徴とするものである。
請求項６に記載の発明は、請求項１に記載の発明において、前記半導体構成体は、前記外部接続用電極としての柱状電極を有するものであることを特徴とするものである。
請求項７に記載の発明は、請求項１に記載の発明において、前記半導体構成体は、前記外部接続用電極としての接続パッド部を有する配線を有するものであることを特徴とするものである。
請求項８に記載の発明は、請求項１に記載の発明において、前記充填材の熱膨張係数は、前記半導体構成体の半導体基板の熱膨張係数よりも大きく、且つ、前記配線板の絶縁基板の熱膨張係数よりも小さいことを特徴とするものである。
請求項９に記載の発明は、請求項８に記載の発明において、前記充填材は、樹脂中に熱膨張係数低下用材料が混入されたものからなることを特徴とするものである。
請求項１０に記載の発明は、請求項１に記載の発明において、前記最上層の上層配線の接続パッド部を除く部分を覆う最上層絶縁膜を有することを特徴とするものである。
請求項１１に記載の発明は、請求項１０に記載の発明において、前記最上層の上層配線の接続パッド部上に半田ボールが設けられていることを特徴とするものである。
請求項１２に記載の発明は、請求項１に記載の発明において、前記ベース部材下に少なくとも１層の下層配線が前記配線板に電気的に接続されて設けられていることを特徴とするものである。
請求項１３に記載の発明は、請求項１２に記載の発明において、前記最下層の下層配線を覆う最下層絶縁膜を有することを特徴とするものである。
請求項１４に記載の発明は、請求項１１に記載の発明において、前記最下層の下層配線の接続パッド部を除く部分を覆う最下層絶縁膜を有することを特徴とするものである。
請求項１５に記載の発明は、請求項１４に記載の発明において、前記最下層絶縁膜下に電子部品が前記最下層の下層配線の接続パッド部に接続されて設けられていることを特徴とするものである。
請求項１６に記載の発明は、請求項１に記載の発明において、前記半導体構成体を複数個備えていることを特徴とするものである。
請求項１７に記載の発明は、各々が半導体基板および該半導体基板上に設けられた複数の外部接続用電極を有する複数の半導体構成体と前記各半導体構成体に対応する部分に開口部を有する集合配線板とを、前記集合配線板の各開口部内に前記半導体構成体が配置されるようにベース部材上に配置する工程と、前記半導体構成体および前記集合配線板上に、接続パッド部を有する少なくとも１層の上層配線を前記半導体構成体の外部接続用電極および前記配線板に電気的に接続させて形成する工程と、前記半導体構成体間における前記ベース部材および前記集合配線板を少なくとも切断して前記半導体構成体が少なくとも１つ含まれる半導体装置を複数個得る工程と、を有することを特徴とするものである。
請求項１８に記載の発明は、請求項１７に記載の発明において、前記集合配線板の各開口部内に前記半導体構成体を配置する工程は、前記集合配線板の各開口部と前記各半導体構成体との間に隙間が形成されるように配置し、前記隙間に充填材を充填する工程を含むことを特徴とするものである。
請求項１９に記載の発明は、請求項１８に記載の発明において、前記集合配線板の各開口部と前記各半導体構成体間に形成された前記隙間に充填材を充填する工程は、前記集合配線板および前記半導体構成体の上面に上層絶縁膜を配置し、加熱加圧板により前記上層絶縁膜を加熱加圧する工程を含むことを特徴とするものである。
請求項２０に記載の発明は、請求項１７に記載の発明において、前記最上層の上層配線の接続パッド部の少なくとも一部を前記集合配線板上に配置することを特徴とするものである。
請求項２１に記載の発明は、請求項１７に記載の発明において、前記ベース部材はプリプレグ材からなることを特徴とするものである。
請求項２２に記載の発明は、請求項１７に記載の発明において、前記集合配線板は多層配線板からなることを特徴とするものである。。
請求項２３に記載の発明は、請求項１７に記載の発明において、前記切断は、前記半導体構成体が複数個含まれるように切断することを特徴とするものである。
請求項２４に記載の発明は、請求項１７に記載の発明において、前記半導体構成体の前記ベース部材上への配置は、切断前の前記集合配線板の開口部の周囲における配線形成部が良品と判定された部分に対応する位置にのみ配置することを特徴とするものである。
請求項２５に記載の発明は、請求項２４に記載の発明において、切断前の前記集合配線板の開口部のうち、前記半導体構成体が配置されない開口部内に充填材を充填することを特徴とするものである。 The invention according to claim 1 is provided with a base member, at least one semiconductor structure provided on the base member and having a semiconductor substrate and a plurality of external connection electrodes provided on the semiconductor substrate; A wiring board having an opening in a portion corresponding to the semiconductor structure, the semiconductor structure being housed in the opening and disposed around the semiconductor structure, and the semiconductor structure and the wiring board; And an external connection electrode of the semiconductor structure and at least one upper layer wiring having a connection pad portion, which is electrically connected to the wiring board.
According to a second aspect of the present invention, in the first aspect of the present invention, a gap is provided between the opening of the wiring board and the semiconductor structure, and the gap is filled with a filler. It is characterized by.
According to a third aspect of the present invention, in the first aspect of the present invention, at least a part of a connection pad portion of the uppermost layer upper layer wiring is arranged on the wiring board. .
According to a fourth aspect of the present invention, in the first aspect of the present invention, the base member is made of a prepreg material.
The invention according to claim 5 is the invention according to claim 1, wherein the wiring board is formed of a multilayer wiring board.
The invention according to claim 6 is the invention according to claim 1, wherein the semiconductor structure has a columnar electrode as the external connection electrode.
According to a seventh aspect of the present invention, in the first aspect of the invention, the semiconductor structure includes a wiring having a connection pad portion as the external connection electrode. .
The invention according to claim 8 is the invention according to claim 1, wherein the thermal expansion coefficient of the filler is larger than the thermal expansion coefficient of the semiconductor substrate of the semiconductor structure, and the insulating substrate of the wiring board. It is characterized by being smaller than the thermal expansion coefficient.
A ninth aspect of the invention is characterized in that, in the eighth aspect of the invention, the filler is made of a material in which a thermal expansion coefficient reducing material is mixed in a resin.
According to a tenth aspect of the present invention, in the first aspect of the present invention, the uppermost layer insulating film covers a portion excluding the connection pad portion of the uppermost layer upper wiring.
According to an eleventh aspect of the present invention, in the tenth aspect of the present invention, a solder ball is provided on a connection pad portion of the uppermost layer upper wiring.
The invention according to claim 12 is characterized in that, in the invention according to claim 1, at least one lower layer wiring is electrically connected to the wiring board under the base member. It is.
A thirteenth aspect of the invention is characterized in that, in the invention of the twelfth aspect, a lowermost layer insulating film covering the lowermost layer wiring is provided.
According to a fourteenth aspect of the present invention, in the invention according to the eleventh aspect, the lowermost layer insulating film covering a portion excluding the connection pad portion of the lowermost lower layer wiring is provided.
According to a fifteenth aspect of the invention, in the invention of the fourteenth aspect, an electronic component is provided below the lowermost insulating film so as to be connected to a connection pad portion of the lowermost lower layer wiring. To do.
The invention described in claim 16 is the invention described in claim 1, characterized in that a plurality of the semiconductor constructs are provided.
The invention described in claim 17 has a plurality of semiconductor structures each having a semiconductor substrate and a plurality of external connection electrodes provided on the semiconductor substrate, and openings in portions corresponding to the semiconductor structures. A step of disposing a collective wiring board on the base member so that the semiconductor structure is disposed in each opening of the collective wiring board; and connecting pad portions on the semiconductor structure and the collective wiring board. A step of electrically connecting at least one upper layer wiring to the external connection electrode of the semiconductor structure and the wiring board; and at least cutting the base member and the assembly wiring board between the semiconductor structures And a step of obtaining a plurality of semiconductor devices including at least one semiconductor structure.
According to an eighteenth aspect of the present invention, in the invention of the seventeenth aspect, the step of disposing the semiconductor structure in each opening of the collective wiring board includes the opening of the collective wiring board and the semiconductor structure. It arrange | positions so that a clearance gap may be formed between bodies, and the process of filling the said clearance gap with a filler is characterized by the above-mentioned.
According to a nineteenth aspect of the present invention, in the invention according to the eighteenth aspect, the step of filling the gaps formed between the openings of the assembly wiring board and the semiconductor constituents is performed by the assembly. An upper layer insulating film is disposed on the upper surface of the wiring board and the semiconductor structure, and the upper layer insulating film is heated and pressed by a heating and pressing plate.
According to a twentieth aspect of the present invention, in the invention of the seventeenth aspect, at least a part of a connection pad portion of the uppermost layer upper layer wiring is arranged on the assembly wiring board.
The invention according to claim 21 is the invention according to claim 17, wherein the base member is made of a prepreg material.
The invention according to claim 22 is the invention according to claim 17, wherein the collective wiring board comprises a multilayer wiring board. .
According to a twenty-third aspect, in the invention according to the seventeenth aspect, the cutting is performed so that a plurality of the semiconductor structural bodies are included.
According to a twenty-fourth aspect of the present invention, in the invention of the seventeenth aspect, the arrangement of the semiconductor structure on the base member is a non-defective wiring forming portion around the opening of the assembly wiring board before cutting. It arrange | positions only in the position corresponding to the part determined to be.
The invention of claim 25 is characterized in that, in the invention of claim 24, among the openings of the collective wiring board before cutting, a filler is filled in an opening where the semiconductor structure is not disposed. To do.

この発明によれば、半導体構成体の周囲におけるベース部材上に配線板を設けているので、配線板上に最上層の上層配線の少なくとも一部の接続パッドを配置するようにして、最上層の上層配線の接続パッド部（外部接続用電極）の数が増加しても、そのサイズおよびピッチを必要な大きさにすることが可能となる。また、ベース部材下に少なくとも１層の下層配線を配線板に電気的に接続させて設けているので、最下層の下層配線に電子部品を接続させて搭載するようにして、電子機器のより一層の小型化が可能で、且つ、配線長を最短として回路特性を向上させることが可能となる。   According to the present invention, since the wiring board is provided on the base member around the semiconductor structure, at least a part of the connection pads of the uppermost upper layer wiring is arranged on the wiring board so that the uppermost layer is formed. Even if the number of connection pad portions (external connection electrodes) of the upper layer wiring is increased, it is possible to make the size and pitch necessary. In addition, since at least one lower layer wiring is electrically connected to the wiring board under the base member, an electronic component is connected to and mounted on the lowermost lower layer wiring so that the electronic device can be further connected. The circuit characteristics can be improved with the wiring length as short as possible.

（第１実施形態）
図１はこの発明の第１実施形態としての半導体装置の断面図を示す。この半導体装置は平面方形状のベース板（ベース部材）１を備えている。ベース板１は、通常、プリプレグ材と言われるもので、例えば、ガラス繊維やアラミド繊維等からなる基材にエポキシ系樹脂等の熱硬化性樹脂を含浸させたものからなっている。 (First embodiment)
FIG. 1 is a sectional view of a semiconductor device as a first embodiment of the present invention. This semiconductor device includes a planar rectangular base plate (base member) 1. The base plate 1 is usually called a prepreg material, and is made of, for example, a base material made of glass fiber, aramid fiber or the like impregnated with a thermosetting resin such as an epoxy resin.

ベース板１の上面には、ベース板１のサイズよりもある程度小さいサイズの平面方形状の半導体構成体２の下面が固着されている。この場合、半導体構成体２は、後述する配線、柱状電極、封止膜を有しており、一般的にはＣＳＰ(chip size package)と呼ばれるものであり、特に、後述の如く、シリコンウエハ上に配線、柱状電極、封止膜を形成した後、ダイシングにより個々の半導体構成体２を得る方法を採用しているため、特に、ウエハレベルＣＳＰ（Ｗ−ＣＳＰ）とも言われている。以下に、半導体構成体２の構成について説明する。   On the upper surface of the base plate 1, the lower surface of the planar rectangular semiconductor structure 2 having a size somewhat smaller than the size of the base plate 1 is fixed. In this case, the semiconductor structure 2 has wiring, columnar electrodes, and a sealing film, which will be described later, and is generally called a CSP (chip size package). Since a method of obtaining individual semiconductor structural bodies 2 by dicing after forming wirings, columnar electrodes, and a sealing film is adopted, it is particularly called wafer level CSP (W-CSP). Below, the structure of the semiconductor structure 2 is demonstrated.

半導体構成体２は平面方形状のシリコン基板（半導体基板）３を備えている。シリコン基板３の下面はベース板１に固着されている。シリコン基板３の上面中央部には所定の機能の集積回路（図示せず）が設けられ、上面周辺部にはアルミニウム系金属等からなる複数の接続パッド４が集積回路に接続されて設けられている。   The semiconductor structure 2 includes a planar rectangular silicon substrate (semiconductor substrate) 3. The lower surface of the silicon substrate 3 is fixed to the base plate 1. An integrated circuit (not shown) having a predetermined function is provided at the center of the upper surface of the silicon substrate 3, and a plurality of connection pads 4 made of aluminum-based metal or the like are provided at the periphery of the upper surface so as to be connected to the integrated circuit. Yes.

接続パッド４の中央部を除くシリコン基板３の上面には酸化シリコン等からなる絶縁膜５が設けられ、接続パッド４の中央部は絶縁膜５に設けられた開口部６を介して露出されている。絶縁膜５の上面にはエポキシ系樹脂やポリイミド系樹脂等からなる保護膜（絶縁膜）７が設けられている。この場合、絶縁膜５の開口部６に対応する部分における保護膜７には開口部８が設けられている。   An insulating film 5 made of silicon oxide or the like is provided on the upper surface of the silicon substrate 3 excluding the central portion of the connection pad 4, and the central portion of the connection pad 4 is exposed through an opening 6 provided in the insulating film 5. Yes. A protective film (insulating film) 7 made of an epoxy resin, a polyimide resin, or the like is provided on the upper surface of the insulating film 5. In this case, an opening 8 is provided in the protective film 7 in a portion corresponding to the opening 6 of the insulating film 5.

保護膜７の上面には銅等からなる下地金属層９が設けられている。下地金属層９の上面全体には銅からなる配線１０が設けられている。下地金属層９を含む配線１０の一端部は、両開口部６、８を介して接続パッド４に接続されている。配線１０の接続パッド部上面には銅からなる柱状電極１１が設けられている。配線１０を含む保護膜７の上面にはエポキシ系樹脂やポリイミド系樹脂等からなる封止膜１２がその上面が柱状電極１１の上面と面一となるように設けられている。   A base metal layer 9 made of copper or the like is provided on the upper surface of the protective film 7. A wiring 10 made of copper is provided on the entire upper surface of the base metal layer 9. One end of the wiring 10 including the base metal layer 9 is connected to the connection pad 4 through both openings 6 and 8. A columnar electrode 11 made of copper is provided on the upper surface of the connection pad portion of the wiring 10. A sealing film 12 made of an epoxy resin, a polyimide resin, or the like is provided on the upper surface of the protective film 7 including the wiring 10 so that the upper surface is flush with the upper surface of the columnar electrode 11.

このように、Ｗ−ＣＳＰと呼ばれる半導体構成体２は、シリコン基板３、接続パッド４、絶縁膜５を含み、さらに、保護膜７、配線１０、柱状電極１１、封止膜１２を含んで構成されている。   As described above, the semiconductor structure 2 called W-CSP includes the silicon substrate 3, the connection pad 4, and the insulating film 5, and further includes the protective film 7, the wiring 10, the columnar electrode 11, and the sealing film 12. Has been.

半導体構成体２の周囲におけるベース板１の上面には方形枠状の配線板１３がその上面が半導体構成体２の上面とほぼ面一となるように設けられている。配線板１３は、多層配線板からなり、例えば、第１の絶縁基板１４の上下面に第２、第３の絶縁基板１５、１６が積層され、第２の絶縁基板１５内に設けられたビア１７と第３の絶縁基板１６内に設けられたビア１８とが、第１の絶縁基板１４内に設けられたビア１９および第１の絶縁基板１４の上下面に設けられた上面配線２０、下面配線２１を介して接続された構造となっている。この場合、第１〜第３の絶縁基板１４〜１６はベース板１と同一の材料であるプリプレグ材からなっている。上面配線２０および下面配線２１は銅箔からなっている。   A rectangular frame-shaped wiring board 13 is provided on the upper surface of the base plate 1 around the semiconductor structure 2 so that the upper surface is substantially flush with the upper surface of the semiconductor structure 2. The wiring board 13 is composed of a multilayer wiring board. For example, the second and third insulating substrates 15 and 16 are stacked on the upper and lower surfaces of the first insulating substrate 14, and the vias provided in the second insulating substrate 15 are provided. 17 and the via 18 provided in the third insulating substrate 16 are the via 19 provided in the first insulating substrate 14 and the upper surface wiring 20 provided on the upper and lower surfaces of the first insulating substrate 14. The structure is connected via the wiring 21. In this case, the first to third insulating substrates 14 to 16 are made of a prepreg material that is the same material as the base plate 1. The upper surface wiring 20 and the lower surface wiring 21 are made of copper foil.

配線板１３には半導体構成体２よりもやや大きめの開口部２２が設けられている。したがって、半導体構成体２と配線板１３との間には隙間２３が形成されている。この隙間２３の間隔は、一例として、０．１〜０．５ｍｍである。隙間２３内には絶縁性の充填材２４が充填されている。充填材２４は、エポキシ系樹脂、ポリイミド系樹脂、アクリル系樹脂、ポリベンゾオキサゾール樹脂、カルゾ樹脂等の樹脂中に熱膨張係数低下用材料としての繊維やフィラーが混入されたものからなっている。この場合、繊維は、ガラス繊維やアラミド繊維等である。フィラーは、シリカフィラー等である。   The wiring board 13 is provided with an opening 22 that is slightly larger than the semiconductor structure 2. Therefore, a gap 23 is formed between the semiconductor structure 2 and the wiring board 13. An example of the gap 23 is 0.1 to 0.5 mm. The gap 23 is filled with an insulating filler 24. The filler 24 is made of a resin such as an epoxy resin, a polyimide resin, an acrylic resin, a polybenzoxazole resin, and a calzo resin in which fibers and fillers as materials for reducing the thermal expansion coefficient are mixed. In this case, the fiber is glass fiber, aramid fiber, or the like. The filler is a silica filler or the like.

半導体構成体２、充填材２４および配線板１３の上面には第１の上層絶縁膜２５がその上面を平坦とされて設けられている。第１の上層絶縁膜２５は、ビルドアップ基板に用いられる、通常、ビルドアップ材と言われるもので、例えば、エポキシ系樹脂やＢＴ樹脂等の熱硬化性樹脂中に繊維やフィラー等の補強材が混入されたものからなっている。この場合、繊維は、ガラス繊維やアラミド繊維等である。フィラーは、シリカフィラー等である。   A first upper-layer insulating film 25 is provided on the upper surface of the semiconductor structure 2, the filler 24 and the wiring board 13 with the upper surface being flat. The first upper insulating film 25 is a so-called build-up material used for a build-up substrate. For example, a reinforcing material such as a fiber or a filler in a thermosetting resin such as an epoxy resin or a BT resin. It is made up of mixed. In this case, the fiber is glass fiber, aramid fiber, or the like. The filler is a silica filler or the like.

柱状電極１１およびビア１７の上面中央部に対応する部分における第１の上層絶縁膜２５には開口部２６が設けられている。第１の上層絶縁膜２５の上面には銅等からなる第１の上層下地金属層２７が設けられている。第１の上層下地金属層２７の上面全体には銅からなる第１の上層配線２８が設けられている。第１の上層下地金属層２７を含む第１の上層配線２８の一端部は、開口部２６を介して柱状電極１１またはビア１７の上面に接続されている。   An opening 26 is provided in the first upper insulating film 25 at a portion corresponding to the center of the upper surface of the columnar electrode 11 and the via 17. A first upper base metal layer 27 made of copper or the like is provided on the upper surface of the first upper insulating film 25. A first upper wiring 28 made of copper is provided on the entire upper surface of the first upper base metal layer 27. One end of the first upper wiring 28 including the first upper base metal layer 27 is connected to the upper surface of the columnar electrode 11 or the via 17 through the opening 26.

第１の上層配線２８を含む第１の上層絶縁膜２５の上面にはエポキシ系樹脂やポリイミド系樹脂等からなる第２の上層絶縁膜２９が設けられている。第１の上層配線２８の接続パッド部に対応する部分における第２の上層絶縁膜２９には開口部３０が設けられている。第２の上層絶縁膜２９の上面には銅等からなる第２の上層下地金属層３１が設けられている。第２の上層下地金属層３１の上面全体には銅からなる第２の上層配線３２が設けられている。第２の上層下地金属層３１を含む第２の上層配線３２の一端部は、開口部３０を介して第１の上層配線２８の接続パッド部に接続されている。   A second upper insulating film 29 made of epoxy resin, polyimide resin or the like is provided on the upper surface of the first upper insulating film 25 including the first upper wiring 28. An opening 30 is provided in the second upper layer insulating film 29 in a portion corresponding to the connection pad portion of the first upper layer wiring 28. A second upper base metal layer 31 made of copper or the like is provided on the upper surface of the second upper insulating film 29. A second upper layer wiring 32 made of copper is provided on the entire upper surface of the second upper base metal layer 31. One end of the second upper wiring 32 including the second upper base metal layer 31 is connected to the connection pad portion of the first upper wiring 28 through the opening 30.

第２の上層配線３２を含む第２の上層絶縁膜２９の上面にはソルダーレジスト等からなる最上層絶縁膜３３が設けられている。第２の上層配線３２の接続パッド部に対応する部分における最上層絶縁膜３３には開口部３４が設けられている。開口部３４内およびその上方には半田ボール３５が第２の上層配線３２の接続パッド部に接続されて設けられている。複数の半田ボール３５は、最上層絶縁膜３３の上面にマトリクス状に配置されている。   On the upper surface of the second upper layer insulating film 29 including the second upper layer wiring 32, an uppermost layer insulating film 33 made of a solder resist or the like is provided. An opening 34 is provided in the uppermost insulating film 33 in a portion corresponding to the connection pad portion of the second upper layer wiring 32. Solder balls 35 are provided in and above the opening 34 so as to be connected to the connection pad portion of the second upper layer wiring 32. The plurality of solder balls 35 are arranged in a matrix on the upper surface of the uppermost insulating film 33.

ビア１８の下面中央部に対応する部分におけるベース板１には開口部３６が設けられている。ベース板１の下面には銅等からなる第１の下層下地金属層３７が設けられている。第１の下層下地金属層３７の下面全体には銅からなる第１の下層配線３８が設けられている。第１の下層下地金属層３７を含む第１の下層配線３８の一端部は、開口部３６を介してビア１８の下面に接続されている。   An opening 36 is provided in the base plate 1 in a portion corresponding to the central portion of the lower surface of the via 18. A first lower base metal layer 37 made of copper or the like is provided on the lower surface of the base plate 1. A first lower wiring 38 made of copper is provided on the entire lower surface of the first lower base metal layer 37. One end of the first lower layer wiring 38 including the first lower base metal layer 37 is connected to the lower surface of the via 18 through the opening 36.

第１の下層配線３８を含むベース板１の下面には第１の上層絶縁膜２５と同一の材料からなる下層絶縁膜３９が設けられている。第１の下層配線３８の接続パッド部に対応する部分における下層絶縁膜３９には開口部４０が設けられている。下層絶縁膜３９の下面には銅等からなる第２の下層下地金属層４１が設けられている。第２の下層下地金属層４１の下面全体には銅からなる第２の下層配線４２が設けられている。第２の下層下地金属層４１を含む第２の下層配線４２の一端部は、開口部４０を介して第１の下層配線３８の接続パッド部に接続されている。第２の下層配線４２を含む下層絶縁膜３９の下面にはソルダーレジスト等からなる最下層絶縁膜４３が設けられている。   A lower insulating film 39 made of the same material as that of the first upper insulating film 25 is provided on the lower surface of the base plate 1 including the first lower wiring 38. An opening 40 is provided in the lower insulating film 39 in a portion corresponding to the connection pad portion of the first lower wiring 38. A second lower base metal layer 41 made of copper or the like is provided on the lower surface of the lower insulating film 39. A second lower layer wiring 42 made of copper is provided on the entire lower surface of the second lower layer underlying metal layer 41. One end portion of the second lower layer wiring 42 including the second lower layer metal layer 41 is connected to the connection pad portion of the first lower layer wiring 38 through the opening 40. A lowermost insulating film 43 made of solder resist or the like is provided on the lower surface of the lower insulating film 39 including the second lower wiring 42.

ところで、ベース板１のサイズを半導体構成体２のサイズよりもある程度大きくしているのは、シリコン基板３上の接続パッド４の数の増加に応じて、半田ボール３５の配置領域を半導体構成体２のサイズよりもある程度大きくし、これにより、第２の上層配線３２の接続パッド部（最上層絶縁膜３３の開口部３４内の部分）のサイズおよびピッチを柱状電極１１のサイズおよびピッチよりも大きくするためである。   By the way, the size of the base plate 1 is made somewhat larger than the size of the semiconductor structure 2 because the area where the solder balls 35 are arranged is increased as the number of connection pads 4 on the silicon substrate 3 increases. Thus, the size and pitch of the connection pad portion (the portion in the opening 34 of the uppermost layer insulating film 33) of the second upper layer wiring 32 is made larger than the size and pitch of the columnar electrode 11. This is to make it larger.

このため、マトリクス状に配置された第２の上層配線３２の接続パッド部は、半導体構成体２に対応する領域のみでなく、半導体構成体２の側面の外側に設けられた配線板１３に対応する領域上にも配置されている。つまり、マトリクス状に配置された半田ボール３５のうち、少なくとも最外周の半田ボール３５は半導体構成体２よりも外側に位置する周囲に配置されている。   For this reason, the connection pad portion of the second upper layer wiring 32 arranged in a matrix shape corresponds not only to the region corresponding to the semiconductor structure 2 but also to the wiring board 13 provided outside the side surface of the semiconductor structure 2. It is also arranged on the area to be. That is, among the solder balls 35 arranged in a matrix, at least the outermost solder balls 35 are arranged around the semiconductor structure 2.

また、この半導体装置では、半導体構成体２の周囲におけるベース１板上に、樹脂中に熱膨張係数低下用材料が混入されたものからなる充填材２４を設けているので、樹脂のみからなる充填材を設ける場合と比較して、半導体構成体２とその側面を覆っている絶縁層２１との間に生じる応力を緩和することができる。この場合、充填材２４の熱膨張係数は、半導体構成体２のシリコン基板２の熱膨張係数よりも大きく、且つ、配線板１３の絶縁基板１４〜１６の熱膨張係数よりも小さくなっている。   Further, in this semiconductor device, since the filler 24 made of a material in which the thermal expansion coefficient reducing material is mixed in the resin is provided on the base 1 plate around the semiconductor structure 2, the filling made of only the resin is provided. Compared with the case where a material is provided, the stress generated between the semiconductor structure 2 and the insulating layer 21 covering the side surface can be relaxed. In this case, the thermal expansion coefficient of the filler 24 is larger than the thermal expansion coefficient of the silicon substrate 2 of the semiconductor structure 2 and smaller than the thermal expansion coefficient of the insulating substrates 14 to 16 of the wiring board 13.

さらに、この半導体装置では、半導体構成体２の周囲におけるベース板１の上面に方形枠状の配線板１３を設けているので、配線板１３の代わりに単なる絶縁層を設けた場合と比較して、高密度配線構造とすることができる。すなわち、配線板１３の代わりに単なる絶縁層を設けた場合には、当該絶縁層にスルーホールを形成して、上層配線２８、３２と下層配線３８、４２とをただ単に接続するだけとなり、高密度配線構造とすることはできない。なお、第２の絶縁基板１５の上面および第３の絶縁基板１６の下面に銅箔からなる配線をビア１７、１８に接続させて設けるようにしてもよい。   Further, in this semiconductor device, since the rectangular frame-like wiring board 13 is provided on the upper surface of the base plate 1 around the semiconductor structure 2, as compared with the case where a simple insulating layer is provided instead of the wiring board 13. A high-density wiring structure can be obtained. That is, when a simple insulating layer is provided instead of the wiring board 13, a through hole is formed in the insulating layer, and the upper wirings 28 and 32 and the lower wirings 38 and 42 are simply connected. It cannot be a density wiring structure. A wiring made of copper foil may be provided on the upper surface of the second insulating substrate 15 and the lower surface of the third insulating substrate 16 so as to be connected to the vias 17 and 18.

次に、この半導体装置の製造方法の一例について説明するに、まず、半導体構成体２の製造方法の一例について説明する。この場合、まず、図２に示すように、ウエハ状態のシリコン基板（半導体基板）３上にアルミニウム系金属等からなる接続パッド４、酸化シリコン等からなる絶縁膜５およびエポキシ系樹脂やポリイミド系樹脂等からなる保護膜７が設けられ、接続パッド４の中央部が絶縁膜５および保護膜７に形成された開口部６、８を介して露出されたものを用意する。上記において、ウエハ状態のシリコン基板３には、各半導体構成体が形成される領域に所定の機能の集積回路が形成され、接続パッド４は、それぞれ、対応する領域に形成された集積回路に電気的に接続されている。   Next, an example of a method for manufacturing the semiconductor device 2 will be described. In this case, first, as shown in FIG. 2, on a silicon substrate (semiconductor substrate) 3 in a wafer state, a connection pad 4 made of aluminum metal or the like, an insulating film 5 made of silicon oxide or the like, and an epoxy resin or polyimide resin. A protective film 7 made of, for example, is provided, and a connection pad 4 whose central part is exposed through openings 6 and 8 formed in the insulating film 5 and the protective film 7 is prepared. In the above, on the silicon substrate 3 in the wafer state, an integrated circuit having a predetermined function is formed in a region where each semiconductor structure is formed, and the connection pad 4 is electrically connected to the integrated circuit formed in the corresponding region. Connected.

次に、図３に示すように、両開口部６、８を介して露出された接続パッド４の上面を含む保護膜７の上面全体に下地金属層９を形成する。この場合、下地金属層９は、無電解メッキにより形成された銅層のみであってもよく、またスパッタにより形成された銅層のみであってもよく、さらにスパッタにより形成されたチタン等の薄膜層上にスパッタにより銅層を形成したものであってもよい。これは、後述する下地金属層２７、３１、３７、４１も同様である。   Next, as shown in FIG. 3, a base metal layer 9 is formed on the entire upper surface of the protective film 7 including the upper surface of the connection pad 4 exposed through the openings 6 and 8. In this case, the base metal layer 9 may be only a copper layer formed by electroless plating, may be only a copper layer formed by sputtering, or a thin film such as titanium formed by sputtering. A copper layer may be formed on the layer by sputtering. The same applies to the base metal layers 27, 31, 37, and 41 described later.

次に、下地金属層９の上面にメッキレジスト膜５１をパターン形成する。この場合、配線１０形成領域に対応する部分におけるメッキレジスト膜５１には開口部５２が形成されている。次に、下地金属層９をメッキ電流路として銅の電解メッキを行なうことにより、メッキレジスト膜５１の開口部５２内の下地金属層９の上面に配線１０を形成する。次に、メッキレジスト膜５１を剥離する。   Next, a plating resist film 51 is patterned on the upper surface of the base metal layer 9. In this case, an opening 52 is formed in the plating resist film 51 in a portion corresponding to the wiring 10 formation region. Next, by performing copper electroplating using the base metal layer 9 as a plating current path, the wiring 10 is formed on the upper surface of the base metal layer 9 in the opening 52 of the plating resist film 51. Next, the plating resist film 51 is peeled off.

次に、図４に示すように、配線１０を含む下地金属層９の上面にメッキレジスト膜５３をパターン形成する。この場合、柱状電極１１形成領域に対応する部分におけるメッキレジスト膜５３には開口部５４が形成されている。次に、下地金属層９をメッキ電流路として銅の電解メッキを行なうことにより、メッキレジスト膜５３の開口部５４内の配線１０の接続パッド部上面に柱状電極１１を形成する。次に、メッキレジスト膜５３を剥離し、次いで、配線１０をマスクとして下地金属層９の不要な部分をエッチングして除去すると、図５に示すように、配線１０下にのみ下地金属層９が残存される。   Next, as shown in FIG. 4, a plating resist film 53 is patterned on the upper surface of the base metal layer 9 including the wiring 10. In this case, an opening 54 is formed in the plating resist film 53 in a portion corresponding to the columnar electrode 11 formation region. Next, the columnar electrode 11 is formed on the upper surface of the connection pad portion of the wiring 10 in the opening 54 of the plating resist film 53 by performing electrolytic plating of copper using the base metal layer 9 as a plating current path. Next, when the plating resist film 53 is peeled off, and then unnecessary portions of the base metal layer 9 are removed by etching using the wiring 10 as a mask, the base metal layer 9 is formed only under the wiring 10 as shown in FIG. Remain.

次に、図６に示すように、スクリーン印刷法、スピンコーティング法、ダイコート法等により、柱状電極１１および配線１０を含む保護膜７の上面全体にエポキシ系樹脂やポリイミド系樹脂等からなる封止膜１２をその厚さが柱状電極１１の高さよりも厚くなるように形成する。したがって、この状態では、柱状電極１１の上面は封止膜１２によって覆われている。   Next, as shown in FIG. 6, the entire upper surface of the protective film 7 including the columnar electrode 11 and the wiring 10 is sealed with an epoxy resin or a polyimide resin by screen printing, spin coating, die coating, or the like. The film 12 is formed so that its thickness is greater than the height of the columnar electrode 11. Therefore, in this state, the upper surface of the columnar electrode 11 is covered with the sealing film 12.

次に、封止膜１２および柱状電極１１の上面側を適宜に研磨し、図７に示すように、柱状電極１１の上面を露出させ、且つ、この露出された柱状電極１１の上面を含む封止膜１２の上面を平坦化する。ここで、柱状電極１１の上面側を適宜に研磨するのは、電解メッキにより形成される柱状電極１１の高さにばらつきがあるため、このばらつきを解消して、柱状電極１１の高さを均一にするためである。   Next, the upper surface side of the sealing film 12 and the columnar electrode 11 is appropriately polished to expose the upper surface of the columnar electrode 11 and to include the exposed upper surface of the columnar electrode 11 as shown in FIG. The upper surface of the stop film 12 is flattened. Here, the reason why the upper surface side of the columnar electrode 11 is appropriately polished is that there is a variation in the height of the columnar electrode 11 formed by electrolytic plating, so this variation is eliminated and the height of the columnar electrode 11 is made uniform. It is to make it.

次に、図８に示すように、バーンイン用検査治具５５として、下面に配線（図示せず）を有する配線板５６の下面側に複数のプローブピン５７を有するプローブピン支持板５８が配置され、プローブピン５７の上端面が異方導電性ゴム５９を介して配線板５６の配線に接続されたものを用意する。この場合、プローブピン５７の先端部はほぼ半球形状となっている。また、プローブピン５７の直径は柱状電極１１の直径よりもある程度小さくなっている。   Next, as shown in FIG. 8, a probe pin support plate 58 having a plurality of probe pins 57 is arranged on the lower surface side of the wiring board 56 having wiring (not shown) on the lower surface as the burn-in inspection jig 55. A probe pin 57 whose upper end surface is connected to the wiring of the wiring board 56 through an anisotropic conductive rubber 59 is prepared. In this case, the tip of the probe pin 57 has a substantially hemispherical shape. The diameter of the probe pin 57 is somewhat smaller than the diameter of the columnar electrode 11.

そして、図示しないステージ上に配置されたウエハ状態のシリコン基板３上に形成された柱状電極１１の上面に、バーンイン用検査治具５５のプローブピン５７の先端部を接触させ、バーンインを行なう。そして、このバーンインにより、ウエハ状態における各半導体装置の良否を判定する。次に、シリコン基板３をダイシングテープ（図示せず）に貼り付け、図９に示すダイシング工程を経た後に、ダイシングテープから剥がすと、図１に示す半導体構成体２が複数個得られる。そして、上記バーンインによる判定結果に基づいて、良品の半導体構成体２のみを選び出す。   Then, the tip end portion of the probe pin 57 of the burn-in inspection jig 55 is brought into contact with the upper surface of the columnar electrode 11 formed on the silicon substrate 3 in a wafer state arranged on a stage (not shown) to perform burn-in. Then, the quality of each semiconductor device in the wafer state is determined by this burn-in. Next, when the silicon substrate 3 is attached to a dicing tape (not shown), and after the dicing process shown in FIG. 9, the silicon substrate 3 is peeled off from the dicing tape, a plurality of semiconductor structures 2 shown in FIG. 1 are obtained. Then, based on the determination result by the burn-in, only good semiconductor structures 2 are selected.

次に、図１に示す配線板１３の製造方法の一例について、簡単に説明する。まず、図１０に示すように、の上面配線２０および下面配線２１がビア１９により導通されたプリプレグ材またはビルドアップ材からなる第１の絶縁基板１４を用意する。この第１の絶縁基板１４を形成するには、通常のビルドアッププリント基板の製造方法を用いればよく、フォトリソグラフィ技術またはレーザビームによりビアホールを形成し、めっきにより、あるいはスパッタ法とめっきにより、上面配線２０、下面配線２１およびビア１９を形成する。ビア１９は、導電ペーストをビアホールに充填する方法あるいは導電材料からなるピンを圧入する方法によってもよい。   Next, an example of a method for manufacturing the wiring board 13 shown in FIG. 1 will be briefly described. First, as shown in FIG. 10, a first insulating substrate 14 made of a prepreg material or a buildup material in which the upper surface wiring 20 and the lower surface wiring 21 are made conductive by the via 19 is prepared. In order to form the first insulating substrate 14, a normal build-up printed circuit board manufacturing method may be used. Via holes are formed by a photolithography technique or a laser beam, and plating or sputtering or plating is used to form the upper surface. The wiring 20, the lower surface wiring 21, and the via 19 are formed. The via 19 may be formed by a method of filling a via hole with a conductive paste or a method of press-fitting a pin made of a conductive material.

次に、図１１に示すように、上面配線２０を含む第１の絶縁基板１４の上面に、プリプレグ材またはビルドアップ材からなる第２の絶縁基板１５を積層するとともに、下面配線２１を含む第１の絶縁基板１４の下面に、プリプレグ材またはビルドアップ材からなる第３の絶縁基板１６を積層する。そして、第２の絶縁基板１５にビア１７を、また第３の絶縁基板１６にビア１８を、第１の絶縁基板１４にビア１９を形成する場合と同様な方法で形成する。図１１においては、ビア１７上とその周辺部、およびビア１８上とその周縁部を覆う配線は形成されていないが、ビア１７およびビア１８を形成する際、このような配線を同時に形成してもよい。いずれにしても、図１１に図示された状態で、ビア１７は上面配線２０の他端部に接続され、ビア１８は下面配線２１の他端部に接続されている。   Next, as shown in FIG. 11, a second insulating substrate 15 made of a prepreg material or a build-up material is laminated on the upper surface of the first insulating substrate 14 including the upper surface wiring 20, and the second insulating substrate 15 including the lower surface wiring 21 is included. A third insulating substrate 16 made of a prepreg material or a build-up material is laminated on the lower surface of one insulating substrate 14. Then, vias 17 are formed in the second insulating substrate 15, vias 18 are formed in the third insulating substrate 16, and vias 19 are formed in the first insulating substrate 14. In FIG. 11, no wiring is formed to cover the via 17 and its peripheral portion, and the via 18 and its peripheral portion. However, when forming the via 17 and the via 18, such wiring is formed at the same time. Also good. In any case, in the state shown in FIG. 11, the via 17 is connected to the other end of the upper surface wiring 20, and the via 18 is connected to the other end of the lower surface wiring 21.

ここで、第１〜第３の絶縁基板１４〜１６は、図１に示す配線板１３を複数枚採取することができる大きさで、限定する意味ではないが、平面形状が方形状となっている。そして、次に、図１２に示すように、パンチングにより、第１〜第３の絶縁基板１４〜１６に複数の方形状の開口部２２を形成し、平面形状が格子状とされた第１〜第３の絶縁基板１４〜１６からなる集合配線板１３ａを形成する。次に、集合配線板１３ａに対して電気的検査を行ない、集合配線板１３ａにおける各配線板１３形成領域の電気的良否を判定する。   Here, the first to third insulating substrates 14 to 16 are large enough to collect a plurality of wiring boards 13 shown in FIG. Yes. Then, as shown in FIG. 12, a plurality of rectangular openings 22 are formed in the first to third insulating substrates 14 to 16 by punching, and the planar shape is a lattice shape. A collective wiring board 13a composed of the third insulating substrates 14 to 16 is formed. Next, an electrical inspection is performed on the assembly wiring board 13a to determine the electrical quality of each wiring board 13 formation region in the assembly wiring board 13a.

次に、上記のようにして得られた良品の半導体構成体２および各配線板１３形成領域の電気的良否判定済みの集合配線板１３ａを用いて、図１に示す半導体装置を製造する場合の一例について説明する。まず、図１３に示すように、図１に示すベース板１を複数枚採取することができる大きさで、集合配線板１３ａに対応する大きさのプリプレグ材からなるベース板１を用意する。この場合、ベース板１を構成するプリプレグ材中のエポキシ系樹脂等からなる熱硬化性樹脂は、半硬化状態となっている。   Next, in the case of manufacturing the semiconductor device shown in FIG. 1 using the non-defective semiconductor structure 2 obtained as described above and the assembled wiring board 13a in which the electrical quality of each wiring board 13 has been determined is determined. An example will be described. First, as shown in FIG. 13, a base plate 1 made of a prepreg material having a size capable of collecting a plurality of the base plates 1 shown in FIG. 1 and corresponding to the assembly wiring board 13a is prepared. In this case, the thermosetting resin made of epoxy resin or the like in the prepreg material constituting the base plate 1 is in a semi-cured state.

次に、ベース板１の上面の所定の複数箇所にそれぞれ良品の半導体構成体２のシリコン基板３の下面を仮圧着する。すなわち、加熱機構付きのボンディングツール（図示せず）を用い、半導体装置２を、加熱した状態で一定の圧力をかけながら、プリプレグ材からなるベース板１の上面の所定の箇所に仮圧着する。仮圧着条件は、一例として、温度９０〜１３０℃、圧力０．１〜１Ｍｐａである。   Next, the lower surface of the silicon substrate 3 of the non-defective semiconductor structure 2 is temporarily bonded to a plurality of predetermined locations on the upper surface of the base plate 1. That is, using a bonding tool (not shown) with a heating mechanism, the semiconductor device 2 is temporarily pressure-bonded to a predetermined location on the upper surface of the base plate 1 made of a prepreg material while applying a certain pressure in a heated state. Temporary pressure bonding conditions are, for example, a temperature of 90 to 130 ° C. and a pressure of 0.1 to 1 MPa.

次に、半導体構成体２間および最外周に配置された半導体構成体２の外側におけるベース板１の上面に、集合配線板１３ａをピン等で位置決めしながら配置する。この状態では、集合配線板１３ａの開口部２２のサイズは半導体構成体２のサイズよりもやや大きくなっているので、集合配線板１３ａの各開口部２２と半導体構成体２との間には隙間２３が形成されている。また、この状態では、集合配線板１３ａの上面と半導体構成体２の上面とはほぼ同一の平面上に配置されている。上記の工程において、ベース板１上に半導体構成体２および集合配線板１３ａを配置する順序は、逆でもよく、先に集合配線板１３ａを配置した後、この集合配線板１３ａの各開口部内２２内に半導体構成体２を配置するようにしてもよい。   Next, the collective wiring board 13a is disposed on the upper surface of the base plate 1 between the semiconductor structural bodies 2 and outside the semiconductor structural body 2 disposed on the outermost periphery while being positioned with pins or the like. In this state, the size of the opening 22 of the collective wiring board 13a is slightly larger than the size of the semiconductor structure 2, so there is no gap between each opening 22 of the collective wiring board 13a and the semiconductor structure 2. 23 is formed. In this state, the upper surface of the collective wiring board 13a and the upper surface of the semiconductor structure 2 are arranged on substantially the same plane. In the above process, the order in which the semiconductor structure 2 and the collective wiring board 13a are arranged on the base plate 1 may be reversed. After the collective wiring board 13a is arranged first, the inside of each opening 22 of the collective wiring board 13a You may make it arrange | position the semiconductor structure 2 in it.

ここで、集合配線板１３ａの各配線板１３形成領域の電気的良否の判定は済んでいるので、良品と判定された配線板１３形成領域の開口部２２内にのみ半導体構成体２を配置し、不良品と判定された配線板１３形成領域の開口部２２内には半導体構成体２を配置しない。これにより、良品と判定された半導体構成体２の無駄を防止し、歩留の向上を図ることができる。   Here, since the determination of the electrical quality of each wiring board 13 formation region of the collective wiring board 13a has been completed, the semiconductor structure 2 is disposed only in the opening 22 of the wiring board 13 formation region determined to be non-defective. The semiconductor structure 2 is not disposed in the opening 22 in the area where the wiring board 13 is determined to be defective. Thereby, it is possible to prevent waste of the semiconductor structure 2 determined as a non-defective product and to improve the yield.

次に、図１４に示すように、隙間２３内に樹脂中に熱膨張係数低下用材料が混入されたものからなるペースト状または粉末状の充填材２４を印刷法等により充填する。この場合、不良品と判定された配線板１３形成領域の開口部２２内には半導体構成体２が配置されていないので、当該開口部２２全領域内に充填材２４を充填する。   Next, as shown in FIG. 14, a paste-like or powder-like filler 24 made of a material in which a thermal expansion coefficient reducing material is mixed in the gap 23 is filled by a printing method or the like. In this case, since the semiconductor structure 2 is not disposed in the opening 22 of the wiring board 13 formation region determined to be a defective product, the filler 24 is filled in the entire region of the opening 22.

次に、集合配線板１３ａ、半導体構成体２および充填材２４の上面に第１の上層絶縁膜２５を形成するためのシート状のビルドアップ材を配置する。このビルドアップ材としては、エポキシ系樹脂等の熱硬化性樹脂中にシリカフィラーを混入させ、熱硬化性樹脂を半硬化状態にしたものがある。   Next, a sheet-like build-up material for forming the first upper insulating film 25 is disposed on the upper surfaces of the collective wiring board 13 a, the semiconductor structure 2, and the filler 24. As this build-up material, there is a material in which a silica filler is mixed in a thermosetting resin such as an epoxy resin to make the thermosetting resin semi-cured.

次に、一対の加熱加圧板６１、６２を用いて上下からベース板１、充填材２４および第１の上層絶縁膜２５形成用のビルドアップ材を加熱加圧する。すると、ベース板１中の熱硬化性樹脂が硬化し、ベース板１の上面に半導体構成体２のシリコン基板３の下面および第３の絶縁基板１６の下面が固着される。また、充填材２４中の熱硬化性樹脂が硬化し、充填材２４が半導体構成体２の側面、集合配線板１３ａの各開口部２２の内壁面およびその間のベース板１の上面に固着される。さらに、ビルドアップ材中の熱硬化性樹脂が硬化し、半導体構成体２、充填材２４および第２の絶縁基板１５の上面に第１の上層絶縁膜２５が形成される。   Next, the base plate 1, the filler 24 and the buildup material for forming the first upper insulating film 25 are heated and pressed from above and below using a pair of heating and pressing plates 61 and 62. Then, the thermosetting resin in the base plate 1 is cured, and the lower surface of the silicon substrate 3 and the lower surface of the third insulating substrate 16 of the semiconductor structure 2 are fixed to the upper surface of the base plate 1. Further, the thermosetting resin in the filler 24 is cured, and the filler 24 is fixed to the side surface of the semiconductor structure 2, the inner wall surface of each opening 22 of the assembly wiring board 13a, and the upper surface of the base plate 1 therebetween. . Further, the thermosetting resin in the build-up material is cured, and the first upper insulating film 25 is formed on the upper surfaces of the semiconductor structure 2, the filler 24 and the second insulating substrate 15.

この場合、第１の上層絶縁膜２５の上面は、上側の加熱加圧板６１の下面によって押さえ付けられるため、平坦面となる。また、ベース板１の下面は、下側の加熱加圧板６２の上面によって押さえ付けられるため、平坦面となる。したがって、第１の上層絶縁膜２５の上面およびベース板１の下面を平坦化するための研磨工程は不要である。このため、ベース板１のサイズが例えば５００×５００ｍｍ程度と比較的大きくても、その上に配置された複数の半導体構成体２に対して第１の上層絶縁膜２５の上面およびベース板１の下面の平坦化を一括して簡単に行なうことができる。   In this case, since the upper surface of the first upper insulating film 25 is pressed by the lower surface of the upper heating / pressing plate 61, it becomes a flat surface. Further, the lower surface of the base plate 1 is pressed by the upper surface of the lower heating / pressurizing plate 62, and thus becomes a flat surface. Therefore, a polishing step for flattening the upper surface of the first upper insulating film 25 and the lower surface of the base plate 1 is not necessary. For this reason, even if the size of the base plate 1 is relatively large, for example, about 500 × 500 mm, the upper surface of the first upper insulating film 25 and the base plate 1 of the plurality of semiconductor structural bodies 2 arranged thereon are arranged. Flattening of the lower surface can be easily performed at once.

なお、ベース板１上に半導体構成体３および集合配線板１３ａを配置し、次いで、上下から加熱加圧し、次いで、印刷法等により隙間２３内に充填材２４を充填し、次いで、それらの上にビルドアップ材を配置し、次いで、上下から加熱加圧するようにしてもよい。また、ベース板１上に半導体構成体３および集合配線板１３ａを配置し、次いで、上下から加熱加圧し、次いで、印刷法等により隙間２３内に充填材２４を充填するとともにそれらの上に充填材２４と同一の材料からなる第１の上層絶縁膜形成用層を形成し、次いで、上下から加熱加圧するようにしてもよい。   The semiconductor structure 3 and the assembly wiring board 13a are arranged on the base plate 1, and then heated and pressed from above and below, and then the filling material 24 is filled in the gap 23 by a printing method or the like, A build-up material may be disposed on the top and then heated and pressed from above and below. Further, the semiconductor structure 3 and the collective wiring board 13a are arranged on the base plate 1, and then heated and pressed from above and below, and then the filling material 24 is filled in the gaps 23 by a printing method or the like and is filled thereon. A first upper insulating film forming layer made of the same material as the material 24 may be formed, and then heated and pressed from above and below.

次に、図１５に示すように、レーザビームを照射するレーザ加工により、柱状電極１１およびビア１７の上面中央部に対応する部分における第１の上層絶縁膜２５に開口部２６を形成する。また、ビア１８の下面中央部に対応する部分におけるベース板１に開口部３６を形成する。次に、必要に応じて、開口部２６、３６内等に発生したエポキシスミア等をデスミア処理により除去する。   Next, as shown in FIG. 15, an opening 26 is formed in the first upper insulating film 25 at a portion corresponding to the central portion of the upper surface of the columnar electrode 11 and the via 17 by laser processing with laser beam irradiation. In addition, an opening 36 is formed in the base plate 1 at a portion corresponding to the central portion of the lower surface of the via 18. Next, the epoxy smear etc. which generate | occur | produced in the opening parts 26 and 36 etc. are removed by a desmear process as needed.

次に、図１６に示すように、開口部２６を介して露出された柱状電極１１およびビア１７の上面を含む第１の上層絶縁膜２５の上面全体および開口部３６を介して露出されたビア１８の下面を含むベース板１の下面全体に、銅の無電解メッキ等により、第１の上層下地金属層２７および第１の下層下地金属層３７を形成する。   Next, as shown in FIG. 16, the entire upper surface of the first upper insulating film 25 including the upper surfaces of the columnar electrode 11 and the via 17 exposed through the opening 26 and the via exposed through the opening 36. The first upper base metal layer 27 and the first lower base metal layer 37 are formed on the entire lower surface of the base plate 1 including the lower surface 18 by copper electroless plating or the like.

次に、第１の上層下地金属層２７の上面に上層メッキレジスト膜６３をパターン形成し、また、第１の下層下地金属層３７の下面に下層メッキレジスト膜６４をパターン形成する。この場合、第１の上層配線２８形成領域に対応する部分における上層メッキレジスト膜６３には開口部６５が形成されている。また、第１の下層配線３８形成領域に対応する部分における下層メッキレジスト膜６４には開口部６６が形成されている。   Next, the upper plating resist film 63 is patterned on the upper surface of the first upper lower metal layer 27, and the lower plating resist film 64 is patterned on the lower surface of the first lower metal layer 37. In this case, an opening 65 is formed in the upper plating resist film 63 in a portion corresponding to the first upper wiring 28 formation region. An opening 66 is formed in the lower plating resist film 64 in a portion corresponding to the first lower wiring 38 formation region.

次に、下地金属層２７、３７をメッキ電流路として銅の電解メッキを行なうことにより、上層メッキレジスト膜６３の開口部６５内の第１の上層下地金属層２７の上面に第１の上層配線２８を形成し、また、下層メッキレジスト膜６４の開口部６６内の第１の下層下地金属層３７の下面に第１の下層配線３８を形成する。   Next, by performing copper electroplating using the base metal layers 27 and 37 as plating current paths, a first upper layer wiring is formed on the upper surface of the first upper layer base metal layer 27 in the opening 65 of the upper layer plating resist film 63. 28, and a first lower wiring 38 is formed on the lower surface of the first lower base metal layer 37 in the opening 66 of the lower plating resist film 64.

次に、両メッキレジスト膜６３、６４を剥離し、次いで、第１の上層配線２８および第１の下層配線３８をマスクとして第１の上層下地金属層２７および第１の下層下地金属層３７の不要な部分をエッチングして除去すると、図１７に示すように、第１の上層配線２８下にのみ第１の上層下地金属層２７が残存され、また、第１の下層配線３８上にのみ第１の下層下地金属層３７が残存される。   Next, the plating resist films 63 and 64 are peeled off, and then the first upper layer metal layer 27 and the first lower layer metal layer 37 are formed using the first upper layer wiring 28 and the first lower layer wiring 38 as a mask. When unnecessary portions are removed by etching, the first upper base metal layer 27 remains only under the first upper wiring 28 and the first upper wiring 38 only on the first lower wiring 38 as shown in FIG. One lower base metal layer 37 remains.

次に、図１８に示すように、第１の上層配線２８を含む第１の上層絶縁膜２５の上面にシート状のビルドアップ材等からなる第２の上層絶縁膜２９を形成し、また、第１の下層配線３８を含むベース板１の下面にシート状のビルドアップ材等からなる下層絶縁膜３９を形成する。   Next, as shown in FIG. 18, a second upper layer insulating film 29 made of a sheet-like buildup material or the like is formed on the upper surface of the first upper layer insulating film 25 including the first upper layer wiring 28, and A lower insulating film 39 made of a sheet-like buildup material or the like is formed on the lower surface of the base plate 1 including the first lower wiring 38.

次に、レーザビームを照射するレーザ加工により、第１の上層配線２８の接続パッド部に対応する部分における第２の上層絶縁膜２９に開口部３０を形成し、また、第１の下層配線３８の接続パッド部に対応する部分における下層絶縁膜３９に開口部４０を形成する。次に、必要に応じて、開口部３０、４０内等に発生したエポキシスミア等をデスミア処理により除去する。   Next, an opening 30 is formed in the second upper-layer insulating film 29 at a portion corresponding to the connection pad portion of the first upper-layer wiring 28 by laser processing with laser beam irradiation, and the first lower-layer wiring 38 is formed. An opening 40 is formed in the lower insulating film 39 in a portion corresponding to the connection pad portion. Next, the epoxy smear etc. which generate | occur | produced in the opening parts 30 and 40 etc. are removed by a desmear process as needed.

次に、図１９に示すように、開口部３０を介して露出された第１の上層配線２８の接続パッド部を含む第２の上層絶縁膜２９の上面全体および開口部４０を介して露出された第１の下層配線３８の接続パッド部を含む下層絶縁膜３９の下面全体に、銅の無電解メッキ等により、第２の上層下地金属層３１および第２の下層下地金属層４１を形成する。   Next, as shown in FIG. 19, the entire upper surface of the second upper insulating film 29 including the connection pad portion of the first upper layer wiring 28 exposed through the opening 30 and the opening 40 are exposed. The second upper base metal layer 31 and the second lower base metal layer 41 are formed on the entire lower surface of the lower insulating film 39 including the connection pad portion of the first lower wiring 38 by electroless plating of copper or the like. .

次に、第２の上層下地金属層３１の上面に上層メッキレジスト膜６７をパターン形成し、また、第２の下層下地金属層４１の下面に下層メッキレジスト膜６８をパターン形成する。この場合、第２の上層配線３２形成領域に対応する部分における上層メッキレジスト膜６７には開口部６９が形成されている。また、第２の下層配線４２形成領域に対応する部分における下層メッキレジスト膜６８には開口部７０が形成されている。   Next, the upper layer plating resist film 67 is patterned on the upper surface of the second upper layer underlying metal layer 31, and the lower layer plating resist film 68 is patterned on the lower surface of the second lower layer underlying metal layer 41. In this case, an opening 69 is formed in the upper plating resist film 67 in a portion corresponding to the second upper wiring 32 forming region. In addition, an opening 70 is formed in the lower plating resist film 68 in a portion corresponding to the second lower wiring 42 formation region.

次に、下地金属層３１、４１をメッキ電流路として銅の電解メッキを行なうことにより、上層メッキレジスト膜６７の開口部６９内の第２の上層下地金属層３１の上面に第２の上層配線３２を形成し、また、下層メッキレジスト膜６８の開口部７０内の第２の下層下地金属層４１の下面に第２の下層配線４２を形成する。   Next, the second upper layer wiring is formed on the upper surface of the second upper layer base metal layer 31 in the opening 69 of the upper layer plating resist film 67 by performing copper electroplating using the base metal layers 31 and 41 as plating current paths. 32, and a second lower layer wiring 42 is formed on the lower surface of the second lower layer metal layer 41 in the opening 70 of the lower layer plating resist film 68.

次に、両メッキレジスト膜６７、６８を剥離し、次いで、第２の上層配線３２および第２の下層配線４２をマスクとして第２の上層下地金属層３１および第２の下層下地金属層４１の不要な部分をエッチングして除去すると、図２０に示すように、第２の上層配線３２下にのみ第２の上層下地金属層３１が残存され、また、第２の下層配線４２上にのみ第２の下層下地金属層４１が残存される。   Next, the plating resist films 67 and 68 are peeled off, and then the second upper layer metal layer 31 and the second lower layer metal layer 41 are formed using the second upper layer wiring 32 and the second lower layer wiring 42 as a mask. When unnecessary portions are removed by etching, as shown in FIG. 20, the second upper layer underlying metal layer 31 remains only under the second upper layer wiring 32, and the second upper layer wiring 42 is exposed only on the second lower layer wiring. The second lower base metal layer 41 remains.

次に、図２１に示すように、スクリーン印刷法やスピンコーティング法等により、第２の上層配線３２を含む第２の上層絶縁膜２９の上面にソルダーレジスト等からなる最上層絶縁膜３３を形成し、また、第２の下層配線４２を含む下層絶縁膜３９の下面にソルダーレジスト等からなる最下層絶縁膜４３を形成する。この場合、第２の上層配線３２の接続パッド部に対応する部分における最上層絶縁膜３３には開口部３４が形成されている。なお、第２の下層配線４２の接続パッド部に対応する部分における最下層絶縁膜４３には開口部は形成しない。したがって、第２の下層配線４２の接続パッド部は最下層絶縁膜４３によって覆われている。   Next, as shown in FIG. 21, an uppermost insulating film 33 made of a solder resist or the like is formed on the upper surface of the second upper insulating film 29 including the second upper wiring 32 by a screen printing method, a spin coating method, or the like. In addition, a lowermost insulating film 43 made of a solder resist or the like is formed on the lower surface of the lower insulating film 39 including the second lower wiring 42. In this case, an opening 34 is formed in the uppermost insulating film 33 in a portion corresponding to the connection pad portion of the second upper layer wiring 32. Note that no opening is formed in the lowermost insulating film 43 in the portion corresponding to the connection pad portion of the second lower layer wiring 42. Therefore, the connection pad portion of the second lower layer wiring 42 is covered with the lowermost layer insulating film 43.

次に、開口部３４内およびその上方に半田ボール３５を第２の上層配線３２の接続パッド部に接続させて形成する。次に、互いに隣接する半導体構成体２間において、最上層絶縁膜３３、第２の上層絶縁膜２９、第１の上層絶縁膜２５、集合配線板１３ａ、ベース板１、下層絶縁膜３９および最下層絶縁膜４３を切断すると、図１に示す半導体装置が複数個得られる。   Next, the solder ball 35 is formed in the opening 34 and above the connection portion of the second upper wiring 32 in and above the opening 34. Next, between the semiconductor structures 2 adjacent to each other, the uppermost insulating film 33, the second upper insulating film 29, the first upper insulating film 25, the assembly wiring board 13a, the base plate 1, the lower insulating film 39, and the uppermost insulating film When the lower insulating film 43 is cut, a plurality of semiconductor devices shown in FIG. 1 are obtained.

（第２実施形態）
図２２はこの発明の第２実施形態としての半導体装置の断面図を示す。この半導体装置において、図１に示す場合と異なる点は、最下層絶縁膜４３下に複数の半導体構成体（電子部品）７１を搭載した点である。すなわち、第２の下層配線４２の接続パッド部に対応する部分における最下層絶縁膜４３には開口部４４が設けられている。最下層絶縁膜４３の下面には複数の半導体構成体７１が、その上面に設けられた半田ボール７２が最下層絶縁膜４３の開口部４４を介して第２の下層配線４２の接続パッド部に接続されて、搭載されている。 (Second Embodiment)
FIG. 22 is a sectional view of a semiconductor device as a second embodiment of the present invention. This semiconductor device is different from the case shown in FIG. 1 in that a plurality of semiconductor components (electronic parts) 71 are mounted under the lowermost insulating film 43. That is, the opening 44 is provided in the lowermost insulating film 43 in the portion corresponding to the connection pad portion of the second lower layer wiring 42. A plurality of semiconductor structures 71 are formed on the lower surface of the lowermost insulating film 43, and solder balls 72 provided on the upper surface thereof are connected to the connection pad portions of the second lower wiring line 42 through the openings 44 of the lowermost insulating film 43. Connected and mounted.

この場合、半導体構成体７１は、詳細には図示していないが、ベアチップ、ＢＧＡ(ball grid array)、ＣＳＰ等のいずれであってもよく、シリコン等からなる半導体基板の上面には所定の機能の集積回路が設けられ、上面周辺部にはアルミニウム系金属等からなる複数の接続パッドが集積回路に接続されて設けられ、接続パッド自体または該接続パッドに接続された柱状電極等からなる外部接続用電極上に半田ボール７２が設けられた構造となっている。   In this case, although not shown in detail, the semiconductor structure 71 may be any of a bare chip, a BGA (ball grid array), a CSP, and the like, and a predetermined function is provided on the upper surface of the semiconductor substrate made of silicon or the like. The integrated circuit is provided, and a plurality of connection pads made of an aluminum-based metal or the like are connected to the integrated circuit on the periphery of the upper surface, and the connection pad itself or an external connection made of a columnar electrode connected to the connection pad The solder balls 72 are provided on the electrodes for use.

そして、この半導体装置では、ベース板下に第１、第２の下層配線３８、４２を配線板１３のビア１８に接続させて設け、最下層絶縁膜４３下に半導体構成体７１を第２の下層配線４２の接続パッド部に接続させて搭載しているので、電子機器のより一層の小型化が可能になるとともに、配線長を最短として回路特性を向上させることができる。なお、最下層絶縁膜４３下にコンデンサや抵抗等からなるチップ部品（電子部品）を搭載するようにしてもよい。   In this semiconductor device, the first and second lower layer wirings 38 and 42 are provided under the base plate so as to be connected to the via 18 of the wiring plate 13, and the semiconductor structure 71 is disposed under the lowermost insulating film 43. Since the electronic device is mounted while being connected to the connection pad portion of the lower layer wiring 42, the electronic device can be further miniaturized and the circuit characteristics can be improved by making the wiring length the shortest. Note that a chip component (electronic component) made of a capacitor, a resistor, or the like may be mounted under the lowermost insulating film 43.

（その他の実施形態）
上記実施形態では、配線板１３として、多層配線板を用い、例えば、プリプレグ材からなる第１〜第３の絶縁基板を積層してなるものを用いた場合について説明したが、これに限らず、例えば、スルーホールメッキ導通部を有する両面配線構造のものを用いてもよい。 (Other embodiments)
In the said embodiment, although the multilayer wiring board was used as the wiring board 13, for example, the case where the thing formed by laminating | stacking the 1st-3rd insulating substrate which consists of a prepreg material was demonstrated, it is not restricted to this, For example, a double-sided wiring structure having a through-hole plating conductive portion may be used.

また、上記実施形態では、上層配線および下層配線を共に２層とした場合について説明したが、これに限らず、１層または３層以上としてもよく、また、同数層ではなく異数層としてもよい。ただし、同数層とした場合には、半導体装置の反りを低減することができる。   In the above embodiment, the case where both the upper layer wiring and the lower layer wiring are two layers has been described. However, the present invention is not limited to this, and one layer or three or more layers may be used. Good. However, when the number of layers is the same, warpage of the semiconductor device can be reduced.

また、上記実施形態では、互いに隣接する半導体構成体２間において切断したが、これに限らず、２個またはそれ以上の半導体構成体２を１組として切断するようにしてもよい。この場合、複数で１組の半導体構成体２は同種、異種のいずれであってもよい。   Moreover, in the said embodiment, although it cut | disconnected between the mutually adjacent semiconductor structures 2, you may make it cut | disconnect not only to this but two or more semiconductor structures 2 as 1 set. In this case, the plurality of sets of semiconductor structures 2 may be the same type or different types.

また、上記実施形態では、半導体構成体２は、外部接続用電極としての柱状電極１１を有するものとしたが、これに限らず、柱状電極を有せず、外部接続用電極としての接続パッド部を有する配線１１を有するものであってもよく、また、柱状電極および配線を有せず、外部接続用電極としての接続パッド４を有するものであってもよい。   Moreover, in the said embodiment, although the semiconductor structure 2 shall have the columnar electrode 11 as an external connection electrode, it is not restricted to this, It does not have a columnar electrode, but the connection pad part as an external connection electrode The wiring 11 may be provided, or the columnar electrode and the wiring may not be provided, and the connection pad 4 as an external connection electrode may be provided.

また、上記実施形態では、ベース板１としてプリプレグ材を用いた場合について説明したが、これに限らず、樹脂単体、シリコン、ガラス、セラミックス等の絶縁板を用いてもよい。ただし、このような絶縁板を用いる場合には、絶縁板の上面に半導体構成体２のシリコン基板３の下面および配線板１３の下面を接着剤を介して接着するようにしてもよい。   Moreover, although the said embodiment demonstrated the case where a prepreg material was used as the base plate 1, you may use insulating plates, such as not only this but a resin single-piece | unit, silicon, glass, ceramics. However, when such an insulating plate is used, the lower surface of the silicon substrate 3 and the lower surface of the wiring board 13 of the semiconductor structure 2 may be bonded to the upper surface of the insulating plate with an adhesive.

また、上記実施形態では、ベース板１は、そのまま半導体装置の構成部材の一部として残存されるものであるが、図１４に図示された第１の上層絶縁膜２５を形成した以降のいずれかの工程において、半導体構成体３から剥離し、接着、印刷、コーティング等適宜な方法により新たに形成するようにしてもよい。この場合、ベース板としての支持部材に剥離材を介して金属箔等からなる薄膜を形成し、第１の上層絶縁膜２５を形成した後、支持部材を剥離し、薄膜のみを残したり、あるいは残存された薄膜上にさらに導電性あるいは絶縁性の支持用あるいは保護用の膜を形成してもよい。   Further, in the above embodiment, the base plate 1 remains as a part of the constituent member of the semiconductor device, but any one after the first upper insulating film 25 illustrated in FIG. 14 is formed. In this step, the semiconductor structure 3 may be peeled off and newly formed by an appropriate method such as adhesion, printing, or coating. In this case, a thin film made of metal foil or the like is formed on a supporting member as a base plate through a release material, and after forming the first upper insulating film 25, the supporting member is peeled off, leaving only the thin film, or A conductive or insulating support or protection film may be further formed on the remaining thin film.

この発明の第１実施形態としての半導体装置の断面図。1 is a cross-sectional view of a semiconductor device as a first embodiment of the present invention. 図１に示す半導体構成体の製造に際し、当初用意したものの断面図。Sectional drawing of what was prepared initially in the case of manufacture of the semiconductor structure shown in FIG. 図２に続く工程の断面図。Sectional drawing of the process following FIG. 図３に続く工程の断面図。Sectional drawing of the process following FIG. 図４に続く工程の断面図。Sectional drawing of the process following FIG. 図５に続く工程の断面図。Sectional drawing of the process following FIG. 図６に続く工程の断面図。Sectional drawing of the process following FIG. 図７に続く工程の断面図。Sectional drawing of the process following FIG. 図８に続く工程の断面図。FIG. 9 is a cross-sectional view of the process following FIG. 8. 図１に示す配線板の製造に際し、当初用意したものの断面図。Sectional drawing of what was initially prepared in the case of manufacture of the wiring board shown in FIG. 図１０に続く工程の断面図。Sectional drawing of the process following FIG. 図１１に続く工程の断面図。Sectional drawing of the process following FIG. 図１に半導体装置の製造に際し、所定の工程の断面図。FIG. 1 is a cross-sectional view of a predetermined process in manufacturing a semiconductor device. 図１３に続く工程の断面図。Sectional drawing of the process following FIG. 図１４に続く工程の断面図。FIG. 15 is a sectional view of a step following FIG. 14. 図１５に続く工程の断面図。FIG. 16 is a cross-sectional view of the process following FIG. 15. 図１６に続く工程の断面図。FIG. 17 is a cross-sectional view of the process following FIG. 16. 図１７に続く工程の断面図。FIG. 18 is a cross-sectional view of the process following FIG. 17. 図１８に続く工程の断面図。FIG. 19 is a cross-sectional view of the process following FIG. 18. 図１９に続く工程の断面図。FIG. 20 is a cross-sectional view of the process following FIG. 19. 図２０に続く工程の断面図。FIG. 21 is a cross-sectional view of the process following FIG. 20. この発明の第２実施形態としての半導体装置の断面図。Sectional drawing of the semiconductor device as 2nd Embodiment of this invention.

符号の説明Explanation of symbols

１ ベース板
２ 半導体構成体
３ シリコン基板
４ 接続パッド
１０ 配線
１１ 柱状電極
１２ 封止膜
１３ 配線板
２５ 第１の上層絶縁膜
２８ 第１の上層配線
２９ 第２の上層絶縁膜
３２ 第２の上層配線
３３ 最上層絶縁膜
３５ 半田ボール
３８ 第１の下層配線
３９ 下層絶縁膜
４２ 第２の下層配線
４３ 最下層絶縁膜 DESCRIPTION OF SYMBOLS 1 Base board 2 Semiconductor structure 3 Silicon substrate 4 Connection pad 10 Wiring 11 Columnar electrode 12 Sealing film 13 Wiring board 25 1st upper layer insulating film 28 1st upper layer wiring 29 2nd upper layer insulating film 32 2nd upper layer Wiring 33 Uppermost layer insulating film 35 Solder ball 38 First lower layer wiring 39 Lower layer insulating film 42 Second lower layer wiring 43 Lowermost layer insulating film

Claims (25)

ベース部材と、前記ベース部材上に設けられ、且つ、半導体基板および該半導体基板上に設けられた複数の外部接続用電極を有する少なくとも１つの半導体構成体と、前記半導体構成体に対応する部分に開口部を有し、該開口部内に前記半導体構成体を収納して前記半導体構成体の周囲に配置された配線板と、前記半導体構成体および前記配線板上に前記半導体構成体の外部接続用電極および前記配線板に電気的に接続されて設けられ、接続パッド部を有する少なくとも１層の上層配線とを備えていることを特徴とする半導体装置。 A base member, at least one semiconductor structure provided on the base member and having a semiconductor substrate and a plurality of external connection electrodes provided on the semiconductor substrate, and a portion corresponding to the semiconductor structure A wiring board having an opening, housing the semiconductor structure in the opening and arranged around the semiconductor structure, and external connection of the semiconductor structure on the semiconductor structure and the wiring board A semiconductor device comprising: an electrode and at least one upper layer wiring provided electrically connected to the wiring board and having a connection pad portion. 請求項１に記載の発明において、前記配線板の開口部と前記半導体構成体との間には隙間が設けられ、該隙間に充填材が充填されていることを特徴とする半導体装置。 The semiconductor device according to claim 1, wherein a gap is provided between the opening of the wiring board and the semiconductor structure, and the gap is filled with a filler. 請求項１に記載の発明において、前記最上層の上層配線の接続パッド部の少なくとも一部は前記配線板上に配置されていることを特徴とする半導体装置。 2. The semiconductor device according to claim 1, wherein at least a part of the connection pad portion of the uppermost wiring of the uppermost layer is disposed on the wiring board. 請求項１に記載の発明において、前記ベース部材はプリプレグ材からなることを特徴とする半導体装置。 2. The semiconductor device according to claim 1, wherein the base member is made of a prepreg material. 請求項１に記載の発明において、前記配線板は多層配線板からなることを特徴とする半導体装置。 2. The semiconductor device according to claim 1, wherein the wiring board comprises a multilayer wiring board. 請求項１に記載の発明において、前記半導体構成体は、前記外部接続用電極としての柱状電極を有するものであることを特徴とする半導体装置。 The semiconductor device according to claim 1, wherein the semiconductor structure includes a columnar electrode as the external connection electrode. 請求項１に記載の発明において、前記半導体構成体は、前記外部接続用電極としての接続パッド部を有する配線を有するものであることを特徴とする半導体装置。 2. The semiconductor device according to claim 1, wherein the semiconductor structure includes a wiring having a connection pad portion as the external connection electrode. 請求項１に記載の発明において、前記充填材の熱膨張係数は、前記半導体構成体の半導体基板の熱膨張係数よりも大きく、且つ、前記配線板の絶縁基板の熱膨張係数よりも小さいことを特徴とする半導体装置。 In the invention according to claim 1, the thermal expansion coefficient of the filler is larger than the thermal expansion coefficient of the semiconductor substrate of the semiconductor structure and smaller than the thermal expansion coefficient of the insulating substrate of the wiring board. A featured semiconductor device. 請求項８に記載の発明において、前記充填材は、樹脂中に熱膨張係数低下用材料が混入されたものからなることを特徴とする半導体装置。 9. The semiconductor device according to claim 8, wherein the filler is made of a resin in which a material for reducing a thermal expansion coefficient is mixed. 請求項１に記載の発明において、前記最上層の上層配線の接続パッド部を除く部分を覆う最上層絶縁膜を有することを特徴とする半導体装置。 2. The semiconductor device according to claim 1, further comprising an uppermost insulating film that covers a portion of the uppermost layer upper wiring except for a connection pad portion. 請求項１０に記載の発明において、前記最上層の上層配線の接続パッド部上に半田ボールが設けられていることを特徴とする半導体装置。 11. The semiconductor device according to claim 10, wherein a solder ball is provided on a connection pad portion of the uppermost layer upper wiring. 請求項１に記載の発明において、前記ベース部材下に少なくとも１層の下層配線が前記配線板に電気的に接続されて設けられていることを特徴とする半導体装置。 2. The semiconductor device according to claim 1, wherein at least one lower layer wiring is provided below the base member and electrically connected to the wiring board. 請求項１２に記載の発明において、前記最下層の下層配線を覆う最下層絶縁膜を有することを特徴とする半導体装置。 13. The semiconductor device according to claim 12, further comprising a lowermost insulating film that covers the lowermost lower layer wiring. 請求項１１に記載の発明において、前記最下層の下層配線の接続パッド部を除く部分を覆う最下層絶縁膜を有することを特徴とする半導体装置。 12. The semiconductor device according to claim 11, further comprising a lowermost insulating film covering a portion excluding the connection pad portion of the lowermost lower layer wiring. 請求項１４に記載の発明において、前記最下層絶縁膜下に電子部品が前記最下層の下層配線の接続パッド部に接続されて設けられていることを特徴とする半導体装置。 15. The semiconductor device according to claim 14, wherein an electronic component is provided below the lowermost insulating film so as to be connected to a connection pad portion of the lowermost lower layer wiring. 請求項１に記載の発明において、前記半導体構成体を複数個備えていることを特徴とする半導体装置。 The semiconductor device according to claim 1, comprising a plurality of the semiconductor structural bodies. 各々が半導体基板および該半導体基板上に設けられた複数の外部接続用電極を有する複数の半導体構成体と前記各半導体構成体に対応する部分に開口部を有する集合配線板とを、前記集合配線板の各開口部内に前記半導体構成体が配置されるようにベース部材上に配置する工程と、
前記半導体構成体および前記集合配線板上に、接続パッド部を有する少なくとも１層の上層配線を前記半導体構成体の外部接続用電極および前記配線板に電気的に接続させて形成する工程と、
前記半導体構成体間における前記ベース部材および前記集合配線板を少なくとも切断して前記半導体構成体が少なくとも１つ含まれる半導体装置を複数個得る工程と、
を有することを特徴とする半導体装置の製造方法。 A plurality of semiconductor structures each having a semiconductor substrate and a plurality of external connection electrodes provided on the semiconductor substrate, and an assembly wiring board having an opening in a portion corresponding to each semiconductor structure, the assembly wiring Placing on the base member such that the semiconductor construct is placed in each opening of the plate;
Forming at least one upper layer wiring having a connection pad portion on the semiconductor structure and the assembly wiring board by electrically connecting to the external connection electrode of the semiconductor structure and the wiring board;
Cutting at least the base member and the assembly wiring board between the semiconductor structures to obtain a plurality of semiconductor devices including at least one semiconductor structure;
A method for manufacturing a semiconductor device, comprising: 請求項１７に記載の発明において、前記集合配線板の各開口部内に前記半導体構成体を配置する工程は、前記集合配線板の各開口部と前記各半導体構成体との間に隙間が形成されるように配置し、前記隙間に充填材を充填する工程を含むことを特徴とする半導体装置の製造方法。 In the invention according to claim 17, in the step of disposing the semiconductor structure in each opening of the collective wiring board, a gap is formed between each opening of the collective wiring board and each semiconductor structure. And a method of manufacturing a semiconductor device, comprising the step of filling the gap with a filler. 請求項１８に記載の発明において、前記集合配線板の各開口部と前記各半導体構成体間に形成された前記隙間に充填材を充填する工程は、前記集合配線板および前記半導体構成体の上面に上層絶縁膜を配置し、加熱加圧板により前記上層絶縁膜を加熱加圧する工程を含むことを特徴とする半導体装置の製造方法。 19. The process according to claim 18, wherein the step of filling the gaps formed between the openings of the collective wiring board and the semiconductor constituents includes upper surfaces of the collective wiring board and the semiconductor constituents. A method of manufacturing a semiconductor device, comprising the steps of: disposing an upper insulating film on the substrate and heating and pressurizing the upper insulating film with a heating and pressing plate. 請求項１７に記載の発明において、前記最上層の上層配線の接続パッド部の少なくとも一部を前記集合配線板上に配置することを特徴とする半導体装置の製造方法。 18. The method of manufacturing a semiconductor device according to claim 17, wherein at least a part of a connection pad portion of the uppermost wiring of the uppermost layer is disposed on the collective wiring board. 請求項１７に記載の発明において、前記ベース部材はプリプレグ材からなることを特徴とする半導体装置の製造方法。 18. The method of manufacturing a semiconductor device according to claim 17, wherein the base member is made of a prepreg material. 請求項１７に記載の発明において、前記集合配線板は多層配線板からなることを特徴とする半導体装置の製造方法。。 18. The method of manufacturing a semiconductor device according to claim 17, wherein the collective wiring board comprises a multilayer wiring board. . 請求項１７に記載の発明において、前記切断は、前記半導体構成体が複数個含まれるように切断することを特徴とする半導体装置の製造方法。 18. The method of manufacturing a semiconductor device according to claim 17, wherein the cutting is performed so that a plurality of the semiconductor structures are included. 請求項１７に記載の発明において、前記半導体構成体の前記ベース部材上への配置は、切断前の前記集合配線板の開口部の周囲における配線形成部が良品と判定された部分に対応する位置にのみ配置することを特徴とする半導体装置の製造方法。 18. The arrangement according to claim 17, wherein the semiconductor structure is arranged on the base member at a position corresponding to a portion where the wiring forming portion around the opening of the assembly wiring board before cutting is determined to be a non-defective product. A method for manufacturing a semiconductor device, characterized in that the semiconductor device is arranged only in 請求項２４に記載の発明において、切断前の前記集合配線板の開口部のうち、前記半導体構成体が配置されない開口部内に充填材を充填することを特徴とする半導体装置の製造方法。
25. The method of manufacturing a semiconductor device according to claim 24, wherein a filling material is filled in an opening in which the semiconductor structure is not arranged, of the opening of the assembly wiring board before cutting.
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