JP2005158797A - Manufacturing method for semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technique capable of improving polishing characteristics in a CMP. <P>SOLUTION: When a silicon oxide film deposited on a semiconductor substrate is polished by a CMP method and left in trenches and element isolating sections are formed, a polishing pad PD in which the primary working trenches TN1 straightly extended in the outer peripheral direction from a central section, the secondary working trenches TN2 branched from the trenches TN1 and extended in the outer peripheral direction, and the tertiary working trenches TN3 branched from the trenches TN2 and extended in the outer peripheral direction are formed in each region of a surface divided into the plural at a radiation angle θ<SB>1</SB>of 30 to 60°, and a branch angle θ<SB>2</SB>in the outer peripheral direction formed by the trenches TN1 and the trenches TN2 and the branch angle θ<SB>3</SB>in the outer peripheral direction formed by the trenches TN2 and the trenches TN3 are set within 90°, is used. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device manufacturing technique, and in particular, uses a chemical mechanical polishing (CMP) method for processing unevenness of a surface such as an insulating film or a metal film deposited on a semiconductor wafer to be flat. The present invention relates to a technique that is effective when applied to the manufacture of semiconductor devices.

  The CMP apparatus includes a polishing head unit that applies rotation and pressurization while holding a semiconductor wafer on the upper side, and a driving mechanism for the polishing head unit, a platen (surface plate) on which a polishing pad is attached on the lower side in a manner opposed to the polishing head unit, and driving the platen. Other mechanisms include a polishing pad dressing mechanism, a semiconductor wafer or chuck surface cleaning mechanism, a slurry (polishing liquid) supply mechanism, and the like.

By the way, as the integration of semiconductor devices increases, the semiconductor elements are miniaturized and the element structure becomes complicated. For this reason, in the current CMP process, scratches and damages generated on the surface of a material to be polished (for example, an insulating film or a relatively soft metal film such as aluminum or copper), an increase in foreign matter, and polishing characteristics (polishing rate and uniform polishing) )) And other problems have occurred. These are one of the factors that lower the manufacturing yield of semiconductor devices, and are thought to be caused by clogging of the surface of the polishing pad, aggregated particles of slurry deposited on the surface of the polishing pad, or scraps from the pad retainer ring. It is done. Therefore, various studies have been made to solve the above problems. For example, optimization of the material of the polishing pad or the shape of micropores and grooves provided on the surface, or abrasive grains and additives in the slurry has been studied (see Non-Patent Document 1).
Edited by Toshiro Toi, “Semiconductor CMP Technology”, Industrial Research Co., Ltd., January 10, 2001, p. 113-119

  The inventors of the present invention have studied the shape of fine holes and grooves formed on the surface of the polishing pad as a technique for improving the polishing characteristics in the CMP process. For example, by processing the surface of the polishing pad, a hole pattern (Perforation) in which a number of small holes with a diameter of 1 to 2 mm are formed on the surface of the polishing pad, an XY lattice pattern (XY Grooved) in which grooves are formed in a lattice shape, or concentric grooves A concentric pattern (K Grooved) was formed to improve the fluidity of the slurry and the polishing characteristics in the semiconductor wafer surface.

  However, even if these patterns are applied to the surface of the polishing pad, the slurry dropped on the polishing pad does not spread smoothly, and polishing conditions set in the CMP apparatus, such as the platen rotation speed, the amount of slurry dropped, or the polishing head portion When the rotation speed or load of the wafer changes, the polishing characteristics change following this. For this reason, it is necessary to confirm the consistency between the pattern applied to the surface of the polishing pad and the polishing conditions, and there is also a problem that the polishing conditions for obtaining good polishing characteristics are narrow. Furthermore, since a large amount of slurry is required, the manufacturing cost of the CMP process becomes relatively high.

  An object of the present invention is to provide a technique capable of improving polishing characteristics in CMP.

  Another object of the present invention is to provide a technique capable of relatively reducing the dripping amount of slurry used in CMP.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A method of manufacturing a semiconductor device according to the present invention includes a step of chemically and mechanically polishing the surface of a material to be polished formed on a semiconductor substrate using a polishing pad, and the surface of the polishing pad is subjected to a predetermined radiation angle. Are divided into a plurality of regions, and each of the plurality of regions is formed with a processing groove extending radially from the center of the polishing pad toward the outer periphery.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  By forming a processing groove on the surface of the polishing pad that extends while branching radially from the center of the polishing pad to the outer periphery, the spread (self-diffusion) of the slurry dripped onto the polishing pad becomes smoother and the polishing characteristics are improved. To do. Further, since the spread of the slurry becomes smooth, the dripping amount of the slurry can be relatively reduced.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

  An example of a method for manufacturing a complementary metal oxide semiconductor (CMOS) device according to an embodiment of the present invention will be described in the order of steps with reference to FIGS.

  First, as shown in FIG. 1A, a semiconductor substrate (semiconductor wafer processed into a circular thin plate) 1 made of single crystal silicon having a specific resistance of about 10 Ωcm is prepared. Subsequently, the semiconductor substrate 1 is heat-treated at about 850 ° C. to form a thin pad oxide film (not shown) having a thickness of about 10 nm on its main surface. Subsequently, a silicon nitride film (not shown) having a thickness of about 120 nm is deposited on the pad oxide film by a CVD (Chemical Vapor Deposition) method, and then the element isolation region is nitrided by dry etching using the photoresist film as a mask. The silicon film and the pad oxide film are removed. The pad oxide film is formed for the purpose of alleviating stress applied to the semiconductor substrate 1 when a silicon oxide film embedded in the element isolation trench is densified (baked) in a later step. Further, since the silicon nitride film has a property that is not easily oxidized, it is used as a mask for preventing oxidation of the surface of the semiconductor substrate 1 below (active region).

  Next, an isolation groove 4a having a depth of about 350 nm is formed in the semiconductor substrate 1 in the element isolation region by dry etching using the silicon nitride film as a mask, and then the damaged layer generated on the inner wall of the isolation groove 4a is removed by etching. Then, the semiconductor substrate 1 is heat-treated at about 1000 ° C. to form a thin silicon oxide film 2 having a thickness of about 10 nm on the inner wall of the separation groove 4a. Subsequently, a silicon oxide film 4b is deposited on the semiconductor substrate 1 by a CVD method.

  Next, as shown in FIG. 1B, in order to improve the quality of the silicon oxide film 4b, the semiconductor substrate 1 is heat-treated to densify the silicon oxide film 4b. Thereafter, the silicon oxide film 4b is polished by the CMP method using the silicon nitride film as a stopper and left inside the isolation groove 4a, thereby forming an element isolation portion having a planarized surface.

  Here, the CMP process when forming the element isolation part will be described. First, when polishing the silicon oxide film 4b, a silica-based slurry is mainly used as an abrasive, and the polishing pad is made of a polyurethane foam in which closed cells are formed, and has an average diameter of about 150 μm or less. Can be exemplified.

  Further, the surface of the polishing pad is grooved. FIG. 2A shows a first groove pattern provided on the surface of the polishing pad, and FIG. 2B shows an enlarged view of a part of the first groove pattern.

The surface of the polishing pad PD is divided into a plurality of regions (indicated by dotted lines in the figure) with a predetermined radiation angle (θ ₁ ) from the center of the polishing pad PD. A first groove pattern P1 is formed that extends while the groove branches radially from the center of the polishing pad PD toward the outer periphery. The first groove pattern P1 includes a primary processing groove TN1 that extends straight from the center of the polishing pad PD in the outer peripheral direction, a secondary processing groove TN2 that branches from the primary processing groove TN1 and extends in the outer peripheral direction, and further a secondary processing groove TN2. And a tertiary machining groove TN3 extending from the outer circumference and extending in the outer circumferential direction. The primary to tertiary processed grooves TN1, TN2, and TN3 do not reach the outer periphery of the polishing pad PD, and disappear before reaching the outer periphery. Furthermore, in order to maintain the flow rate of the slurry, the primary to tertiary processing grooves TN1, TN2, and TN3 are arranged so as not to be coupled to each other. The first groove pattern P1 employs a staircase branch. That is, even after the secondary machining groove TN2 is branched from the primary machining groove TN1, the primary machining groove TN1 extends in the same direction as before the branching, and similarly, the secondary machining groove TN2 is branched from the tertiary machining groove TN3. After that, the secondary machining groove TN2 extends in the same direction as before branching.

The branch angle θ _{2 in the} outer circumferential direction formed by the primary machining groove TN1 and the secondary machining groove TN2 branched therefrom, and the branch angle θ ₃ in the outer circumferential direction formed by the secondary machining groove TN2 and the tertiary machining groove TN3 branched therefrom. Although it should just be within 90 degree | times, 30-60 degree | times can be mentioned as a suitable angle. In the first groove pattern P1 shown in FIG. 2, the branch angles θ ₂ and θ ₃ are set to 45 degrees. Further, the radiation angle θ ₁ of one region where the first groove pattern P1 is formed is preferably 30 to 60 degrees. In the first groove pattern P1 shown in FIG. 2, the radiation angle θ ₁ is 45 degrees.

  In the first groove pattern P1, primary to tertiary processed grooves TN1, TN2, and TN3 are formed. However, the present invention is not limited to this, and fourth or higher processed grooves may be formed. However, if many processed grooves are formed in the polishing pad PD, the processed grooves may be coupled to each other and the slurry flow rate may not be maintained. Therefore, it is desirable to form the processed grooves up to the third order. Further, in the first groove pattern P1, all the primary processing grooves TN1 extend in the outer peripheral direction from the center of the polishing pad PD, and the primary processing grooves TN1 extending in the outer peripheral direction from other than the center are not formed.

  The widths of the primary to tertiary processed grooves TN1, TN2, and TN3 can all be the same. However, in order to maintain the flow rate of the slurry, it is desirable that the width is gradually reduced as the order increases. FIG. 3 shows an enlarged view of a part of the machining groove. Here, the primary machining groove TN1 and a part of the secondary machining groove TN2 branched therefrom are shown. The width of the secondary machining groove TN2 is narrower than the width of the primary machining groove TN1, and the relationship can be expressed by, for example, Expression (1).

A = α × Bβ Formula (1)
In Formula (1), A is the width of the primary machining groove TN1, B is the width of the secondary machining groove TN2, and α and β are arbitrary constants. Here, the relationship between the width of the primary machining groove TN1 and the width of the secondary machining groove TN2 has been described. However, the present invention is not limited to this, and the width of the n (n is an integer of 1 or more) secondary machining groove. And the width of the (n + 1) -order processed groove, for example, the width of the tertiary-processed groove TN3 is narrower than the width of the secondary-processed groove TN2, and satisfies the relationship expressed by Expression (1). be able to.

  In this way, by forming a processing groove on the surface of the polishing pad PD that extends while radially branching from the center of the polishing pad PD toward the outer peripheral direction, the spread of the slurry dropped on the polishing pad PD is made smooth. As a result, the polishing characteristics can be improved. Further, since the spread of the slurry becomes smooth, the dripping amount of the slurry can be reduced by about 30 to 40% as compared with the case where a polishing pad that does not form micropores or grooves on the surface is used. Thereby, the manufacturing cost in the CMP process can be reduced.

Next, other groove patterns obtained by changing the branching rule of the first groove pattern P1 with the radiation angle θ ₁ being 60 degrees are shown in FIGS.

FIG. 4 shows the second groove pattern of the step branch with the branch angles θ ₂ and θ _{3 set} to 30 degrees. The second groove pattern P2 employs the same stepped branch as the first groove pattern P1, but the branch angle θ _{2 in the} outer circumferential direction formed by the primary machining groove TN1 and the secondary machining groove TN2 branched therefrom and The branch angle θ ₃ in the outer circumferential direction formed by the secondary machining groove TN2 and the tertiary machining groove TN3 branched therefrom is 30 degrees.

  FIG. 5 shows a third groove pattern employing a complete branch in which the n-th processed groove extends in a direction different from that before the branch after the (n + 1) -th processed groove is branched from the n-th processed groove. In the third groove pattern P3, the processing groove extends radially from the center of the polishing pad PD in the outer peripheral direction and branches, but the branching angle and the branching order are arbitrary.

  FIG. 6 shows a fourth groove pattern that employs a first mixed branch in which the n-th processed groove extends in the same direction as that before the branch and a different direction after the (n + 1) -th processed groove branches from the n-th processed groove. In the fourth groove pattern P4, the processing grooves extend radially from the center of the polishing pad PD toward the outer peripheral direction and branch. However, the branch angle is 30 degrees or an arbitrary angle, and the branching dimension is arbitrary. .

FIG. 7 shows a fifth groove pattern employing a second mixed branch in which the (n + 1) -th processed groove is branched from the n-th processed groove and then the n-th processed groove extends in the same direction as that before branching and in a different direction. In the fifth groove pattern P5, similarly to the fourth groove pattern P4, the branching angle θ ₃ is 30 degrees or an arbitrary angle, and the branching dimension is arbitrary. Further, in the fifth groove pattern P5, the ratio of the processed grooves per unit area is made substantially constant. That is, the processing grooves are arranged so that the area ratio of the processing grooves is substantially constant in the A region and the B region shown in the drawing. Thereby, the flow rate of the slurry can be maintained.

Next, FIG. 8 shows another groove pattern in which the radiation angle θ ₁ is 30 degrees and the branching rule of the first groove pattern P1 is changed. In the sixth groove pattern P6, processing grooves depending on the rotation direction of the polishing pad PD are arranged. For example, the secondary processing groove TN2 and the tertiary processing groove TN3 extend only in the outer peripheral direction opposite to the rotation direction of the polishing pad PD, and thereby the slurry smoothly spreads in the direction opposite to the rotation direction of the polishing pad PD. Can do.

Using such a polishing pad PD, the silicon oxide film 4b outside the separation groove 4a is polished using the silicon nitride film as a polishing end point. In polishing the silicon oxide film 4b, a CMP apparatus as shown in FIG. 9 is used. In this CMP apparatus, a polishing pad PD is placed on a platen PLT that rotates by a driving force of a motor M1. The carrier CRY holds the main surface of the semiconductor wafer (semiconductor substrate 1) toward the polishing pad PD, and rotates by the driving force of the motor M2. Under such circumstances, while supplying the slurry SLR to the surface of the polishing pad PD, the silicon oxide film 4b formed on the main surface of the semiconductor wafer by the rotational motion of the platen PLT and the rotational motion of the carrier CRY is chemically and It is mechanically polished. FIG. 10 is an enlarged view of the carrier CRY in the CMP apparatus shown in FIG. The carrier CRY is formed of a wafer chuck CHK that holds a semiconductor wafer, a retainer ring RNG that prevents the semiconductor wafer from being removed during polishing, and a polishing housing HOS that holds these portions and applies polishing pressure to the semiconductor wafer. After the formation of the silicon oxide film 4b, polishing abrasive grains and contamination adhering to the surface of the semiconductor substrate 1 are removed by cleaning using, for example, diluted ammonia water, pure water, and DHF (dilute hydrofluoric acid) solution.

  Next, as shown in FIG. 11A, after the silicon nitride film remaining on the active region of the semiconductor substrate 1 is removed by wet etching using hot phosphoric acid, the n-channel MISFET (Metal) of the semiconductor substrate 1 is removed. Boron (B) is ion-implanted into a region where an Insulator Semiconductor Field Effect Transistor is to be formed to form a p-type well 5. Subsequently, phosphorus (P) is ion-implanted into a region of the semiconductor substrate 1 where a p-channel MISFET is to be formed, thereby forming an n-type well 6.

  Next, the semiconductor substrate 1 is heat-treated to form the gate insulating film 7 on the surfaces of the p-type well 5 and the n-type well 6, and then the gate electrode 8 is formed on the gate insulating film 7. The gate electrode 8 is composed of, for example, a three-layer conductive film in which a low-resistance polycrystalline silicon film doped with phosphorus, a tungsten nitride (WN) film, and a tungsten (W) film are stacked in this order.

  Then, phosphorus or arsenic (As) is ion-implanted into the p-type well 5 to form an n-type semiconductor region (source / drain) 9, and boron is ion-implanted into the n-type well 6 to form a p-type semiconductor region ( (Source, drain) 10 is formed. Through the steps so far, the n-channel MISFET Qn is formed in the p-type well 5, and the p-channel MISFET Qp is formed in the n-type well 6. Subsequently, an interlayer insulating film 11 made of silicon oxide is formed on the n-channel MISFET Qn and the p-channel MISFET Qp.

  Next, as shown in FIG. 11B, the surface of the interlayer insulating film 11 is polished by the CMP method, and the surface is processed to be flat. At the time of polishing, the CMP apparatus shown in FIG. 9 is used to polish the interlayer insulating film 11 with the polishing pad in which the processing groove according to the present embodiment is formed.

  Next, as shown in FIG. 12A, the interlayer insulating film 11 is dry-etched using the photoresist film as a mask, so that an n-type semiconductor region (source, drain) 9 and a p-type semiconductor region (source, drain) are formed. ) A contact hole 12 is formed above 10. Subsequently, for example, a titanium (Ti) film having a thickness of about 10 nm and a titanium nitride (TiN) film having a thickness of about 10 nm are sequentially deposited on the semiconductor substrate 1 including the inside of the contact hole 12 by a sputtering method. Then, a tungsten film 13b having a film thickness of, for example, about 500 nm is further deposited by CVD, and the contact hole 12 is buried.

  Next, as shown in FIG. 12B, the barrier conductor film 13a and the tungsten film 13b on the interlayer insulating film 11 other than the contact hole 12 are removed by, for example, a CMP method, and the plug 13 is formed. At the time of polishing, using the CMP apparatus shown in FIG. 9 above, the barrier conductor film 13a outside the contact hole 12 with the interlayer insulating film 11 as the polishing end point by the polishing pad in which the processing groove according to the present embodiment is formed and The tungsten film 13b is polished.

  Next, as shown in FIG. 13A, an etching stopper film 14 is formed on the semiconductor substrate 1 by depositing a silicon nitride film by, for example, the CVD method. The etching stopper film 14 is for avoiding damage to the lower layer due to excessive digging or deterioration of processing dimensional accuracy when forming a wiring forming groove or hole in the upper insulating film. Is. In this embodiment, the use of a silicon nitride film as the etching stopper film 14 is exemplified. However, instead of the silicon nitride film, a silicon carbide (SiC) film deposited by a plasma CVD method or a component of a silicon carbide film contains nitrogen. A silicon carbonitride (SiCN) film containing a predetermined amount of (N) may be used.

  Next, for example, a silicon oxide film is deposited on the surface of the etching stopper film 14 by a CVD method, and an interlayer insulating film 15 having a thickness of about 200 nm is deposited. Subsequently, by using the photoresist film as a mask, the etching stopper film 14 and the interlayer insulating film 15 are dry-etched to form a wiring groove 16 for forming a buried wiring. Subsequently, in order to remove the reaction layer on the surface of the plug 13 exposed at the bottom of the wiring groove 16, surface treatment of the semiconductor substrate 1 is performed by sputter etching in an argon (Ar) atmosphere.

  Next, a tantalum nitride (TaN) film, for example, which becomes the barrier conductor film 17A is deposited on the entire surface of the semiconductor substrate 1 by reactive sputtering. The deposition of the tantalum nitride film is performed in order to improve the adhesion of the copper (Cu) film deposited in the subsequent process and to prevent the diffusion of copper, and the film thickness can be exemplified as about 30 nm. In the present embodiment, a tantalum nitride film is exemplified as the barrier conductor film 17A, but a metal film such as tantalum (Ta), a laminated film of tantalum nitride and tantalum, a titanium nitride film, or a metal film and a titanium nitride film The laminated film may be used.

Next, for example, a copper film or a copper alloy film serving as a seed film is deposited on the entire surface of the semiconductor substrate 1 on which the barrier conductor film 17A is deposited by ionization sputtering or CVD. Subsequently, a copper film is deposited on the entire surface of the semiconductor substrate 1 on which the seed film is deposited so as to fill the wiring groove 16, and the copper film and the seed film are combined to form a conductive film 17B. The copper film filling the wiring groove 16 is formed by, for example, an electrolytic plating method. As a plating solution, for example, 10% copper sulfate (CuSO ₄ ) in sulfuric acid (H ₂ SO ₄ ) and copper film for improving the coverage. Use with additives. In this embodiment, the case where the electrolytic plating method is used for the deposition of the copper film filling the wiring groove 16 is illustrated, but the electroless plating method may be used. Subsequently, by relaxing the distortion of the copper film by annealing, a high-quality copper film can be obtained.

  Next, as shown in FIG. 13B, the excess barrier conductor film 17A and the conductive film 17B on the interlayer insulating film 15 are removed, leaving the barrier conductor film 17A and the conductive film 17B in the wiring groove 16. As a result, the buried wiring 17 is formed. The removal of the barrier conductor film 17A and the conductive film 17B is performed by polishing using a CMP method. At this time, in order to completely remove the barrier conductor film 17A in the region other than the wiring groove 16, it is necessary to perform over polishing. Further, since the polishing rate of the barrier conductor film 17A is lower than the polishing rate of the conductive film 17B, the conductive film 17B to be embedded is selectively used in the wiring groove 16 having a relatively wide width during the over-polishing process. It may be polished and a dent may be generated in the center. At the time of polishing, using the CMP apparatus shown in FIG. 9 above, the barrier conductor film 17A outside the wiring groove 16 with the interlayer insulating film 15 as the polishing end point is polished by the polishing pad in which the processing groove according to the present embodiment is formed. The conductive film 17B is polished.

  Next, as shown in FIG. 14A, a silicon nitride film is deposited on the buried wiring 17 and the interlayer insulating film 15 to form an etching stopper film 18. For the deposition of the silicon nitride film, for example, a plasma CVD method can be used, and the film thickness is about 50 nm. Similar to the etching stopper film 14, a silicon carbide film or a silicon carbonitride film may be used as the etching stopper film 18. The etching stopper film 18 can function as an etching stopper layer when etching is performed in a later process. The etching stopper film 18 also has a function of suppressing the diffusion of copper forming the conductive film 17B of the embedded wiring 17.

  Next, an insulating film 19 having a thickness of about 200 nm is deposited on the surface of the etching stopper film 18. Examples of the insulating film 19 include a low dielectric constant film (SiOF film) such as a CVD oxide film to which fluorine is added. Subsequently, the surface of the insulating film 19 is polished by the CMP method, and the surface is processed to be flat. At the time of polishing, the insulating film 19 is polished by using the CMP apparatus shown in FIG. 9 with the polishing pad in which the processing groove according to the present embodiment is formed.

  Next, a silicon nitride film is deposited on the surface of the insulating film 19 by, for example, plasma CVD to form an etching stopper film 20 having a thickness of about 25 nm. Similar to the etching stopper films 14 and 18, a silicon carbide film or a silicon carbonitride film may be used as the etching stopper film 20. This etching stopper film 20 forms an insulating film on the etching stopper film 20 in a later step, and when a trench or hole for forming a wiring is formed in the insulating film, the underlying layer may be damaged due to excessive digging. This is to avoid the deterioration of the machining dimensional accuracy.

  Next, a silicon oxide film is deposited on the surface of the etching stopper film 20 by, for example, a CVD method to form an insulating film 21 having a thickness of about 225 nm. Similar to the insulating film 19, the insulating film 21 may be a low dielectric constant film such as a CVD oxide film to which fluorine is added. Thereby, the total dielectric constant of the wiring of the semiconductor device of this embodiment can be lowered, and wiring delay can be improved. Although illustration is omitted, after the insulating film 21 is formed, a silicon nitride film is deposited on the surface of the insulating film 21 by, for example, a plasma CVD method, so that the same etching stopper as the etching stopper films 14, 18, and 20 is formed. A film is formed.

  Next, a contact hole is formed for connecting the embedded wiring 17 which is a wiring and the embedded wiring which is an upper layer wiring formed in a later process. It is assumed that this contact hole is formed in a region not shown in FIG. In addition, a photoresist film having the same shape as the contact hole pattern for connecting to the buried wiring 17 is formed on the insulating film 21 as the contact hole, and the insulating film 21, the etching stopper film 20, the insulating film 19, and the like are used as a mask. The etching stopper film 18 can be formed by sequentially dry etching. Subsequently, the photoresist film is removed, a photoresist film having the same shape as the wiring groove pattern is formed on the insulating film 21, and the insulating film 21 and the etching stopper film 20 are sequentially dry-etched using the photoresist film as a mask, thereby increasing the width. A wiring groove 22 of about 0.25 μm to 50 μm is formed.

  Next, a barrier conductor film 23A having a thickness of about 50 nm is deposited by a process similar to the process of depositing the barrier conductor film 17A. As this barrier conductor film 23A, for example, a tantalum (Ta) film can be used. In this embodiment, a tantalum film is exemplified as the barrier conductor film 23A, but a tantalum nitride film, a titanium nitride film, or a laminated film of a nitride film and a metal film such as a tantalum film may be used. When the barrier conductor film 23A is a titanium nitride film, the surface of the titanium nitride film can be sputter etched immediately before the copper film is deposited in the subsequent process.

  Next, for example, a copper film or a copper alloy film serving as a seed film is deposited on the entire surface of the semiconductor substrate 1 on which the barrier conductor film 23A is deposited by a long-distance sputtering method or a CVD method. Subsequently, on the entire surface of the semiconductor substrate 1 on which the seed film is deposited, a conductive film made of, for example, a copper film having a thickness of about 750 nm is deposited so as to fill the contact hole and the wiring groove 22. Together with the seed film, a conductive film 23B is obtained. The conductive film filling the contact hole and the wiring groove 22 can be formed by, for example, an electrolytic plating method. Subsequently, the distortion of the conductive film 23B is removed and stabilized by annealing.

  Next, as shown in FIG. 14B, the excess barrier conductor film 23A and the conductive film 23B on the insulating film 21 are removed by polishing using the CMP method, and a barrier is formed in the contact hole and the wiring groove 22. By leaving the conductor film 23A and the conductive film 23B, the embedded wiring 23 is formed.

  After the formation of the embedded wiring 23, for example, by repeating the same process as described with reference to FIG. 14, wiring is formed in multiple layers above the embedded wiring 23, and the entire surface of the semiconductor substrate 1 is further covered with a passivation film. By covering, the CMOS device is almost completed.

  In the present embodiment, the case where the present invention is applied to the CMP process, which is a process for manufacturing a CMOS device, has been described. However, the present invention is not limited to the material of the material to be polished, and any process for manufacturing a semiconductor device. It can also be applied to processes.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the above-described embodiment, the case where the present invention is applied to a CMP polishing pad has been described. However, the present invention can also be applied to a silicon crystal polishing pad or an optical lens polishing pad.

  The present invention can be applied to a method of manufacturing a semiconductor device having a CMP process in which unevenness on the surface of an insulating film or a metal film deposited on a semiconductor wafer is processed flat.

It is principal part sectional drawing explaining the manufacturing method of the semiconductor device which is embodiment of this invention. It is a principal part top view of the polishing pad in which the 1st groove | channel pattern used at the time of the CMP process performed during the manufacturing process of the semiconductor device which is embodiment of this invention was formed. FIG. 3 is a main part explanatory view of a first groove pattern shown in FIG. 2. It is a principal part top view of the polishing pad in which the 2nd groove | channel pattern used at the time of the CMP process performed during the manufacturing process of the semiconductor device which is embodiment of this invention was formed. It is a principal part top view of the polishing pad in which the 3rd groove pattern used at the time of CMP processing performed during the manufacturing process of the semiconductor device which is embodiment of this invention was formed. It is a principal part top view of the polishing pad in which the 4th groove | channel pattern used at the time of the CMP process performed during the manufacturing process of the semiconductor device which is embodiment of this invention was formed. It is a principal part top view of the polishing pad in which the 5th groove | channel pattern used at the time of the CMP process performed during the manufacturing process of the semiconductor device which is embodiment of this invention was formed. It is a principal part top view of the polishing pad in which the 7th groove | channel pattern used at the time of CMP processing performed during the manufacturing process of the semiconductor device which is embodiment of this invention was formed. It is explanatory drawing of the CMP apparatus used for manufacture of the semiconductor device which is embodiment of this invention. It is principal part explanatory drawing of the CMP apparatus shown in FIG. FIG. 2 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 1; FIG. 12 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 11; FIG. 13 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 12; FIG. 14 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 13;

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Silicon oxide film 4a Separation groove 4b Silicon oxide film 5 P type well 6 N type well 7 Gate insulating film 8 Gate electrode 9 N type semiconductor region (source, drain)
10 p-type semiconductor region (source, drain)
DESCRIPTION OF SYMBOLS 11 Interlayer insulating film 12 Contact hole 13 Plug 13a Barrier conductor film 13b Tungsten film 14 Etching stopper film 15 Interlayer insulating film 16 Wiring groove 17 Embedded wiring 17A Barrier conductor film 17B Conductive film 18 Etching stopper film 19 Insulating film 20 Etching stopper film 21 Insulating film 22 Wiring groove (groove)
23 Embedded wiring 23A Barrier conductor film 23B Conductive film CHK Wafer chuck CRY Carrier HOS Polishing housing M1, M2 Motor TN1 Primary machining groove TN2 Secondary machining groove TN3 Tertiary machining groove P1 First groove pattern P2 Second groove pattern P3 Second 3 groove pattern P4 4th groove pattern P5 5th groove pattern P6 6th groove pattern PD Polishing pad PLT Platen Qn n channel type MISFET
Qp p-channel MISFET
RNG Retainer Ring SLR Slurry

Claims (5)

A step of chemically and mechanically polishing a surface of a material to be polished formed on a semiconductor substrate using a polishing pad;
The surface of the polishing pad is divided into a plurality of regions with a predetermined radiation angle,
Each of the plurality of regions is formed with a processing groove extending radially from the central portion of the polishing pad in the outer circumferential direction. A step of chemically and mechanically polishing a surface of a material to be polished formed on a semiconductor substrate using a polishing pad;
The surface of the polishing pad is divided into a plurality of regions with a predetermined radiation angle,
Each of the plurality of regions is formed with a processing groove extending while radially branching from the center of the polishing pad toward the outer periphery.
A method of manufacturing a semiconductor device, wherein a width of an (n + 1) -order processed groove branched from an n-number (where n is an integer of 1 or more) next-processed groove is narrower than the width of the n-order processed groove. A step of chemically and mechanically polishing a surface of a material to be polished formed on a semiconductor substrate using a polishing pad;
The surface of the polishing pad is divided into a plurality of regions with a predetermined radiation angle,
Each of the plurality of regions is formed with a processing groove extending while radially branching from the center of the polishing pad toward the outer periphery.
A branching angle in the outer peripheral direction formed by an n (where n is an integer greater than or equal to 1) primary processing groove and an (n + 1) primary processing groove branched from the n-order processing groove is within 90 degrees. Manufacturing method. A step of chemically and mechanically polishing a surface of a material to be polished formed on a semiconductor substrate using a polishing pad;
The surface of the polishing pad is divided into a plurality of regions with a predetermined radiation angle,
Each of the plurality of regions is formed with a processing groove extending while radially branching from the center of the polishing pad toward the outer periphery.
A method of manufacturing a semiconductor device, wherein a ratio of the processing groove per unit area of the polishing pad is substantially constant. A step of chemically and mechanically polishing a surface of a material to be polished formed on a semiconductor substrate using a polishing pad;
The surface of the polishing pad is divided into a plurality of regions with a predetermined radiation angle,
Each of the plurality of regions is formed with a processing groove extending radially from the central portion of the polishing pad to an outer peripheral direction opposite to the rotation direction of the polishing pad. Production method.

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